include/exec/cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_DEFS_H
  20 #define CPU_DEFS_H
  21
  22 #ifndef NEED_CPU_H
  23 #error cpu.h included from common code
  24 #endif
  25
  26 #include "config.h"
  27 #include <setjmp.h>
  28 #include <inttypes.h>
  29 #include "qemu/osdep.h"
  30 #include "qemu/queue.h"
  31 #ifndef CONFIG_USER_ONLY
  32 #include "exec/hwaddr.h"
  33 #endif
  34
  35 #ifndef TARGET_LONG_BITS
  36 #error TARGET_LONG_BITS must be defined before including this header
  37 #endif
  38
  39 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
  40
  41 /* target_ulong is the type of a virtual address */
  42 #if TARGET_LONG_SIZE == 4
  43 typedef int32_t target_long;
  44 typedef uint32_t target_ulong;
  45 #define TARGET_FMT_lx "%08x"
  46 #define TARGET_FMT_ld "%d"
  47 #define TARGET_FMT_lu "%u"
  48 #elif TARGET_LONG_SIZE == 8
  49 typedef int64_t target_long;
  50 typedef uint64_t target_ulong;
  51 #define TARGET_FMT_lx "%016" PRIx64
  52 #define TARGET_FMT_ld "%" PRId64
  53 #define TARGET_FMT_lu "%" PRIu64
  54 #else
  55 #error TARGET_LONG_SIZE undefined
  56 #endif
  57
  58 #define EXCP_INTERRUPT  0x10000 /* async interruption */
  59 #define EXCP_HLT        0x10001 /* hlt instruction reached */
  60 #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
  61 #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
  62 #define EXCP_YIELD      0x10004 /* cpu wants to yield timeslice to another */
  63
  64 #define TB_JMP_CACHE_BITS 12
  65 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
  66
  67 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
  68    addresses on the same page.  The top bits are the same.  This allows
  69    TLB invalidation to quickly clear a subset of the hash table.  */
  70 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
  71 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
  72 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
  73 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
  74
  75 #if !defined(CONFIG_USER_ONLY)
  76 #define CPU_TLB_BITS 8
  77 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
  78
  79 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
  80 #define CPU_TLB_ENTRY_BITS 4
  81 #else
  82 #define CPU_TLB_ENTRY_BITS 5
  83 #endif
  84
  85 typedef struct CPUTLBEntry {
  86     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
  87        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
  88                                     go directly to ram.
  89        bit 3                      : indicates that the entry is invalid
  90        bit 2..0                   : zero
  91     */
  92     target_ulong addr_read;
  93     target_ulong addr_write;
  94     target_ulong addr_code;
  95     /* Addend to virtual address to get host address.  IO accesses
  96        use the corresponding iotlb value.  */
  97     uintptr_t addend;
  98     /* padding to get a power of two size */
  99     uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
 100                   (sizeof(target_ulong) * 3 +
 101                    ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
 102                    sizeof(uintptr_t))];
 103 } CPUTLBEntry;
 104
 105 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
 106
 107 #define CPU_COMMON_TLB \
 108     /* The meaning of the MMU modes is defined in the target code. */   \
 109     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
 110     hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
 111     target_ulong tlb_flush_addr;                                        \
 112     target_ulong tlb_flush_mask;
 113
 114 #else
 115
 116 #define CPU_COMMON_TLB
 117
 118 #endif
 119
 120
 121 #ifdef HOST_WORDS_BIGENDIAN
 122 typedef struct icount_decr_u16 {
 123     uint16_t high;
 124     uint16_t low;
 125 } icount_decr_u16;
 126 #else
 127 typedef struct icount_decr_u16 {
 128     uint16_t low;
 129     uint16_t high;
 130 } icount_decr_u16;
 131 #endif
 132
 133 typedef struct CPUBreakpoint {
 134     target_ulong pc;
 135     int flags; /* BP_* */
 136     QTAILQ_ENTRY(CPUBreakpoint) entry;
 137 } CPUBreakpoint;
 138
 139 typedef struct CPUWatchpoint {
 140     target_ulong vaddr;
 141     target_ulong len_mask;
 142     int flags; /* BP_* */
 143     QTAILQ_ENTRY(CPUWatchpoint) entry;
 144 } CPUWatchpoint;
 145
 146 #define CPU_TEMP_BUF_NLONGS 128
 147 #define CPU_COMMON                                                      \
 148     /* soft mmu support */                                              \
 149     CPU_COMMON_TLB                                                      \
 150     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
 151                                                                         \
 152     int64_t icount_extra; /* Instructions until next timer event.  */   \
 153     /* Number of cycles left, with interrupt flag in high bit.          \
 154        This allows a single read-compare-cbranch-write sequence to test \
 155        for both decrementer underflow and exceptions.  */               \
 156     union {                                                             \
 157         uint32_t u32;                                                   \
 158         icount_decr_u16 u16;                                            \
 159     } icount_decr;                                                      \
 160     uint32_t can_do_io; /* nonzero if memory mapped IO is safe.  */     \
 161                                                                         \
 162     /* from this point: preserved by CPU reset */                       \
 163     /* ice debug support */                                             \
 164     QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;            \
 165                                                                         \
 166     QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;            \
 167     CPUWatchpoint *watchpoint_hit;                                      \
 168                                                                         \
 169     /* Core interrupt code */                                           \
 170     sigjmp_buf jmp_env;                                                 \
 171     int exception_index;                                                \
 172                                                                         \
 173     /* user data */                                                     \
 174     void *opaque;                                                       \
 175
 176 #endif