target-sh4/cpu.c

   1 /*
   2  * QEMU SuperH CPU
   3  *
   4  * Copyright (c) 2005 Samuel Tardieu
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "cpu.h"
  23 #include "qemu-common.h"
  24 #include "migration/vmstate.h"
  25
  26
  27 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
  28 {
  29     SuperHCPU *cpu = SUPERH_CPU(cs);
  30
  31     cpu->env.pc = value;
  32 }
  33
  34 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  35 {
  36     SuperHCPU *cpu = SUPERH_CPU(cs);
  37
  38     cpu->env.pc = tb->pc;
  39     cpu->env.flags = tb->flags;
  40 }
  41
  42 static bool superh_cpu_has_work(CPUState *cs)
  43 {
  44     return cs->interrupt_request & CPU_INTERRUPT_HARD;
  45 }
  46
  47 /* CPUClass::reset() */
  48 static void superh_cpu_reset(CPUState *s)
  49 {
  50     SuperHCPU *cpu = SUPERH_CPU(s);
  51     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
  52     CPUSH4State *env = &cpu->env;
  53
  54     scc->parent_reset(s);
  55
  56     memset(env, 0, offsetof(CPUSH4State, id));
  57     tlb_flush(s, 1);
  58
  59     env->pc = 0xA0000000;
  60 #if defined(CONFIG_USER_ONLY)
  61     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
  62     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
  63 #else
  64     env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
  65               (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
  66     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
  67     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
  68     set_flush_to_zero(1, &env->fp_status);
  69 #endif
  70     set_default_nan_mode(1, &env->fp_status);
  71 }
  72
  73 typedef struct SuperHCPUListState {
  74     fprintf_function cpu_fprintf;
  75     FILE *file;
  76 } SuperHCPUListState;
  77
  78 /* Sort alphabetically by type name. */
  79 static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
  80 {
  81     ObjectClass *class_a = (ObjectClass *)a;
  82     ObjectClass *class_b = (ObjectClass *)b;
  83     const char *name_a, *name_b;
  84
  85     name_a = object_class_get_name(class_a);
  86     name_b = object_class_get_name(class_b);
  87     return strcmp(name_a, name_b);
  88 }
  89
  90 static void superh_cpu_list_entry(gpointer data, gpointer user_data)
  91 {
  92     ObjectClass *oc = data;
  93     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
  94     SuperHCPUListState *s = user_data;
  95
  96     (*s->cpu_fprintf)(s->file, "%s\n",
  97                       scc->name);
  98 }
  99
 100 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 101 {
 102     SuperHCPUListState s = {
 103         .cpu_fprintf = cpu_fprintf,
 104         .file = f,
 105     };
 106     GSList *list;
 107
 108     list = object_class_get_list(TYPE_SUPERH_CPU, false);
 109     list = g_slist_sort(list, superh_cpu_list_compare);
 110     g_slist_foreach(list, superh_cpu_list_entry, &s);
 111     g_slist_free(list);
 112 }
 113
 114 static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
 115 {
 116     const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
 117     const char *name = b;
 118
 119     return strcasecmp(scc->name, name);
 120 }
 121
 122 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
 123 {
 124     ObjectClass *oc;
 125     GSList *list, *item;
 126
 127     if (cpu_model == NULL) {
 128         return NULL;
 129     }
 130     if (strcasecmp(cpu_model, "any") == 0) {
 131         return object_class_by_name(TYPE_SH7750R_CPU);
 132     }
 133
 134     oc = object_class_by_name(cpu_model);
 135     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
 136         && !object_class_is_abstract(oc)) {
 137         return oc;
 138     }
 139
 140     oc = NULL;
 141     list = object_class_get_list(TYPE_SUPERH_CPU, false);
 142     item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
 143     if (item != NULL) {
 144         oc = item->data;
 145     }
 146     g_slist_free(list);
 147     return oc;
 148 }
 149
 150 SuperHCPU *cpu_sh4_init(const char *cpu_model)
 151 {
 152     return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
 153 }
 154
 155 static void sh7750r_cpu_initfn(Object *obj)
 156 {
 157     SuperHCPU *cpu = SUPERH_CPU(obj);
 158     CPUSH4State *env = &cpu->env;
 159
 160     env->id = SH_CPU_SH7750R;
 161     env->features = SH_FEATURE_BCR3_AND_BCR4;
 162 }
 163
 164 static void sh7750r_class_init(ObjectClass *oc, void *data)
 165 {
 166     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 167
 168     scc->name = "SH7750R";
 169     scc->pvr = 0x00050000;
 170     scc->prr = 0x00000100;
 171     scc->cvr = 0x00110000;
 172 }
 173
 174 static const TypeInfo sh7750r_type_info = {
 175     .name = TYPE_SH7750R_CPU,
 176     .parent = TYPE_SUPERH_CPU,
 177     .class_init = sh7750r_class_init,
 178     .instance_init = sh7750r_cpu_initfn,
 179 };
 180
 181 static void sh7751r_cpu_initfn(Object *obj)
 182 {
 183     SuperHCPU *cpu = SUPERH_CPU(obj);
 184     CPUSH4State *env = &cpu->env;
 185
 186     env->id = SH_CPU_SH7751R;
 187     env->features = SH_FEATURE_BCR3_AND_BCR4;
 188 }
 189
 190 static void sh7751r_class_init(ObjectClass *oc, void *data)
 191 {
 192     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 193
 194     scc->name = "SH7751R";
 195     scc->pvr = 0x04050005;
 196     scc->prr = 0x00000113;
 197     scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
 198 }
 199
 200 static const TypeInfo sh7751r_type_info = {
 201     .name = TYPE_SH7751R_CPU,
 202     .parent = TYPE_SUPERH_CPU,
 203     .class_init = sh7751r_class_init,
 204     .instance_init = sh7751r_cpu_initfn,
 205 };
 206
 207 static void sh7785_cpu_initfn(Object *obj)
 208 {
 209     SuperHCPU *cpu = SUPERH_CPU(obj);
 210     CPUSH4State *env = &cpu->env;
 211
 212     env->id = SH_CPU_SH7785;
 213     env->features = SH_FEATURE_SH4A;
 214 }
 215
 216 static void sh7785_class_init(ObjectClass *oc, void *data)
 217 {
 218     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 219
 220     scc->name = "SH7785";
 221     scc->pvr = 0x10300700;
 222     scc->prr = 0x00000200;
 223     scc->cvr = 0x71440211;
 224 }
 225
 226 static const TypeInfo sh7785_type_info = {
 227     .name = TYPE_SH7785_CPU,
 228     .parent = TYPE_SUPERH_CPU,
 229     .class_init = sh7785_class_init,
 230     .instance_init = sh7785_cpu_initfn,
 231 };
 232
 233 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
 234 {
 235     CPUState *cs = CPU(dev);
 236     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
 237
 238     cpu_reset(cs);
 239     qemu_init_vcpu(cs);
 240
 241     scc->parent_realize(dev, errp);
 242 }
 243
 244 static void superh_cpu_initfn(Object *obj)
 245 {
 246     CPUState *cs = CPU(obj);
 247     SuperHCPU *cpu = SUPERH_CPU(obj);
 248     CPUSH4State *env = &cpu->env;
 249
 250     cs->env_ptr = env;
 251     cpu_exec_init(cs, &error_abort);
 252
 253     env->movcal_backup_tail = &(env->movcal_backup);
 254
 255     if (tcg_enabled()) {
 256         sh4_translate_init();
 257     }
 258 }
 259
 260 static const VMStateDescription vmstate_sh_cpu = {
 261     .name = "cpu",
 262     .unmigratable = 1,
 263 };
 264
 265 static void superh_cpu_class_init(ObjectClass *oc, void *data)
 266 {
 267     DeviceClass *dc = DEVICE_CLASS(oc);
 268     CPUClass *cc = CPU_CLASS(oc);
 269     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 270
 271     scc->parent_realize = dc->realize;
 272     dc->realize = superh_cpu_realizefn;
 273
 274     scc->parent_reset = cc->reset;
 275     cc->reset = superh_cpu_reset;
 276
 277     cc->class_by_name = superh_cpu_class_by_name;
 278     cc->has_work = superh_cpu_has_work;
 279     cc->do_interrupt = superh_cpu_do_interrupt;
 280     cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
 281     cc->dump_state = superh_cpu_dump_state;
 282     cc->set_pc = superh_cpu_set_pc;
 283     cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
 284     cc->gdb_read_register = superh_cpu_gdb_read_register;
 285     cc->gdb_write_register = superh_cpu_gdb_write_register;
 286 #ifdef CONFIG_USER_ONLY
 287     cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
 288 #else
 289     cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
 290 #endif
 291     dc->vmsd = &vmstate_sh_cpu;
 292     cc->gdb_num_core_regs = 59;
 293 }
 294
 295 static const TypeInfo superh_cpu_type_info = {
 296     .name = TYPE_SUPERH_CPU,
 297     .parent = TYPE_CPU,
 298     .instance_size = sizeof(SuperHCPU),
 299     .instance_init = superh_cpu_initfn,
 300     .abstract = true,
 301     .class_size = sizeof(SuperHCPUClass),
 302     .class_init = superh_cpu_class_init,
 303 };
 304
 305 static void superh_cpu_register_types(void)
 306 {
 307     type_register_static(&superh_cpu_type_info);
 308     type_register_static(&sh7750r_type_info);
 309     type_register_static(&sh7751r_type_info);
 310     type_register_static(&sh7785_type_info);
 311 }
 312
 313 type_init(superh_cpu_register_types)