tests/ahci-test.c

   1 /*
   2  * AHCI test cases
   3  *
   4  * Copyright (c) 2014 John Snow <jsnow@redhat.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <stdio.h>
  28 #include <getopt.h>
  29 #include <glib.h>
  30
  31 #include "libqtest.h"
  32 #include "libqos/ahci.h"
  33 #include "libqos/pci-pc.h"
  34 #include "libqos/malloc-pc.h"
  35
  36 #include "qemu-common.h"
  37 #include "qemu/host-utils.h"
  38
  39 #include "hw/pci/pci_ids.h"
  40 #include "hw/pci/pci_regs.h"
  41
  42 /* Test-specific defines. */
  43 #define TEST_IMAGE_SIZE    (64 * 1024 * 1024)
  44
  45 /*** Globals ***/
  46 static QGuestAllocator *guest_malloc;
  47 static QPCIBus *pcibus;
  48 static uint64_t barsize;
  49 static char tmp_path[] = "/tmp/qtest.XXXXXX";
  50 static bool ahci_pedantic;
  51 static uint32_t ahci_fingerprint;
  52
  53 /*** IO macros for the AHCI memory registers. ***/
  54 #define AHCI_READ(OFST) qpci_io_readl(ahci, hba_base + (OFST))
  55 #define AHCI_WRITE(OFST, VAL) qpci_io_writel(ahci, hba_base + (OFST), (VAL))
  56 #define AHCI_RREG(regno)      AHCI_READ(4 * (regno))
  57 #define AHCI_WREG(regno, val) AHCI_WRITE(4 * (regno), (val))
  58 #define AHCI_SET(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) | (mask))
  59 #define AHCI_CLR(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) & ~(mask))
  60
  61 /*** IO macros for port-specific offsets inside of AHCI memory. ***/
  62 #define PX_OFST(port, regno) (HBA_PORT_NUM_REG * (port) + AHCI_PORTS + (regno))
  63 #define PX_RREG(port, regno)      AHCI_RREG(PX_OFST((port), (regno)))
  64 #define PX_WREG(port, regno, val) AHCI_WREG(PX_OFST((port), (regno)), (val))
  65 #define PX_SET(port, reg, mask)   PX_WREG((port), (reg),                \
  66                                           PX_RREG((port), (reg)) | (mask));
  67 #define PX_CLR(port, reg, mask)   PX_WREG((port), (reg),                \
  68                                           PX_RREG((port), (reg)) & ~(mask));
  69
  70 /*** Function Declarations ***/
  71 static QPCIDevice *get_ahci_device(void);
  72 static QPCIDevice *start_ahci_device(QPCIDevice *dev, void **hba_base);
  73 static void free_ahci_device(QPCIDevice *dev);
  74 static void ahci_test_port_spec(QPCIDevice *ahci, void *hba_base,
  75                                 HBACap *hcap, uint8_t port);
  76 static void ahci_test_pci_spec(QPCIDevice *ahci);
  77 static void ahci_test_pci_caps(QPCIDevice *ahci, uint16_t header,
  78                                uint8_t offset);
  79 static void ahci_test_satacap(QPCIDevice *ahci, uint8_t offset);
  80 static void ahci_test_msicap(QPCIDevice *ahci, uint8_t offset);
  81 static void ahci_test_pmcap(QPCIDevice *ahci, uint8_t offset);
  82
  83 /*** Utilities ***/
  84
  85 static void string_bswap16(uint16_t *s, size_t bytes)
  86 {
  87     g_assert_cmphex((bytes & 1), ==, 0);
  88     bytes /= 2;
  89
  90     while (bytes--) {
  91         *s = bswap16(*s);
  92         s++;
  93     }
  94 }
  95
  96 /**
  97  * Locate, verify, and return a handle to the AHCI device.
  98  */
  99 static QPCIDevice *get_ahci_device(void)
 100 {
 101     QPCIDevice *ahci;
 102
 103     pcibus = qpci_init_pc();
 104
 105     /* Find the AHCI PCI device and verify it's the right one. */
 106     ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
 107     g_assert(ahci != NULL);
 108
 109     ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
 110
 111     switch (ahci_fingerprint) {
 112     case AHCI_INTEL_ICH9:
 113         break;
 114     default:
 115         /* Unknown device. */
 116         g_assert_not_reached();
 117     }
 118
 119     return ahci;
 120 }
 121
 122 static void free_ahci_device(QPCIDevice *ahci)
 123 {
 124     /* libqos doesn't have a function for this, so free it manually */
 125     g_free(ahci);
 126
 127     if (pcibus) {
 128         qpci_free_pc(pcibus);
 129         pcibus = NULL;
 130     }
 131
 132     /* Clear our cached barsize information. */
 133     barsize = 0;
 134 }
 135
 136 /*** Test Setup & Teardown ***/
 137
 138 /**
 139  * Launch QEMU with the given command line,
 140  * and then set up interrupts and our guest malloc interface.
 141  */
 142 static void qtest_boot(const char *cmdline_fmt, ...)
 143 {
 144     va_list ap;
 145     char *cmdline;
 146
 147     va_start(ap, cmdline_fmt);
 148     cmdline = g_strdup_vprintf(cmdline_fmt, ap);
 149     va_end(ap);
 150
 151     qtest_start(cmdline);
 152     qtest_irq_intercept_in(global_qtest, "ioapic");
 153     guest_malloc = pc_alloc_init();
 154
 155     g_free(cmdline);
 156 }
 157
 158 /**
 159  * Tear down the QEMU instance.
 160  */
 161 static void qtest_shutdown(void)
 162 {
 163     g_free(guest_malloc);
 164     guest_malloc = NULL;
 165     qtest_end();
 166 }
 167
 168 /**
 169  * Start a Q35 machine and bookmark a handle to the AHCI device.
 170  */
 171 static QPCIDevice *ahci_boot(void)
 172 {
 173     qtest_boot("-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s,"
 174                "format=raw"
 175                " -M q35 "
 176                "-device ide-hd,drive=drive0 "
 177                "-global ide-hd.ver=%s",
 178                tmp_path, "testdisk", "version");
 179
 180     /* Verify that we have an AHCI device present. */
 181     return get_ahci_device();
 182 }
 183
 184 /**
 185  * Clean up the PCI device, then terminate the QEMU instance.
 186  */
 187 static void ahci_shutdown(QPCIDevice *ahci)
 188 {
 189     free_ahci_device(ahci);
 190     qtest_shutdown();
 191 }
 192
 193 /*** Logical Device Initialization ***/
 194
 195 /**
 196  * Start the PCI device and sanity-check default operation.
 197  */
 198 static void ahci_pci_enable(QPCIDevice *ahci, void **hba_base)
 199 {
 200     uint8_t reg;
 201
 202     start_ahci_device(ahci, hba_base);
 203
 204     switch (ahci_fingerprint) {
 205     case AHCI_INTEL_ICH9:
 206         /* ICH9 has a register at PCI 0x92 that
 207          * acts as a master port enabler mask. */
 208         reg = qpci_config_readb(ahci, 0x92);
 209         reg |= 0x3F;
 210         qpci_config_writeb(ahci, 0x92, reg);
 211         /* 0...0111111b -- bit significant, ports 0-5 enabled. */
 212         ASSERT_BIT_SET(qpci_config_readb(ahci, 0x92), 0x3F);
 213         break;
 214     }
 215
 216 }
 217
 218 /**
 219  * Map BAR5/ABAR, and engage the PCI device.
 220  */
 221 static QPCIDevice *start_ahci_device(QPCIDevice *ahci, void **hba_base)
 222 {
 223     /* Map AHCI's ABAR (BAR5) */
 224     *hba_base = qpci_iomap(ahci, 5, &barsize);
 225
 226     /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
 227     qpci_device_enable(ahci);
 228
 229     return ahci;
 230 }
 231
 232 /**
 233  * Test and initialize the AHCI's HBA memory areas.
 234  * Initialize and start any ports with devices attached.
 235  * Bring the HBA into the idle state.
 236  */
 237 static void ahci_hba_enable(QPCIDevice *ahci, void *hba_base)
 238 {
 239     /* Bits of interest in this section:
 240      * GHC.AE     Global Host Control / AHCI Enable
 241      * PxCMD.ST   Port Command: Start
 242      * PxCMD.SUD  "Spin Up Device"
 243      * PxCMD.POD  "Power On Device"
 244      * PxCMD.FRE  "FIS Receive Enable"
 245      * PxCMD.FR   "FIS Receive Running"
 246      * PxCMD.CR   "Command List Running"
 247      */
 248
 249     g_assert(ahci != NULL);
 250     g_assert(hba_base != NULL);
 251
 252     uint32_t reg, ports_impl, clb, fb;
 253     uint16_t i;
 254     uint8_t num_cmd_slots;
 255
 256     g_assert(hba_base != 0);
 257
 258     /* Set GHC.AE to 1 */
 259     AHCI_SET(AHCI_GHC, AHCI_GHC_AE);
 260     reg = AHCI_RREG(AHCI_GHC);
 261     ASSERT_BIT_SET(reg, AHCI_GHC_AE);
 262
 263     /* Read CAP.NCS, how many command slots do we have? */
 264     reg = AHCI_RREG(AHCI_CAP);
 265     num_cmd_slots = ((reg & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
 266     g_test_message("Number of Command Slots: %u", num_cmd_slots);
 267
 268     /* Determine which ports are implemented. */
 269     ports_impl = AHCI_RREG(AHCI_PI);
 270
 271     for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
 272         if (!(ports_impl & 0x01)) {
 273             continue;
 274         }
 275
 276         g_test_message("Initializing port %u", i);
 277
 278         reg = PX_RREG(i, AHCI_PX_CMD);
 279         if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
 280                    AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
 281             g_test_message("port is idle");
 282         } else {
 283             g_test_message("port needs to be idled");
 284             PX_CLR(i, AHCI_PX_CMD, (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
 285             /* The port has 500ms to disengage. */
 286             usleep(500000);
 287             reg = PX_RREG(i, AHCI_PX_CMD);
 288             ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
 289             ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
 290             g_test_message("port is now idle");
 291             /* The spec does allow for possibly needing a PORT RESET
 292              * or HBA reset if we fail to idle the port. */
 293         }
 294
 295         /* Allocate Memory for the Command List Buffer & FIS Buffer */
 296         /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
 297         clb = guest_alloc(guest_malloc, num_cmd_slots * 0x20);
 298         g_test_message("CLB: 0x%08x", clb);
 299         PX_WREG(i, AHCI_PX_CLB, clb);
 300         g_assert_cmphex(clb, ==, PX_RREG(i, AHCI_PX_CLB));
 301
 302         /* PxFB space ... 0x100, as in 4.2.1 p 35 */
 303         fb = guest_alloc(guest_malloc, 0x100);
 304         g_test_message("FB: 0x%08x", fb);
 305         PX_WREG(i, AHCI_PX_FB, fb);
 306         g_assert_cmphex(fb, ==, PX_RREG(i, AHCI_PX_FB));
 307
 308         /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
 309         PX_WREG(i, AHCI_PX_SERR, 0xFFFFFFFF);
 310         PX_WREG(i, AHCI_PX_IS, 0xFFFFFFFF);
 311         AHCI_WREG(AHCI_IS, (1 << i));
 312
 313         /* Verify Interrupts Cleared */
 314         reg = PX_RREG(i, AHCI_PX_SERR);
 315         g_assert_cmphex(reg, ==, 0);
 316
 317         reg = PX_RREG(i, AHCI_PX_IS);
 318         g_assert_cmphex(reg, ==, 0);
 319
 320         reg = AHCI_RREG(AHCI_IS);
 321         ASSERT_BIT_CLEAR(reg, (1 << i));
 322
 323         /* Enable All Interrupts: */
 324         PX_WREG(i, AHCI_PX_IE, 0xFFFFFFFF);
 325         reg = PX_RREG(i, AHCI_PX_IE);
 326         g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
 327
 328         /* Enable the FIS Receive Engine. */
 329         PX_SET(i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
 330         reg = PX_RREG(i, AHCI_PX_CMD);
 331         ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
 332
 333         /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
 334          * physical presence, a device is present and may be started. However,
 335          * PxSERR.DIAG.X /may/ need to be cleared a priori. */
 336         reg = PX_RREG(i, AHCI_PX_SERR);
 337         if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
 338             PX_SET(i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
 339         }
 340
 341         reg = PX_RREG(i, AHCI_PX_TFD);
 342         if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
 343             reg = PX_RREG(i, AHCI_PX_SSTS);
 344             if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
 345                 /* Device Found: set PxCMD.ST := 1 */
 346                 PX_SET(i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
 347                 ASSERT_BIT_SET(PX_RREG(i, AHCI_PX_CMD), AHCI_PX_CMD_CR);
 348                 g_test_message("Started Device %u", i);
 349             } else if ((reg & AHCI_PX_SSTS_DET)) {
 350                 /* Device present, but in some unknown state. */
 351                 g_assert_not_reached();
 352             }
 353         }
 354     }
 355
 356     /* Enable GHC.IE */
 357     AHCI_SET(AHCI_GHC, AHCI_GHC_IE);
 358     reg = AHCI_RREG(AHCI_GHC);
 359     ASSERT_BIT_SET(reg, AHCI_GHC_IE);
 360
 361     /* TODO: The device should now be idling and waiting for commands.
 362      * In the future, a small test-case to inspect the Register D2H FIS
 363      * and clear the initial interrupts might be good. */
 364 }
 365
 366 /*** Specification Adherence Tests ***/
 367
 368 /**
 369  * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
 370  */
 371 static void ahci_test_pci_spec(QPCIDevice *ahci)
 372 {
 373     uint8_t datab;
 374     uint16_t data;
 375     uint32_t datal;
 376
 377     /* Most of these bits should start cleared until we turn them on. */
 378     data = qpci_config_readw(ahci, PCI_COMMAND);
 379     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
 380     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
 381     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);     /* Reserved */
 382     ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
 383     ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
 384     ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);        /* Reserved */
 385     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
 386     ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
 387     ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
 388     ASSERT_BIT_CLEAR(data, 0xF800);                  /* Reserved */
 389
 390     data = qpci_config_readw(ahci, PCI_STATUS);
 391     ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);     /* Reserved */
 392     ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
 393     ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);      /* must be set */
 394     ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);         /* Reserved */
 395     ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
 396     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
 397     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
 398     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
 399     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
 400     ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
 401
 402     /* RID occupies the low byte, CCs occupy the high three. */
 403     datal = qpci_config_readl(ahci, PCI_CLASS_REVISION);
 404     if (ahci_pedantic) {
 405         /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
 406          * Though in practice this is likely seldom true. */
 407         ASSERT_BIT_CLEAR(datal, 0xFF);
 408     }
 409
 410     /* BCC *must* equal 0x01. */
 411     g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
 412     if (PCI_SCC(datal) == 0x01) {
 413         /* IDE */
 414         ASSERT_BIT_SET(0x80000000, datal);
 415         ASSERT_BIT_CLEAR(0x60000000, datal);
 416     } else if (PCI_SCC(datal) == 0x04) {
 417         /* RAID */
 418         g_assert_cmphex(PCI_PI(datal), ==, 0);
 419     } else if (PCI_SCC(datal) == 0x06) {
 420         /* AHCI */
 421         g_assert_cmphex(PCI_PI(datal), ==, 0x01);
 422     } else {
 423         g_assert_not_reached();
 424     }
 425
 426     datab = qpci_config_readb(ahci, PCI_CACHE_LINE_SIZE);
 427     g_assert_cmphex(datab, ==, 0);
 428
 429     datab = qpci_config_readb(ahci, PCI_LATENCY_TIMER);
 430     g_assert_cmphex(datab, ==, 0);
 431
 432     /* Only the bottom 7 bits must be off. */
 433     datab = qpci_config_readb(ahci, PCI_HEADER_TYPE);
 434     ASSERT_BIT_CLEAR(datab, 0x7F);
 435
 436     /* BIST is optional, but the low 7 bits must always start off regardless. */
 437     datab = qpci_config_readb(ahci, PCI_BIST);
 438     ASSERT_BIT_CLEAR(datab, 0x7F);
 439
 440     /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
 441     datal = qpci_config_readl(ahci, PCI_BASE_ADDRESS_5);
 442     g_assert_cmphex(datal, ==, 0);
 443
 444     qpci_config_writel(ahci, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
 445     datal = qpci_config_readl(ahci, PCI_BASE_ADDRESS_5);
 446     /* ABAR must be 32-bit, memory mapped, non-prefetchable and
 447      * must be >= 512 bytes. To that end, bits 0-8 must be off. */
 448     ASSERT_BIT_CLEAR(datal, 0xFF);
 449
 450     /* Capability list MUST be present, */
 451     datal = qpci_config_readl(ahci, PCI_CAPABILITY_LIST);
 452     /* But these bits are reserved. */
 453     ASSERT_BIT_CLEAR(datal, ~0xFF);
 454     g_assert_cmphex(datal, !=, 0);
 455
 456     /* Check specification adherence for capability extenstions. */
 457     data = qpci_config_readw(ahci, datal);
 458
 459     switch (ahci_fingerprint) {
 460     case AHCI_INTEL_ICH9:
 461         /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
 462         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
 463         break;
 464     default:
 465         /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
 466         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
 467     }
 468
 469     ahci_test_pci_caps(ahci, data, (uint8_t)datal);
 470
 471     /* Reserved. */
 472     datal = qpci_config_readl(ahci, PCI_CAPABILITY_LIST + 4);
 473     g_assert_cmphex(datal, ==, 0);
 474
 475     /* IPIN might vary, but ILINE must be off. */
 476     datab = qpci_config_readb(ahci, PCI_INTERRUPT_LINE);
 477     g_assert_cmphex(datab, ==, 0);
 478 }
 479
 480 /**
 481  * Test PCI capabilities for AHCI specification adherence.
 482  */
 483 static void ahci_test_pci_caps(QPCIDevice *ahci, uint16_t header,
 484                                uint8_t offset)
 485 {
 486     uint8_t cid = header & 0xFF;
 487     uint8_t next = header >> 8;
 488
 489     g_test_message("CID: %02x; next: %02x", cid, next);
 490
 491     switch (cid) {
 492     case PCI_CAP_ID_PM:
 493         ahci_test_pmcap(ahci, offset);
 494         break;
 495     case PCI_CAP_ID_MSI:
 496         ahci_test_msicap(ahci, offset);
 497         break;
 498     case PCI_CAP_ID_SATA:
 499         ahci_test_satacap(ahci, offset);
 500         break;
 501
 502     default:
 503         g_test_message("Unknown CAP 0x%02x", cid);
 504     }
 505
 506     if (next) {
 507         ahci_test_pci_caps(ahci, qpci_config_readw(ahci, next), next);
 508     }
 509 }
 510
 511 /**
 512  * Test SATA PCI capabilitity for AHCI specification adherence.
 513  */
 514 static void ahci_test_satacap(QPCIDevice *ahci, uint8_t offset)
 515 {
 516     uint16_t dataw;
 517     uint32_t datal;
 518
 519     g_test_message("Verifying SATACAP");
 520
 521     /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
 522     dataw = qpci_config_readw(ahci, offset + 2);
 523     g_assert_cmphex(dataw, ==, 0x10);
 524
 525     /* Grab the SATACR1 register. */
 526     datal = qpci_config_readw(ahci, offset + 4);
 527
 528     switch (datal & 0x0F) {
 529     case 0x04: /* BAR0 */
 530     case 0x05: /* BAR1 */
 531     case 0x06:
 532     case 0x07:
 533     case 0x08:
 534     case 0x09: /* BAR5 */
 535     case 0x0F: /* Immediately following SATACR1 in PCI config space. */
 536         break;
 537     default:
 538         /* Invalid BARLOC for the Index Data Pair. */
 539         g_assert_not_reached();
 540     }
 541
 542     /* Reserved. */
 543     g_assert_cmphex((datal >> 24), ==, 0x00);
 544 }
 545
 546 /**
 547  * Test MSI PCI capability for AHCI specification adherence.
 548  */
 549 static void ahci_test_msicap(QPCIDevice *ahci, uint8_t offset)
 550 {
 551     uint16_t dataw;
 552     uint32_t datal;
 553
 554     g_test_message("Verifying MSICAP");
 555
 556     dataw = qpci_config_readw(ahci, offset + PCI_MSI_FLAGS);
 557     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
 558     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
 559     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
 560
 561     datal = qpci_config_readl(ahci, offset + PCI_MSI_ADDRESS_LO);
 562     g_assert_cmphex(datal, ==, 0);
 563
 564     if (dataw & PCI_MSI_FLAGS_64BIT) {
 565         g_test_message("MSICAP is 64bit");
 566         datal = qpci_config_readl(ahci, offset + PCI_MSI_ADDRESS_HI);
 567         g_assert_cmphex(datal, ==, 0);
 568         dataw = qpci_config_readw(ahci, offset + PCI_MSI_DATA_64);
 569         g_assert_cmphex(dataw, ==, 0);
 570     } else {
 571         g_test_message("MSICAP is 32bit");
 572         dataw = qpci_config_readw(ahci, offset + PCI_MSI_DATA_32);
 573         g_assert_cmphex(dataw, ==, 0);
 574     }
 575 }
 576
 577 /**
 578  * Test Power Management PCI capability for AHCI specification adherence.
 579  */
 580 static void ahci_test_pmcap(QPCIDevice *ahci, uint8_t offset)
 581 {
 582     uint16_t dataw;
 583
 584     g_test_message("Verifying PMCAP");
 585
 586     dataw = qpci_config_readw(ahci, offset + PCI_PM_PMC);
 587     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
 588     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
 589     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
 590     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
 591
 592     dataw = qpci_config_readw(ahci, offset + PCI_PM_CTRL);
 593     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
 594     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
 595     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
 596     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
 597 }
 598
 599 static void ahci_test_hba_spec(QPCIDevice *ahci, void *hba_base)
 600 {
 601     HBACap hcap;
 602     unsigned i;
 603     uint32_t cap, cap2, reg;
 604     uint32_t ports;
 605     uint8_t nports_impl;
 606     uint8_t maxports;
 607
 608     g_assert(ahci != 0);
 609     g_assert(hba_base != 0);
 610
 611     /*
 612      * Note that the AHCI spec does expect the BIOS to set up a few things:
 613      * CAP.SSS    - Support for staggered spin-up            (t/f)
 614      * CAP.SMPS   - Support for mechanical presence switches (t/f)
 615      * PI         - Ports Implemented                        (1-32)
 616      * PxCMD.HPCP - Hot Plug Capable Port
 617      * PxCMD.MPSP - Mechanical Presence Switch Present
 618      * PxCMD.CPD  - Cold Presence Detection support
 619      *
 620      * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
 621      * Foreach Port Implemented:
 622      * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
 623      * -PxCLB/U and PxFB/U are set to valid regions in memory
 624      * -PxSUD is set to 1.
 625      * -PxSSTS.DET is polled for presence; if detected, we continue:
 626      * -PxSERR is cleared with 1's.
 627      * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
 628      *  the device is ready.
 629      */
 630
 631     /* 1 CAP - Capabilities Register */
 632     cap = AHCI_RREG(AHCI_CAP);
 633     ASSERT_BIT_CLEAR(cap, AHCI_CAP_RESERVED);
 634
 635     /* 2 GHC - Global Host Control */
 636     reg = AHCI_RREG(AHCI_GHC);
 637     ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
 638     ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
 639     ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
 640     if (BITSET(cap, AHCI_CAP_SAM)) {
 641         g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
 642         ASSERT_BIT_SET(reg, AHCI_GHC_AE);
 643     } else {
 644         g_test_message("Supports AHCI/Legacy mix.");
 645         ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
 646     }
 647
 648     /* 3 IS - Interrupt Status */
 649     reg = AHCI_RREG(AHCI_IS);
 650     g_assert_cmphex(reg, ==, 0);
 651
 652     /* 4 PI - Ports Implemented */
 653     ports = AHCI_RREG(AHCI_PI);
 654     /* Ports Implemented must be non-zero. */
 655     g_assert_cmphex(ports, !=, 0);
 656     /* Ports Implemented must be <= Number of Ports. */
 657     nports_impl = ctpopl(ports);
 658     g_assert_cmpuint(((AHCI_CAP_NP & cap) + 1), >=, nports_impl);
 659
 660     g_assert_cmphex(barsize, >, 0);
 661     /* Ports must be within the proper range. Given a mapping of SIZE,
 662      * 256 bytes are used for global HBA control, and the rest is used
 663      * for ports data, at 0x80 bytes each. */
 664     maxports = (barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
 665     /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
 666     g_assert_cmphex((reg >> maxports), ==, 0);
 667
 668     /* 5 AHCI Version */
 669     reg = AHCI_RREG(AHCI_VS);
 670     switch (reg) {
 671     case AHCI_VERSION_0_95:
 672     case AHCI_VERSION_1_0:
 673     case AHCI_VERSION_1_1:
 674     case AHCI_VERSION_1_2:
 675     case AHCI_VERSION_1_3:
 676         break;
 677     default:
 678         g_assert_not_reached();
 679     }
 680
 681     /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
 682     reg = AHCI_RREG(AHCI_CCCCTL);
 683     if (BITSET(cap, AHCI_CAP_CCCS)) {
 684         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
 685         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
 686         ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
 687         ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
 688     } else {
 689         g_assert_cmphex(reg, ==, 0);
 690     }
 691
 692     /* 7 CCC_PORTS */
 693     reg = AHCI_RREG(AHCI_CCCPORTS);
 694     /* Must be zeroes initially regardless of CAP.CCCS */
 695     g_assert_cmphex(reg, ==, 0);
 696
 697     /* 8 EM_LOC */
 698     reg = AHCI_RREG(AHCI_EMLOC);
 699     if (BITCLR(cap, AHCI_CAP_EMS)) {
 700         g_assert_cmphex(reg, ==, 0);
 701     }
 702
 703     /* 9 EM_CTL */
 704     reg = AHCI_RREG(AHCI_EMCTL);
 705     if (BITSET(cap, AHCI_CAP_EMS)) {
 706         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
 707         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
 708         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
 709         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
 710     } else {
 711         g_assert_cmphex(reg, ==, 0);
 712     }
 713
 714     /* 10 CAP2 -- Capabilities Extended */
 715     cap2 = AHCI_RREG(AHCI_CAP2);
 716     ASSERT_BIT_CLEAR(cap2, AHCI_CAP2_RESERVED);
 717
 718     /* 11 BOHC -- Bios/OS Handoff Control */
 719     reg = AHCI_RREG(AHCI_BOHC);
 720     g_assert_cmphex(reg, ==, 0);
 721
 722     /* 12 -- 23: Reserved */
 723     g_test_message("Verifying HBA reserved area is empty.");
 724     for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
 725         reg = AHCI_RREG(i);
 726         g_assert_cmphex(reg, ==, 0);
 727     }
 728
 729     /* 24 -- 39: NVMHCI */
 730     if (BITCLR(cap2, AHCI_CAP2_NVMP)) {
 731         g_test_message("Verifying HBA/NVMHCI area is empty.");
 732         for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
 733             reg = AHCI_RREG(i);
 734             g_assert_cmphex(reg, ==, 0);
 735         }
 736     }
 737
 738     /* 40 -- 63: Vendor */
 739     g_test_message("Verifying HBA/Vendor area is empty.");
 740     for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
 741         reg = AHCI_RREG(i);
 742         g_assert_cmphex(reg, ==, 0);
 743     }
 744
 745     /* 64 -- XX: Port Space */
 746     hcap.cap = cap;
 747     hcap.cap2 = cap2;
 748     for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
 749         if (BITSET(ports, 0x1)) {
 750             g_test_message("Testing port %u for spec", i);
 751             ahci_test_port_spec(ahci, hba_base, &hcap, i);
 752         } else {
 753             uint16_t j;
 754             uint16_t low = AHCI_PORTS + (32 * i);
 755             uint16_t high = AHCI_PORTS + (32 * (i + 1));
 756             g_test_message("Asserting unimplemented port %u "
 757                            "(reg [%u-%u]) is empty.",
 758                            i, low, high - 1);
 759             for (j = low; j < high; ++j) {
 760                 reg = AHCI_RREG(j);
 761                 g_assert_cmphex(reg, ==, 0);
 762             }
 763         }
 764     }
 765 }
 766
 767 /**
 768  * Test the memory space for one port for specification adherence.
 769  */
 770 static void ahci_test_port_spec(QPCIDevice *ahci, void *hba_base,
 771                                 HBACap *hcap, uint8_t port)
 772 {
 773     uint32_t reg;
 774     unsigned i;
 775
 776     /* (0) CLB */
 777     reg = PX_RREG(port, AHCI_PX_CLB);
 778     ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
 779
 780     /* (1) CLBU */
 781     if (BITCLR(hcap->cap, AHCI_CAP_S64A)) {
 782         reg = PX_RREG(port, AHCI_PX_CLBU);
 783         g_assert_cmphex(reg, ==, 0);
 784     }
 785
 786     /* (2) FB */
 787     reg = PX_RREG(port, AHCI_PX_FB);
 788     ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
 789
 790     /* (3) FBU */
 791     if (BITCLR(hcap->cap, AHCI_CAP_S64A)) {
 792         reg = PX_RREG(port, AHCI_PX_FBU);
 793         g_assert_cmphex(reg, ==, 0);
 794     }
 795
 796     /* (4) IS */
 797     reg = PX_RREG(port, AHCI_PX_IS);
 798     g_assert_cmphex(reg, ==, 0);
 799
 800     /* (5) IE */
 801     reg = PX_RREG(port, AHCI_PX_IE);
 802     g_assert_cmphex(reg, ==, 0);
 803
 804     /* (6) CMD */
 805     reg = PX_RREG(port, AHCI_PX_CMD);
 806     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
 807     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
 808     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
 809     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
 810     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
 811     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
 812     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
 813     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
 814     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
 815     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);  /* RW only if CAP.SALP */
 816     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);   /* RW only if CAP.SALP */
 817     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
 818     /* If CPDetect support does not exist, CPState must be off. */
 819     if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
 820         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
 821     }
 822     /* If MPSPresence is not set, MPSState must be off. */
 823     if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
 824         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 825     }
 826     /* If we do not support MPS, MPSS and MPSP must be off. */
 827     if (BITCLR(hcap->cap, AHCI_CAP_SMPS)) {
 828         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 829         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
 830     }
 831     /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
 832     if (BITANY(reg, AHCI_PX_CMD_CPD || AHCI_PX_CMD_MPSP)) {
 833         ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
 834     }
 835     /* HPCP and ESP cannot both be active. */
 836     g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
 837     /* If CAP.FBSS is not set, FBSCP must not be set. */
 838     if (BITCLR(hcap->cap, AHCI_CAP_FBSS)) {
 839         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
 840     }
 841
 842     /* (7) RESERVED */
 843     reg = PX_RREG(port, AHCI_PX_RES1);
 844     g_assert_cmphex(reg, ==, 0);
 845
 846     /* (8) TFD */
 847     reg = PX_RREG(port, AHCI_PX_TFD);
 848     /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
 849      * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
 850     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
 851     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
 852     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
 853     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
 854     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
 855     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
 856     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
 857
 858     /* (9) SIG */
 859     /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
 860      * Even when GHC.ST is zero, the AHCI HBA may receive the initial
 861      * D2H register FIS and update the signature asynchronously,
 862      * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
 863
 864     /* (10) SSTS / SCR0: SStatus */
 865     reg = PX_RREG(port, AHCI_PX_SSTS);
 866     ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
 867     /* Even though the register should be 0 at boot, it is asynchronous and
 868      * prone to change, so we cannot test any well known value. */
 869
 870     /* (11) SCTL / SCR2: SControl */
 871     reg = PX_RREG(port, AHCI_PX_SCTL);
 872     g_assert_cmphex(reg, ==, 0);
 873
 874     /* (12) SERR / SCR1: SError */
 875     reg = PX_RREG(port, AHCI_PX_SERR);
 876     g_assert_cmphex(reg, ==, 0);
 877
 878     /* (13) SACT / SCR3: SActive */
 879     reg = PX_RREG(port, AHCI_PX_SACT);
 880     g_assert_cmphex(reg, ==, 0);
 881
 882     /* (14) CI */
 883     reg = PX_RREG(port, AHCI_PX_CI);
 884     g_assert_cmphex(reg, ==, 0);
 885
 886     /* (15) SNTF */
 887     reg = PX_RREG(port, AHCI_PX_SNTF);
 888     g_assert_cmphex(reg, ==, 0);
 889
 890     /* (16) FBS */
 891     reg = PX_RREG(port, AHCI_PX_FBS);
 892     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
 893     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
 894     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
 895     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
 896     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
 897     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
 898     if (BITSET(hcap->cap, AHCI_CAP_FBSS)) {
 899         /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
 900         g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
 901     }
 902
 903     /* [17 -- 27] RESERVED */
 904     for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
 905         reg = PX_RREG(port, i);
 906         g_assert_cmphex(reg, ==, 0);
 907     }
 908
 909     /* [28 -- 31] Vendor-Specific */
 910     for (i = AHCI_PX_VS; i < 32; ++i) {
 911         reg = PX_RREG(port, i);
 912         if (reg) {
 913             g_test_message("INFO: Vendor register %u non-empty", i);
 914         }
 915     }
 916 }
 917
 918 /**
 919  * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
 920  * device we see, then read and check the response.
 921  */
 922 static void ahci_test_identify(QPCIDevice *ahci, void *hba_base)
 923 {
 924     RegD2HFIS *d2h = g_malloc0(0x20);
 925     RegD2HFIS *pio = g_malloc0(0x20);
 926     RegH2DFIS fis;
 927     AHCICommand cmd;
 928     PRD prd;
 929     uint32_t ports, reg, clb, table, fb, data_ptr;
 930     uint16_t buff[256];
 931     unsigned i;
 932     int rc;
 933
 934     g_assert(ahci != NULL);
 935     g_assert(hba_base != NULL);
 936
 937     /* We need to:
 938      * (1) Create a Command Table Buffer and update the Command List Slot #0
 939      *     to point to this buffer.
 940      * (2) Construct an FIS host-to-device command structure, and write it to
 941      *     the top of the command table buffer.
 942      * (3) Create a data buffer for the IDENTIFY response to be sent to
 943      * (4) Create a Physical Region Descriptor that points to the data buffer,
 944      *     and write it to the bottom (offset 0x80) of the command table.
 945      * (5) Now, PxCLB points to the command list, command 0 points to
 946      *     our table, and our table contains an FIS instruction and a
 947      *     PRD that points to our rx buffer.
 948      * (6) We inform the HBA via PxCI that there is a command ready in slot #0.
 949      */
 950
 951     /* Pick the first implemented and running port */
 952     ports = AHCI_RREG(AHCI_PI);
 953     for (i = 0; i < 32; ports >>= 1, ++i) {
 954         if (ports == 0) {
 955             i = 32;
 956         }
 957
 958         if (!(ports & 0x01)) {
 959             continue;
 960         }
 961
 962         reg = PX_RREG(i, AHCI_PX_CMD);
 963         if (BITSET(reg, AHCI_PX_CMD_ST)) {
 964             break;
 965         }
 966     }
 967     g_assert_cmphex(i, <, 32);
 968     g_test_message("Selected port %u for test", i);
 969
 970     /* Clear out this port's interrupts (ignore the init register d2h fis) */
 971     reg = PX_RREG(i, AHCI_PX_IS);
 972     PX_WREG(i, AHCI_PX_IS, reg);
 973     g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
 974
 975     /* Wipe the FIS-Receive Buffer */
 976     fb = PX_RREG(i, AHCI_PX_FB);
 977     g_assert_cmphex(fb, !=, 0);
 978     qmemset(fb, 0x00, 0x100);
 979
 980     /* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */
 981     /* We need at least one PRD, so round up to the nearest 0x80 multiple.    */
 982     table = guest_alloc(guest_malloc, CMD_TBL_SIZ(1));
 983     g_assert(table);
 984     ASSERT_BIT_CLEAR(table, 0x7F);
 985
 986     /* Create a data buffer ... where we will dump the IDENTIFY data to. */
 987     data_ptr = guest_alloc(guest_malloc, 512);
 988     g_assert(data_ptr);
 989
 990     /* Grab the Command List Buffer pointer */
 991     clb = PX_RREG(i, AHCI_PX_CLB);
 992     g_assert(clb);
 993
 994     /* Copy the existing Command #0 structure from the CLB into local memory,
 995      * and build a new command #0. */
 996     memread(clb, &cmd, sizeof(cmd));
 997     cmd.b1 = 5;    /* reg_h2d_fis is 5 double-words long */
 998     cmd.b2 = 0x04; /* clear PxTFD.STS.BSY when done */
 999     cmd.prdtl = cpu_to_le16(1); /* One PRD table entry. */
1000     cmd.prdbc = 0;
1001     cmd.ctba = cpu_to_le32(table);
1002     cmd.ctbau = 0;
1003
1004     /* Construct our PRD, noting that DBC is 0-indexed. */
1005     prd.dba = cpu_to_le32(data_ptr);
1006     prd.dbau = 0;
1007     prd.res = 0;
1008     /* 511+1 bytes, request DPS interrupt */
1009     prd.dbc = cpu_to_le32(511 | 0x80000000);
1010
1011     /* Construct our Command FIS, Based on http://wiki.osdev.org/AHCI */
1012     memset(&fis, 0x00, sizeof(fis));
1013     fis.fis_type = 0x27; /* Register Host-to-Device FIS */
1014     fis.command = 0xEC;  /* IDENTIFY */
1015     fis.device = 0;
1016     fis.flags = 0x80;    /* Indicate this is a command FIS */
1017
1018     /* We've committed nothing yet, no interrupts should be posted yet. */
1019     g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
1020
1021     /* Commit the Command FIS to the Command Table */
1022     memwrite(table, &fis, sizeof(fis));
1023
1024     /* Commit the PRD entry to the Command Table */
1025     memwrite(table + 0x80, &prd, sizeof(prd));
1026
1027     /* Commit Command #0, pointing to the Table, to the Command List Buffer. */
1028     memwrite(clb, &cmd, sizeof(cmd));
1029
1030     /* Everything is in place, but we haven't given the go-ahead yet. */
1031     g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
1032
1033     /* Issue Command #0 via PxCI */
1034     PX_WREG(i, AHCI_PX_CI, (1 << 0));
1035     while (BITSET(PX_RREG(i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) {
1036         usleep(50);
1037     }
1038
1039     /* Check for expected interrupts */
1040     reg = PX_RREG(i, AHCI_PX_IS);
1041     ASSERT_BIT_SET(reg, AHCI_PX_IS_DHRS);
1042     ASSERT_BIT_SET(reg, AHCI_PX_IS_PSS);
1043     /* BUG: we expect AHCI_PX_IS_DPS to be set. */
1044     ASSERT_BIT_CLEAR(reg, AHCI_PX_IS_DPS);
1045
1046     /* Clear expected interrupts and assert all interrupts now cleared. */
1047     PX_WREG(i, AHCI_PX_IS, AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS | AHCI_PX_IS_DPS);
1048     g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
1049
1050     /* Check for errors. */
1051     reg = PX_RREG(i, AHCI_PX_SERR);
1052     g_assert_cmphex(reg, ==, 0);
1053     reg = PX_RREG(i, AHCI_PX_TFD);
1054     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
1055     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
1056
1057     /* Investigate CMD #0, assert that we read 512 bytes */
1058     memread(clb, &cmd, sizeof(cmd));
1059     g_assert_cmphex(512, ==, le32_to_cpu(cmd.prdbc));
1060
1061     /* Investigate FIS responses */
1062     memread(fb + 0x20, pio, 0x20);
1063     memread(fb + 0x40, d2h, 0x20);
1064     g_assert_cmphex(pio->fis_type, ==, 0x5f);
1065     g_assert_cmphex(d2h->fis_type, ==, 0x34);
1066     g_assert_cmphex(pio->flags, ==, d2h->flags);
1067     g_assert_cmphex(pio->status, ==, d2h->status);
1068     g_assert_cmphex(pio->error, ==, d2h->error);
1069
1070     reg = PX_RREG(i, AHCI_PX_TFD);
1071     g_assert_cmphex((reg & AHCI_PX_TFD_ERR), ==, pio->error);
1072     g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, pio->status);
1073     /* The PIO Setup FIS contains a "bytes read" field, which is a
1074      * 16-bit value. The Physical Region Descriptor Byte Count is
1075      * 32-bit, but for small transfers using one PRD, it should match. */
1076     g_assert_cmphex(le16_to_cpu(pio->res4), ==, le32_to_cpu(cmd.prdbc));
1077
1078     /* Last, but not least: Investigate the IDENTIFY response data. */
1079     memread(data_ptr, &buff, 512);
1080
1081     /* Check serial number/version in the buffer */
1082     /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
1083      * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
1084      * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
1085      * as a consequence, only needs to unchunk the data on LE machines. */
1086     string_bswap16(&buff[10], 20);
1087     rc = memcmp(&buff[10], "testdisk            ", 20);
1088     g_assert_cmphex(rc, ==, 0);
1089
1090     string_bswap16(&buff[23], 8);
1091     rc = memcmp(&buff[23], "version ", 8);
1092     g_assert_cmphex(rc, ==, 0);
1093
1094     g_free(d2h);
1095     g_free(pio);
1096 }
1097
1098 /******************************************************************************/
1099 /* Test Interfaces                                                            */
1100 /******************************************************************************/
1101
1102 /**
1103  * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1104  */
1105 static void test_sanity(void)
1106 {
1107     QPCIDevice *ahci;
1108     ahci = ahci_boot();
1109     ahci_shutdown(ahci);
1110 }
1111
1112 /**
1113  * Ensure that the PCI configuration space for the AHCI device is in-line with
1114  * the AHCI 1.3 specification for initial values.
1115  */
1116 static void test_pci_spec(void)
1117 {
1118     QPCIDevice *ahci;
1119     ahci = ahci_boot();
1120     ahci_test_pci_spec(ahci);
1121     ahci_shutdown(ahci);
1122 }
1123
1124 /**
1125  * Engage the PCI AHCI device and sanity check the response.
1126  * Perform additional PCI config space bringup for the HBA.
1127  */
1128 static void test_pci_enable(void)
1129 {
1130     QPCIDevice *ahci;
1131     void *hba_base;
1132     ahci = ahci_boot();
1133     ahci_pci_enable(ahci, &hba_base);
1134     ahci_shutdown(ahci);
1135 }
1136
1137 /**
1138  * Investigate the memory mapped regions of the HBA,
1139  * and test them for AHCI specification adherence.
1140  */
1141 static void test_hba_spec(void)
1142 {
1143     QPCIDevice *ahci;
1144     void *hba_base;
1145
1146     ahci = ahci_boot();
1147     ahci_pci_enable(ahci, &hba_base);
1148     ahci_test_hba_spec(ahci, hba_base);
1149     ahci_shutdown(ahci);
1150 }
1151
1152 /**
1153  * Engage the HBA functionality of the AHCI PCI device,
1154  * and bring it into a functional idle state.
1155  */
1156 static void test_hba_enable(void)
1157 {
1158     QPCIDevice *ahci;
1159     void *hba_base;
1160
1161     ahci = ahci_boot();
1162     ahci_pci_enable(ahci, &hba_base);
1163     ahci_hba_enable(ahci, hba_base);
1164     ahci_shutdown(ahci);
1165 }
1166
1167 /**
1168  * Bring up the device and issue an IDENTIFY command.
1169  * Inspect the state of the HBA device and the data returned.
1170  */
1171 static void test_identify(void)
1172 {
1173     QPCIDevice *ahci;
1174     void *hba_base;
1175
1176     ahci = ahci_boot();
1177     ahci_pci_enable(ahci, &hba_base);
1178     ahci_hba_enable(ahci, hba_base);
1179     ahci_test_identify(ahci, hba_base);
1180     ahci_shutdown(ahci);
1181 }
1182
1183 /******************************************************************************/
1184
1185 int main(int argc, char **argv)
1186 {
1187     const char *arch;
1188     int fd;
1189     int ret;
1190     int c;
1191
1192     static struct option long_options[] = {
1193         {"pedantic", no_argument, 0, 'p' },
1194         {0, 0, 0, 0},
1195     };
1196
1197     /* Should be first to utilize g_test functionality, So we can see errors. */
1198     g_test_init(&argc, &argv, NULL);
1199
1200     while (1) {
1201         c = getopt_long(argc, argv, "", long_options, NULL);
1202         if (c == -1) {
1203             break;
1204         }
1205         switch (c) {
1206         case -1:
1207             break;
1208         case 'p':
1209             ahci_pedantic = 1;
1210             break;
1211         default:
1212             fprintf(stderr, "Unrecognized ahci_test option.\n");
1213             g_assert_not_reached();
1214         }
1215     }
1216
1217     /* Check architecture */
1218     arch = qtest_get_arch();
1219     if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1220         g_test_message("Skipping test for non-x86");
1221         return 0;
1222     }
1223
1224     /* Create a temporary raw image */
1225     fd = mkstemp(tmp_path);
1226     g_assert(fd >= 0);
1227     ret = ftruncate(fd, TEST_IMAGE_SIZE);
1228     g_assert(ret == 0);
1229     close(fd);
1230
1231     /* Run the tests */
1232     qtest_add_func("/ahci/sanity",     test_sanity);
1233     qtest_add_func("/ahci/pci_spec",   test_pci_spec);
1234     qtest_add_func("/ahci/pci_enable", test_pci_enable);
1235     qtest_add_func("/ahci/hba_spec",   test_hba_spec);
1236     qtest_add_func("/ahci/hba_enable", test_hba_enable);
1237     qtest_add_func("/ahci/identify",   test_identify);
1238
1239     ret = g_test_run();
1240
1241     /* Cleanup */
1242     unlink(tmp_path);
1243
1244     return ret;
1245 }