hw/lm32/lm32_boards.c

   1 /*
   2  *  QEMU models for LatticeMico32 uclinux and evr32 boards.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "hw/sysbus.h"
  21 #include "hw/hw.h"
  22 #include "hw/block/flash.h"
  23 #include "hw/devices.h"
  24 #include "hw/boards.h"
  25 #include "hw/loader.h"
  26 #include "sysemu/blockdev.h"
  27 #include "elf.h"
  28 #include "lm32_hwsetup.h"
  29 #include "lm32.h"
  30 #include "exec/address-spaces.h"
  31
  32 typedef struct {
  33     LM32CPU *cpu;
  34     hwaddr bootstrap_pc;
  35     hwaddr flash_base;
  36     hwaddr hwsetup_base;
  37     hwaddr initrd_base;
  38     size_t initrd_size;
  39     hwaddr cmdline_base;
  40 } ResetInfo;
  41
  42 static void cpu_irq_handler(void *opaque, int irq, int level)
  43 {
  44     LM32CPU *cpu = opaque;
  45     CPUState *cs = CPU(cpu);
  46
  47     if (level) {
  48         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  49     } else {
  50         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  51     }
  52 }
  53
  54 static void main_cpu_reset(void *opaque)
  55 {
  56     ResetInfo *reset_info = opaque;
  57     CPULM32State *env = &reset_info->cpu->env;
  58
  59     cpu_reset(CPU(reset_info->cpu));
  60
  61     /* init defaults */
  62     env->pc = (uint32_t)reset_info->bootstrap_pc;
  63     env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
  64     env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
  65     env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
  66     env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
  67         reset_info->initrd_size);
  68     env->eba = reset_info->flash_base;
  69     env->deba = reset_info->flash_base;
  70 }
  71
  72 static void lm32_evr_init(QEMUMachineInitArgs *args)
  73 {
  74     const char *cpu_model = args->cpu_model;
  75     const char *kernel_filename = args->kernel_filename;
  76     LM32CPU *cpu;
  77     CPULM32State *env;
  78     DriveInfo *dinfo;
  79     MemoryRegion *address_space_mem =  get_system_memory();
  80     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
  81     qemu_irq *cpu_irq, irq[32];
  82     ResetInfo *reset_info;
  83     int i;
  84
  85     /* memory map */
  86     hwaddr flash_base  = 0x04000000;
  87     size_t flash_sector_size       = 256 * 1024;
  88     size_t flash_size              = 32 * 1024 * 1024;
  89     hwaddr ram_base    = 0x08000000;
  90     size_t ram_size                = 64 * 1024 * 1024;
  91     hwaddr timer0_base = 0x80002000;
  92     hwaddr uart0_base  = 0x80006000;
  93     hwaddr timer1_base = 0x8000a000;
  94     int uart0_irq                  = 0;
  95     int timer0_irq                 = 1;
  96     int timer1_irq                 = 3;
  97
  98     reset_info = g_malloc0(sizeof(ResetInfo));
  99
 100     if (cpu_model == NULL) {
 101         cpu_model = "lm32-full";
 102     }
 103     cpu = cpu_lm32_init(cpu_model);
 104     if (cpu == NULL) {
 105         fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
 106         exit(1);
 107     }
 108
 109     env = &cpu->env;
 110     reset_info->cpu = cpu;
 111
 112     reset_info->flash_base = flash_base;
 113
 114     memory_region_init_ram(phys_ram, NULL, "lm32_evr.sdram", ram_size);
 115     vmstate_register_ram_global(phys_ram);
 116     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 117
 118     dinfo = drive_get(IF_PFLASH, 0, 0);
 119     /* Spansion S29NS128P */
 120     pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
 121                           dinfo ? dinfo->bdrv : NULL, flash_sector_size,
 122                           flash_size / flash_sector_size, 1, 2,
 123                           0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 124
 125     /* create irq lines */
 126     cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
 127     env->pic_state = lm32_pic_init(*cpu_irq);
 128     for (i = 0; i < 32; i++) {
 129         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 130     }
 131
 132     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 133     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 134     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 135
 136     /* make sure juart isn't the first chardev */
 137     env->juart_state = lm32_juart_init();
 138
 139     reset_info->bootstrap_pc = flash_base;
 140
 141     if (kernel_filename) {
 142         uint64_t entry;
 143         int kernel_size;
 144
 145         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 146                                1, ELF_MACHINE, 0);
 147         reset_info->bootstrap_pc = entry;
 148
 149         if (kernel_size < 0) {
 150             kernel_size = load_image_targphys(kernel_filename, ram_base,
 151                                               ram_size);
 152             reset_info->bootstrap_pc = ram_base;
 153         }
 154
 155         if (kernel_size < 0) {
 156             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 157                     kernel_filename);
 158             exit(1);
 159         }
 160     }
 161
 162     qemu_register_reset(main_cpu_reset, reset_info);
 163 }
 164
 165 static void lm32_uclinux_init(QEMUMachineInitArgs *args)
 166 {
 167     const char *cpu_model = args->cpu_model;
 168     const char *kernel_filename = args->kernel_filename;
 169     const char *kernel_cmdline = args->kernel_cmdline;
 170     const char *initrd_filename = args->initrd_filename;
 171     LM32CPU *cpu;
 172     CPULM32State *env;
 173     DriveInfo *dinfo;
 174     MemoryRegion *address_space_mem =  get_system_memory();
 175     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
 176     qemu_irq *cpu_irq, irq[32];
 177     HWSetup *hw;
 178     ResetInfo *reset_info;
 179     int i;
 180
 181     /* memory map */
 182     hwaddr flash_base   = 0x04000000;
 183     size_t flash_sector_size        = 256 * 1024;
 184     size_t flash_size               = 32 * 1024 * 1024;
 185     hwaddr ram_base     = 0x08000000;
 186     size_t ram_size                 = 64 * 1024 * 1024;
 187     hwaddr uart0_base   = 0x80000000;
 188     hwaddr timer0_base  = 0x80002000;
 189     hwaddr timer1_base  = 0x80010000;
 190     hwaddr timer2_base  = 0x80012000;
 191     int uart0_irq                   = 0;
 192     int timer0_irq                  = 1;
 193     int timer1_irq                  = 20;
 194     int timer2_irq                  = 21;
 195     hwaddr hwsetup_base = 0x0bffe000;
 196     hwaddr cmdline_base = 0x0bfff000;
 197     hwaddr initrd_base  = 0x08400000;
 198     size_t initrd_max               = 0x01000000;
 199
 200     reset_info = g_malloc0(sizeof(ResetInfo));
 201
 202     if (cpu_model == NULL) {
 203         cpu_model = "lm32-full";
 204     }
 205     cpu = cpu_lm32_init(cpu_model);
 206     if (cpu == NULL) {
 207         fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
 208         exit(1);
 209     }
 210
 211     env = &cpu->env;
 212     reset_info->cpu = cpu;
 213
 214     reset_info->flash_base = flash_base;
 215
 216     memory_region_init_ram(phys_ram, NULL, "lm32_uclinux.sdram", ram_size);
 217     vmstate_register_ram_global(phys_ram);
 218     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 219
 220     dinfo = drive_get(IF_PFLASH, 0, 0);
 221     /* Spansion S29NS128P */
 222     pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
 223                           dinfo ? dinfo->bdrv : NULL, flash_sector_size,
 224                           flash_size / flash_sector_size, 1, 2,
 225                           0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 226
 227     /* create irq lines */
 228     cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
 229     env->pic_state = lm32_pic_init(*cpu_irq);
 230     for (i = 0; i < 32; i++) {
 231         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 232     }
 233
 234     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 235     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 236     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 237     sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
 238
 239     /* make sure juart isn't the first chardev */
 240     env->juart_state = lm32_juart_init();
 241
 242     reset_info->bootstrap_pc = flash_base;
 243
 244     if (kernel_filename) {
 245         uint64_t entry;
 246         int kernel_size;
 247
 248         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 249                                1, ELF_MACHINE, 0);
 250         reset_info->bootstrap_pc = entry;
 251
 252         if (kernel_size < 0) {
 253             kernel_size = load_image_targphys(kernel_filename, ram_base,
 254                                               ram_size);
 255             reset_info->bootstrap_pc = ram_base;
 256         }
 257
 258         if (kernel_size < 0) {
 259             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 260                     kernel_filename);
 261             exit(1);
 262         }
 263     }
 264
 265     /* generate a rom with the hardware description */
 266     hw = hwsetup_init();
 267     hwsetup_add_cpu(hw, "LM32", 75000000);
 268     hwsetup_add_flash(hw, "flash", flash_base, flash_size);
 269     hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
 270     hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
 271     hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
 272     hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
 273     hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
 274     hwsetup_add_trailer(hw);
 275     hwsetup_create_rom(hw, hwsetup_base);
 276     hwsetup_free(hw);
 277
 278     reset_info->hwsetup_base = hwsetup_base;
 279
 280     if (kernel_cmdline && strlen(kernel_cmdline)) {
 281         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
 282                 kernel_cmdline);
 283         reset_info->cmdline_base = cmdline_base;
 284     }
 285
 286     if (initrd_filename) {
 287         size_t initrd_size;
 288         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 289                 initrd_max);
 290         reset_info->initrd_base = initrd_base;
 291         reset_info->initrd_size = initrd_size;
 292     }
 293
 294     qemu_register_reset(main_cpu_reset, reset_info);
 295 }
 296
 297 static QEMUMachine lm32_evr_machine = {
 298     .name = "lm32-evr",
 299     .desc = "LatticeMico32 EVR32 eval system",
 300     .init = lm32_evr_init,
 301     .is_default = 1,
 302 };
 303
 304 static QEMUMachine lm32_uclinux_machine = {
 305     .name = "lm32-uclinux",
 306     .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
 307     .init = lm32_uclinux_init,
 308     .is_default = 0,
 309 };
 310
 311 static void lm32_machine_init(void)
 312 {
 313     qemu_register_machine(&lm32_uclinux_machine);
 314     qemu_register_machine(&lm32_evr_machine);
 315 }
 316
 317 machine_init(lm32_machine_init);