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pc: acpi-build: drop template patching and create Device(SMC) dynamically
[qemu/cris-port.git] / hw / i386 / acpi-build.c
blob05eb80a277d7cc9b4c2340ef6d675786ffb68eca
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/range.h"
30 #include "qemu/error-report.h"
31 #include "hw/pci/pci.h"
32 #include "qom/cpu.h"
33 #include "hw/i386/pc.h"
34 #include "target-i386/cpu.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/i386/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/isa/isa.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45
46 /* Supported chipsets: */
47 #include "hw/acpi/piix4.h"
48 #include "hw/acpi/pcihp.h"
49 #include "hw/i386/ich9.h"
50 #include "hw/pci/pci_bus.h"
51 #include "hw/pci-host/q35.h"
52 #include "hw/i386/intel_iommu.h"
53
54 #include "hw/i386/q35-acpi-dsdt.hex"
55 #include "hw/i386/acpi-dsdt.hex"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61 #include "exec/ram_addr.h"
62
63 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
64 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
65 * a little bit, there should be plenty of free space since the DSDT
66 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
67 */
68 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
69 #define ACPI_BUILD_ALIGN_SIZE 0x1000
70
71 #define ACPI_BUILD_TABLE_SIZE 0x20000
72
73 /* Reserve RAM space for tables: add another order of magnitude. */
74 #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
75
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
80 #else
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
82 #endif
83
84 typedef struct AcpiCpuInfo {
85 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
86 } AcpiCpuInfo;
87
88 typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91 } AcpiMcfgInfo;
92
93 typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 uint8_t s4_val;
98 uint16_t sci_int;
99 uint8_t acpi_enable_cmd;
100 uint8_t acpi_disable_cmd;
101 uint32_t gpe0_blk;
102 uint32_t gpe0_blk_len;
103 uint32_t io_base;
104 uint16_t cpu_hp_io_base;
105 uint16_t cpu_hp_io_len;
106 uint16_t mem_hp_io_base;
107 uint16_t mem_hp_io_len;
108 uint16_t pcihp_io_base;
109 uint16_t pcihp_io_len;
110 } AcpiPmInfo;
111
112 typedef struct AcpiMiscInfo {
113 bool has_hpet;
114 bool has_tpm;
115 DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
116 const unsigned char *dsdt_code;
117 unsigned dsdt_size;
118 uint16_t pvpanic_port;
119 uint16_t applesmc_io_base;
120 } AcpiMiscInfo;
121
122 typedef struct AcpiBuildPciBusHotplugState {
123 GArray *device_table;
124 GArray *notify_table;
125 struct AcpiBuildPciBusHotplugState *parent;
126 bool pcihp_bridge_en;
127 } AcpiBuildPciBusHotplugState;
128
129 static void acpi_get_dsdt(AcpiMiscInfo *info)
130 {
131 Object *piix = piix4_pm_find();
132 Object *lpc = ich9_lpc_find();
133 assert(!!piix != !!lpc);
134
135 if (piix) {
136 info->dsdt_code = AcpiDsdtAmlCode;
137 info->dsdt_size = sizeof AcpiDsdtAmlCode;
138 }
139 if (lpc) {
140 info->dsdt_code = Q35AcpiDsdtAmlCode;
141 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
142 }
143 }
144
145 static
146 int acpi_add_cpu_info(Object *o, void *opaque)
147 {
148 AcpiCpuInfo *cpu = opaque;
149 uint64_t apic_id;
150
151 if (object_dynamic_cast(o, TYPE_CPU)) {
152 apic_id = object_property_get_int(o, "apic-id", NULL);
153 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
154
155 set_bit(apic_id, cpu->found_cpus);
156 }
157
158 object_child_foreach(o, acpi_add_cpu_info, opaque);
159 return 0;
160 }
161
162 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
163 {
164 Object *root = object_get_root();
165
166 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
167 object_child_foreach(root, acpi_add_cpu_info, cpu);
168 }
169
170 static void acpi_get_pm_info(AcpiPmInfo *pm)
171 {
172 Object *piix = piix4_pm_find();
173 Object *lpc = ich9_lpc_find();
174 Object *obj = NULL;
175 QObject *o;
176
177 pm->pcihp_io_base = 0;
178 pm->pcihp_io_len = 0;
179 if (piix) {
180 obj = piix;
181 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
182 pm->pcihp_io_base =
183 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
184 pm->pcihp_io_len =
185 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
186 }
187 if (lpc) {
188 obj = lpc;
189 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
190 }
191 assert(obj);
192
193 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
194 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
195 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
196
197 /* Fill in optional s3/s4 related properties */
198 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
199 if (o) {
200 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
201 } else {
202 pm->s3_disabled = false;
203 }
204 qobject_decref(o);
205 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
206 if (o) {
207 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
208 } else {
209 pm->s4_disabled = false;
210 }
211 qobject_decref(o);
212 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
213 if (o) {
214 pm->s4_val = qint_get_int(qobject_to_qint(o));
215 } else {
216 pm->s4_val = false;
217 }
218 qobject_decref(o);
219
220 /* Fill in mandatory properties */
221 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
222
223 pm->acpi_enable_cmd = object_property_get_int(obj,
224 ACPI_PM_PROP_ACPI_ENABLE_CMD,
225 NULL);
226 pm->acpi_disable_cmd = object_property_get_int(obj,
227 ACPI_PM_PROP_ACPI_DISABLE_CMD,
228 NULL);
229 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
230 NULL);
231 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
232 NULL);
233 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
234 NULL);
235 pm->pcihp_bridge_en =
236 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
237 NULL);
238 }
239
240 static void acpi_get_misc_info(AcpiMiscInfo *info)
241 {
242 info->has_hpet = hpet_find();
243 info->has_tpm = tpm_find();
244 info->pvpanic_port = pvpanic_port();
245 info->applesmc_io_base = applesmc_port();
246 }
247
248 static void acpi_get_pci_info(PcPciInfo *info)
249 {
250 Object *pci_host;
251 bool ambiguous;
252
253 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
254 g_assert(!ambiguous);
255 g_assert(pci_host);
256
257 info->w32.begin = object_property_get_int(pci_host,
258 PCI_HOST_PROP_PCI_HOLE_START,
259 NULL);
260 info->w32.end = object_property_get_int(pci_host,
261 PCI_HOST_PROP_PCI_HOLE_END,
262 NULL);
263 info->w64.begin = object_property_get_int(pci_host,
264 PCI_HOST_PROP_PCI_HOLE64_START,
265 NULL);
266 info->w64.end = object_property_get_int(pci_host,
267 PCI_HOST_PROP_PCI_HOLE64_END,
268 NULL);
269 }
270
271 #define ACPI_BUILD_APPNAME "Bochs"
272 #define ACPI_BUILD_APPNAME6 "BOCHS "
273 #define ACPI_BUILD_APPNAME4 "BXPC"
274
275 #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
276 #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
277 #define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
278
279 static void
280 build_header(GArray *linker, GArray *table_data,
281 AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
282 {
283 memcpy(&h->signature, sig, 4);
284 h->length = cpu_to_le32(len);
285 h->revision = rev;
286 memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
287 memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
288 memcpy(h->oem_table_id + 4, sig, 4);
289 h->oem_revision = cpu_to_le32(1);
290 memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
291 h->asl_compiler_revision = cpu_to_le32(1);
292 h->checksum = 0;
293 /* Checksum to be filled in by Guest linker */
294 bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
295 table_data->data, h, len, &h->checksum);
296 }
297
298 static GArray *build_alloc_method(const char *name, uint8_t arg_count)
299 {
300 GArray *method = build_alloc_array();
301
302 build_append_namestring(method, "%s", name);
303 build_append_byte(method, arg_count); /* MethodFlags: ArgCount */
304
305 return method;
306 }
307
308 static void build_append_and_cleanup_method(GArray *device, GArray *method)
309 {
310 uint8_t op = 0x14; /* MethodOp */
311
312 build_package(method, op);
313
314 build_append_array(device, method);
315 build_free_array(method);
316 }
317
318 /* End here */
319 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
320
321 static inline void *acpi_data_push(GArray *table_data, unsigned size)
322 {
323 unsigned off = table_data->len;
324 g_array_set_size(table_data, off + size);
325 return table_data->data + off;
326 }
327
328 static unsigned acpi_data_len(GArray *table)
329 {
330 #if GLIB_CHECK_VERSION(2, 22, 0)
331 assert(g_array_get_element_size(table) == 1);
332 #endif
333 return table->len;
334 }
335
336 static void acpi_align_size(GArray *blob, unsigned align)
337 {
338 /* Align size to multiple of given size. This reduces the chance
339 * we need to change size in the future (breaking cross version migration).
340 */
341 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
342 }
343
344 static inline void acpi_add_table(GArray *table_offsets, GArray *table_data)
345 {
346 uint32_t offset = cpu_to_le32(table_data->len);
347 g_array_append_val(table_offsets, offset);
348 }
349
350 /* FACS */
351 static void
352 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
353 {
354 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
355 memcpy(&facs->signature, "FACS", 4);
356 facs->length = cpu_to_le32(sizeof(*facs));
357 }
358
359 /* Load chipset information in FADT */
360 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
361 {
362 fadt->model = 1;
363 fadt->reserved1 = 0;
364 fadt->sci_int = cpu_to_le16(pm->sci_int);
365 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
366 fadt->acpi_enable = pm->acpi_enable_cmd;
367 fadt->acpi_disable = pm->acpi_disable_cmd;
368 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
369 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
370 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
371 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
372 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
373 /* EVT, CNT, TMR length matches hw/acpi/core.c */
374 fadt->pm1_evt_len = 4;
375 fadt->pm1_cnt_len = 2;
376 fadt->pm_tmr_len = 4;
377 fadt->gpe0_blk_len = pm->gpe0_blk_len;
378 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
379 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
380 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
381 (1 << ACPI_FADT_F_PROC_C1) |
382 (1 << ACPI_FADT_F_SLP_BUTTON) |
383 (1 << ACPI_FADT_F_RTC_S4));
384 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
385 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
386 * For more than 8 CPUs, "Clustered Logical" mode has to be used
387 */
388 if (max_cpus > 8) {
389 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
390 }
391 }
392
393
394 /* FADT */
395 static void
396 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
397 unsigned facs, unsigned dsdt)
398 {
399 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
400
401 fadt->firmware_ctrl = cpu_to_le32(facs);
402 /* FACS address to be filled by Guest linker */
403 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
404 ACPI_BUILD_TABLE_FILE,
405 table_data, &fadt->firmware_ctrl,
406 sizeof fadt->firmware_ctrl);
407
408 fadt->dsdt = cpu_to_le32(dsdt);
409 /* DSDT address to be filled by Guest linker */
410 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
411 ACPI_BUILD_TABLE_FILE,
412 table_data, &fadt->dsdt,
413 sizeof fadt->dsdt);
414
415 fadt_setup(fadt, pm);
416
417 build_header(linker, table_data,
418 (void *)fadt, "FACP", sizeof(*fadt), 1);
419 }
420
421 static void
422 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
423 PcGuestInfo *guest_info)
424 {
425 int madt_start = table_data->len;
426
427 AcpiMultipleApicTable *madt;
428 AcpiMadtIoApic *io_apic;
429 AcpiMadtIntsrcovr *intsrcovr;
430 AcpiMadtLocalNmi *local_nmi;
431 int i;
432
433 madt = acpi_data_push(table_data, sizeof *madt);
434 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
435 madt->flags = cpu_to_le32(1);
436
437 for (i = 0; i < guest_info->apic_id_limit; i++) {
438 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
439 apic->type = ACPI_APIC_PROCESSOR;
440 apic->length = sizeof(*apic);
441 apic->processor_id = i;
442 apic->local_apic_id = i;
443 if (test_bit(i, cpu->found_cpus)) {
444 apic->flags = cpu_to_le32(1);
445 } else {
446 apic->flags = cpu_to_le32(0);
447 }
448 }
449 io_apic = acpi_data_push(table_data, sizeof *io_apic);
450 io_apic->type = ACPI_APIC_IO;
451 io_apic->length = sizeof(*io_apic);
452 #define ACPI_BUILD_IOAPIC_ID 0x0
453 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
454 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
455 io_apic->interrupt = cpu_to_le32(0);
456
457 if (guest_info->apic_xrupt_override) {
458 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
459 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
460 intsrcovr->length = sizeof(*intsrcovr);
461 intsrcovr->source = 0;
462 intsrcovr->gsi = cpu_to_le32(2);
463 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
464 }
465 for (i = 1; i < 16; i++) {
466 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
467 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
468 /* No need for a INT source override structure. */
469 continue;
470 }
471 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
472 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
473 intsrcovr->length = sizeof(*intsrcovr);
474 intsrcovr->source = i;
475 intsrcovr->gsi = cpu_to_le32(i);
476 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
477 }
478
479 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
480 local_nmi->type = ACPI_APIC_LOCAL_NMI;
481 local_nmi->length = sizeof(*local_nmi);
482 local_nmi->processor_id = 0xff; /* all processors */
483 local_nmi->flags = cpu_to_le16(0);
484 local_nmi->lint = 1; /* ACPI_LINT1 */
485
486 build_header(linker, table_data,
487 (void *)(table_data->data + madt_start), "APIC",
488 table_data->len - madt_start, 1);
489 }
490
491 /* Encode a hex value */
492 static inline char acpi_get_hex(uint32_t val)
493 {
494 val &= 0x0f;
495 return (val <= 9) ? ('0' + val) : ('A' + val - 10);
496 }
497
498 /* 0x5B 0x82 DeviceOp PkgLength NameString */
499 #define ACPI_PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1)
500 #define ACPI_PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start)
501 #define ACPI_PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start)
502 #define ACPI_PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start)
503 #define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start)
504 #define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start)
505
506 #define ACPI_PCINOHP_OFFSET_HEX (*ssdt_pcinohp_name - *ssdt_pcinohp_start + 1)
507 #define ACPI_PCINOHP_OFFSET_ADR (*ssdt_pcinohp_adr - *ssdt_pcinohp_start)
508 #define ACPI_PCINOHP_SIZEOF (*ssdt_pcinohp_end - *ssdt_pcinohp_start)
509 #define ACPI_PCINOHP_AML (ssdp_pcihp_aml + *ssdt_pcinohp_start)
510
511 #define ACPI_PCIVGA_OFFSET_HEX (*ssdt_pcivga_name - *ssdt_pcivga_start + 1)
512 #define ACPI_PCIVGA_OFFSET_ADR (*ssdt_pcivga_adr - *ssdt_pcivga_start)
513 #define ACPI_PCIVGA_SIZEOF (*ssdt_pcivga_end - *ssdt_pcivga_start)
514 #define ACPI_PCIVGA_AML (ssdp_pcihp_aml + *ssdt_pcivga_start)
515
516 #define ACPI_PCIQXL_OFFSET_HEX (*ssdt_pciqxl_name - *ssdt_pciqxl_start + 1)
517 #define ACPI_PCIQXL_OFFSET_ADR (*ssdt_pciqxl_adr - *ssdt_pciqxl_start)
518 #define ACPI_PCIQXL_SIZEOF (*ssdt_pciqxl_end - *ssdt_pciqxl_start)
519 #define ACPI_PCIQXL_AML (ssdp_pcihp_aml + *ssdt_pciqxl_start)
520
521 #define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */
522 #define ACPI_SSDT_HEADER_LENGTH 36
523
524 #include "hw/i386/ssdt-pcihp.hex"
525 #include "hw/i386/ssdt-tpm.hex"
526
527 static void patch_pcihp(int slot, uint8_t *ssdt_ptr)
528 {
529 unsigned devfn = PCI_DEVFN(slot, 0);
530
531 ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
532 ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
533 ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot;
534 ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot;
535 }
536
537 static void patch_pcinohp(int slot, uint8_t *ssdt_ptr)
538 {
539 unsigned devfn = PCI_DEVFN(slot, 0);
540
541 ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
542 ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
543 ssdt_ptr[ACPI_PCINOHP_OFFSET_ADR + 2] = slot;
544 }
545
546 static void patch_pcivga(int slot, uint8_t *ssdt_ptr)
547 {
548 unsigned devfn = PCI_DEVFN(slot, 0);
549
550 ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
551 ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX + 1] = acpi_get_hex(devfn);
552 ssdt_ptr[ACPI_PCIVGA_OFFSET_ADR + 2] = slot;
553 }
554
555 static void patch_pciqxl(int slot, uint8_t *ssdt_ptr)
556 {
557 unsigned devfn = PCI_DEVFN(slot, 0);
558
559 ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
560 ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX + 1] = acpi_get_hex(devfn);
561 ssdt_ptr[ACPI_PCIQXL_OFFSET_ADR + 2] = slot;
562 }
563
564 /* Assign BSEL property to all buses. In the future, this can be changed
565 * to only assign to buses that support hotplug.
566 */
567 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
568 {
569 unsigned *bsel_alloc = opaque;
570 unsigned *bus_bsel;
571
572 if (qbus_is_hotpluggable(BUS(bus))) {
573 bus_bsel = g_malloc(sizeof *bus_bsel);
574
575 *bus_bsel = (*bsel_alloc)++;
576 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
577 bus_bsel, NULL);
578 }
579
580 return bsel_alloc;
581 }
582
583 static void acpi_set_pci_info(void)
584 {
585 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
586 unsigned bsel_alloc = 0;
587
588 if (bus) {
589 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
590 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
591 }
592 }
593
594 static void build_pci_bus_state_init(AcpiBuildPciBusHotplugState *state,
595 AcpiBuildPciBusHotplugState *parent,
596 bool pcihp_bridge_en)
597 {
598 state->parent = parent;
599 state->device_table = build_alloc_array();
600 state->notify_table = build_alloc_array();
601 state->pcihp_bridge_en = pcihp_bridge_en;
602 }
603
604 static void build_pci_bus_state_cleanup(AcpiBuildPciBusHotplugState *state)
605 {
606 build_free_array(state->device_table);
607 build_free_array(state->notify_table);
608 }
609
610 static void *build_pci_bus_begin(PCIBus *bus, void *parent_state)
611 {
612 AcpiBuildPciBusHotplugState *parent = parent_state;
613 AcpiBuildPciBusHotplugState *child = g_malloc(sizeof *child);
614
615 build_pci_bus_state_init(child, parent, parent->pcihp_bridge_en);
616
617 return child;
618 }
619
620 static void build_pci_bus_end(PCIBus *bus, void *bus_state)
621 {
622 AcpiBuildPciBusHotplugState *child = bus_state;
623 AcpiBuildPciBusHotplugState *parent = child->parent;
624 GArray *bus_table = build_alloc_array();
625 DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
626 DECLARE_BITMAP(slot_device_present, PCI_SLOT_MAX);
627 DECLARE_BITMAP(slot_device_system, PCI_SLOT_MAX);
628 DECLARE_BITMAP(slot_device_vga, PCI_SLOT_MAX);
629 DECLARE_BITMAP(slot_device_qxl, PCI_SLOT_MAX);
630 uint8_t op;
631 int i;
632 QObject *bsel;
633 GArray *method;
634 bool bus_hotplug_support = false;
635
636 /*
637 * Skip bridge subtree creation if bridge hotplug is disabled
638 * to make acpi tables compatible with legacy machine types.
639 * Skip creation for hotplugged bridges as well.
640 */
641 if (bus->parent_dev && (!child->pcihp_bridge_en ||
642 DEVICE(bus->parent_dev)->hotplugged)) {
643 build_free_array(bus_table);
644 build_pci_bus_state_cleanup(child);
645 g_free(child);
646 return;
647 }
648
649 if (bus->parent_dev) {
650 op = 0x82; /* DeviceOp */
651 build_append_namestring(bus_table, "S%.02X",
652 bus->parent_dev->devfn);
653 build_append_byte(bus_table, 0x08); /* NameOp */
654 build_append_namestring(bus_table, "_SUN");
655 build_append_int(bus_table, PCI_SLOT(bus->parent_dev->devfn));
656 build_append_byte(bus_table, 0x08); /* NameOp */
657 build_append_namestring(bus_table, "_ADR");
658 build_append_int(bus_table, (PCI_SLOT(bus->parent_dev->devfn) << 16) |
659 PCI_FUNC(bus->parent_dev->devfn));
660 } else {
661 op = 0x10; /* ScopeOp */;
662 build_append_namestring(bus_table, "PCI0");
663 }
664
665 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
666 if (bsel) {
667 build_append_byte(bus_table, 0x08); /* NameOp */
668 build_append_namestring(bus_table, "BSEL");
669 build_append_int(bus_table, qint_get_int(qobject_to_qint(bsel)));
670 memset(slot_hotplug_enable, 0xff, sizeof slot_hotplug_enable);
671 } else {
672 /* No bsel - no slots are hot-pluggable */
673 memset(slot_hotplug_enable, 0x00, sizeof slot_hotplug_enable);
674 }
675
676 memset(slot_device_present, 0x00, sizeof slot_device_present);
677 memset(slot_device_system, 0x00, sizeof slot_device_present);
678 memset(slot_device_vga, 0x00, sizeof slot_device_vga);
679 memset(slot_device_qxl, 0x00, sizeof slot_device_qxl);
680
681 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
682 DeviceClass *dc;
683 PCIDeviceClass *pc;
684 PCIDevice *pdev = bus->devices[i];
685 int slot = PCI_SLOT(i);
686 bool bridge_in_acpi;
687
688 if (!pdev) {
689 continue;
690 }
691
692 set_bit(slot, slot_device_present);
693 pc = PCI_DEVICE_GET_CLASS(pdev);
694 dc = DEVICE_GET_CLASS(pdev);
695
696 /* When hotplug for bridges is enabled, bridges are
697 * described in ACPI separately (see build_pci_bus_end).
698 * In this case they aren't themselves hot-pluggable.
699 * Hotplugged bridges *are* hot-pluggable.
700 */
701 bridge_in_acpi = pc->is_bridge && child->pcihp_bridge_en &&
702 !DEVICE(pdev)->hotplugged;
703
704 if (pc->class_id == PCI_CLASS_BRIDGE_ISA || bridge_in_acpi) {
705 set_bit(slot, slot_device_system);
706 }
707
708 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
709 set_bit(slot, slot_device_vga);
710
711 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
712 set_bit(slot, slot_device_qxl);
713 }
714 }
715
716 if (!dc->hotpluggable || bridge_in_acpi) {
717 clear_bit(slot, slot_hotplug_enable);
718 }
719 }
720
721 /* Append Device object for each slot */
722 for (i = 0; i < PCI_SLOT_MAX; i++) {
723 bool can_eject = test_bit(i, slot_hotplug_enable);
724 bool present = test_bit(i, slot_device_present);
725 bool vga = test_bit(i, slot_device_vga);
726 bool qxl = test_bit(i, slot_device_qxl);
727 bool system = test_bit(i, slot_device_system);
728 if (can_eject) {
729 void *pcihp = acpi_data_push(bus_table,
730 ACPI_PCIHP_SIZEOF);
731 memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
732 patch_pcihp(i, pcihp);
733 bus_hotplug_support = true;
734 } else if (qxl) {
735 void *pcihp = acpi_data_push(bus_table,
736 ACPI_PCIQXL_SIZEOF);
737 memcpy(pcihp, ACPI_PCIQXL_AML, ACPI_PCIQXL_SIZEOF);
738 patch_pciqxl(i, pcihp);
739 } else if (vga) {
740 void *pcihp = acpi_data_push(bus_table,
741 ACPI_PCIVGA_SIZEOF);
742 memcpy(pcihp, ACPI_PCIVGA_AML, ACPI_PCIVGA_SIZEOF);
743 patch_pcivga(i, pcihp);
744 } else if (system) {
745 /* Nothing to do: system devices are in DSDT or in SSDT above. */
746 } else if (present) {
747 void *pcihp = acpi_data_push(bus_table,
748 ACPI_PCINOHP_SIZEOF);
749 memcpy(pcihp, ACPI_PCINOHP_AML, ACPI_PCINOHP_SIZEOF);
750 patch_pcinohp(i, pcihp);
751 }
752 }
753
754 if (bsel) {
755 method = build_alloc_method("DVNT", 2);
756
757 for (i = 0; i < PCI_SLOT_MAX; i++) {
758 GArray *notify;
759 uint8_t op;
760
761 if (!test_bit(i, slot_hotplug_enable)) {
762 continue;
763 }
764
765 notify = build_alloc_array();
766 op = 0xA0; /* IfOp */
767
768 build_append_byte(notify, 0x7B); /* AndOp */
769 build_append_byte(notify, 0x68); /* Arg0Op */
770 build_append_int(notify, 0x1U << i);
771 build_append_byte(notify, 0x00); /* NullName */
772 build_append_byte(notify, 0x86); /* NotifyOp */
773 build_append_namestring(notify, "S%.02X", PCI_DEVFN(i, 0));
774 build_append_byte(notify, 0x69); /* Arg1Op */
775
776 /* Pack it up */
777 build_package(notify, op);
778
779 build_append_array(method, notify);
780
781 build_free_array(notify);
782 }
783
784 build_append_and_cleanup_method(bus_table, method);
785 }
786
787 /* Append PCNT method to notify about events on local and child buses.
788 * Add unconditionally for root since DSDT expects it.
789 */
790 if (bus_hotplug_support || child->notify_table->len || !bus->parent_dev) {
791 method = build_alloc_method("PCNT", 0);
792
793 /* If bus supports hotplug select it and notify about local events */
794 if (bsel) {
795 build_append_byte(method, 0x70); /* StoreOp */
796 build_append_int(method, qint_get_int(qobject_to_qint(bsel)));
797 build_append_namestring(method, "BNUM");
798 build_append_namestring(method, "DVNT");
799 build_append_namestring(method, "PCIU");
800 build_append_int(method, 1); /* Device Check */
801 build_append_namestring(method, "DVNT");
802 build_append_namestring(method, "PCID");
803 build_append_int(method, 3); /* Eject Request */
804 }
805
806 /* Notify about child bus events in any case */
807 build_append_array(method, child->notify_table);
808
809 build_append_and_cleanup_method(bus_table, method);
810
811 /* Append description of child buses */
812 build_append_array(bus_table, child->device_table);
813
814 /* Pack it up */
815 if (bus->parent_dev) {
816 build_extop_package(bus_table, op);
817 } else {
818 build_package(bus_table, op);
819 }
820
821 /* Append our bus description to parent table */
822 build_append_array(parent->device_table, bus_table);
823
824 /* Also tell parent how to notify us, invoking PCNT method.
825 * At the moment this is not needed for root as we have a single root.
826 */
827 if (bus->parent_dev) {
828 build_append_namestring(parent->notify_table, "^PCNT.S%.02X",
829 bus->parent_dev->devfn);
830 }
831 }
832
833 qobject_decref(bsel);
834 build_free_array(bus_table);
835 build_pci_bus_state_cleanup(child);
836 g_free(child);
837 }
838
839 static void
840 build_ssdt(GArray *table_data, GArray *linker,
841 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
842 PcPciInfo *pci, PcGuestInfo *guest_info)
843 {
844 MachineState *machine = MACHINE(qdev_get_machine());
845 uint32_t nr_mem = machine->ram_slots;
846 unsigned acpi_cpus = guest_info->apic_id_limit;
847 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
848 int i;
849
850 ssdt = init_aml_allocator();
851 /* The current AML generator can cover the APIC ID range [0..255],
852 * inclusive, for VCPU hotplug. */
853 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
854 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
855
856 /* Reserve space for header */
857 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
858
859 scope = aml_scope("\\_SB.PCI0");
860 /* build PCI0._CRS */
861 crs = aml_resource_template();
862 aml_append(crs,
863 aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
864 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100));
865 aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08));
866
867 aml_append(crs,
868 aml_word_io(aml_min_fixed, aml_max_fixed,
869 aml_pos_decode, aml_entire_range,
870 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
871 aml_append(crs,
872 aml_word_io(aml_min_fixed, aml_max_fixed,
873 aml_pos_decode, aml_entire_range,
874 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
875 aml_append(crs,
876 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
877 aml_cacheable, aml_ReadWrite,
878 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
879 aml_append(crs,
880 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
881 aml_non_cacheable, aml_ReadWrite,
882 0, pci->w32.begin, pci->w32.end - 1, 0,
883 pci->w32.end - pci->w32.begin));
884 if (pci->w64.begin) {
885 aml_append(crs,
886 aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
887 aml_cacheable, aml_ReadWrite,
888 0, pci->w64.begin, pci->w64.end - 1, 0,
889 pci->w64.end - pci->w64.begin));
890 }
891 aml_append(scope, aml_name_decl("_CRS", crs));
892
893 /* reserve GPE0 block resources */
894 dev = aml_device("GPE0");
895 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
896 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
897 /* device present, functioning, decoding, not shown in UI */
898 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
899 crs = aml_resource_template();
900 aml_append(crs,
901 aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
902 );
903 aml_append(dev, aml_name_decl("_CRS", crs));
904 aml_append(scope, dev);
905
906 /* reserve PCIHP resources */
907 if (pm->pcihp_io_len) {
908 dev = aml_device("PHPR");
909 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
910 aml_append(dev,
911 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
912 /* device present, functioning, decoding, not shown in UI */
913 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
914 crs = aml_resource_template();
915 aml_append(crs,
916 aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
917 pm->pcihp_io_len)
918 );
919 aml_append(dev, aml_name_decl("_CRS", crs));
920 aml_append(scope, dev);
921 }
922 aml_append(ssdt, scope);
923
924 /* create S3_ / S4_ / S5_ packages if necessary */
925 scope = aml_scope("\\");
926 if (!pm->s3_disabled) {
927 pkg = aml_package(4);
928 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
929 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
930 aml_append(pkg, aml_int(0)); /* reserved */
931 aml_append(pkg, aml_int(0)); /* reserved */
932 aml_append(scope, aml_name_decl("_S3", pkg));
933 }
934
935 if (!pm->s4_disabled) {
936 pkg = aml_package(4);
937 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
938 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
939 aml_append(pkg, aml_int(pm->s4_val));
940 aml_append(pkg, aml_int(0)); /* reserved */
941 aml_append(pkg, aml_int(0)); /* reserved */
942 aml_append(scope, aml_name_decl("_S4", pkg));
943 }
944
945 pkg = aml_package(4);
946 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
947 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
948 aml_append(pkg, aml_int(0)); /* reserved */
949 aml_append(pkg, aml_int(0)); /* reserved */
950 aml_append(scope, aml_name_decl("_S5", pkg));
951 aml_append(ssdt, scope);
952
953 if (misc->applesmc_io_base) {
954 scope = aml_scope("\\_SB.PCI0.ISA");
955 dev = aml_device("SMC");
956
957 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
958 /* device present, functioning, decoding, not shown in UI */
959 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
960
961 crs = aml_resource_template();
962 aml_append(crs,
963 aml_io(aml_decode16, misc->applesmc_io_base, misc->applesmc_io_base,
964 0x01, APPLESMC_MAX_DATA_LENGTH)
965 );
966 aml_append(crs, aml_irq_no_flags(6));
967 aml_append(dev, aml_name_decl("_CRS", crs));
968
969 aml_append(scope, dev);
970 aml_append(ssdt, scope);
971 }
972
973 if (misc->pvpanic_port) {
974 scope = aml_scope("\\_SB.PCI0.ISA");
975
976 dev = aml_device("PEVR");
977 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
978
979 crs = aml_resource_template();
980 aml_append(crs,
981 aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
982 );
983 aml_append(dev, aml_name_decl("_CRS", crs));
984
985 aml_append(dev, aml_operation_region("PEOR", aml_system_io,
986 misc->pvpanic_port, 1));
987 field = aml_field("PEOR", aml_byte_acc);
988 aml_append(field, aml_named_field("PEPT", 8));
989 aml_append(dev, field);
990
991 method = aml_method("RDPT", 0);
992 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
993 aml_append(method, aml_return(aml_local(0)));
994 aml_append(dev, method);
995
996 method = aml_method("WRPT", 1);
997 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
998 aml_append(dev, method);
999
1000 aml_append(scope, dev);
1001 aml_append(ssdt, scope);
1002 }
1003
1004 sb_scope = aml_scope("_SB");
1005 {
1006 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
1007 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
1008 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1009 aml_append(dev,
1010 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
1011 );
1012 /* device present, functioning, decoding, not shown in UI */
1013 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1014 crs = aml_resource_template();
1015 aml_append(crs,
1016 aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
1017 pm->cpu_hp_io_len)
1018 );
1019 aml_append(dev, aml_name_decl("_CRS", crs));
1020 aml_append(sb_scope, dev);
1021 /* declare CPU hotplug MMIO region and PRS field to access it */
1022 aml_append(sb_scope, aml_operation_region(
1023 "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
1024 field = aml_field("PRST", aml_byte_acc);
1025 aml_append(field, aml_named_field("PRS", 256));
1026 aml_append(sb_scope, field);
1027
1028 /* build Processor object for each processor */
1029 for (i = 0; i < acpi_cpus; i++) {
1030 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1031
1032 method = aml_method("_MAT", 0);
1033 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i))));
1034 aml_append(dev, method);
1035
1036 method = aml_method("_STA", 0);
1037 aml_append(method, aml_return(aml_call1("CPST", aml_int(i))));
1038 aml_append(dev, method);
1039
1040 method = aml_method("_EJ0", 1);
1041 aml_append(method,
1042 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0)))
1043 );
1044 aml_append(dev, method);
1045
1046 aml_append(sb_scope, dev);
1047 }
1048
1049 /* build this code:
1050 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1051 */
1052 /* Arg0 = Processor ID = APIC ID */
1053 method = aml_method("NTFY", 2);
1054 for (i = 0; i < acpi_cpus; i++) {
1055 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1056 aml_append(ifctx,
1057 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1058 );
1059 aml_append(method, ifctx);
1060 }
1061 aml_append(sb_scope, method);
1062
1063 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1064 *
1065 * Note: The ability to create variable-sized packages was first
1066 * ntroduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1067 * ith up to 255 elements. Windows guests up to win2k8 fail when
1068 * VarPackageOp is used.
1069 */
1070 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1071 aml_varpackage(acpi_cpus);
1072
1073 for (i = 0; i < acpi_cpus; i++) {
1074 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1075 aml_append(pkg, aml_int(b));
1076 }
1077 aml_append(sb_scope, aml_name_decl("CPON", pkg));
1078
1079 /* build memory devices */
1080 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1081 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE));
1082 aml_append(scope,
1083 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem))
1084 );
1085
1086 crs = aml_resource_template();
1087 aml_append(crs,
1088 aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
1089 pm->mem_hp_io_len)
1090 );
1091 aml_append(scope, aml_name_decl("_CRS", crs));
1092
1093 aml_append(scope, aml_operation_region(
1094 stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io,
1095 pm->mem_hp_io_base, pm->mem_hp_io_len)
1096 );
1097
1098 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc);
1099 aml_append(field, /* read only */
1100 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
1101 aml_append(field, /* read only */
1102 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32));
1103 aml_append(field, /* read only */
1104 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32));
1105 aml_append(field, /* read only */
1106 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32));
1107 aml_append(field, /* read only */
1108 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32));
1109 aml_append(scope, field);
1110
1111 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc);
1112 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1113 aml_append(field, /* 1 if enabled, read only */
1114 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
1115 aml_append(field,
1116 /*(read) 1 if has a insert event. (write) 1 to clear event */
1117 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1));
1118 aml_append(scope, field);
1119
1120 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc);
1121 aml_append(field, /* DIMM selector, write only */
1122 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
1123 aml_append(field, /* _OST event code, write only */
1124 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32));
1125 aml_append(field, /* _OST status code, write only */
1126 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32));
1127 aml_append(scope, field);
1128
1129 aml_append(sb_scope, scope);
1130
1131 for (i = 0; i < nr_mem; i++) {
1132 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
1133 const char *s;
1134
1135 dev = aml_device("MP%02X", i);
1136 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1137 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1138
1139 method = aml_method("_CRS", 0);
1140 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD);
1141 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1142 aml_append(dev, method);
1143
1144 method = aml_method("_STA", 0);
1145 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD);
1146 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1147 aml_append(dev, method);
1148
1149 method = aml_method("_PXM", 0);
1150 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD);
1151 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1152 aml_append(dev, method);
1153
1154 method = aml_method("_OST", 3);
1155 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD);
1156 aml_append(method, aml_return(aml_call4(
1157 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1158 )));
1159 aml_append(dev, method);
1160
1161 aml_append(sb_scope, dev);
1162 }
1163
1164 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1165 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ...
1166 */
1167 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2);
1168 for (i = 0; i < nr_mem; i++) {
1169 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1170 aml_append(ifctx,
1171 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1172 );
1173 aml_append(method, ifctx);
1174 }
1175 aml_append(sb_scope, method);
1176
1177 {
1178 AcpiBuildPciBusHotplugState hotplug_state;
1179 Object *pci_host;
1180 PCIBus *bus = NULL;
1181 bool ambiguous;
1182
1183 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1184 if (!ambiguous && pci_host) {
1185 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1186 }
1187
1188 build_pci_bus_state_init(&hotplug_state, NULL, pm->pcihp_bridge_en);
1189
1190 if (bus) {
1191 /* Scan all PCI buses. Generate tables to support hotplug. */
1192 pci_for_each_bus_depth_first(bus, build_pci_bus_begin,
1193 build_pci_bus_end, &hotplug_state);
1194 }
1195
1196 build_append_array(sb_scope->buf, hotplug_state.device_table);
1197 build_pci_bus_state_cleanup(&hotplug_state);
1198 }
1199 aml_append(ssdt, sb_scope);
1200 }
1201
1202 /* copy AML table into ACPI tables blob and patch header there */
1203 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1204 build_header(linker, table_data,
1205 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1206 "SSDT", ssdt->buf->len, 1);
1207 free_aml_allocator();
1208 }
1209
1210 static void
1211 build_hpet(GArray *table_data, GArray *linker)
1212 {
1213 Acpi20Hpet *hpet;
1214
1215 hpet = acpi_data_push(table_data, sizeof(*hpet));
1216 /* Note timer_block_id value must be kept in sync with value advertised by
1217 * emulated hpet
1218 */
1219 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1220 hpet->addr.address = cpu_to_le64(HPET_BASE);
1221 build_header(linker, table_data,
1222 (void *)hpet, "HPET", sizeof(*hpet), 1);
1223 }
1224
1225 static void
1226 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1227 {
1228 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1229 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1230
1231 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1232 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1233 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1234
1235 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1236 false /* high memory */);
1237
1238 /* log area start address to be filled by Guest linker */
1239 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1240 ACPI_BUILD_TPMLOG_FILE,
1241 table_data, &tcpa->log_area_start_address,
1242 sizeof(tcpa->log_area_start_address));
1243
1244 build_header(linker, table_data,
1245 (void *)tcpa, "TCPA", sizeof(*tcpa), 2);
1246
1247 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1248 }
1249
1250 static void
1251 build_tpm_ssdt(GArray *table_data, GArray *linker)
1252 {
1253 void *tpm_ptr;
1254
1255 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml));
1256 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml));
1257 }
1258
1259 typedef enum {
1260 MEM_AFFINITY_NOFLAGS = 0,
1261 MEM_AFFINITY_ENABLED = (1 << 0),
1262 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1263 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1264 } MemoryAffinityFlags;
1265
1266 static void
1267 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1268 uint64_t len, int node, MemoryAffinityFlags flags)
1269 {
1270 numamem->type = ACPI_SRAT_MEMORY;
1271 numamem->length = sizeof(*numamem);
1272 memset(numamem->proximity, 0, 4);
1273 numamem->proximity[0] = node;
1274 numamem->flags = cpu_to_le32(flags);
1275 numamem->base_addr = cpu_to_le64(base);
1276 numamem->range_length = cpu_to_le64(len);
1277 }
1278
1279 static void
1280 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1281 {
1282 AcpiSystemResourceAffinityTable *srat;
1283 AcpiSratProcessorAffinity *core;
1284 AcpiSratMemoryAffinity *numamem;
1285
1286 int i;
1287 uint64_t curnode;
1288 int srat_start, numa_start, slots;
1289 uint64_t mem_len, mem_base, next_base;
1290 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1291 ram_addr_t hotplugabble_address_space_size =
1292 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1293 NULL);
1294
1295 srat_start = table_data->len;
1296
1297 srat = acpi_data_push(table_data, sizeof *srat);
1298 srat->reserved1 = cpu_to_le32(1);
1299 core = (void *)(srat + 1);
1300
1301 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1302 core = acpi_data_push(table_data, sizeof *core);
1303 core->type = ACPI_SRAT_PROCESSOR;
1304 core->length = sizeof(*core);
1305 core->local_apic_id = i;
1306 curnode = guest_info->node_cpu[i];
1307 core->proximity_lo = curnode;
1308 memset(core->proximity_hi, 0, 3);
1309 core->local_sapic_eid = 0;
1310 core->flags = cpu_to_le32(1);
1311 }
1312
1313
1314 /* the memory map is a bit tricky, it contains at least one hole
1315 * from 640k-1M and possibly another one from 3.5G-4G.
1316 */
1317 next_base = 0;
1318 numa_start = table_data->len;
1319
1320 numamem = acpi_data_push(table_data, sizeof *numamem);
1321 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
1322 next_base = 1024 * 1024;
1323 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
1324 mem_base = next_base;
1325 mem_len = guest_info->node_mem[i - 1];
1326 if (i == 1) {
1327 mem_len -= 1024 * 1024;
1328 }
1329 next_base = mem_base + mem_len;
1330
1331 /* Cut out the ACPI_PCI hole */
1332 if (mem_base <= guest_info->ram_size_below_4g &&
1333 next_base > guest_info->ram_size_below_4g) {
1334 mem_len -= next_base - guest_info->ram_size_below_4g;
1335 if (mem_len > 0) {
1336 numamem = acpi_data_push(table_data, sizeof *numamem);
1337 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1338 MEM_AFFINITY_ENABLED);
1339 }
1340 mem_base = 1ULL << 32;
1341 mem_len = next_base - guest_info->ram_size_below_4g;
1342 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
1343 }
1344 numamem = acpi_data_push(table_data, sizeof *numamem);
1345 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1346 MEM_AFFINITY_ENABLED);
1347 }
1348 slots = (table_data->len - numa_start) / sizeof *numamem;
1349 for (; slots < guest_info->numa_nodes + 2; slots++) {
1350 numamem = acpi_data_push(table_data, sizeof *numamem);
1351 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1352 }
1353
1354 /*
1355 * Entry is required for Windows to enable memory hotplug in OS.
1356 * Memory devices may override proximity set by this entry,
1357 * providing _PXM method if necessary.
1358 */
1359 if (hotplugabble_address_space_size) {
1360 numamem = acpi_data_push(table_data, sizeof *numamem);
1361 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base,
1362 hotplugabble_address_space_size, 0,
1363 MEM_AFFINITY_HOTPLUGGABLE |
1364 MEM_AFFINITY_ENABLED);
1365 }
1366
1367 build_header(linker, table_data,
1368 (void *)(table_data->data + srat_start),
1369 "SRAT",
1370 table_data->len - srat_start, 1);
1371 }
1372
1373 static void
1374 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
1375 {
1376 AcpiTableMcfg *mcfg;
1377 const char *sig;
1378 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
1379
1380 mcfg = acpi_data_push(table_data, len);
1381 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
1382 /* Only a single allocation so no need to play with segments */
1383 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
1384 mcfg->allocation[0].start_bus_number = 0;
1385 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
1386
1387 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1388 * To avoid table size changes (which create migration issues),
1389 * always create the table even if there are no allocations,
1390 * but set the signature to a reserved value in this case.
1391 * ACPI spec requires OSPMs to ignore such tables.
1392 */
1393 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
1394 /* Reserved signature: ignored by OSPM */
1395 sig = "QEMU";
1396 } else {
1397 sig = "MCFG";
1398 }
1399 build_header(linker, table_data, (void *)mcfg, sig, len, 1);
1400 }
1401
1402 static void
1403 build_dmar_q35(GArray *table_data, GArray *linker)
1404 {
1405 int dmar_start = table_data->len;
1406
1407 AcpiTableDmar *dmar;
1408 AcpiDmarHardwareUnit *drhd;
1409
1410 dmar = acpi_data_push(table_data, sizeof(*dmar));
1411 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
1412 dmar->flags = 0; /* No intr_remap for now */
1413
1414 /* DMAR Remapping Hardware Unit Definition structure */
1415 drhd = acpi_data_push(table_data, sizeof(*drhd));
1416 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1417 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
1418 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1419 drhd->pci_segment = cpu_to_le16(0);
1420 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1421
1422 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1423 "DMAR", table_data->len - dmar_start, 1);
1424 }
1425
1426 static void
1427 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
1428 {
1429 AcpiTableHeader *dsdt;
1430
1431 assert(misc->dsdt_code && misc->dsdt_size);
1432
1433 dsdt = acpi_data_push(table_data, misc->dsdt_size);
1434 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
1435
1436 memset(dsdt, 0, sizeof *dsdt);
1437 build_header(linker, table_data, dsdt, "DSDT",
1438 misc->dsdt_size, 1);
1439 }
1440
1441 /* Build final rsdt table */
1442 static void
1443 build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
1444 {
1445 AcpiRsdtDescriptorRev1 *rsdt;
1446 size_t rsdt_len;
1447 int i;
1448
1449 rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
1450 rsdt = acpi_data_push(table_data, rsdt_len);
1451 memcpy(rsdt->table_offset_entry, table_offsets->data,
1452 sizeof(uint32_t) * table_offsets->len);
1453 for (i = 0; i < table_offsets->len; ++i) {
1454 /* rsdt->table_offset_entry to be filled by Guest linker */
1455 bios_linker_loader_add_pointer(linker,
1456 ACPI_BUILD_TABLE_FILE,
1457 ACPI_BUILD_TABLE_FILE,
1458 table_data, &rsdt->table_offset_entry[i],
1459 sizeof(uint32_t));
1460 }
1461 build_header(linker, table_data,
1462 (void *)rsdt, "RSDT", rsdt_len, 1);
1463 }
1464
1465 static GArray *
1466 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
1467 {
1468 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
1469
1470 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
1471 true /* fseg memory */);
1472
1473 memcpy(&rsdp->signature, "RSD PTR ", 8);
1474 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
1475 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
1476 /* Address to be filled by Guest linker */
1477 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
1478 ACPI_BUILD_TABLE_FILE,
1479 rsdp_table, &rsdp->rsdt_physical_address,
1480 sizeof rsdp->rsdt_physical_address);
1481 rsdp->checksum = 0;
1482 /* Checksum to be filled by Guest linker */
1483 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
1484 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
1485
1486 return rsdp_table;
1487 }
1488
1489 typedef
1490 struct AcpiBuildTables {
1491 GArray *table_data;
1492 GArray *rsdp;
1493 GArray *tcpalog;
1494 GArray *linker;
1495 } AcpiBuildTables;
1496
1497 static inline void acpi_build_tables_init(AcpiBuildTables *tables)
1498 {
1499 tables->rsdp = g_array_new(false, true /* clear */, 1);
1500 tables->table_data = g_array_new(false, true /* clear */, 1);
1501 tables->tcpalog = g_array_new(false, true /* clear */, 1);
1502 tables->linker = bios_linker_loader_init();
1503 }
1504
1505 static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
1506 {
1507 void *linker_data = bios_linker_loader_cleanup(tables->linker);
1508 g_free(linker_data);
1509 g_array_free(tables->rsdp, true);
1510 g_array_free(tables->table_data, true);
1511 g_array_free(tables->tcpalog, mfre);
1512 }
1513
1514 typedef
1515 struct AcpiBuildState {
1516 /* Copy of table in RAM (for patching). */
1517 ram_addr_t table_ram;
1518 /* Is table patched? */
1519 uint8_t patched;
1520 PcGuestInfo *guest_info;
1521 void *rsdp;
1522 ram_addr_t rsdp_ram;
1523 ram_addr_t linker_ram;
1524 } AcpiBuildState;
1525
1526 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1527 {
1528 Object *pci_host;
1529 QObject *o;
1530 bool ambiguous;
1531
1532 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1533 g_assert(!ambiguous);
1534 g_assert(pci_host);
1535
1536 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1537 if (!o) {
1538 return false;
1539 }
1540 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
1541 qobject_decref(o);
1542
1543 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
1544 assert(o);
1545 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
1546 qobject_decref(o);
1547 return true;
1548 }
1549
1550 static bool acpi_has_iommu(void)
1551 {
1552 bool ambiguous;
1553 Object *intel_iommu;
1554
1555 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
1556 &ambiguous);
1557 return intel_iommu && !ambiguous;
1558 }
1559
1560 static
1561 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
1562 {
1563 GArray *table_offsets;
1564 unsigned facs, ssdt, dsdt, rsdt;
1565 AcpiCpuInfo cpu;
1566 AcpiPmInfo pm;
1567 AcpiMiscInfo misc;
1568 AcpiMcfgInfo mcfg;
1569 PcPciInfo pci;
1570 uint8_t *u;
1571 size_t aml_len = 0;
1572 GArray *tables_blob = tables->table_data;
1573
1574 acpi_get_cpu_info(&cpu);
1575 acpi_get_pm_info(&pm);
1576 acpi_get_dsdt(&misc);
1577 acpi_get_misc_info(&misc);
1578 acpi_get_pci_info(&pci);
1579
1580 table_offsets = g_array_new(false, true /* clear */,
1581 sizeof(uint32_t));
1582 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1583
1584 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
1585 64 /* Ensure FACS is aligned */,
1586 false /* high memory */);
1587
1588 /*
1589 * FACS is pointed to by FADT.
1590 * We place it first since it's the only table that has alignment
1591 * requirements.
1592 */
1593 facs = tables_blob->len;
1594 build_facs(tables_blob, tables->linker, guest_info);
1595
1596 /* DSDT is pointed to by FADT */
1597 dsdt = tables_blob->len;
1598 build_dsdt(tables_blob, tables->linker, &misc);
1599
1600 /* Count the size of the DSDT and SSDT, we will need it for legacy
1601 * sizing of ACPI tables.
1602 */
1603 aml_len += tables_blob->len - dsdt;
1604
1605 /* ACPI tables pointed to by RSDT */
1606 acpi_add_table(table_offsets, tables_blob);
1607 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
1608
1609 ssdt = tables_blob->len;
1610 acpi_add_table(table_offsets, tables_blob);
1611 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
1612 guest_info);
1613 aml_len += tables_blob->len - ssdt;
1614
1615 acpi_add_table(table_offsets, tables_blob);
1616 build_madt(tables_blob, tables->linker, &cpu, guest_info);
1617
1618 if (misc.has_hpet) {
1619 acpi_add_table(table_offsets, tables_blob);
1620 build_hpet(tables_blob, tables->linker);
1621 }
1622 if (misc.has_tpm) {
1623 acpi_add_table(table_offsets, tables_blob);
1624 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
1625
1626 acpi_add_table(table_offsets, tables_blob);
1627 build_tpm_ssdt(tables_blob, tables->linker);
1628 }
1629 if (guest_info->numa_nodes) {
1630 acpi_add_table(table_offsets, tables_blob);
1631 build_srat(tables_blob, tables->linker, guest_info);
1632 }
1633 if (acpi_get_mcfg(&mcfg)) {
1634 acpi_add_table(table_offsets, tables_blob);
1635 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
1636 }
1637 if (acpi_has_iommu()) {
1638 acpi_add_table(table_offsets, tables_blob);
1639 build_dmar_q35(tables_blob, tables->linker);
1640 }
1641
1642 /* Add tables supplied by user (if any) */
1643 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
1644 unsigned len = acpi_table_len(u);
1645
1646 acpi_add_table(table_offsets, tables_blob);
1647 g_array_append_vals(tables_blob, u, len);
1648 }
1649
1650 /* RSDT is pointed to by RSDP */
1651 rsdt = tables_blob->len;
1652 build_rsdt(tables_blob, tables->linker, table_offsets);
1653
1654 /* RSDP is in FSEG memory, so allocate it separately */
1655 build_rsdp(tables->rsdp, tables->linker, rsdt);
1656
1657 /* We'll expose it all to Guest so we want to reduce
1658 * chance of size changes.
1659 *
1660 * We used to align the tables to 4k, but of course this would
1661 * too simple to be enough. 4k turned out to be too small an
1662 * alignment very soon, and in fact it is almost impossible to
1663 * keep the table size stable for all (max_cpus, max_memory_slots)
1664 * combinations. So the table size is always 64k for pc-i440fx-2.1
1665 * and we give an error if the table grows beyond that limit.
1666 *
1667 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1668 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1669 * than 2.0 and we can always pad the smaller tables with zeros. We can
1670 * then use the exact size of the 2.0 tables.
1671 *
1672 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1673 */
1674 if (guest_info->legacy_acpi_table_size) {
1675 /* Subtracting aml_len gives the size of fixed tables. Then add the
1676 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1677 */
1678 int legacy_aml_len =
1679 guest_info->legacy_acpi_table_size +
1680 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
1681 int legacy_table_size =
1682 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
1683 ACPI_BUILD_ALIGN_SIZE);
1684 if (tables_blob->len > legacy_table_size) {
1685 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1686 error_report("Warning: migration may not work.");
1687 }
1688 g_array_set_size(tables_blob, legacy_table_size);
1689 } else {
1690 /* Make sure we have a buffer in case we need to resize the tables. */
1691 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1692 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1693 error_report("Warning: ACPI tables are larger than 64k.");
1694 error_report("Warning: migration may not work.");
1695 error_report("Warning: please remove CPUs, NUMA nodes, "
1696 "memory slots or PCI bridges.");
1697 }
1698 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1699 }
1700
1701 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
1702
1703 /* Cleanup memory that's no longer used. */
1704 g_array_free(table_offsets, true);
1705 }
1706
1707 static void acpi_ram_update(ram_addr_t ram, GArray *data)
1708 {
1709 uint32_t size = acpi_data_len(data);
1710
1711 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1712 qemu_ram_resize(ram, size, &error_abort);
1713
1714 memcpy(qemu_get_ram_ptr(ram), data->data, size);
1715 cpu_physical_memory_set_dirty_range_nocode(ram, size);
1716 }
1717
1718 static void acpi_build_update(void *build_opaque, uint32_t offset)
1719 {
1720 AcpiBuildState *build_state = build_opaque;
1721 AcpiBuildTables tables;
1722
1723 /* No state to update or already patched? Nothing to do. */
1724 if (!build_state || build_state->patched) {
1725 return;
1726 }
1727 build_state->patched = 1;
1728
1729 acpi_build_tables_init(&tables);
1730
1731 acpi_build(build_state->guest_info, &tables);
1732
1733 acpi_ram_update(build_state->table_ram, tables.table_data);
1734
1735 if (build_state->rsdp) {
1736 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
1737 } else {
1738 acpi_ram_update(build_state->rsdp_ram, tables.rsdp);
1739 }
1740
1741 acpi_ram_update(build_state->linker_ram, tables.linker);
1742 acpi_build_tables_cleanup(&tables, true);
1743 }
1744
1745 static void acpi_build_reset(void *build_opaque)
1746 {
1747 AcpiBuildState *build_state = build_opaque;
1748 build_state->patched = 0;
1749 }
1750
1751 static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob,
1752 const char *name, uint64_t max_size)
1753 {
1754 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
1755 name, acpi_build_update, build_state);
1756 }
1757
1758 static const VMStateDescription vmstate_acpi_build = {
1759 .name = "acpi_build",
1760 .version_id = 1,
1761 .minimum_version_id = 1,
1762 .fields = (VMStateField[]) {
1763 VMSTATE_UINT8(patched, AcpiBuildState),
1764 VMSTATE_END_OF_LIST()
1765 },
1766 };
1767
1768 void acpi_setup(PcGuestInfo *guest_info)
1769 {
1770 AcpiBuildTables tables;
1771 AcpiBuildState *build_state;
1772
1773 if (!guest_info->fw_cfg) {
1774 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1775 return;
1776 }
1777
1778 if (!guest_info->has_acpi_build) {
1779 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1780 return;
1781 }
1782
1783 if (!acpi_enabled) {
1784 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1785 return;
1786 }
1787
1788 build_state = g_malloc0(sizeof *build_state);
1789
1790 build_state->guest_info = guest_info;
1791
1792 acpi_set_pci_info();
1793
1794 acpi_build_tables_init(&tables);
1795 acpi_build(build_state->guest_info, &tables);
1796
1797 /* Now expose it all to Guest */
1798 build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data,
1799 ACPI_BUILD_TABLE_FILE,
1800 ACPI_BUILD_TABLE_MAX_SIZE);
1801 assert(build_state->table_ram != RAM_ADDR_MAX);
1802
1803 build_state->linker_ram =
1804 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
1805
1806 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
1807 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
1808
1809 if (!guest_info->rsdp_in_ram) {
1810 /*
1811 * Keep for compatibility with old machine types.
1812 * Though RSDP is small, its contents isn't immutable, so
1813 * we'll update it along with the rest of tables on guest access.
1814 */
1815 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
1816
1817 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
1818 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
1819 acpi_build_update, build_state,
1820 build_state->rsdp, rsdp_size);
1821 build_state->rsdp_ram = (ram_addr_t)-1;
1822 } else {
1823 build_state->rsdp = NULL;
1824 build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp,
1825 ACPI_BUILD_RSDP_FILE, 0);
1826 }
1827
1828 qemu_register_reset(acpi_build_reset, build_state);
1829 acpi_build_reset(build_state);
1830 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
1831
1832 /* Cleanup tables but don't free the memory: we track it
1833 * in build_state.
1834 */
1835 acpi_build_tables_cleanup(&tables, false);
1836 }
CRIS target port of Qemu