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vhost-user: unit test for new messages
[qemu/cris-port.git] / target-i386 / kvm.c
blob7b0ba179cc8af31ebe67530e3becbb86e18bf1f7
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm_int.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include "standard-headers/asm-x86/hyperv.h"
37 #include "hw/pci/pci.h"
38 #include "migration/migration.h"
39 #include "exec/memattrs.h"
40
41 //#define DEBUG_KVM
42
43 #ifdef DEBUG_KVM
44 #define DPRINTF(fmt, ...) \
45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
46 #else
47 #define DPRINTF(fmt, ...) \
48 do { } while (0)
49 #endif
50
51 #define MSR_KVM_WALL_CLOCK 0x11
52 #define MSR_KVM_SYSTEM_TIME 0x12
53
54 #ifndef BUS_MCEERR_AR
55 #define BUS_MCEERR_AR 4
56 #endif
57 #ifndef BUS_MCEERR_AO
58 #define BUS_MCEERR_AO 5
59 #endif
60
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_INFO(SET_TSS_ADDR),
63 KVM_CAP_INFO(EXT_CPUID),
64 KVM_CAP_INFO(MP_STATE),
65 KVM_CAP_LAST_INFO
66 };
67
68 static bool has_msr_star;
69 static bool has_msr_hsave_pa;
70 static bool has_msr_tsc_adjust;
71 static bool has_msr_tsc_deadline;
72 static bool has_msr_feature_control;
73 static bool has_msr_async_pf_en;
74 static bool has_msr_pv_eoi_en;
75 static bool has_msr_misc_enable;
76 static bool has_msr_smbase;
77 static bool has_msr_bndcfgs;
78 static bool has_msr_kvm_steal_time;
79 static int lm_capable_kernel;
80 static bool has_msr_hv_hypercall;
81 static bool has_msr_hv_vapic;
82 static bool has_msr_hv_tsc;
83 static bool has_msr_hv_crash;
84 static bool has_msr_mtrr;
85 static bool has_msr_xss;
86
87 static bool has_msr_architectural_pmu;
88 static uint32_t num_architectural_pmu_counters;
89
90 bool kvm_has_smm(void)
91 {
92 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
93 }
94
95 bool kvm_allows_irq0_override(void)
96 {
97 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
98 }
99
100 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
101 {
102 struct kvm_cpuid2 *cpuid;
103 int r, size;
104
105 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
106 cpuid = g_malloc0(size);
107 cpuid->nent = max;
108 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
109 if (r == 0 && cpuid->nent >= max) {
110 r = -E2BIG;
111 }
112 if (r < 0) {
113 if (r == -E2BIG) {
114 g_free(cpuid);
115 return NULL;
116 } else {
117 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
118 strerror(-r));
119 exit(1);
120 }
121 }
122 return cpuid;
123 }
124
125 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
126 * for all entries.
127 */
128 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
129 {
130 struct kvm_cpuid2 *cpuid;
131 int max = 1;
132 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
133 max *= 2;
134 }
135 return cpuid;
136 }
137
138 static const struct kvm_para_features {
139 int cap;
140 int feature;
141 } para_features[] = {
142 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
143 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
144 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
145 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
146 };
147
148 static int get_para_features(KVMState *s)
149 {
150 int i, features = 0;
151
152 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
153 if (kvm_check_extension(s, para_features[i].cap)) {
154 features |= (1 << para_features[i].feature);
155 }
156 }
157
158 return features;
159 }
160
161
162 /* Returns the value for a specific register on the cpuid entry
163 */
164 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
165 {
166 uint32_t ret = 0;
167 switch (reg) {
168 case R_EAX:
169 ret = entry->eax;
170 break;
171 case R_EBX:
172 ret = entry->ebx;
173 break;
174 case R_ECX:
175 ret = entry->ecx;
176 break;
177 case R_EDX:
178 ret = entry->edx;
179 break;
180 }
181 return ret;
182 }
183
184 /* Find matching entry for function/index on kvm_cpuid2 struct
185 */
186 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
187 uint32_t function,
188 uint32_t index)
189 {
190 int i;
191 for (i = 0; i < cpuid->nent; ++i) {
192 if (cpuid->entries[i].function == function &&
193 cpuid->entries[i].index == index) {
194 return &cpuid->entries[i];
195 }
196 }
197 /* not found: */
198 return NULL;
199 }
200
201 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
202 uint32_t index, int reg)
203 {
204 struct kvm_cpuid2 *cpuid;
205 uint32_t ret = 0;
206 uint32_t cpuid_1_edx;
207 bool found = false;
208
209 cpuid = get_supported_cpuid(s);
210
211 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
212 if (entry) {
213 found = true;
214 ret = cpuid_entry_get_reg(entry, reg);
215 }
216
217 /* Fixups for the data returned by KVM, below */
218
219 if (function == 1 && reg == R_EDX) {
220 /* KVM before 2.6.30 misreports the following features */
221 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
222 } else if (function == 1 && reg == R_ECX) {
223 /* We can set the hypervisor flag, even if KVM does not return it on
224 * GET_SUPPORTED_CPUID
225 */
226 ret |= CPUID_EXT_HYPERVISOR;
227 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
228 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
229 * and the irqchip is in the kernel.
230 */
231 if (kvm_irqchip_in_kernel() &&
232 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
233 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
234 }
235
236 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
237 * without the in-kernel irqchip
238 */
239 if (!kvm_irqchip_in_kernel()) {
240 ret &= ~CPUID_EXT_X2APIC;
241 }
242 } else if (function == 6 && reg == R_EAX) {
243 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
244 } else if (function == 0x80000001 && reg == R_EDX) {
245 /* On Intel, kvm returns cpuid according to the Intel spec,
246 * so add missing bits according to the AMD spec:
247 */
248 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
249 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
250 }
251
252 g_free(cpuid);
253
254 /* fallback for older kernels */
255 if ((function == KVM_CPUID_FEATURES) && !found) {
256 ret = get_para_features(s);
257 }
258
259 return ret;
260 }
261
262 typedef struct HWPoisonPage {
263 ram_addr_t ram_addr;
264 QLIST_ENTRY(HWPoisonPage) list;
265 } HWPoisonPage;
266
267 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
268 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
269
270 static void kvm_unpoison_all(void *param)
271 {
272 HWPoisonPage *page, *next_page;
273
274 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
275 QLIST_REMOVE(page, list);
276 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
277 g_free(page);
278 }
279 }
280
281 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
282 {
283 HWPoisonPage *page;
284
285 QLIST_FOREACH(page, &hwpoison_page_list, list) {
286 if (page->ram_addr == ram_addr) {
287 return;
288 }
289 }
290 page = g_new(HWPoisonPage, 1);
291 page->ram_addr = ram_addr;
292 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
293 }
294
295 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
296 int *max_banks)
297 {
298 int r;
299
300 r = kvm_check_extension(s, KVM_CAP_MCE);
301 if (r > 0) {
302 *max_banks = r;
303 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
304 }
305 return -ENOSYS;
306 }
307
308 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
309 {
310 CPUX86State *env = &cpu->env;
311 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
312 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
313 uint64_t mcg_status = MCG_STATUS_MCIP;
314
315 if (code == BUS_MCEERR_AR) {
316 status |= MCI_STATUS_AR | 0x134;
317 mcg_status |= MCG_STATUS_EIPV;
318 } else {
319 status |= 0xc0;
320 mcg_status |= MCG_STATUS_RIPV;
321 }
322 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
323 (MCM_ADDR_PHYS << 6) | 0xc,
324 cpu_x86_support_mca_broadcast(env) ?
325 MCE_INJECT_BROADCAST : 0);
326 }
327
328 static void hardware_memory_error(void)
329 {
330 fprintf(stderr, "Hardware memory error!\n");
331 exit(1);
332 }
333
334 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
335 {
336 X86CPU *cpu = X86_CPU(c);
337 CPUX86State *env = &cpu->env;
338 ram_addr_t ram_addr;
339 hwaddr paddr;
340
341 if ((env->mcg_cap & MCG_SER_P) && addr
342 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
343 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
344 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
345 fprintf(stderr, "Hardware memory error for memory used by "
346 "QEMU itself instead of guest system!\n");
347 /* Hope we are lucky for AO MCE */
348 if (code == BUS_MCEERR_AO) {
349 return 0;
350 } else {
351 hardware_memory_error();
352 }
353 }
354 kvm_hwpoison_page_add(ram_addr);
355 kvm_mce_inject(cpu, paddr, code);
356 } else {
357 if (code == BUS_MCEERR_AO) {
358 return 0;
359 } else if (code == BUS_MCEERR_AR) {
360 hardware_memory_error();
361 } else {
362 return 1;
363 }
364 }
365 return 0;
366 }
367
368 int kvm_arch_on_sigbus(int code, void *addr)
369 {
370 X86CPU *cpu = X86_CPU(first_cpu);
371
372 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
373 ram_addr_t ram_addr;
374 hwaddr paddr;
375
376 /* Hope we are lucky for AO MCE */
377 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
378 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
379 addr, &paddr)) {
380 fprintf(stderr, "Hardware memory error for memory used by "
381 "QEMU itself instead of guest system!: %p\n", addr);
382 return 0;
383 }
384 kvm_hwpoison_page_add(ram_addr);
385 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
386 } else {
387 if (code == BUS_MCEERR_AO) {
388 return 0;
389 } else if (code == BUS_MCEERR_AR) {
390 hardware_memory_error();
391 } else {
392 return 1;
393 }
394 }
395 return 0;
396 }
397
398 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
399 {
400 CPUX86State *env = &cpu->env;
401
402 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
403 unsigned int bank, bank_num = env->mcg_cap & 0xff;
404 struct kvm_x86_mce mce;
405
406 env->exception_injected = -1;
407
408 /*
409 * There must be at least one bank in use if an MCE is pending.
410 * Find it and use its values for the event injection.
411 */
412 for (bank = 0; bank < bank_num; bank++) {
413 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
414 break;
415 }
416 }
417 assert(bank < bank_num);
418
419 mce.bank = bank;
420 mce.status = env->mce_banks[bank * 4 + 1];
421 mce.mcg_status = env->mcg_status;
422 mce.addr = env->mce_banks[bank * 4 + 2];
423 mce.misc = env->mce_banks[bank * 4 + 3];
424
425 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
426 }
427 return 0;
428 }
429
430 static void cpu_update_state(void *opaque, int running, RunState state)
431 {
432 CPUX86State *env = opaque;
433
434 if (running) {
435 env->tsc_valid = false;
436 }
437 }
438
439 unsigned long kvm_arch_vcpu_id(CPUState *cs)
440 {
441 X86CPU *cpu = X86_CPU(cs);
442 return cpu->apic_id;
443 }
444
445 #ifndef KVM_CPUID_SIGNATURE_NEXT
446 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
447 #endif
448
449 static bool hyperv_hypercall_available(X86CPU *cpu)
450 {
451 return cpu->hyperv_vapic ||
452 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
453 }
454
455 static bool hyperv_enabled(X86CPU *cpu)
456 {
457 CPUState *cs = CPU(cpu);
458 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
459 (hyperv_hypercall_available(cpu) ||
460 cpu->hyperv_time ||
461 cpu->hyperv_relaxed_timing ||
462 cpu->hyperv_crash);
463 }
464
465 static Error *invtsc_mig_blocker;
466
467 #define KVM_MAX_CPUID_ENTRIES 100
468
469 int kvm_arch_init_vcpu(CPUState *cs)
470 {
471 struct {
472 struct kvm_cpuid2 cpuid;
473 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
474 } QEMU_PACKED cpuid_data;
475 X86CPU *cpu = X86_CPU(cs);
476 CPUX86State *env = &cpu->env;
477 uint32_t limit, i, j, cpuid_i;
478 uint32_t unused;
479 struct kvm_cpuid_entry2 *c;
480 uint32_t signature[3];
481 int kvm_base = KVM_CPUID_SIGNATURE;
482 int r;
483
484 memset(&cpuid_data, 0, sizeof(cpuid_data));
485
486 cpuid_i = 0;
487
488 /* Paravirtualization CPUIDs */
489 if (hyperv_enabled(cpu)) {
490 c = &cpuid_data.entries[cpuid_i++];
491 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
492 memcpy(signature, "Microsoft Hv", 12);
493 c->eax = HYPERV_CPUID_MIN;
494 c->ebx = signature[0];
495 c->ecx = signature[1];
496 c->edx = signature[2];
497
498 c = &cpuid_data.entries[cpuid_i++];
499 c->function = HYPERV_CPUID_INTERFACE;
500 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
501 c->eax = signature[0];
502 c->ebx = 0;
503 c->ecx = 0;
504 c->edx = 0;
505
506 c = &cpuid_data.entries[cpuid_i++];
507 c->function = HYPERV_CPUID_VERSION;
508 c->eax = 0x00001bbc;
509 c->ebx = 0x00060001;
510
511 c = &cpuid_data.entries[cpuid_i++];
512 c->function = HYPERV_CPUID_FEATURES;
513 if (cpu->hyperv_relaxed_timing) {
514 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
515 }
516 if (cpu->hyperv_vapic) {
517 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
518 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
519 has_msr_hv_vapic = true;
520 }
521 if (cpu->hyperv_time &&
522 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
523 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
524 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
525 c->eax |= 0x200;
526 has_msr_hv_tsc = true;
527 }
528 if (cpu->hyperv_crash && has_msr_hv_crash) {
529 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
530 }
531
532 c = &cpuid_data.entries[cpuid_i++];
533 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
534 if (cpu->hyperv_relaxed_timing) {
535 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
536 }
537 if (has_msr_hv_vapic) {
538 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
539 }
540 c->ebx = cpu->hyperv_spinlock_attempts;
541
542 c = &cpuid_data.entries[cpuid_i++];
543 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
544 c->eax = 0x40;
545 c->ebx = 0x40;
546
547 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
548 has_msr_hv_hypercall = true;
549 }
550
551 if (cpu->expose_kvm) {
552 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
553 c = &cpuid_data.entries[cpuid_i++];
554 c->function = KVM_CPUID_SIGNATURE | kvm_base;
555 c->eax = KVM_CPUID_FEATURES | kvm_base;
556 c->ebx = signature[0];
557 c->ecx = signature[1];
558 c->edx = signature[2];
559
560 c = &cpuid_data.entries[cpuid_i++];
561 c->function = KVM_CPUID_FEATURES | kvm_base;
562 c->eax = env->features[FEAT_KVM];
563
564 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
565
566 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
567
568 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
569 }
570
571 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
572
573 for (i = 0; i <= limit; i++) {
574 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
575 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
576 abort();
577 }
578 c = &cpuid_data.entries[cpuid_i++];
579
580 switch (i) {
581 case 2: {
582 /* Keep reading function 2 till all the input is received */
583 int times;
584
585 c->function = i;
586 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
587 KVM_CPUID_FLAG_STATE_READ_NEXT;
588 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
589 times = c->eax & 0xff;
590
591 for (j = 1; j < times; ++j) {
592 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
593 fprintf(stderr, "cpuid_data is full, no space for "
594 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
595 abort();
596 }
597 c = &cpuid_data.entries[cpuid_i++];
598 c->function = i;
599 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
600 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
601 }
602 break;
603 }
604 case 4:
605 case 0xb:
606 case 0xd:
607 for (j = 0; ; j++) {
608 if (i == 0xd && j == 64) {
609 break;
610 }
611 c->function = i;
612 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
613 c->index = j;
614 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
615
616 if (i == 4 && c->eax == 0) {
617 break;
618 }
619 if (i == 0xb && !(c->ecx & 0xff00)) {
620 break;
621 }
622 if (i == 0xd && c->eax == 0) {
623 continue;
624 }
625 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
626 fprintf(stderr, "cpuid_data is full, no space for "
627 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
628 abort();
629 }
630 c = &cpuid_data.entries[cpuid_i++];
631 }
632 break;
633 default:
634 c->function = i;
635 c->flags = 0;
636 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
637 break;
638 }
639 }
640
641 if (limit >= 0x0a) {
642 uint32_t ver;
643
644 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
645 if ((ver & 0xff) > 0) {
646 has_msr_architectural_pmu = true;
647 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
648
649 /* Shouldn't be more than 32, since that's the number of bits
650 * available in EBX to tell us _which_ counters are available.
651 * Play it safe.
652 */
653 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
654 num_architectural_pmu_counters = MAX_GP_COUNTERS;
655 }
656 }
657 }
658
659 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
660
661 for (i = 0x80000000; i <= limit; i++) {
662 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
663 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
664 abort();
665 }
666 c = &cpuid_data.entries[cpuid_i++];
667
668 c->function = i;
669 c->flags = 0;
670 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
671 }
672
673 /* Call Centaur's CPUID instructions they are supported. */
674 if (env->cpuid_xlevel2 > 0) {
675 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
676
677 for (i = 0xC0000000; i <= limit; i++) {
678 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
679 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
680 abort();
681 }
682 c = &cpuid_data.entries[cpuid_i++];
683
684 c->function = i;
685 c->flags = 0;
686 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
687 }
688 }
689
690 cpuid_data.cpuid.nent = cpuid_i;
691
692 if (((env->cpuid_version >> 8)&0xF) >= 6
693 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
694 (CPUID_MCE | CPUID_MCA)
695 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
696 uint64_t mcg_cap;
697 int banks;
698 int ret;
699
700 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
701 if (ret < 0) {
702 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
703 return ret;
704 }
705
706 if (banks > MCE_BANKS_DEF) {
707 banks = MCE_BANKS_DEF;
708 }
709 mcg_cap &= MCE_CAP_DEF;
710 mcg_cap |= banks;
711 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
712 if (ret < 0) {
713 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
714 return ret;
715 }
716
717 env->mcg_cap = mcg_cap;
718 }
719
720 qemu_add_vm_change_state_handler(cpu_update_state, env);
721
722 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
723 if (c) {
724 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
725 !!(c->ecx & CPUID_EXT_SMX);
726 }
727
728 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
729 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
730 /* for migration */
731 error_setg(&invtsc_mig_blocker,
732 "State blocked by non-migratable CPU device"
733 " (invtsc flag)");
734 migrate_add_blocker(invtsc_mig_blocker);
735 /* for savevm */
736 vmstate_x86_cpu.unmigratable = 1;
737 }
738
739 cpuid_data.cpuid.padding = 0;
740 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
741 if (r) {
742 return r;
743 }
744
745 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
746 if (r && env->tsc_khz) {
747 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
748 if (r < 0) {
749 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
750 return r;
751 }
752 }
753
754 if (kvm_has_xsave()) {
755 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
756 }
757
758 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
759 has_msr_mtrr = true;
760 }
761
762 return 0;
763 }
764
765 void kvm_arch_reset_vcpu(X86CPU *cpu)
766 {
767 CPUX86State *env = &cpu->env;
768
769 env->exception_injected = -1;
770 env->interrupt_injected = -1;
771 env->xcr0 = 1;
772 if (kvm_irqchip_in_kernel()) {
773 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
774 KVM_MP_STATE_UNINITIALIZED;
775 } else {
776 env->mp_state = KVM_MP_STATE_RUNNABLE;
777 }
778 }
779
780 void kvm_arch_do_init_vcpu(X86CPU *cpu)
781 {
782 CPUX86State *env = &cpu->env;
783
784 /* APs get directly into wait-for-SIPI state. */
785 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
786 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
787 }
788 }
789
790 static int kvm_get_supported_msrs(KVMState *s)
791 {
792 static int kvm_supported_msrs;
793 int ret = 0;
794
795 /* first time */
796 if (kvm_supported_msrs == 0) {
797 struct kvm_msr_list msr_list, *kvm_msr_list;
798
799 kvm_supported_msrs = -1;
800
801 /* Obtain MSR list from KVM. These are the MSRs that we must
802 * save/restore */
803 msr_list.nmsrs = 0;
804 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
805 if (ret < 0 && ret != -E2BIG) {
806 return ret;
807 }
808 /* Old kernel modules had a bug and could write beyond the provided
809 memory. Allocate at least a safe amount of 1K. */
810 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
811 msr_list.nmsrs *
812 sizeof(msr_list.indices[0])));
813
814 kvm_msr_list->nmsrs = msr_list.nmsrs;
815 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
816 if (ret >= 0) {
817 int i;
818
819 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
820 if (kvm_msr_list->indices[i] == MSR_STAR) {
821 has_msr_star = true;
822 continue;
823 }
824 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
825 has_msr_hsave_pa = true;
826 continue;
827 }
828 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
829 has_msr_tsc_adjust = true;
830 continue;
831 }
832 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
833 has_msr_tsc_deadline = true;
834 continue;
835 }
836 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
837 has_msr_smbase = true;
838 continue;
839 }
840 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
841 has_msr_misc_enable = true;
842 continue;
843 }
844 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
845 has_msr_bndcfgs = true;
846 continue;
847 }
848 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
849 has_msr_xss = true;
850 continue;
851 }
852 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
853 has_msr_hv_crash = true;
854 continue;
855 }
856 }
857 }
858
859 g_free(kvm_msr_list);
860 }
861
862 return ret;
863 }
864
865 static Notifier smram_machine_done;
866 static KVMMemoryListener smram_listener;
867 static AddressSpace smram_address_space;
868 static MemoryRegion smram_as_root;
869 static MemoryRegion smram_as_mem;
870
871 static void register_smram_listener(Notifier *n, void *unused)
872 {
873 MemoryRegion *smram =
874 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
875
876 /* Outer container... */
877 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
878 memory_region_set_enabled(&smram_as_root, true);
879
880 /* ... with two regions inside: normal system memory with low
881 * priority, and...
882 */
883 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
884 get_system_memory(), 0, ~0ull);
885 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
886 memory_region_set_enabled(&smram_as_mem, true);
887
888 if (smram) {
889 /* ... SMRAM with higher priority */
890 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
891 memory_region_set_enabled(smram, true);
892 }
893
894 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
895 kvm_memory_listener_register(kvm_state, &smram_listener,
896 &smram_address_space, 1);
897 }
898
899 int kvm_arch_init(MachineState *ms, KVMState *s)
900 {
901 uint64_t identity_base = 0xfffbc000;
902 uint64_t shadow_mem;
903 int ret;
904 struct utsname utsname;
905
906 ret = kvm_get_supported_msrs(s);
907 if (ret < 0) {
908 return ret;
909 }
910
911 uname(&utsname);
912 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
913
914 /*
915 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
916 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
917 * Since these must be part of guest physical memory, we need to allocate
918 * them, both by setting their start addresses in the kernel and by
919 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
920 *
921 * Older KVM versions may not support setting the identity map base. In
922 * that case we need to stick with the default, i.e. a 256K maximum BIOS
923 * size.
924 */
925 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
926 /* Allows up to 16M BIOSes. */
927 identity_base = 0xfeffc000;
928
929 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
930 if (ret < 0) {
931 return ret;
932 }
933 }
934
935 /* Set TSS base one page after EPT identity map. */
936 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
937 if (ret < 0) {
938 return ret;
939 }
940
941 /* Tell fw_cfg to notify the BIOS to reserve the range. */
942 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
943 if (ret < 0) {
944 fprintf(stderr, "e820_add_entry() table is full\n");
945 return ret;
946 }
947 qemu_register_reset(kvm_unpoison_all, NULL);
948
949 shadow_mem = machine_kvm_shadow_mem(ms);
950 if (shadow_mem != -1) {
951 shadow_mem /= 4096;
952 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
953 if (ret < 0) {
954 return ret;
955 }
956 }
957
958 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
959 smram_machine_done.notify = register_smram_listener;
960 qemu_add_machine_init_done_notifier(&smram_machine_done);
961 }
962 return 0;
963 }
964
965 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
966 {
967 lhs->selector = rhs->selector;
968 lhs->base = rhs->base;
969 lhs->limit = rhs->limit;
970 lhs->type = 3;
971 lhs->present = 1;
972 lhs->dpl = 3;
973 lhs->db = 0;
974 lhs->s = 1;
975 lhs->l = 0;
976 lhs->g = 0;
977 lhs->avl = 0;
978 lhs->unusable = 0;
979 }
980
981 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
982 {
983 unsigned flags = rhs->flags;
984 lhs->selector = rhs->selector;
985 lhs->base = rhs->base;
986 lhs->limit = rhs->limit;
987 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
988 lhs->present = (flags & DESC_P_MASK) != 0;
989 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
990 lhs->db = (flags >> DESC_B_SHIFT) & 1;
991 lhs->s = (flags & DESC_S_MASK) != 0;
992 lhs->l = (flags >> DESC_L_SHIFT) & 1;
993 lhs->g = (flags & DESC_G_MASK) != 0;
994 lhs->avl = (flags & DESC_AVL_MASK) != 0;
995 lhs->unusable = 0;
996 lhs->padding = 0;
997 }
998
999 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1000 {
1001 lhs->selector = rhs->selector;
1002 lhs->base = rhs->base;
1003 lhs->limit = rhs->limit;
1004 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1005 (rhs->present * DESC_P_MASK) |
1006 (rhs->dpl << DESC_DPL_SHIFT) |
1007 (rhs->db << DESC_B_SHIFT) |
1008 (rhs->s * DESC_S_MASK) |
1009 (rhs->l << DESC_L_SHIFT) |
1010 (rhs->g * DESC_G_MASK) |
1011 (rhs->avl * DESC_AVL_MASK);
1012 }
1013
1014 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1015 {
1016 if (set) {
1017 *kvm_reg = *qemu_reg;
1018 } else {
1019 *qemu_reg = *kvm_reg;
1020 }
1021 }
1022
1023 static int kvm_getput_regs(X86CPU *cpu, int set)
1024 {
1025 CPUX86State *env = &cpu->env;
1026 struct kvm_regs regs;
1027 int ret = 0;
1028
1029 if (!set) {
1030 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1031 if (ret < 0) {
1032 return ret;
1033 }
1034 }
1035
1036 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1037 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1038 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1039 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1040 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1041 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1042 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1043 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1044 #ifdef TARGET_X86_64
1045 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1046 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1047 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1048 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1049 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1050 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1051 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1052 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1053 #endif
1054
1055 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1056 kvm_getput_reg(&regs.rip, &env->eip, set);
1057
1058 if (set) {
1059 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1060 }
1061
1062 return ret;
1063 }
1064
1065 static int kvm_put_fpu(X86CPU *cpu)
1066 {
1067 CPUX86State *env = &cpu->env;
1068 struct kvm_fpu fpu;
1069 int i;
1070
1071 memset(&fpu, 0, sizeof fpu);
1072 fpu.fsw = env->fpus & ~(7 << 11);
1073 fpu.fsw |= (env->fpstt & 7) << 11;
1074 fpu.fcw = env->fpuc;
1075 fpu.last_opcode = env->fpop;
1076 fpu.last_ip = env->fpip;
1077 fpu.last_dp = env->fpdp;
1078 for (i = 0; i < 8; ++i) {
1079 fpu.ftwx |= (!env->fptags[i]) << i;
1080 }
1081 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1082 for (i = 0; i < CPU_NB_REGS; i++) {
1083 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1084 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1085 }
1086 fpu.mxcsr = env->mxcsr;
1087
1088 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1089 }
1090
1091 #define XSAVE_FCW_FSW 0
1092 #define XSAVE_FTW_FOP 1
1093 #define XSAVE_CWD_RIP 2
1094 #define XSAVE_CWD_RDP 4
1095 #define XSAVE_MXCSR 6
1096 #define XSAVE_ST_SPACE 8
1097 #define XSAVE_XMM_SPACE 40
1098 #define XSAVE_XSTATE_BV 128
1099 #define XSAVE_YMMH_SPACE 144
1100 #define XSAVE_BNDREGS 240
1101 #define XSAVE_BNDCSR 256
1102 #define XSAVE_OPMASK 272
1103 #define XSAVE_ZMM_Hi256 288
1104 #define XSAVE_Hi16_ZMM 416
1105
1106 static int kvm_put_xsave(X86CPU *cpu)
1107 {
1108 CPUX86State *env = &cpu->env;
1109 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1110 uint16_t cwd, swd, twd;
1111 uint8_t *xmm, *ymmh, *zmmh;
1112 int i, r;
1113
1114 if (!kvm_has_xsave()) {
1115 return kvm_put_fpu(cpu);
1116 }
1117
1118 memset(xsave, 0, sizeof(struct kvm_xsave));
1119 twd = 0;
1120 swd = env->fpus & ~(7 << 11);
1121 swd |= (env->fpstt & 7) << 11;
1122 cwd = env->fpuc;
1123 for (i = 0; i < 8; ++i) {
1124 twd |= (!env->fptags[i]) << i;
1125 }
1126 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1127 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1128 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1129 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1130 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1131 sizeof env->fpregs);
1132 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1133 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1134 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1135 sizeof env->bnd_regs);
1136 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1137 sizeof(env->bndcs_regs));
1138 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1139 sizeof env->opmask_regs);
1140
1141 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1142 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1143 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1144 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1145 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1146 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
1147 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1148 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1149 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1150 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1151 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1152 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
1153 }
1154
1155 #ifdef TARGET_X86_64
1156 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1157 16 * sizeof env->xmm_regs[16]);
1158 #endif
1159 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1160 return r;
1161 }
1162
1163 static int kvm_put_xcrs(X86CPU *cpu)
1164 {
1165 CPUX86State *env = &cpu->env;
1166 struct kvm_xcrs xcrs = {};
1167
1168 if (!kvm_has_xcrs()) {
1169 return 0;
1170 }
1171
1172 xcrs.nr_xcrs = 1;
1173 xcrs.flags = 0;
1174 xcrs.xcrs[0].xcr = 0;
1175 xcrs.xcrs[0].value = env->xcr0;
1176 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1177 }
1178
1179 static int kvm_put_sregs(X86CPU *cpu)
1180 {
1181 CPUX86State *env = &cpu->env;
1182 struct kvm_sregs sregs;
1183
1184 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1185 if (env->interrupt_injected >= 0) {
1186 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1187 (uint64_t)1 << (env->interrupt_injected % 64);
1188 }
1189
1190 if ((env->eflags & VM_MASK)) {
1191 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1192 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1193 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1194 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1195 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1196 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1197 } else {
1198 set_seg(&sregs.cs, &env->segs[R_CS]);
1199 set_seg(&sregs.ds, &env->segs[R_DS]);
1200 set_seg(&sregs.es, &env->segs[R_ES]);
1201 set_seg(&sregs.fs, &env->segs[R_FS]);
1202 set_seg(&sregs.gs, &env->segs[R_GS]);
1203 set_seg(&sregs.ss, &env->segs[R_SS]);
1204 }
1205
1206 set_seg(&sregs.tr, &env->tr);
1207 set_seg(&sregs.ldt, &env->ldt);
1208
1209 sregs.idt.limit = env->idt.limit;
1210 sregs.idt.base = env->idt.base;
1211 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1212 sregs.gdt.limit = env->gdt.limit;
1213 sregs.gdt.base = env->gdt.base;
1214 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1215
1216 sregs.cr0 = env->cr[0];
1217 sregs.cr2 = env->cr[2];
1218 sregs.cr3 = env->cr[3];
1219 sregs.cr4 = env->cr[4];
1220
1221 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1222 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1223
1224 sregs.efer = env->efer;
1225
1226 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1227 }
1228
1229 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1230 uint32_t index, uint64_t value)
1231 {
1232 entry->index = index;
1233 entry->reserved = 0;
1234 entry->data = value;
1235 }
1236
1237 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1238 {
1239 CPUX86State *env = &cpu->env;
1240 struct {
1241 struct kvm_msrs info;
1242 struct kvm_msr_entry entries[1];
1243 } msr_data;
1244 struct kvm_msr_entry *msrs = msr_data.entries;
1245
1246 if (!has_msr_tsc_deadline) {
1247 return 0;
1248 }
1249
1250 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1251
1252 msr_data.info = (struct kvm_msrs) {
1253 .nmsrs = 1,
1254 };
1255
1256 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1257 }
1258
1259 /*
1260 * Provide a separate write service for the feature control MSR in order to
1261 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1262 * before writing any other state because forcibly leaving nested mode
1263 * invalidates the VCPU state.
1264 */
1265 static int kvm_put_msr_feature_control(X86CPU *cpu)
1266 {
1267 struct {
1268 struct kvm_msrs info;
1269 struct kvm_msr_entry entry;
1270 } msr_data;
1271
1272 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1273 cpu->env.msr_ia32_feature_control);
1274
1275 msr_data.info = (struct kvm_msrs) {
1276 .nmsrs = 1,
1277 };
1278
1279 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1280 }
1281
1282 static int kvm_put_msrs(X86CPU *cpu, int level)
1283 {
1284 CPUX86State *env = &cpu->env;
1285 struct {
1286 struct kvm_msrs info;
1287 struct kvm_msr_entry entries[150];
1288 } msr_data;
1289 struct kvm_msr_entry *msrs = msr_data.entries;
1290 int n = 0, i;
1291
1292 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1293 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1294 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1295 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1296 if (has_msr_star) {
1297 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1298 }
1299 if (has_msr_hsave_pa) {
1300 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1301 }
1302 if (has_msr_tsc_adjust) {
1303 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1304 }
1305 if (has_msr_misc_enable) {
1306 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1307 env->msr_ia32_misc_enable);
1308 }
1309 if (has_msr_smbase) {
1310 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1311 }
1312 if (has_msr_bndcfgs) {
1313 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1314 }
1315 if (has_msr_xss) {
1316 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1317 }
1318 #ifdef TARGET_X86_64
1319 if (lm_capable_kernel) {
1320 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1321 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1322 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1323 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1324 }
1325 #endif
1326 /*
1327 * The following MSRs have side effects on the guest or are too heavy
1328 * for normal writeback. Limit them to reset or full state updates.
1329 */
1330 if (level >= KVM_PUT_RESET_STATE) {
1331 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1332 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1333 env->system_time_msr);
1334 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1335 if (has_msr_async_pf_en) {
1336 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1337 env->async_pf_en_msr);
1338 }
1339 if (has_msr_pv_eoi_en) {
1340 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1341 env->pv_eoi_en_msr);
1342 }
1343 if (has_msr_kvm_steal_time) {
1344 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1345 env->steal_time_msr);
1346 }
1347 if (has_msr_architectural_pmu) {
1348 /* Stop the counter. */
1349 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1350 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1351
1352 /* Set the counter values. */
1353 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1354 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1355 env->msr_fixed_counters[i]);
1356 }
1357 for (i = 0; i < num_architectural_pmu_counters; i++) {
1358 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1359 env->msr_gp_counters[i]);
1360 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1361 env->msr_gp_evtsel[i]);
1362 }
1363 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1364 env->msr_global_status);
1365 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1366 env->msr_global_ovf_ctrl);
1367
1368 /* Now start the PMU. */
1369 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1370 env->msr_fixed_ctr_ctrl);
1371 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1372 env->msr_global_ctrl);
1373 }
1374 if (has_msr_hv_hypercall) {
1375 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1376 env->msr_hv_guest_os_id);
1377 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1378 env->msr_hv_hypercall);
1379 }
1380 if (has_msr_hv_vapic) {
1381 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1382 env->msr_hv_vapic);
1383 }
1384 if (has_msr_hv_tsc) {
1385 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1386 env->msr_hv_tsc);
1387 }
1388 if (has_msr_hv_crash) {
1389 int j;
1390
1391 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1392 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1393 env->msr_hv_crash_params[j]);
1394
1395 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1396 HV_X64_MSR_CRASH_CTL_NOTIFY);
1397 }
1398 if (has_msr_mtrr) {
1399 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1400 kvm_msr_entry_set(&msrs[n++],
1401 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1402 kvm_msr_entry_set(&msrs[n++],
1403 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1404 kvm_msr_entry_set(&msrs[n++],
1405 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1406 kvm_msr_entry_set(&msrs[n++],
1407 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1408 kvm_msr_entry_set(&msrs[n++],
1409 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1410 kvm_msr_entry_set(&msrs[n++],
1411 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1412 kvm_msr_entry_set(&msrs[n++],
1413 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1414 kvm_msr_entry_set(&msrs[n++],
1415 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1416 kvm_msr_entry_set(&msrs[n++],
1417 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1418 kvm_msr_entry_set(&msrs[n++],
1419 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1420 kvm_msr_entry_set(&msrs[n++],
1421 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1422 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1423 kvm_msr_entry_set(&msrs[n++],
1424 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1425 kvm_msr_entry_set(&msrs[n++],
1426 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1427 }
1428 }
1429
1430 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1431 * kvm_put_msr_feature_control. */
1432 }
1433 if (env->mcg_cap) {
1434 int i;
1435
1436 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1437 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1438 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1439 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1440 }
1441 }
1442
1443 msr_data.info = (struct kvm_msrs) {
1444 .nmsrs = n,
1445 };
1446
1447 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1448
1449 }
1450
1451
1452 static int kvm_get_fpu(X86CPU *cpu)
1453 {
1454 CPUX86State *env = &cpu->env;
1455 struct kvm_fpu fpu;
1456 int i, ret;
1457
1458 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1459 if (ret < 0) {
1460 return ret;
1461 }
1462
1463 env->fpstt = (fpu.fsw >> 11) & 7;
1464 env->fpus = fpu.fsw;
1465 env->fpuc = fpu.fcw;
1466 env->fpop = fpu.last_opcode;
1467 env->fpip = fpu.last_ip;
1468 env->fpdp = fpu.last_dp;
1469 for (i = 0; i < 8; ++i) {
1470 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1471 }
1472 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1473 for (i = 0; i < CPU_NB_REGS; i++) {
1474 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1475 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1476 }
1477 env->mxcsr = fpu.mxcsr;
1478
1479 return 0;
1480 }
1481
1482 static int kvm_get_xsave(X86CPU *cpu)
1483 {
1484 CPUX86State *env = &cpu->env;
1485 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1486 int ret, i;
1487 const uint8_t *xmm, *ymmh, *zmmh;
1488 uint16_t cwd, swd, twd;
1489
1490 if (!kvm_has_xsave()) {
1491 return kvm_get_fpu(cpu);
1492 }
1493
1494 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1495 if (ret < 0) {
1496 return ret;
1497 }
1498
1499 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1500 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1501 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1502 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1503 env->fpstt = (swd >> 11) & 7;
1504 env->fpus = swd;
1505 env->fpuc = cwd;
1506 for (i = 0; i < 8; ++i) {
1507 env->fptags[i] = !((twd >> i) & 1);
1508 }
1509 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1510 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1511 env->mxcsr = xsave->region[XSAVE_MXCSR];
1512 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1513 sizeof env->fpregs);
1514 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1515 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1516 sizeof env->bnd_regs);
1517 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1518 sizeof(env->bndcs_regs));
1519 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1520 sizeof env->opmask_regs);
1521
1522 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1523 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1524 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1525 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1526 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1527 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
1528 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1529 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1530 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1531 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1532 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1533 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
1534 }
1535
1536 #ifdef TARGET_X86_64
1537 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1538 16 * sizeof env->xmm_regs[16]);
1539 #endif
1540 return 0;
1541 }
1542
1543 static int kvm_get_xcrs(X86CPU *cpu)
1544 {
1545 CPUX86State *env = &cpu->env;
1546 int i, ret;
1547 struct kvm_xcrs xcrs;
1548
1549 if (!kvm_has_xcrs()) {
1550 return 0;
1551 }
1552
1553 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1554 if (ret < 0) {
1555 return ret;
1556 }
1557
1558 for (i = 0; i < xcrs.nr_xcrs; i++) {
1559 /* Only support xcr0 now */
1560 if (xcrs.xcrs[i].xcr == 0) {
1561 env->xcr0 = xcrs.xcrs[i].value;
1562 break;
1563 }
1564 }
1565 return 0;
1566 }
1567
1568 static int kvm_get_sregs(X86CPU *cpu)
1569 {
1570 CPUX86State *env = &cpu->env;
1571 struct kvm_sregs sregs;
1572 uint32_t hflags;
1573 int bit, i, ret;
1574
1575 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1576 if (ret < 0) {
1577 return ret;
1578 }
1579
1580 /* There can only be one pending IRQ set in the bitmap at a time, so try
1581 to find it and save its number instead (-1 for none). */
1582 env->interrupt_injected = -1;
1583 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1584 if (sregs.interrupt_bitmap[i]) {
1585 bit = ctz64(sregs.interrupt_bitmap[i]);
1586 env->interrupt_injected = i * 64 + bit;
1587 break;
1588 }
1589 }
1590
1591 get_seg(&env->segs[R_CS], &sregs.cs);
1592 get_seg(&env->segs[R_DS], &sregs.ds);
1593 get_seg(&env->segs[R_ES], &sregs.es);
1594 get_seg(&env->segs[R_FS], &sregs.fs);
1595 get_seg(&env->segs[R_GS], &sregs.gs);
1596 get_seg(&env->segs[R_SS], &sregs.ss);
1597
1598 get_seg(&env->tr, &sregs.tr);
1599 get_seg(&env->ldt, &sregs.ldt);
1600
1601 env->idt.limit = sregs.idt.limit;
1602 env->idt.base = sregs.idt.base;
1603 env->gdt.limit = sregs.gdt.limit;
1604 env->gdt.base = sregs.gdt.base;
1605
1606 env->cr[0] = sregs.cr0;
1607 env->cr[2] = sregs.cr2;
1608 env->cr[3] = sregs.cr3;
1609 env->cr[4] = sregs.cr4;
1610
1611 env->efer = sregs.efer;
1612
1613 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1614
1615 #define HFLAG_COPY_MASK \
1616 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1617 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1618 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1619 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1620
1621 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1622 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1623 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1624 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1625 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1626 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1627 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1628
1629 if (env->efer & MSR_EFER_LMA) {
1630 hflags |= HF_LMA_MASK;
1631 }
1632
1633 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1634 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1635 } else {
1636 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1637 (DESC_B_SHIFT - HF_CS32_SHIFT);
1638 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1639 (DESC_B_SHIFT - HF_SS32_SHIFT);
1640 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1641 !(hflags & HF_CS32_MASK)) {
1642 hflags |= HF_ADDSEG_MASK;
1643 } else {
1644 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1645 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1646 }
1647 }
1648 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1649
1650 return 0;
1651 }
1652
1653 static int kvm_get_msrs(X86CPU *cpu)
1654 {
1655 CPUX86State *env = &cpu->env;
1656 struct {
1657 struct kvm_msrs info;
1658 struct kvm_msr_entry entries[150];
1659 } msr_data;
1660 struct kvm_msr_entry *msrs = msr_data.entries;
1661 int ret, i, n;
1662
1663 n = 0;
1664 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1665 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1666 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1667 msrs[n++].index = MSR_PAT;
1668 if (has_msr_star) {
1669 msrs[n++].index = MSR_STAR;
1670 }
1671 if (has_msr_hsave_pa) {
1672 msrs[n++].index = MSR_VM_HSAVE_PA;
1673 }
1674 if (has_msr_tsc_adjust) {
1675 msrs[n++].index = MSR_TSC_ADJUST;
1676 }
1677 if (has_msr_tsc_deadline) {
1678 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1679 }
1680 if (has_msr_misc_enable) {
1681 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1682 }
1683 if (has_msr_smbase) {
1684 msrs[n++].index = MSR_IA32_SMBASE;
1685 }
1686 if (has_msr_feature_control) {
1687 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1688 }
1689 if (has_msr_bndcfgs) {
1690 msrs[n++].index = MSR_IA32_BNDCFGS;
1691 }
1692 if (has_msr_xss) {
1693 msrs[n++].index = MSR_IA32_XSS;
1694 }
1695
1696
1697 if (!env->tsc_valid) {
1698 msrs[n++].index = MSR_IA32_TSC;
1699 env->tsc_valid = !runstate_is_running();
1700 }
1701
1702 #ifdef TARGET_X86_64
1703 if (lm_capable_kernel) {
1704 msrs[n++].index = MSR_CSTAR;
1705 msrs[n++].index = MSR_KERNELGSBASE;
1706 msrs[n++].index = MSR_FMASK;
1707 msrs[n++].index = MSR_LSTAR;
1708 }
1709 #endif
1710 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1711 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1712 if (has_msr_async_pf_en) {
1713 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1714 }
1715 if (has_msr_pv_eoi_en) {
1716 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1717 }
1718 if (has_msr_kvm_steal_time) {
1719 msrs[n++].index = MSR_KVM_STEAL_TIME;
1720 }
1721 if (has_msr_architectural_pmu) {
1722 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1723 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1724 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1725 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1726 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1727 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1728 }
1729 for (i = 0; i < num_architectural_pmu_counters; i++) {
1730 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1731 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1732 }
1733 }
1734
1735 if (env->mcg_cap) {
1736 msrs[n++].index = MSR_MCG_STATUS;
1737 msrs[n++].index = MSR_MCG_CTL;
1738 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1739 msrs[n++].index = MSR_MC0_CTL + i;
1740 }
1741 }
1742
1743 if (has_msr_hv_hypercall) {
1744 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1745 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1746 }
1747 if (has_msr_hv_vapic) {
1748 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1749 }
1750 if (has_msr_hv_tsc) {
1751 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1752 }
1753 if (has_msr_hv_crash) {
1754 int j;
1755
1756 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
1757 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
1758 }
1759 }
1760 if (has_msr_mtrr) {
1761 msrs[n++].index = MSR_MTRRdefType;
1762 msrs[n++].index = MSR_MTRRfix64K_00000;
1763 msrs[n++].index = MSR_MTRRfix16K_80000;
1764 msrs[n++].index = MSR_MTRRfix16K_A0000;
1765 msrs[n++].index = MSR_MTRRfix4K_C0000;
1766 msrs[n++].index = MSR_MTRRfix4K_C8000;
1767 msrs[n++].index = MSR_MTRRfix4K_D0000;
1768 msrs[n++].index = MSR_MTRRfix4K_D8000;
1769 msrs[n++].index = MSR_MTRRfix4K_E0000;
1770 msrs[n++].index = MSR_MTRRfix4K_E8000;
1771 msrs[n++].index = MSR_MTRRfix4K_F0000;
1772 msrs[n++].index = MSR_MTRRfix4K_F8000;
1773 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1774 msrs[n++].index = MSR_MTRRphysBase(i);
1775 msrs[n++].index = MSR_MTRRphysMask(i);
1776 }
1777 }
1778
1779 msr_data.info = (struct kvm_msrs) {
1780 .nmsrs = n,
1781 };
1782
1783 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1784 if (ret < 0) {
1785 return ret;
1786 }
1787
1788 for (i = 0; i < ret; i++) {
1789 uint32_t index = msrs[i].index;
1790 switch (index) {
1791 case MSR_IA32_SYSENTER_CS:
1792 env->sysenter_cs = msrs[i].data;
1793 break;
1794 case MSR_IA32_SYSENTER_ESP:
1795 env->sysenter_esp = msrs[i].data;
1796 break;
1797 case MSR_IA32_SYSENTER_EIP:
1798 env->sysenter_eip = msrs[i].data;
1799 break;
1800 case MSR_PAT:
1801 env->pat = msrs[i].data;
1802 break;
1803 case MSR_STAR:
1804 env->star = msrs[i].data;
1805 break;
1806 #ifdef TARGET_X86_64
1807 case MSR_CSTAR:
1808 env->cstar = msrs[i].data;
1809 break;
1810 case MSR_KERNELGSBASE:
1811 env->kernelgsbase = msrs[i].data;
1812 break;
1813 case MSR_FMASK:
1814 env->fmask = msrs[i].data;
1815 break;
1816 case MSR_LSTAR:
1817 env->lstar = msrs[i].data;
1818 break;
1819 #endif
1820 case MSR_IA32_TSC:
1821 env->tsc = msrs[i].data;
1822 break;
1823 case MSR_TSC_ADJUST:
1824 env->tsc_adjust = msrs[i].data;
1825 break;
1826 case MSR_IA32_TSCDEADLINE:
1827 env->tsc_deadline = msrs[i].data;
1828 break;
1829 case MSR_VM_HSAVE_PA:
1830 env->vm_hsave = msrs[i].data;
1831 break;
1832 case MSR_KVM_SYSTEM_TIME:
1833 env->system_time_msr = msrs[i].data;
1834 break;
1835 case MSR_KVM_WALL_CLOCK:
1836 env->wall_clock_msr = msrs[i].data;
1837 break;
1838 case MSR_MCG_STATUS:
1839 env->mcg_status = msrs[i].data;
1840 break;
1841 case MSR_MCG_CTL:
1842 env->mcg_ctl = msrs[i].data;
1843 break;
1844 case MSR_IA32_MISC_ENABLE:
1845 env->msr_ia32_misc_enable = msrs[i].data;
1846 break;
1847 case MSR_IA32_SMBASE:
1848 env->smbase = msrs[i].data;
1849 break;
1850 case MSR_IA32_FEATURE_CONTROL:
1851 env->msr_ia32_feature_control = msrs[i].data;
1852 break;
1853 case MSR_IA32_BNDCFGS:
1854 env->msr_bndcfgs = msrs[i].data;
1855 break;
1856 case MSR_IA32_XSS:
1857 env->xss = msrs[i].data;
1858 break;
1859 default:
1860 if (msrs[i].index >= MSR_MC0_CTL &&
1861 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1862 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1863 }
1864 break;
1865 case MSR_KVM_ASYNC_PF_EN:
1866 env->async_pf_en_msr = msrs[i].data;
1867 break;
1868 case MSR_KVM_PV_EOI_EN:
1869 env->pv_eoi_en_msr = msrs[i].data;
1870 break;
1871 case MSR_KVM_STEAL_TIME:
1872 env->steal_time_msr = msrs[i].data;
1873 break;
1874 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1875 env->msr_fixed_ctr_ctrl = msrs[i].data;
1876 break;
1877 case MSR_CORE_PERF_GLOBAL_CTRL:
1878 env->msr_global_ctrl = msrs[i].data;
1879 break;
1880 case MSR_CORE_PERF_GLOBAL_STATUS:
1881 env->msr_global_status = msrs[i].data;
1882 break;
1883 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1884 env->msr_global_ovf_ctrl = msrs[i].data;
1885 break;
1886 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1887 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1888 break;
1889 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1890 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1891 break;
1892 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1893 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1894 break;
1895 case HV_X64_MSR_HYPERCALL:
1896 env->msr_hv_hypercall = msrs[i].data;
1897 break;
1898 case HV_X64_MSR_GUEST_OS_ID:
1899 env->msr_hv_guest_os_id = msrs[i].data;
1900 break;
1901 case HV_X64_MSR_APIC_ASSIST_PAGE:
1902 env->msr_hv_vapic = msrs[i].data;
1903 break;
1904 case HV_X64_MSR_REFERENCE_TSC:
1905 env->msr_hv_tsc = msrs[i].data;
1906 break;
1907 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
1908 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
1909 break;
1910 case MSR_MTRRdefType:
1911 env->mtrr_deftype = msrs[i].data;
1912 break;
1913 case MSR_MTRRfix64K_00000:
1914 env->mtrr_fixed[0] = msrs[i].data;
1915 break;
1916 case MSR_MTRRfix16K_80000:
1917 env->mtrr_fixed[1] = msrs[i].data;
1918 break;
1919 case MSR_MTRRfix16K_A0000:
1920 env->mtrr_fixed[2] = msrs[i].data;
1921 break;
1922 case MSR_MTRRfix4K_C0000:
1923 env->mtrr_fixed[3] = msrs[i].data;
1924 break;
1925 case MSR_MTRRfix4K_C8000:
1926 env->mtrr_fixed[4] = msrs[i].data;
1927 break;
1928 case MSR_MTRRfix4K_D0000:
1929 env->mtrr_fixed[5] = msrs[i].data;
1930 break;
1931 case MSR_MTRRfix4K_D8000:
1932 env->mtrr_fixed[6] = msrs[i].data;
1933 break;
1934 case MSR_MTRRfix4K_E0000:
1935 env->mtrr_fixed[7] = msrs[i].data;
1936 break;
1937 case MSR_MTRRfix4K_E8000:
1938 env->mtrr_fixed[8] = msrs[i].data;
1939 break;
1940 case MSR_MTRRfix4K_F0000:
1941 env->mtrr_fixed[9] = msrs[i].data;
1942 break;
1943 case MSR_MTRRfix4K_F8000:
1944 env->mtrr_fixed[10] = msrs[i].data;
1945 break;
1946 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
1947 if (index & 1) {
1948 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
1949 } else {
1950 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
1951 }
1952 break;
1953 }
1954 }
1955
1956 return 0;
1957 }
1958
1959 static int kvm_put_mp_state(X86CPU *cpu)
1960 {
1961 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1962
1963 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1964 }
1965
1966 static int kvm_get_mp_state(X86CPU *cpu)
1967 {
1968 CPUState *cs = CPU(cpu);
1969 CPUX86State *env = &cpu->env;
1970 struct kvm_mp_state mp_state;
1971 int ret;
1972
1973 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1974 if (ret < 0) {
1975 return ret;
1976 }
1977 env->mp_state = mp_state.mp_state;
1978 if (kvm_irqchip_in_kernel()) {
1979 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1980 }
1981 return 0;
1982 }
1983
1984 static int kvm_get_apic(X86CPU *cpu)
1985 {
1986 DeviceState *apic = cpu->apic_state;
1987 struct kvm_lapic_state kapic;
1988 int ret;
1989
1990 if (apic && kvm_irqchip_in_kernel()) {
1991 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1992 if (ret < 0) {
1993 return ret;
1994 }
1995
1996 kvm_get_apic_state(apic, &kapic);
1997 }
1998 return 0;
1999 }
2000
2001 static int kvm_put_apic(X86CPU *cpu)
2002 {
2003 DeviceState *apic = cpu->apic_state;
2004 struct kvm_lapic_state kapic;
2005
2006 if (apic && kvm_irqchip_in_kernel()) {
2007 kvm_put_apic_state(apic, &kapic);
2008
2009 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2010 }
2011 return 0;
2012 }
2013
2014 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2015 {
2016 CPUState *cs = CPU(cpu);
2017 CPUX86State *env = &cpu->env;
2018 struct kvm_vcpu_events events = {};
2019
2020 if (!kvm_has_vcpu_events()) {
2021 return 0;
2022 }
2023
2024 events.exception.injected = (env->exception_injected >= 0);
2025 events.exception.nr = env->exception_injected;
2026 events.exception.has_error_code = env->has_error_code;
2027 events.exception.error_code = env->error_code;
2028 events.exception.pad = 0;
2029
2030 events.interrupt.injected = (env->interrupt_injected >= 0);
2031 events.interrupt.nr = env->interrupt_injected;
2032 events.interrupt.soft = env->soft_interrupt;
2033
2034 events.nmi.injected = env->nmi_injected;
2035 events.nmi.pending = env->nmi_pending;
2036 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2037 events.nmi.pad = 0;
2038
2039 events.sipi_vector = env->sipi_vector;
2040
2041 if (has_msr_smbase) {
2042 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2043 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2044 if (kvm_irqchip_in_kernel()) {
2045 /* As soon as these are moved to the kernel, remove them
2046 * from cs->interrupt_request.
2047 */
2048 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2049 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2050 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2051 } else {
2052 /* Keep these in cs->interrupt_request. */
2053 events.smi.pending = 0;
2054 events.smi.latched_init = 0;
2055 }
2056 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2057 }
2058
2059 events.flags = 0;
2060 if (level >= KVM_PUT_RESET_STATE) {
2061 events.flags |=
2062 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2063 }
2064
2065 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2066 }
2067
2068 static int kvm_get_vcpu_events(X86CPU *cpu)
2069 {
2070 CPUX86State *env = &cpu->env;
2071 struct kvm_vcpu_events events;
2072 int ret;
2073
2074 if (!kvm_has_vcpu_events()) {
2075 return 0;
2076 }
2077
2078 memset(&events, 0, sizeof(events));
2079 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2080 if (ret < 0) {
2081 return ret;
2082 }
2083 env->exception_injected =
2084 events.exception.injected ? events.exception.nr : -1;
2085 env->has_error_code = events.exception.has_error_code;
2086 env->error_code = events.exception.error_code;
2087
2088 env->interrupt_injected =
2089 events.interrupt.injected ? events.interrupt.nr : -1;
2090 env->soft_interrupt = events.interrupt.soft;
2091
2092 env->nmi_injected = events.nmi.injected;
2093 env->nmi_pending = events.nmi.pending;
2094 if (events.nmi.masked) {
2095 env->hflags2 |= HF2_NMI_MASK;
2096 } else {
2097 env->hflags2 &= ~HF2_NMI_MASK;
2098 }
2099
2100 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2101 if (events.smi.smm) {
2102 env->hflags |= HF_SMM_MASK;
2103 } else {
2104 env->hflags &= ~HF_SMM_MASK;
2105 }
2106 if (events.smi.pending) {
2107 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2108 } else {
2109 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2110 }
2111 if (events.smi.smm_inside_nmi) {
2112 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2113 } else {
2114 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2115 }
2116 if (events.smi.latched_init) {
2117 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2118 } else {
2119 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2120 }
2121 }
2122
2123 env->sipi_vector = events.sipi_vector;
2124
2125 return 0;
2126 }
2127
2128 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2129 {
2130 CPUState *cs = CPU(cpu);
2131 CPUX86State *env = &cpu->env;
2132 int ret = 0;
2133 unsigned long reinject_trap = 0;
2134
2135 if (!kvm_has_vcpu_events()) {
2136 if (env->exception_injected == 1) {
2137 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2138 } else if (env->exception_injected == 3) {
2139 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2140 }
2141 env->exception_injected = -1;
2142 }
2143
2144 /*
2145 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2146 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2147 * by updating the debug state once again if single-stepping is on.
2148 * Another reason to call kvm_update_guest_debug here is a pending debug
2149 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2150 * reinject them via SET_GUEST_DEBUG.
2151 */
2152 if (reinject_trap ||
2153 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2154 ret = kvm_update_guest_debug(cs, reinject_trap);
2155 }
2156 return ret;
2157 }
2158
2159 static int kvm_put_debugregs(X86CPU *cpu)
2160 {
2161 CPUX86State *env = &cpu->env;
2162 struct kvm_debugregs dbgregs;
2163 int i;
2164
2165 if (!kvm_has_debugregs()) {
2166 return 0;
2167 }
2168
2169 for (i = 0; i < 4; i++) {
2170 dbgregs.db[i] = env->dr[i];
2171 }
2172 dbgregs.dr6 = env->dr[6];
2173 dbgregs.dr7 = env->dr[7];
2174 dbgregs.flags = 0;
2175
2176 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2177 }
2178
2179 static int kvm_get_debugregs(X86CPU *cpu)
2180 {
2181 CPUX86State *env = &cpu->env;
2182 struct kvm_debugregs dbgregs;
2183 int i, ret;
2184
2185 if (!kvm_has_debugregs()) {
2186 return 0;
2187 }
2188
2189 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2190 if (ret < 0) {
2191 return ret;
2192 }
2193 for (i = 0; i < 4; i++) {
2194 env->dr[i] = dbgregs.db[i];
2195 }
2196 env->dr[4] = env->dr[6] = dbgregs.dr6;
2197 env->dr[5] = env->dr[7] = dbgregs.dr7;
2198
2199 return 0;
2200 }
2201
2202 int kvm_arch_put_registers(CPUState *cpu, int level)
2203 {
2204 X86CPU *x86_cpu = X86_CPU(cpu);
2205 int ret;
2206
2207 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2208
2209 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2210 ret = kvm_put_msr_feature_control(x86_cpu);
2211 if (ret < 0) {
2212 return ret;
2213 }
2214 }
2215
2216 ret = kvm_getput_regs(x86_cpu, 1);
2217 if (ret < 0) {
2218 return ret;
2219 }
2220 ret = kvm_put_xsave(x86_cpu);
2221 if (ret < 0) {
2222 return ret;
2223 }
2224 ret = kvm_put_xcrs(x86_cpu);
2225 if (ret < 0) {
2226 return ret;
2227 }
2228 ret = kvm_put_sregs(x86_cpu);
2229 if (ret < 0) {
2230 return ret;
2231 }
2232 /* must be before kvm_put_msrs */
2233 ret = kvm_inject_mce_oldstyle(x86_cpu);
2234 if (ret < 0) {
2235 return ret;
2236 }
2237 ret = kvm_put_msrs(x86_cpu, level);
2238 if (ret < 0) {
2239 return ret;
2240 }
2241 if (level >= KVM_PUT_RESET_STATE) {
2242 ret = kvm_put_mp_state(x86_cpu);
2243 if (ret < 0) {
2244 return ret;
2245 }
2246 ret = kvm_put_apic(x86_cpu);
2247 if (ret < 0) {
2248 return ret;
2249 }
2250 }
2251
2252 ret = kvm_put_tscdeadline_msr(x86_cpu);
2253 if (ret < 0) {
2254 return ret;
2255 }
2256
2257 ret = kvm_put_vcpu_events(x86_cpu, level);
2258 if (ret < 0) {
2259 return ret;
2260 }
2261 ret = kvm_put_debugregs(x86_cpu);
2262 if (ret < 0) {
2263 return ret;
2264 }
2265 /* must be last */
2266 ret = kvm_guest_debug_workarounds(x86_cpu);
2267 if (ret < 0) {
2268 return ret;
2269 }
2270 return 0;
2271 }
2272
2273 int kvm_arch_get_registers(CPUState *cs)
2274 {
2275 X86CPU *cpu = X86_CPU(cs);
2276 int ret;
2277
2278 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2279
2280 ret = kvm_getput_regs(cpu, 0);
2281 if (ret < 0) {
2282 return ret;
2283 }
2284 ret = kvm_get_xsave(cpu);
2285 if (ret < 0) {
2286 return ret;
2287 }
2288 ret = kvm_get_xcrs(cpu);
2289 if (ret < 0) {
2290 return ret;
2291 }
2292 ret = kvm_get_sregs(cpu);
2293 if (ret < 0) {
2294 return ret;
2295 }
2296 ret = kvm_get_msrs(cpu);
2297 if (ret < 0) {
2298 return ret;
2299 }
2300 ret = kvm_get_mp_state(cpu);
2301 if (ret < 0) {
2302 return ret;
2303 }
2304 ret = kvm_get_apic(cpu);
2305 if (ret < 0) {
2306 return ret;
2307 }
2308 ret = kvm_get_vcpu_events(cpu);
2309 if (ret < 0) {
2310 return ret;
2311 }
2312 ret = kvm_get_debugregs(cpu);
2313 if (ret < 0) {
2314 return ret;
2315 }
2316 return 0;
2317 }
2318
2319 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2320 {
2321 X86CPU *x86_cpu = X86_CPU(cpu);
2322 CPUX86State *env = &x86_cpu->env;
2323 int ret;
2324
2325 /* Inject NMI */
2326 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2327 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2328 qemu_mutex_lock_iothread();
2329 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2330 qemu_mutex_unlock_iothread();
2331 DPRINTF("injected NMI\n");
2332 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2333 if (ret < 0) {
2334 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2335 strerror(-ret));
2336 }
2337 }
2338 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2339 qemu_mutex_lock_iothread();
2340 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2341 qemu_mutex_unlock_iothread();
2342 DPRINTF("injected SMI\n");
2343 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2344 if (ret < 0) {
2345 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2346 strerror(-ret));
2347 }
2348 }
2349 }
2350
2351 if (!kvm_irqchip_in_kernel()) {
2352 qemu_mutex_lock_iothread();
2353 }
2354
2355 /* Force the VCPU out of its inner loop to process any INIT requests
2356 * or (for userspace APIC, but it is cheap to combine the checks here)
2357 * pending TPR access reports.
2358 */
2359 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2360 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2361 !(env->hflags & HF_SMM_MASK)) {
2362 cpu->exit_request = 1;
2363 }
2364 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2365 cpu->exit_request = 1;
2366 }
2367 }
2368
2369 if (!kvm_irqchip_in_kernel()) {
2370 /* Try to inject an interrupt if the guest can accept it */
2371 if (run->ready_for_interrupt_injection &&
2372 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2373 (env->eflags & IF_MASK)) {
2374 int irq;
2375
2376 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2377 irq = cpu_get_pic_interrupt(env);
2378 if (irq >= 0) {
2379 struct kvm_interrupt intr;
2380
2381 intr.irq = irq;
2382 DPRINTF("injected interrupt %d\n", irq);
2383 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2384 if (ret < 0) {
2385 fprintf(stderr,
2386 "KVM: injection failed, interrupt lost (%s)\n",
2387 strerror(-ret));
2388 }
2389 }
2390 }
2391
2392 /* If we have an interrupt but the guest is not ready to receive an
2393 * interrupt, request an interrupt window exit. This will
2394 * cause a return to userspace as soon as the guest is ready to
2395 * receive interrupts. */
2396 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2397 run->request_interrupt_window = 1;
2398 } else {
2399 run->request_interrupt_window = 0;
2400 }
2401
2402 DPRINTF("setting tpr\n");
2403 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2404
2405 qemu_mutex_unlock_iothread();
2406 }
2407 }
2408
2409 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2410 {
2411 X86CPU *x86_cpu = X86_CPU(cpu);
2412 CPUX86State *env = &x86_cpu->env;
2413
2414 if (run->flags & KVM_RUN_X86_SMM) {
2415 env->hflags |= HF_SMM_MASK;
2416 } else {
2417 env->hflags &= HF_SMM_MASK;
2418 }
2419 if (run->if_flag) {
2420 env->eflags |= IF_MASK;
2421 } else {
2422 env->eflags &= ~IF_MASK;
2423 }
2424
2425 /* We need to protect the apic state against concurrent accesses from
2426 * different threads in case the userspace irqchip is used. */
2427 if (!kvm_irqchip_in_kernel()) {
2428 qemu_mutex_lock_iothread();
2429 }
2430 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2431 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2432 if (!kvm_irqchip_in_kernel()) {
2433 qemu_mutex_unlock_iothread();
2434 }
2435 return cpu_get_mem_attrs(env);
2436 }
2437
2438 int kvm_arch_process_async_events(CPUState *cs)
2439 {
2440 X86CPU *cpu = X86_CPU(cs);
2441 CPUX86State *env = &cpu->env;
2442
2443 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2444 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2445 assert(env->mcg_cap);
2446
2447 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2448
2449 kvm_cpu_synchronize_state(cs);
2450
2451 if (env->exception_injected == EXCP08_DBLE) {
2452 /* this means triple fault */
2453 qemu_system_reset_request();
2454 cs->exit_request = 1;
2455 return 0;
2456 }
2457 env->exception_injected = EXCP12_MCHK;
2458 env->has_error_code = 0;
2459
2460 cs->halted = 0;
2461 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2462 env->mp_state = KVM_MP_STATE_RUNNABLE;
2463 }
2464 }
2465
2466 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2467 !(env->hflags & HF_SMM_MASK)) {
2468 kvm_cpu_synchronize_state(cs);
2469 do_cpu_init(cpu);
2470 }
2471
2472 if (kvm_irqchip_in_kernel()) {
2473 return 0;
2474 }
2475
2476 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2477 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2478 apic_poll_irq(cpu->apic_state);
2479 }
2480 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2481 (env->eflags & IF_MASK)) ||
2482 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2483 cs->halted = 0;
2484 }
2485 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2486 kvm_cpu_synchronize_state(cs);
2487 do_cpu_sipi(cpu);
2488 }
2489 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2490 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2491 kvm_cpu_synchronize_state(cs);
2492 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2493 env->tpr_access_type);
2494 }
2495
2496 return cs->halted;
2497 }
2498
2499 static int kvm_handle_halt(X86CPU *cpu)
2500 {
2501 CPUState *cs = CPU(cpu);
2502 CPUX86State *env = &cpu->env;
2503
2504 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2505 (env->eflags & IF_MASK)) &&
2506 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2507 cs->halted = 1;
2508 return EXCP_HLT;
2509 }
2510
2511 return 0;
2512 }
2513
2514 static int kvm_handle_tpr_access(X86CPU *cpu)
2515 {
2516 CPUState *cs = CPU(cpu);
2517 struct kvm_run *run = cs->kvm_run;
2518
2519 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2520 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2521 : TPR_ACCESS_READ);
2522 return 1;
2523 }
2524
2525 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2526 {
2527 static const uint8_t int3 = 0xcc;
2528
2529 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2530 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2531 return -EINVAL;
2532 }
2533 return 0;
2534 }
2535
2536 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2537 {
2538 uint8_t int3;
2539
2540 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2541 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2542 return -EINVAL;
2543 }
2544 return 0;
2545 }
2546
2547 static struct {
2548 target_ulong addr;
2549 int len;
2550 int type;
2551 } hw_breakpoint[4];
2552
2553 static int nb_hw_breakpoint;
2554
2555 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2556 {
2557 int n;
2558
2559 for (n = 0; n < nb_hw_breakpoint; n++) {
2560 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2561 (hw_breakpoint[n].len == len || len == -1)) {
2562 return n;
2563 }
2564 }
2565 return -1;
2566 }
2567
2568 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2569 target_ulong len, int type)
2570 {
2571 switch (type) {
2572 case GDB_BREAKPOINT_HW:
2573 len = 1;
2574 break;
2575 case GDB_WATCHPOINT_WRITE:
2576 case GDB_WATCHPOINT_ACCESS:
2577 switch (len) {
2578 case 1:
2579 break;
2580 case 2:
2581 case 4:
2582 case 8:
2583 if (addr & (len - 1)) {
2584 return -EINVAL;
2585 }
2586 break;
2587 default:
2588 return -EINVAL;
2589 }
2590 break;
2591 default:
2592 return -ENOSYS;
2593 }
2594
2595 if (nb_hw_breakpoint == 4) {
2596 return -ENOBUFS;
2597 }
2598 if (find_hw_breakpoint(addr, len, type) >= 0) {
2599 return -EEXIST;
2600 }
2601 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2602 hw_breakpoint[nb_hw_breakpoint].len = len;
2603 hw_breakpoint[nb_hw_breakpoint].type = type;
2604 nb_hw_breakpoint++;
2605
2606 return 0;
2607 }
2608
2609 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2610 target_ulong len, int type)
2611 {
2612 int n;
2613
2614 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2615 if (n < 0) {
2616 return -ENOENT;
2617 }
2618 nb_hw_breakpoint--;
2619 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2620
2621 return 0;
2622 }
2623
2624 void kvm_arch_remove_all_hw_breakpoints(void)
2625 {
2626 nb_hw_breakpoint = 0;
2627 }
2628
2629 static CPUWatchpoint hw_watchpoint;
2630
2631 static int kvm_handle_debug(X86CPU *cpu,
2632 struct kvm_debug_exit_arch *arch_info)
2633 {
2634 CPUState *cs = CPU(cpu);
2635 CPUX86State *env = &cpu->env;
2636 int ret = 0;
2637 int n;
2638
2639 if (arch_info->exception == 1) {
2640 if (arch_info->dr6 & (1 << 14)) {
2641 if (cs->singlestep_enabled) {
2642 ret = EXCP_DEBUG;
2643 }
2644 } else {
2645 for (n = 0; n < 4; n++) {
2646 if (arch_info->dr6 & (1 << n)) {
2647 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2648 case 0x0:
2649 ret = EXCP_DEBUG;
2650 break;
2651 case 0x1:
2652 ret = EXCP_DEBUG;
2653 cs->watchpoint_hit = &hw_watchpoint;
2654 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2655 hw_watchpoint.flags = BP_MEM_WRITE;
2656 break;
2657 case 0x3:
2658 ret = EXCP_DEBUG;
2659 cs->watchpoint_hit = &hw_watchpoint;
2660 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2661 hw_watchpoint.flags = BP_MEM_ACCESS;
2662 break;
2663 }
2664 }
2665 }
2666 }
2667 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2668 ret = EXCP_DEBUG;
2669 }
2670 if (ret == 0) {
2671 cpu_synchronize_state(cs);
2672 assert(env->exception_injected == -1);
2673
2674 /* pass to guest */
2675 env->exception_injected = arch_info->exception;
2676 env->has_error_code = 0;
2677 }
2678
2679 return ret;
2680 }
2681
2682 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2683 {
2684 const uint8_t type_code[] = {
2685 [GDB_BREAKPOINT_HW] = 0x0,
2686 [GDB_WATCHPOINT_WRITE] = 0x1,
2687 [GDB_WATCHPOINT_ACCESS] = 0x3
2688 };
2689 const uint8_t len_code[] = {
2690 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2691 };
2692 int n;
2693
2694 if (kvm_sw_breakpoints_active(cpu)) {
2695 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2696 }
2697 if (nb_hw_breakpoint > 0) {
2698 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2699 dbg->arch.debugreg[7] = 0x0600;
2700 for (n = 0; n < nb_hw_breakpoint; n++) {
2701 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2702 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2703 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2704 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2705 }
2706 }
2707 }
2708
2709 static bool host_supports_vmx(void)
2710 {
2711 uint32_t ecx, unused;
2712
2713 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2714 return ecx & CPUID_EXT_VMX;
2715 }
2716
2717 #define VMX_INVALID_GUEST_STATE 0x80000021
2718
2719 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2720 {
2721 X86CPU *cpu = X86_CPU(cs);
2722 uint64_t code;
2723 int ret;
2724
2725 switch (run->exit_reason) {
2726 case KVM_EXIT_HLT:
2727 DPRINTF("handle_hlt\n");
2728 qemu_mutex_lock_iothread();
2729 ret = kvm_handle_halt(cpu);
2730 qemu_mutex_unlock_iothread();
2731 break;
2732 case KVM_EXIT_SET_TPR:
2733 ret = 0;
2734 break;
2735 case KVM_EXIT_TPR_ACCESS:
2736 qemu_mutex_lock_iothread();
2737 ret = kvm_handle_tpr_access(cpu);
2738 qemu_mutex_unlock_iothread();
2739 break;
2740 case KVM_EXIT_FAIL_ENTRY:
2741 code = run->fail_entry.hardware_entry_failure_reason;
2742 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2743 code);
2744 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2745 fprintf(stderr,
2746 "\nIf you're running a guest on an Intel machine without "
2747 "unrestricted mode\n"
2748 "support, the failure can be most likely due to the guest "
2749 "entering an invalid\n"
2750 "state for Intel VT. For example, the guest maybe running "
2751 "in big real mode\n"
2752 "which is not supported on less recent Intel processors."
2753 "\n\n");
2754 }
2755 ret = -1;
2756 break;
2757 case KVM_EXIT_EXCEPTION:
2758 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2759 run->ex.exception, run->ex.error_code);
2760 ret = -1;
2761 break;
2762 case KVM_EXIT_DEBUG:
2763 DPRINTF("kvm_exit_debug\n");
2764 qemu_mutex_lock_iothread();
2765 ret = kvm_handle_debug(cpu, &run->debug.arch);
2766 qemu_mutex_unlock_iothread();
2767 break;
2768 default:
2769 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2770 ret = -1;
2771 break;
2772 }
2773
2774 return ret;
2775 }
2776
2777 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2778 {
2779 X86CPU *cpu = X86_CPU(cs);
2780 CPUX86State *env = &cpu->env;
2781
2782 kvm_cpu_synchronize_state(cs);
2783 return !(env->cr[0] & CR0_PE_MASK) ||
2784 ((env->segs[R_CS].selector & 3) != 3);
2785 }
2786
2787 void kvm_arch_init_irq_routing(KVMState *s)
2788 {
2789 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2790 /* If kernel can't do irq routing, interrupt source
2791 * override 0->2 cannot be set up as required by HPET.
2792 * So we have to disable it.
2793 */
2794 no_hpet = 1;
2795 }
2796 /* We know at this point that we're using the in-kernel
2797 * irqchip, so we can use irqfds, and on x86 we know
2798 * we can use msi via irqfd and GSI routing.
2799 */
2800 kvm_msi_via_irqfd_allowed = true;
2801 kvm_gsi_routing_allowed = true;
2802 }
2803
2804 /* Classic KVM device assignment interface. Will remain x86 only. */
2805 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2806 uint32_t flags, uint32_t *dev_id)
2807 {
2808 struct kvm_assigned_pci_dev dev_data = {
2809 .segnr = dev_addr->domain,
2810 .busnr = dev_addr->bus,
2811 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2812 .flags = flags,
2813 };
2814 int ret;
2815
2816 dev_data.assigned_dev_id =
2817 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2818
2819 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2820 if (ret < 0) {
2821 return ret;
2822 }
2823
2824 *dev_id = dev_data.assigned_dev_id;
2825
2826 return 0;
2827 }
2828
2829 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2830 {
2831 struct kvm_assigned_pci_dev dev_data = {
2832 .assigned_dev_id = dev_id,
2833 };
2834
2835 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2836 }
2837
2838 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2839 uint32_t irq_type, uint32_t guest_irq)
2840 {
2841 struct kvm_assigned_irq assigned_irq = {
2842 .assigned_dev_id = dev_id,
2843 .guest_irq = guest_irq,
2844 .flags = irq_type,
2845 };
2846
2847 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2848 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2849 } else {
2850 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2851 }
2852 }
2853
2854 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2855 uint32_t guest_irq)
2856 {
2857 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2858 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2859
2860 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2861 }
2862
2863 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2864 {
2865 struct kvm_assigned_pci_dev dev_data = {
2866 .assigned_dev_id = dev_id,
2867 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2868 };
2869
2870 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2871 }
2872
2873 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2874 uint32_t type)
2875 {
2876 struct kvm_assigned_irq assigned_irq = {
2877 .assigned_dev_id = dev_id,
2878 .flags = type,
2879 };
2880
2881 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2882 }
2883
2884 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2885 {
2886 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2887 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2888 }
2889
2890 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2891 {
2892 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2893 KVM_DEV_IRQ_GUEST_MSI, virq);
2894 }
2895
2896 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2897 {
2898 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2899 KVM_DEV_IRQ_HOST_MSI);
2900 }
2901
2902 bool kvm_device_msix_supported(KVMState *s)
2903 {
2904 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2905 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2906 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2907 }
2908
2909 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2910 uint32_t nr_vectors)
2911 {
2912 struct kvm_assigned_msix_nr msix_nr = {
2913 .assigned_dev_id = dev_id,
2914 .entry_nr = nr_vectors,
2915 };
2916
2917 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2918 }
2919
2920 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2921 int virq)
2922 {
2923 struct kvm_assigned_msix_entry msix_entry = {
2924 .assigned_dev_id = dev_id,
2925 .gsi = virq,
2926 .entry = vector,
2927 };
2928
2929 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2930 }
2931
2932 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2933 {
2934 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2935 KVM_DEV_IRQ_GUEST_MSIX, 0);
2936 }
2937
2938 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2939 {
2940 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2941 KVM_DEV_IRQ_HOST_MSIX);
2942 }
2943
2944 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2945 uint64_t address, uint32_t data)
2946 {
2947 return 0;
2948 }
2949
2950 int kvm_arch_msi_data_to_gsi(uint32_t data)
2951 {
2952 abort();
2953 }
CRIS target port of Qemu