target-lm32/cpu.h

   1 /*
   2  *  LatticeMico32 virtual CPU header.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef CPU_LM32_H
  21 #define CPU_LM32_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define CPUArchState struct CPULM32State
  26
  27 #include "config.h"
  28 #include "qemu-common.h"
  29 #include "exec/cpu-defs.h"
  30 struct CPULM32State;
  31 typedef struct CPULM32State CPULM32State;
  32
  33 #define ELF_MACHINE EM_LATTICEMICO32
  34
  35 #define NB_MMU_MODES 1
  36 #define TARGET_PAGE_BITS 12
  37 static inline int cpu_mmu_index(CPULM32State *env)
  38 {
  39     return 0;
  40 }
  41
  42 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  43 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  44
  45 /* Exceptions indices */
  46 enum {
  47     EXCP_RESET = 0,
  48     EXCP_BREAKPOINT,
  49     EXCP_INSN_BUS_ERROR,
  50     EXCP_WATCHPOINT,
  51     EXCP_DATA_BUS_ERROR,
  52     EXCP_DIVIDE_BY_ZERO,
  53     EXCP_IRQ,
  54     EXCP_SYSTEMCALL
  55 };
  56
  57 /* Registers */
  58 enum {
  59     R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10,
  60     R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20,
  61     R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30,
  62     R_R31
  63 };
  64
  65 /* Register aliases */
  66 enum {
  67     R_GP = R_R26,
  68     R_FP = R_R27,
  69     R_SP = R_R28,
  70     R_RA = R_R29,
  71     R_EA = R_R30,
  72     R_BA = R_R31
  73 };
  74
  75 /* IE flags */
  76 enum {
  77     IE_IE  = (1<<0),
  78     IE_EIE = (1<<1),
  79     IE_BIE = (1<<2),
  80 };
  81
  82 /* DC flags */
  83 enum {
  84     DC_SS  = (1<<0),
  85     DC_RE  = (1<<1),
  86     DC_C0  = (1<<2),
  87     DC_C1  = (1<<3),
  88     DC_C2  = (1<<4),
  89     DC_C3  = (1<<5),
  90 };
  91
  92 /* CFG mask */
  93 enum {
  94     CFG_M         = (1<<0),
  95     CFG_D         = (1<<1),
  96     CFG_S         = (1<<2),
  97     CFG_U         = (1<<3),
  98     CFG_X         = (1<<4),
  99     CFG_CC        = (1<<5),
 100     CFG_IC        = (1<<6),
 101     CFG_DC        = (1<<7),
 102     CFG_G         = (1<<8),
 103     CFG_H         = (1<<9),
 104     CFG_R         = (1<<10),
 105     CFG_J         = (1<<11),
 106     CFG_INT_SHIFT = 12,
 107     CFG_BP_SHIFT  = 18,
 108     CFG_WP_SHIFT  = 22,
 109     CFG_REV_SHIFT = 26,
 110 };
 111
 112 /* CSRs */
 113 enum {
 114     CSR_IE   = 0x00,
 115     CSR_IM   = 0x01,
 116     CSR_IP   = 0x02,
 117     CSR_ICC  = 0x03,
 118     CSR_DCC  = 0x04,
 119     CSR_CC   = 0x05,
 120     CSR_CFG  = 0x06,
 121     CSR_EBA  = 0x07,
 122     CSR_DC   = 0x08,
 123     CSR_DEBA = 0x09,
 124     CSR_JTX  = 0x0e,
 125     CSR_JRX  = 0x0f,
 126     CSR_BP0  = 0x10,
 127     CSR_BP1  = 0x11,
 128     CSR_BP2  = 0x12,
 129     CSR_BP3  = 0x13,
 130     CSR_WP0  = 0x18,
 131     CSR_WP1  = 0x19,
 132     CSR_WP2  = 0x1a,
 133     CSR_WP3  = 0x1b,
 134 };
 135
 136 enum {
 137     LM32_FEATURE_MULTIPLY     =  1,
 138     LM32_FEATURE_DIVIDE       =  2,
 139     LM32_FEATURE_SHIFT        =  4,
 140     LM32_FEATURE_SIGN_EXTEND  =  8,
 141     LM32_FEATURE_I_CACHE      = 16,
 142     LM32_FEATURE_D_CACHE      = 32,
 143     LM32_FEATURE_CYCLE_COUNT  = 64,
 144 };
 145
 146 enum {
 147     LM32_FLAG_IGNORE_MSB = 1,
 148 };
 149
 150 struct CPULM32State {
 151     /* general registers */
 152     uint32_t regs[32];
 153
 154     /* special registers */
 155     uint32_t pc;        /* program counter */
 156     uint32_t ie;        /* interrupt enable */
 157     uint32_t icc;       /* instruction cache control */
 158     uint32_t dcc;       /* data cache control */
 159     uint32_t cc;        /* cycle counter */
 160     uint32_t cfg;       /* configuration */
 161
 162     /* debug registers */
 163     uint32_t dc;        /* debug control */
 164     uint32_t bp[4];     /* breakpoints */
 165     uint32_t wp[4];     /* watchpoints */
 166
 167     struct CPUBreakpoint *cpu_breakpoint[4];
 168     struct CPUWatchpoint *cpu_watchpoint[4];
 169
 170     CPU_COMMON
 171
 172     /* Fields from here on are preserved across CPU reset. */
 173     uint32_t eba;       /* exception base address */
 174     uint32_t deba;      /* debug exception base address */
 175
 176     /* interrupt controller handle for callbacks */
 177     DeviceState *pic_state;
 178     /* JTAG UART handle for callbacks */
 179     DeviceState *juart_state;
 180
 181     /* processor core features */
 182     uint32_t flags;
 183
 184 };
 185
 186 typedef enum {
 187     LM32_WP_DISABLED = 0,
 188     LM32_WP_READ,
 189     LM32_WP_WRITE,
 190     LM32_WP_READ_WRITE,
 191 } lm32_wp_t;
 192
 193 static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
 194 {
 195     assert(idx < 4);
 196     return (dc >> (idx+1)*2) & 0x3;
 197 }
 198
 199 #include "cpu-qom.h"
 200
 201 LM32CPU *cpu_lm32_init(const char *cpu_model);
 202 int cpu_lm32_exec(CPULM32State *s);
 203 /* you can call this signal handler from your SIGBUS and SIGSEGV
 204    signal handlers to inform the virtual CPU of exceptions. non zero
 205    is returned if the signal was handled by the virtual CPU.  */
 206 int cpu_lm32_signal_handler(int host_signum, void *pinfo,
 207                           void *puc);
 208 void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 209 void lm32_translate_init(void);
 210 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
 211 void QEMU_NORETURN raise_exception(CPULM32State *env, int index);
 212 void lm32_debug_excp_handler(CPUState *cs);
 213 void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address);
 214 void lm32_breakpoint_remove(CPULM32State *env, int index);
 215 void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address,
 216         lm32_wp_t wp_type);
 217 void lm32_watchpoint_remove(CPULM32State *env, int index);
 218 bool lm32_cpu_do_semihosting(CPUState *cs);
 219
 220 static inline CPULM32State *cpu_init(const char *cpu_model)
 221 {
 222     LM32CPU *cpu = cpu_lm32_init(cpu_model);
 223     if (cpu == NULL) {
 224         return NULL;
 225     }
 226     return &cpu->env;
 227 }
 228
 229 #define cpu_list lm32_cpu_list
 230 #define cpu_exec cpu_lm32_exec
 231 #define cpu_gen_code cpu_lm32_gen_code
 232 #define cpu_signal_handler cpu_lm32_signal_handler
 233
 234 int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 235                               int mmu_idx);
 236
 237 #include "exec/cpu-all.h"
 238
 239 static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
 240                                         target_ulong *cs_base, int *flags)
 241 {
 242     *pc = env->pc;
 243     *cs_base = 0;
 244     *flags = 0;
 245 }
 246
 247 #include "exec/exec-all.h"
 248
 249 #endif