pc: Don't use QEMUMachine anymore
[qemu/cris-port.git] / hw / i386 / pc_q35.c
blob6a9fe5850068658486ab005a2fa8efc7a0701a36
1 /*
2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on pc.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
30 #include "hw/hw.h"
31 #include "hw/loader.h"
32 #include "sysemu/arch_init.h"
33 #include "hw/i2c/smbus.h"
34 #include "hw/boards.h"
35 #include "hw/timer/mc146818rtc.h"
36 #include "hw/xen/xen.h"
37 #include "sysemu/kvm.h"
38 #include "hw/kvm/clock.h"
39 #include "hw/pci-host/q35.h"
40 #include "exec/address-spaces.h"
41 #include "hw/i386/ich9.h"
42 #include "hw/i386/smbios.h"
43 #include "hw/ide/pci.h"
44 #include "hw/ide/ahci.h"
45 #include "hw/usb.h"
46 #include "hw/cpu/icc_bus.h"
47 #include "qemu/error-report.h"
49 /* ICH9 AHCI has 6 ports */
50 #define MAX_SATA_PORTS 6
52 static bool has_acpi_build = true;
53 static bool rsdp_in_ram = true;
54 static bool smbios_defaults = true;
55 static bool smbios_legacy_mode;
56 static bool smbios_uuid_encoded = true;
57 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
58 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte
59 * pages in the host.
61 static bool gigabyte_align = true;
62 static bool has_reserved_memory = true;
64 /* PC hardware initialisation */
65 static void pc_q35_init(MachineState *machine)
67 PCMachineState *pc_machine = PC_MACHINE(machine);
68 ram_addr_t below_4g_mem_size, above_4g_mem_size;
69 Q35PCIHost *q35_host;
70 PCIHostState *phb;
71 PCIBus *host_bus;
72 PCIDevice *lpc;
73 BusState *idebus[MAX_SATA_PORTS];
74 ISADevice *rtc_state;
75 ISADevice *floppy;
76 MemoryRegion *pci_memory;
77 MemoryRegion *rom_memory;
78 MemoryRegion *ram_memory;
79 GSIState *gsi_state;
80 ISABus *isa_bus;
81 int pci_enabled = 1;
82 qemu_irq *cpu_irq;
83 qemu_irq *gsi;
84 qemu_irq *i8259;
85 int i;
86 ICH9LPCState *ich9_lpc;
87 PCIDevice *ahci;
88 DeviceState *icc_bridge;
89 PcGuestInfo *guest_info;
90 ram_addr_t lowmem;
91 DriveInfo *hd[MAX_SATA_PORTS];
93 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
94 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
95 * also known as MMCFG).
96 * If it doesn't, we need to split it in chunks below and above 4G.
97 * In any case, try to make sure that guest addresses aligned at
98 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
99 * For old machine types, use whatever split we used historically to avoid
100 * breaking migration.
102 if (machine->ram_size >= 0xb0000000) {
103 lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
104 } else {
105 lowmem = 0xb0000000;
108 /* Handle the machine opt max-ram-below-4g. It is basically doing
109 * min(qemu limit, user limit).
111 if (lowmem > pc_machine->max_ram_below_4g) {
112 lowmem = pc_machine->max_ram_below_4g;
113 if (machine->ram_size - lowmem > lowmem &&
114 lowmem & ((1ULL << 30) - 1)) {
115 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
116 ") not a multiple of 1G; possible bad performance.",
117 pc_machine->max_ram_below_4g);
121 if (machine->ram_size >= lowmem) {
122 above_4g_mem_size = machine->ram_size - lowmem;
123 below_4g_mem_size = lowmem;
124 } else {
125 above_4g_mem_size = 0;
126 below_4g_mem_size = machine->ram_size;
129 if (xen_enabled() && xen_hvm_init(&below_4g_mem_size, &above_4g_mem_size,
130 &ram_memory) != 0) {
131 fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
132 exit(1);
135 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
136 object_property_add_child(qdev_get_machine(), "icc-bridge",
137 OBJECT(icc_bridge), NULL);
139 pc_cpus_init(machine->cpu_model, icc_bridge);
140 pc_acpi_init("q35-acpi-dsdt.aml");
142 kvmclock_create();
144 /* pci enabled */
145 if (pci_enabled) {
146 pci_memory = g_new(MemoryRegion, 1);
147 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
148 rom_memory = pci_memory;
149 } else {
150 pci_memory = NULL;
151 rom_memory = get_system_memory();
154 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
155 guest_info->isapc_ram_fw = false;
156 guest_info->has_acpi_build = has_acpi_build;
157 guest_info->has_reserved_memory = has_reserved_memory;
158 guest_info->rsdp_in_ram = rsdp_in_ram;
160 /* Migration was not supported in 2.0 for Q35, so do not bother
161 * with this hack (see hw/i386/acpi-build.c).
163 guest_info->legacy_acpi_table_size = 0;
165 if (smbios_defaults) {
166 MachineClass *mc = MACHINE_GET_CLASS(machine);
167 /* These values are guest ABI, do not change */
168 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
169 mc->name, smbios_legacy_mode, smbios_uuid_encoded);
172 /* allocate ram and load rom/bios */
173 if (!xen_enabled()) {
174 pc_memory_init(machine, get_system_memory(),
175 below_4g_mem_size, above_4g_mem_size,
176 rom_memory, &ram_memory, guest_info);
179 /* irq lines */
180 gsi_state = g_malloc0(sizeof(*gsi_state));
181 if (kvm_irqchip_in_kernel()) {
182 kvm_pc_setup_irq_routing(pci_enabled);
183 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
184 GSI_NUM_PINS);
185 } else {
186 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
189 /* create pci host bus */
190 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
192 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
193 q35_host->mch.ram_memory = ram_memory;
194 q35_host->mch.pci_address_space = pci_memory;
195 q35_host->mch.system_memory = get_system_memory();
196 q35_host->mch.address_space_io = get_system_io();
197 q35_host->mch.below_4g_mem_size = below_4g_mem_size;
198 q35_host->mch.above_4g_mem_size = above_4g_mem_size;
199 q35_host->mch.guest_info = guest_info;
200 /* pci */
201 qdev_init_nofail(DEVICE(q35_host));
202 phb = PCI_HOST_BRIDGE(q35_host);
203 host_bus = phb->bus;
204 /* create ISA bus */
205 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
206 ICH9_LPC_FUNC), true,
207 TYPE_ICH9_LPC_DEVICE);
209 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
210 TYPE_HOTPLUG_HANDLER,
211 (Object **)&pc_machine->acpi_dev,
212 object_property_allow_set_link,
213 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
214 object_property_set_link(OBJECT(machine), OBJECT(lpc),
215 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
217 ich9_lpc = ICH9_LPC_DEVICE(lpc);
218 ich9_lpc->pic = gsi;
219 ich9_lpc->ioapic = gsi_state->ioapic_irq;
220 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
221 ICH9_LPC_NB_PIRQS);
222 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
223 isa_bus = ich9_lpc->isa_bus;
225 /*end early*/
226 isa_bus_irqs(isa_bus, gsi);
228 if (kvm_irqchip_in_kernel()) {
229 i8259 = kvm_i8259_init(isa_bus);
230 } else if (xen_enabled()) {
231 i8259 = xen_interrupt_controller_init();
232 } else {
233 cpu_irq = pc_allocate_cpu_irq();
234 i8259 = i8259_init(isa_bus, cpu_irq[0]);
237 for (i = 0; i < ISA_NUM_IRQS; i++) {
238 gsi_state->i8259_irq[i] = i8259[i];
240 if (pci_enabled) {
241 ioapic_init_gsi(gsi_state, "q35");
243 qdev_init_nofail(icc_bridge);
245 pc_register_ferr_irq(gsi[13]);
247 assert(pc_machine->vmport != ON_OFF_AUTO_MAX);
248 if (pc_machine->vmport == ON_OFF_AUTO_AUTO) {
249 pc_machine->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
252 /* init basic PC hardware */
253 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy,
254 (pc_machine->vmport != ON_OFF_AUTO_ON), 0xff0104);
256 /* connect pm stuff to lpc */
257 ich9_lpc_pm_init(lpc);
259 /* ahci and SATA device, for q35 1 ahci controller is built-in */
260 ahci = pci_create_simple_multifunction(host_bus,
261 PCI_DEVFN(ICH9_SATA1_DEV,
262 ICH9_SATA1_FUNC),
263 true, "ich9-ahci");
264 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
265 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
266 g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
267 ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
268 ahci_ide_create_devs(ahci, hd);
270 if (usb_enabled()) {
271 /* Should we create 6 UHCI according to ich9 spec? */
272 ehci_create_ich9_with_companions(host_bus, 0x1d);
275 /* TODO: Populate SPD eeprom data. */
276 smbus_eeprom_init(ich9_smb_init(host_bus,
277 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
278 0xb100),
279 8, NULL, 0);
281 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order,
282 machine, floppy, idebus[0], idebus[1], rtc_state);
284 /* the rest devices to which pci devfn is automatically assigned */
285 pc_vga_init(isa_bus, host_bus);
286 pc_nic_init(isa_bus, host_bus);
287 if (pci_enabled) {
288 pc_pci_device_init(host_bus);
292 static void pc_compat_2_3(MachineState *machine)
296 static void pc_compat_2_2(MachineState *machine)
298 pc_compat_2_3(machine);
299 rsdp_in_ram = false;
300 x86_cpu_compat_set_features("kvm64", FEAT_1_EDX, 0, CPUID_VME);
301 x86_cpu_compat_set_features("kvm32", FEAT_1_EDX, 0, CPUID_VME);
302 x86_cpu_compat_set_features("Conroe", FEAT_1_EDX, 0, CPUID_VME);
303 x86_cpu_compat_set_features("Penryn", FEAT_1_EDX, 0, CPUID_VME);
304 x86_cpu_compat_set_features("Nehalem", FEAT_1_EDX, 0, CPUID_VME);
305 x86_cpu_compat_set_features("Westmere", FEAT_1_EDX, 0, CPUID_VME);
306 x86_cpu_compat_set_features("SandyBridge", FEAT_1_EDX, 0, CPUID_VME);
307 x86_cpu_compat_set_features("Haswell", FEAT_1_EDX, 0, CPUID_VME);
308 x86_cpu_compat_set_features("Broadwell", FEAT_1_EDX, 0, CPUID_VME);
309 x86_cpu_compat_set_features("Opteron_G1", FEAT_1_EDX, 0, CPUID_VME);
310 x86_cpu_compat_set_features("Opteron_G2", FEAT_1_EDX, 0, CPUID_VME);
311 x86_cpu_compat_set_features("Opteron_G3", FEAT_1_EDX, 0, CPUID_VME);
312 x86_cpu_compat_set_features("Opteron_G4", FEAT_1_EDX, 0, CPUID_VME);
313 x86_cpu_compat_set_features("Opteron_G5", FEAT_1_EDX, 0, CPUID_VME);
314 x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_F16C);
315 x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
316 x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);
317 x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
318 machine->suppress_vmdesc = true;
321 static void pc_compat_2_1(MachineState *machine)
323 PCMachineState *pcms = PC_MACHINE(machine);
325 pc_compat_2_2(machine);
326 pcms->enforce_aligned_dimm = false;
327 smbios_uuid_encoded = false;
328 x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0);
329 x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0);
330 x86_cpu_compat_kvm_no_autodisable(FEAT_8000_0001_ECX, CPUID_EXT3_SVM);
333 static void pc_compat_2_0(MachineState *machine)
335 pc_compat_2_1(machine);
336 smbios_legacy_mode = true;
337 has_reserved_memory = false;
338 pc_set_legacy_acpi_data_size();
341 static void pc_compat_1_7(MachineState *machine)
343 pc_compat_2_0(machine);
344 smbios_defaults = false;
345 gigabyte_align = false;
346 option_rom_has_mr = true;
347 x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX, CPUID_EXT_X2APIC);
350 static void pc_compat_1_6(MachineState *machine)
352 pc_compat_1_7(machine);
353 rom_file_has_mr = false;
354 has_acpi_build = false;
357 static void pc_compat_1_5(MachineState *machine)
359 pc_compat_1_6(machine);
362 static void pc_compat_1_4(MachineState *machine)
364 pc_compat_1_5(machine);
365 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
366 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
369 static void pc_q35_init_2_3(MachineState *machine)
371 pc_compat_2_3(machine);
372 pc_q35_init(machine);
375 static void pc_q35_init_2_2(MachineState *machine)
377 pc_compat_2_2(machine);
378 pc_q35_init(machine);
381 static void pc_q35_init_2_1(MachineState *machine)
383 pc_compat_2_1(machine);
384 pc_q35_init(machine);
387 static void pc_q35_init_2_0(MachineState *machine)
389 pc_compat_2_0(machine);
390 pc_q35_init(machine);
393 static void pc_q35_init_1_7(MachineState *machine)
395 pc_compat_1_7(machine);
396 pc_q35_init(machine);
399 static void pc_q35_init_1_6(MachineState *machine)
401 pc_compat_1_6(machine);
402 pc_q35_init(machine);
405 static void pc_q35_init_1_5(MachineState *machine)
407 pc_compat_1_5(machine);
408 pc_q35_init(machine);
411 static void pc_q35_init_1_4(MachineState *machine)
413 pc_compat_1_4(machine);
414 pc_q35_init(machine);
417 static void pc_q35_machine_options(MachineClass *m)
419 pc_default_machine_options(m);
420 m->family = "pc_q35";
421 m->desc = "Standard PC (Q35 + ICH9, 2009)";
422 m->hot_add_cpu = pc_hot_add_cpu;
423 m->units_per_default_bus = 1;
426 static void pc_q35_2_4_machine_options(MachineClass *m)
428 pc_q35_machine_options(m);
429 m->default_machine_opts = "firmware=bios-256k.bin";
430 m->default_display = "std";
431 m->alias = "q35";
434 DEFINE_PC_MACHINE(v2_4, "pc-q35-2.4", pc_q35_init,
435 pc_q35_2_4_machine_options);
438 static void pc_q35_2_3_machine_options(MachineClass *m)
440 pc_q35_2_4_machine_options(m);
441 m->alias = NULL;
442 SET_MACHINE_COMPAT(m, PC_COMPAT_2_3);
445 DEFINE_PC_MACHINE(v2_3, "pc-q35-2.3", pc_q35_init_2_3,
446 pc_q35_2_3_machine_options);
449 static void pc_q35_2_2_machine_options(MachineClass *m)
451 pc_q35_2_3_machine_options(m);
452 SET_MACHINE_COMPAT(m, PC_COMPAT_2_2);
455 DEFINE_PC_MACHINE(v2_2, "pc-q35-2.2", pc_q35_init_2_2,
456 pc_q35_2_2_machine_options);
459 static void pc_q35_2_1_machine_options(MachineClass *m)
461 pc_q35_2_2_machine_options(m);
462 m->default_display = NULL;
463 SET_MACHINE_COMPAT(m, PC_COMPAT_2_1);
466 DEFINE_PC_MACHINE(v2_1, "pc-q35-2.1", pc_q35_init_2_1,
467 pc_q35_2_1_machine_options);
470 static void pc_q35_2_0_machine_options(MachineClass *m)
472 pc_q35_2_1_machine_options(m);
473 SET_MACHINE_COMPAT(m, PC_COMPAT_2_0);
476 DEFINE_PC_MACHINE(v2_0, "pc-q35-2.0", pc_q35_init_2_0,
477 pc_q35_2_0_machine_options);
480 static void pc_q35_1_7_machine_options(MachineClass *m)
482 pc_q35_2_0_machine_options(m);
483 m->default_machine_opts = NULL;
484 SET_MACHINE_COMPAT(m, PC_COMPAT_1_7);
487 DEFINE_PC_MACHINE(v1_7, "pc-q35-1.7", pc_q35_init_1_7,
488 pc_q35_1_7_machine_options);
491 static void pc_q35_1_6_machine_options(MachineClass *m)
493 pc_q35_machine_options(m);
494 SET_MACHINE_COMPAT(m, PC_COMPAT_1_6);
497 DEFINE_PC_MACHINE(v1_6, "pc-q35-1.6", pc_q35_init_1_6,
498 pc_q35_1_6_machine_options);
501 static void pc_q35_1_5_machine_options(MachineClass *m)
503 pc_q35_1_6_machine_options(m);
504 SET_MACHINE_COMPAT(m, PC_COMPAT_1_5);
507 DEFINE_PC_MACHINE(v1_5, "pc-q35-1.5", pc_q35_init_1_5,
508 pc_q35_1_5_machine_options);
511 static void pc_q35_1_4_machine_options(MachineClass *m)
513 pc_q35_1_5_machine_options(m);
514 m->hot_add_cpu = NULL;
515 SET_MACHINE_COMPAT(m, PC_COMPAT_1_4);
518 DEFINE_PC_MACHINE(v1_4, "pc-q35-1.4", pc_q35_init_1_4,
519 pc_q35_1_4_machine_options);