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arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2
[qemu/cris-port.git] / target-mips / translate_init.c
blob29dc2ef73851c10efdad03ec69b470e1887a0140
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
50
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
53
54 /* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56 enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64 };
65
66 struct mips_def_t {
67 const char *name;
68 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
71 int32_t CP0_Config2;
72 int32_t CP0_Config3;
73 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
75 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
77 int32_t CP0_Config6;
78 int32_t CP0_Config7;
79 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
81 int32_t SYNCI_Step;
82 int32_t CCRes;
83 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
86 int32_t CP1_fcr0;
87 int32_t SEGBITS;
88 int32_t PABITS;
89 int32_t CP0_SRSConf0_rw_bitmask;
90 int32_t CP0_SRSConf0;
91 int32_t CP0_SRSConf1_rw_bitmask;
92 int32_t CP0_SRSConf1;
93 int32_t CP0_SRSConf2_rw_bitmask;
94 int32_t CP0_SRSConf2;
95 int32_t CP0_SRSConf3_rw_bitmask;
96 int32_t CP0_SRSConf3;
97 int32_t CP0_SRSConf4_rw_bitmask;
98 int32_t CP0_SRSConf4;
99 int insn_flags;
100 enum mips_mmu_types mmu_type;
101 };
102
103 /*****************************************************************************/
104 /* MIPS CPU definitions */
105 static const mips_def_t mips_defs[] =
106 {
107 {
108 .name = "4Kc",
109 .CP0_PRid = 0x00018000,
110 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
111 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
112 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
113 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
114 (0 << CP0C1_CA),
115 .CP0_Config2 = MIPS_CONFIG2,
116 .CP0_Config3 = MIPS_CONFIG3,
117 .CP0_LLAddr_rw_bitmask = 0,
118 .CP0_LLAddr_shift = 4,
119 .SYNCI_Step = 32,
120 .CCRes = 2,
121 .CP0_Status_rw_bitmask = 0x1278FF17,
122 .SEGBITS = 32,
123 .PABITS = 32,
124 .insn_flags = CPU_MIPS32,
125 .mmu_type = MMU_TYPE_R4000,
126 },
127 {
128 .name = "4Km",
129 .CP0_PRid = 0x00018300,
130 /* Config1 implemented, fixed mapping MMU,
131 no virtual icache, uncached coherency. */
132 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
133 .CP0_Config1 = MIPS_CONFIG1 |
134 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
135 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
136 (1 << CP0C1_CA),
137 .CP0_Config2 = MIPS_CONFIG2,
138 .CP0_Config3 = MIPS_CONFIG3,
139 .CP0_LLAddr_rw_bitmask = 0,
140 .CP0_LLAddr_shift = 4,
141 .SYNCI_Step = 32,
142 .CCRes = 2,
143 .CP0_Status_rw_bitmask = 0x1258FF17,
144 .SEGBITS = 32,
145 .PABITS = 32,
146 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
147 .mmu_type = MMU_TYPE_FMT,
148 },
149 {
150 .name = "4KEcR1",
151 .CP0_PRid = 0x00018400,
152 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
153 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
154 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
155 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
156 (0 << CP0C1_CA),
157 .CP0_Config2 = MIPS_CONFIG2,
158 .CP0_Config3 = MIPS_CONFIG3,
159 .CP0_LLAddr_rw_bitmask = 0,
160 .CP0_LLAddr_shift = 4,
161 .SYNCI_Step = 32,
162 .CCRes = 2,
163 .CP0_Status_rw_bitmask = 0x1278FF17,
164 .SEGBITS = 32,
165 .PABITS = 32,
166 .insn_flags = CPU_MIPS32,
167 .mmu_type = MMU_TYPE_R4000,
168 },
169 {
170 .name = "4KEmR1",
171 .CP0_PRid = 0x00018500,
172 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
173 .CP0_Config1 = MIPS_CONFIG1 |
174 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
175 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
176 (1 << CP0C1_CA),
177 .CP0_Config2 = MIPS_CONFIG2,
178 .CP0_Config3 = MIPS_CONFIG3,
179 .CP0_LLAddr_rw_bitmask = 0,
180 .CP0_LLAddr_shift = 4,
181 .SYNCI_Step = 32,
182 .CCRes = 2,
183 .CP0_Status_rw_bitmask = 0x1258FF17,
184 .SEGBITS = 32,
185 .PABITS = 32,
186 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
187 .mmu_type = MMU_TYPE_FMT,
188 },
189 {
190 .name = "4KEc",
191 .CP0_PRid = 0x00019000,
192 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
193 (MMU_TYPE_R4000 << CP0C0_MT),
194 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
195 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
196 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
197 (0 << CP0C1_CA),
198 .CP0_Config2 = MIPS_CONFIG2,
199 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
200 .CP0_LLAddr_rw_bitmask = 0,
201 .CP0_LLAddr_shift = 4,
202 .SYNCI_Step = 32,
203 .CCRes = 2,
204 .CP0_Status_rw_bitmask = 0x1278FF17,
205 .SEGBITS = 32,
206 .PABITS = 32,
207 .insn_flags = CPU_MIPS32R2,
208 .mmu_type = MMU_TYPE_R4000,
209 },
210 {
211 .name = "4KEm",
212 .CP0_PRid = 0x00019100,
213 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
214 (MMU_TYPE_FMT << CP0C0_MT),
215 .CP0_Config1 = MIPS_CONFIG1 |
216 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
217 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
218 (1 << CP0C1_CA),
219 .CP0_Config2 = MIPS_CONFIG2,
220 .CP0_Config3 = MIPS_CONFIG3,
221 .CP0_LLAddr_rw_bitmask = 0,
222 .CP0_LLAddr_shift = 4,
223 .SYNCI_Step = 32,
224 .CCRes = 2,
225 .CP0_Status_rw_bitmask = 0x1258FF17,
226 .SEGBITS = 32,
227 .PABITS = 32,
228 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
229 .mmu_type = MMU_TYPE_FMT,
230 },
231 {
232 .name = "24Kc",
233 .CP0_PRid = 0x00019300,
234 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
235 (MMU_TYPE_R4000 << CP0C0_MT),
236 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
237 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
238 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
239 (1 << CP0C1_CA),
240 .CP0_Config2 = MIPS_CONFIG2,
241 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
242 .CP0_LLAddr_rw_bitmask = 0,
243 .CP0_LLAddr_shift = 4,
244 .SYNCI_Step = 32,
245 .CCRes = 2,
246 /* No DSP implemented. */
247 .CP0_Status_rw_bitmask = 0x1278FF1F,
248 .SEGBITS = 32,
249 .PABITS = 32,
250 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
251 .mmu_type = MMU_TYPE_R4000,
252 },
253 {
254 .name = "24Kf",
255 .CP0_PRid = 0x00019300,
256 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
257 (MMU_TYPE_R4000 << CP0C0_MT),
258 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
259 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
260 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
261 (1 << CP0C1_CA),
262 .CP0_Config2 = MIPS_CONFIG2,
263 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
264 .CP0_LLAddr_rw_bitmask = 0,
265 .CP0_LLAddr_shift = 4,
266 .SYNCI_Step = 32,
267 .CCRes = 2,
268 /* No DSP implemented. */
269 .CP0_Status_rw_bitmask = 0x3678FF1F,
270 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
271 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
272 .SEGBITS = 32,
273 .PABITS = 32,
274 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
275 .mmu_type = MMU_TYPE_R4000,
276 },
277 {
278 .name = "34Kf",
279 .CP0_PRid = 0x00019500,
280 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
281 (MMU_TYPE_R4000 << CP0C0_MT),
282 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
283 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
284 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
285 (1 << CP0C1_CA),
286 .CP0_Config2 = MIPS_CONFIG2,
287 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
288 (1 << CP0C3_DSPP),
289 .CP0_LLAddr_rw_bitmask = 0,
290 .CP0_LLAddr_shift = 0,
291 .SYNCI_Step = 32,
292 .CCRes = 2,
293 .CP0_Status_rw_bitmask = 0x3778FF1F,
294 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
295 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
296 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
297 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
298 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
299 (0xff << CP0TCSt_TASID),
300 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
301 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
302 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
303 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
304 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
305 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
306 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
307 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
308 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
309 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
310 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
311 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
312 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
313 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
314 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
315 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
316 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
317 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
318 .SEGBITS = 32,
319 .PABITS = 32,
320 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
321 .mmu_type = MMU_TYPE_R4000,
322 },
323 {
324 .name = "74Kf",
325 .CP0_PRid = 0x00019700,
326 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
327 (MMU_TYPE_R4000 << CP0C0_MT),
328 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
329 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
330 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
331 (1 << CP0C1_CA),
332 .CP0_Config2 = MIPS_CONFIG2,
333 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
334 .CP0_LLAddr_rw_bitmask = 0,
335 .CP0_LLAddr_shift = 4,
336 .SYNCI_Step = 32,
337 .CCRes = 2,
338 .CP0_Status_rw_bitmask = 0x3778FF1F,
339 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
340 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
341 .SEGBITS = 32,
342 .PABITS = 32,
343 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
344 .mmu_type = MMU_TYPE_R4000,
345 },
346 {
347 /* A generic CPU providing MIPS32 Release 5 features.
348 FIXME: Eventually this should be replaced by a real CPU model. */
349 .name = "mips32r5-generic",
350 .CP0_PRid = 0x00019700,
351 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
352 (MMU_TYPE_R4000 << CP0C0_MT),
353 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
354 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
355 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
356 (1 << CP0C1_CA),
357 .CP0_Config2 = MIPS_CONFIG2,
358 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M),
359 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
360 .CP0_Config4_rw_bitmask = 0,
361 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
362 .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
363 (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
364 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
365 (0 << CP0C5_NFExists),
366 .CP0_LLAddr_rw_bitmask = 0,
367 .CP0_LLAddr_shift = 4,
368 .SYNCI_Step = 32,
369 .CCRes = 2,
370 .CP0_Status_rw_bitmask = 0x3778FF1F,
371 .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
372 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
373 (0x93 << FCR0_PRID),
374 .SEGBITS = 32,
375 .PABITS = 32,
376 .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
377 .mmu_type = MMU_TYPE_R4000,
378 },
379 #if defined(TARGET_MIPS64)
380 {
381 .name = "R4000",
382 .CP0_PRid = 0x00000400,
383 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
384 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
385 /* Note: Config1 is only used internally, the R4000 has only Config0. */
386 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
387 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
388 .CP0_LLAddr_shift = 4,
389 .SYNCI_Step = 16,
390 .CCRes = 2,
391 .CP0_Status_rw_bitmask = 0x3678FFFF,
392 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
393 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
394 .SEGBITS = 40,
395 .PABITS = 36,
396 .insn_flags = CPU_MIPS3,
397 .mmu_type = MMU_TYPE_R4000,
398 },
399 {
400 .name = "VR5432",
401 .CP0_PRid = 0x00005400,
402 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
403 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
404 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
405 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
406 .CP0_LLAddr_shift = 4,
407 .SYNCI_Step = 16,
408 .CCRes = 2,
409 .CP0_Status_rw_bitmask = 0x3678FFFF,
410 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
411 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
412 .SEGBITS = 40,
413 .PABITS = 32,
414 .insn_flags = CPU_VR54XX,
415 .mmu_type = MMU_TYPE_R4000,
416 },
417 {
418 .name = "5Kc",
419 .CP0_PRid = 0x00018100,
420 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
421 (MMU_TYPE_R4000 << CP0C0_MT),
422 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
423 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
424 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
425 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
426 .CP0_Config2 = MIPS_CONFIG2,
427 .CP0_Config3 = MIPS_CONFIG3,
428 .CP0_LLAddr_rw_bitmask = 0,
429 .CP0_LLAddr_shift = 4,
430 .SYNCI_Step = 32,
431 .CCRes = 2,
432 .CP0_Status_rw_bitmask = 0x32F8FFFF,
433 .SEGBITS = 42,
434 .PABITS = 36,
435 .insn_flags = CPU_MIPS64,
436 .mmu_type = MMU_TYPE_R4000,
437 },
438 {
439 .name = "5Kf",
440 .CP0_PRid = 0x00018100,
441 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
442 (MMU_TYPE_R4000 << CP0C0_MT),
443 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
444 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
445 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
446 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
447 .CP0_Config2 = MIPS_CONFIG2,
448 .CP0_Config3 = MIPS_CONFIG3,
449 .CP0_LLAddr_rw_bitmask = 0,
450 .CP0_LLAddr_shift = 4,
451 .SYNCI_Step = 32,
452 .CCRes = 2,
453 .CP0_Status_rw_bitmask = 0x36F8FFFF,
454 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
455 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
456 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
457 .SEGBITS = 42,
458 .PABITS = 36,
459 .insn_flags = CPU_MIPS64,
460 .mmu_type = MMU_TYPE_R4000,
461 },
462 {
463 .name = "20Kc",
464 /* We emulate a later version of the 20Kc, earlier ones had a broken
465 WAIT instruction. */
466 .CP0_PRid = 0x000182a0,
467 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
468 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
469 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
470 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
471 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
472 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
473 .CP0_Config2 = MIPS_CONFIG2,
474 .CP0_Config3 = MIPS_CONFIG3,
475 .CP0_LLAddr_rw_bitmask = 0,
476 .CP0_LLAddr_shift = 0,
477 .SYNCI_Step = 32,
478 .CCRes = 1,
479 .CP0_Status_rw_bitmask = 0x36FBFFFF,
480 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
481 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
482 (1 << FCR0_D) | (1 << FCR0_S) |
483 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
484 .SEGBITS = 40,
485 .PABITS = 36,
486 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
487 .mmu_type = MMU_TYPE_R4000,
488 },
489 {
490 /* A generic CPU providing MIPS64 Release 2 features.
491 FIXME: Eventually this should be replaced by a real CPU model. */
492 .name = "MIPS64R2-generic",
493 .CP0_PRid = 0x00010000,
494 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
495 (MMU_TYPE_R4000 << CP0C0_MT),
496 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
497 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
498 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
499 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
500 .CP0_Config2 = MIPS_CONFIG2,
501 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
502 .CP0_LLAddr_rw_bitmask = 0,
503 .CP0_LLAddr_shift = 0,
504 .SYNCI_Step = 32,
505 .CCRes = 2,
506 .CP0_Status_rw_bitmask = 0x36FBFFFF,
507 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
508 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
509 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
510 .SEGBITS = 42,
511 /* The architectural limit is 59, but we have hardcoded 36 bit
512 in some places...
513 .PABITS = 59, */ /* the architectural limit */
514 .PABITS = 36,
515 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
516 .mmu_type = MMU_TYPE_R4000,
517 },
518 {
519 .name = "Loongson-2E",
520 .CP0_PRid = 0x6302,
521 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
522 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
523 (0x1<<4) | (0x1<<1),
524 /* Note: Config1 is only used internally, Loongson-2E has only Config0. */
525 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
526 .SYNCI_Step = 16,
527 .CCRes = 2,
528 .CP0_Status_rw_bitmask = 0x35D0FFFF,
529 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
530 .SEGBITS = 40,
531 .PABITS = 40,
532 .insn_flags = CPU_LOONGSON2E,
533 .mmu_type = MMU_TYPE_R4000,
534 },
535 {
536 .name = "Loongson-2F",
537 .CP0_PRid = 0x6303,
538 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
539 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
540 (0x1<<4) | (0x1<<1),
541 /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
542 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
543 .SYNCI_Step = 16,
544 .CCRes = 2,
545 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/
546 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
547 .SEGBITS = 40,
548 .PABITS = 40,
549 .insn_flags = CPU_LOONGSON2F,
550 .mmu_type = MMU_TYPE_R4000,
551 },
552 {
553 /* A generic CPU providing MIPS64 ASE DSP 2 features.
554 FIXME: Eventually this should be replaced by a real CPU model. */
555 .name = "mips64dspr2",
556 .CP0_PRid = 0x00010000,
557 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
558 (MMU_TYPE_R4000 << CP0C0_MT),
559 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
560 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
561 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
562 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
563 .CP0_Config2 = MIPS_CONFIG2,
564 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
565 .CP0_LLAddr_rw_bitmask = 0,
566 .CP0_LLAddr_shift = 0,
567 .SYNCI_Step = 32,
568 .CCRes = 2,
569 .CP0_Status_rw_bitmask = 0x37FBFFFF,
570 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
571 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
572 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
573 .SEGBITS = 42,
574 /* The architectural limit is 59, but we have hardcoded 36 bit
575 in some places...
576 .PABITS = 59, */ /* the architectural limit */
577 .PABITS = 36,
578 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
579 .mmu_type = MMU_TYPE_R4000,
580 },
581
582 #endif
583 };
584
585 static const mips_def_t *cpu_mips_find_by_name (const char *name)
586 {
587 int i;
588
589 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
590 if (strcasecmp(name, mips_defs[i].name) == 0) {
591 return &mips_defs[i];
592 }
593 }
594 return NULL;
595 }
596
597 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
598 {
599 int i;
600
601 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
602 (*cpu_fprintf)(f, "MIPS '%s'\n",
603 mips_defs[i].name);
604 }
605 }
606
607 #ifndef CONFIG_USER_ONLY
608 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
609 {
610 env->tlb->nb_tlb = 1;
611 env->tlb->map_address = &no_mmu_map_address;
612 }
613
614 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
615 {
616 env->tlb->nb_tlb = 1;
617 env->tlb->map_address = &fixed_mmu_map_address;
618 }
619
620 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
621 {
622 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
623 env->tlb->map_address = &r4k_map_address;
624 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
625 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
626 env->tlb->helper_tlbp = r4k_helper_tlbp;
627 env->tlb->helper_tlbr = r4k_helper_tlbr;
628 }
629
630 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
631 {
632 MIPSCPU *cpu = mips_env_get_cpu(env);
633
634 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
635
636 switch (def->mmu_type) {
637 case MMU_TYPE_NONE:
638 no_mmu_init(env, def);
639 break;
640 case MMU_TYPE_R4000:
641 r4k_mmu_init(env, def);
642 break;
643 case MMU_TYPE_FMT:
644 fixed_mmu_init(env, def);
645 break;
646 case MMU_TYPE_R3000:
647 case MMU_TYPE_R6000:
648 case MMU_TYPE_R8000:
649 default:
650 cpu_abort(CPU(cpu), "MMU type not supported\n");
651 }
652 }
653 #endif /* CONFIG_USER_ONLY */
654
655 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
656 {
657 int i;
658
659 for (i = 0; i < MIPS_FPU_MAX; i++)
660 env->fpus[i].fcr0 = def->CP1_fcr0;
661
662 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
663 }
664
665 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
666 {
667 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
668
669 /* MVPConf1 implemented, TLB sharable, no gating storage support,
670 programmable cache partitioning implemented, number of allocatable
671 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
672 implemented, 5 TCs implemented. */
673 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
674 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
675 // TODO: actually do 2 VPEs.
676 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
677 // (0x04 << CP0MVPC0_PTC);
678 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
679 (0x00 << CP0MVPC0_PTC);
680 #if !defined(CONFIG_USER_ONLY)
681 /* Usermode has no TLB support */
682 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
683 #endif
684
685 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
686 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
687 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
688 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
689 (0x1 << CP0MVPC1_PCP1);
690 }
CRIS target port of Qemu