2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on pc.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "qemu/osdep.h"
32 #include "hw/loader.h"
33 #include "sysemu/arch_init.h"
34 #include "hw/i2c/smbus.h"
35 #include "hw/boards.h"
36 #include "hw/timer/mc146818rtc.h"
37 #include "hw/xen/xen.h"
38 #include "sysemu/kvm.h"
39 #include "hw/kvm/clock.h"
40 #include "hw/pci-host/q35.h"
41 #include "exec/address-spaces.h"
42 #include "hw/i386/ich9.h"
43 #include "hw/smbios/smbios.h"
44 #include "hw/ide/pci.h"
45 #include "hw/ide/ahci.h"
47 #include "qemu/error-report.h"
48 #include "migration/migration.h"
50 /* ICH9 AHCI has 6 ports */
51 #define MAX_SATA_PORTS 6
53 /* PC hardware initialisation */
54 static void pc_q35_init(MachineState
*machine
)
56 PCMachineState
*pcms
= PC_MACHINE(machine
);
57 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
62 BusState
*idebus
[MAX_SATA_PORTS
];
64 MemoryRegion
*pci_memory
;
65 MemoryRegion
*rom_memory
;
66 MemoryRegion
*ram_memory
;
72 ICH9LPCState
*ich9_lpc
;
75 DriveInfo
*hd
[MAX_SATA_PORTS
];
76 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
78 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
79 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
80 * also known as MMCFG).
81 * If it doesn't, we need to split it in chunks below and above 4G.
82 * In any case, try to make sure that guest addresses aligned at
83 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
84 * For old machine types, use whatever split we used historically to avoid
87 if (machine
->ram_size
>= 0xb0000000) {
88 lowmem
= pcmc
->gigabyte_align
? 0x80000000 : 0xb0000000;
93 /* Handle the machine opt max-ram-below-4g. It is basically doing
94 * min(qemu limit, user limit).
96 if (lowmem
> pcms
->max_ram_below_4g
) {
97 lowmem
= pcms
->max_ram_below_4g
;
98 if (machine
->ram_size
- lowmem
> lowmem
&&
99 lowmem
& ((1ULL << 30) - 1)) {
100 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
101 ") not a multiple of 1G; possible bad performance.",
102 pcms
->max_ram_below_4g
);
106 if (machine
->ram_size
>= lowmem
) {
107 pcms
->above_4g_mem_size
= machine
->ram_size
- lowmem
;
108 pcms
->below_4g_mem_size
= lowmem
;
110 pcms
->above_4g_mem_size
= 0;
111 pcms
->below_4g_mem_size
= machine
->ram_size
;
115 xen_hvm_init(pcms
, &ram_memory
);
119 if (!pcmc
->has_acpi_build
) {
120 /* only machine types 1.7 & older need this */
121 pc_acpi_init("q35-acpi-dsdt.aml");
127 if (pcmc
->pci_enabled
) {
128 pci_memory
= g_new(MemoryRegion
, 1);
129 memory_region_init(pci_memory
, NULL
, "pci", UINT64_MAX
);
130 rom_memory
= pci_memory
;
133 rom_memory
= get_system_memory();
136 pc_guest_info_init(pcms
);
138 if (pcmc
->smbios_defaults
) {
139 /* These values are guest ABI, do not change */
140 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
141 mc
->name
, pcmc
->smbios_legacy_mode
,
142 pcmc
->smbios_uuid_encoded
,
143 SMBIOS_ENTRY_POINT_21
);
146 /* allocate ram and load rom/bios */
147 if (!xen_enabled()) {
148 pc_memory_init(pcms
, get_system_memory(),
149 rom_memory
, &ram_memory
);
153 gsi_state
= g_malloc0(sizeof(*gsi_state
));
154 if (kvm_irqchip_in_kernel()) {
155 kvm_pc_setup_irq_routing(pcmc
->pci_enabled
);
156 gsi
= qemu_allocate_irqs(kvm_pc_gsi_handler
, gsi_state
,
159 gsi
= qemu_allocate_irqs(gsi_handler
, gsi_state
, GSI_NUM_PINS
);
162 /* create pci host bus */
163 q35_host
= Q35_HOST_DEVICE(qdev_create(NULL
, TYPE_Q35_HOST_DEVICE
));
165 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host
), NULL
);
166 q35_host
->mch
.ram_memory
= ram_memory
;
167 q35_host
->mch
.pci_address_space
= pci_memory
;
168 q35_host
->mch
.system_memory
= get_system_memory();
169 q35_host
->mch
.address_space_io
= get_system_io();
170 q35_host
->mch
.below_4g_mem_size
= pcms
->below_4g_mem_size
;
171 q35_host
->mch
.above_4g_mem_size
= pcms
->above_4g_mem_size
;
173 qdev_init_nofail(DEVICE(q35_host
));
174 phb
= PCI_HOST_BRIDGE(q35_host
);
176 pcms
->bus
= phb
->bus
;
178 lpc
= pci_create_simple_multifunction(host_bus
, PCI_DEVFN(ICH9_LPC_DEV
,
179 ICH9_LPC_FUNC
), true,
180 TYPE_ICH9_LPC_DEVICE
);
182 object_property_add_link(OBJECT(machine
), PC_MACHINE_ACPI_DEVICE_PROP
,
183 TYPE_HOTPLUG_HANDLER
,
184 (Object
**)&pcms
->acpi_dev
,
185 object_property_allow_set_link
,
186 OBJ_PROP_LINK_UNREF_ON_RELEASE
, &error_abort
);
187 object_property_set_link(OBJECT(machine
), OBJECT(lpc
),
188 PC_MACHINE_ACPI_DEVICE_PROP
, &error_abort
);
190 ich9_lpc
= ICH9_LPC_DEVICE(lpc
);
192 ich9_lpc
->ioapic
= gsi_state
->ioapic_irq
;
193 pci_bus_irqs(host_bus
, ich9_lpc_set_irq
, ich9_lpc_map_irq
, ich9_lpc
,
195 pci_bus_set_route_irq_fn(host_bus
, ich9_route_intx_pin_to_irq
);
196 isa_bus
= ich9_lpc
->isa_bus
;
199 isa_bus_irqs(isa_bus
, gsi
);
201 if (kvm_irqchip_in_kernel()) {
202 i8259
= kvm_i8259_init(isa_bus
);
203 } else if (xen_enabled()) {
204 i8259
= xen_interrupt_controller_init();
206 i8259
= i8259_init(isa_bus
, pc_allocate_cpu_irq());
209 for (i
= 0; i
< ISA_NUM_IRQS
; i
++) {
210 gsi_state
->i8259_irq
[i
] = i8259
[i
];
212 if (pcmc
->pci_enabled
) {
213 ioapic_init_gsi(gsi_state
, "q35");
216 pc_register_ferr_irq(gsi
[13]);
218 assert(pcms
->vmport
!= ON_OFF_AUTO__MAX
);
219 if (pcms
->vmport
== ON_OFF_AUTO_AUTO
) {
220 pcms
->vmport
= xen_enabled() ? ON_OFF_AUTO_OFF
: ON_OFF_AUTO_ON
;
223 /* init basic PC hardware */
224 pc_basic_device_init(isa_bus
, gsi
, &rtc_state
, !mc
->no_floppy
,
225 (pcms
->vmport
!= ON_OFF_AUTO_ON
), 0xff0104);
227 /* connect pm stuff to lpc */
228 ich9_lpc_pm_init(lpc
, pc_machine_is_smm_enabled(pcms
), !mc
->no_tco
);
230 /* ahci and SATA device, for q35 1 ahci controller is built-in */
231 ahci
= pci_create_simple_multifunction(host_bus
,
232 PCI_DEVFN(ICH9_SATA1_DEV
,
235 idebus
[0] = qdev_get_child_bus(&ahci
->qdev
, "ide.0");
236 idebus
[1] = qdev_get_child_bus(&ahci
->qdev
, "ide.1");
237 g_assert(MAX_SATA_PORTS
== ICH_AHCI(ahci
)->ahci
.ports
);
238 ide_drive_get(hd
, ICH_AHCI(ahci
)->ahci
.ports
);
239 ahci_ide_create_devs(ahci
, hd
);
242 /* Should we create 6 UHCI according to ich9 spec? */
243 ehci_create_ich9_with_companions(host_bus
, 0x1d);
246 /* TODO: Populate SPD eeprom data. */
247 smbus_eeprom_init(ich9_smb_init(host_bus
,
248 PCI_DEVFN(ICH9_SMB_DEV
, ICH9_SMB_FUNC
),
252 pc_cmos_init(pcms
, idebus
[0], idebus
[1], rtc_state
);
254 /* the rest devices to which pci devfn is automatically assigned */
255 pc_vga_init(isa_bus
, host_bus
);
256 pc_nic_init(isa_bus
, host_bus
);
257 if (pcmc
->pci_enabled
) {
258 pc_pci_device_init(host_bus
);
262 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
263 static void pc_init_##suffix(MachineState *machine) \
265 void (*compat)(MachineState *m) = (compatfn); \
269 pc_q35_init(machine); \
271 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
274 static void pc_q35_machine_options(MachineClass
*m
)
276 m
->family
= "pc_q35";
277 m
->desc
= "Standard PC (Q35 + ICH9, 2009)";
278 m
->hot_add_cpu
= pc_hot_add_cpu
;
279 m
->units_per_default_bus
= 1;
280 m
->default_machine_opts
= "firmware=bios-256k.bin";
281 m
->default_display
= "std";
286 static void pc_q35_2_6_machine_options(MachineClass
*m
)
288 pc_q35_machine_options(m
);
292 DEFINE_Q35_MACHINE(v2_6
, "pc-q35-2.6", NULL
,
293 pc_q35_2_6_machine_options
);
295 static void pc_q35_2_5_machine_options(MachineClass
*m
)
297 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
298 pc_q35_2_6_machine_options(m
);
300 pcmc
->save_tsc_khz
= false;
301 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_5
);
304 DEFINE_Q35_MACHINE(v2_5
, "pc-q35-2.5", NULL
,
305 pc_q35_2_5_machine_options
);
307 static void pc_q35_2_4_machine_options(MachineClass
*m
)
309 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
310 pc_q35_2_5_machine_options(m
);
311 m
->hw_version
= "2.4.0";
312 pcmc
->broken_reserved_end
= true;
313 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_4
);
316 DEFINE_Q35_MACHINE(v2_4
, "pc-q35-2.4", NULL
,
317 pc_q35_2_4_machine_options
);