hw/arm/boot.c

   1 /*
   2  * ARM kernel loader.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "config.h"
  11 #include "hw/hw.h"
  12 #include "hw/arm/arm.h"
  13 #include "sysemu/sysemu.h"
  14 #include "hw/boards.h"
  15 #include "hw/loader.h"
  16 #include "elf.h"
  17 #include "sysemu/device_tree.h"
  18 #include "qemu/config-file.h"
  19
  20 /* Kernel boot protocol is specified in the kernel docs
  21  * Documentation/arm/Booting and Documentation/arm64/booting.txt
  22  * They have different preferred image load offsets from system RAM base.
  23  */
  24 #define KERNEL_ARGS_ADDR 0x100
  25 #define KERNEL_LOAD_ADDR 0x00010000
  26 #define KERNEL64_LOAD_ADDR 0x00080000
  27
  28 typedef enum {
  29     FIXUP_NONE = 0,   /* do nothing */
  30     FIXUP_TERMINATOR, /* end of insns */
  31     FIXUP_BOARDID,    /* overwrite with board ID number */
  32     FIXUP_ARGPTR,     /* overwrite with pointer to kernel args */
  33     FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */
  34     FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
  35     FIXUP_BOOTREG,    /* overwrite with boot register address */
  36     FIXUP_DSB,        /* overwrite with correct DSB insn for cpu */
  37     FIXUP_MAX,
  38 } FixupType;
  39
  40 typedef struct ARMInsnFixup {
  41     uint32_t insn;
  42     FixupType fixup;
  43 } ARMInsnFixup;
  44
  45 static const ARMInsnFixup bootloader_aarch64[] = {
  46     { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
  47     { 0xaa1f03e1 }, /* mov x1, xzr */
  48     { 0xaa1f03e2 }, /* mov x2, xzr */
  49     { 0xaa1f03e3 }, /* mov x3, xzr */
  50     { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
  51     { 0xd61f0080 }, /* br x4      ; Jump to the kernel entry point */
  52     { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */
  53     { 0 }, /* .word @DTB Higher 32-bits */
  54     { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */
  55     { 0 }, /* .word @Kernel Entry Higher 32-bits */
  56     { 0, FIXUP_TERMINATOR }
  57 };
  58
  59 /* The worlds second smallest bootloader.  Set r0-r2, then jump to kernel.  */
  60 static const ARMInsnFixup bootloader[] = {
  61     { 0xe3a00000 }, /* mov     r0, #0 */
  62     { 0xe59f1004 }, /* ldr     r1, [pc, #4] */
  63     { 0xe59f2004 }, /* ldr     r2, [pc, #4] */
  64     { 0xe59ff004 }, /* ldr     pc, [pc, #4] */
  65     { 0, FIXUP_BOARDID },
  66     { 0, FIXUP_ARGPTR },
  67     { 0, FIXUP_ENTRYPOINT },
  68     { 0, FIXUP_TERMINATOR }
  69 };
  70
  71 /* Handling for secondary CPU boot in a multicore system.
  72  * Unlike the uniprocessor/primary CPU boot, this is platform
  73  * dependent. The default code here is based on the secondary
  74  * CPU boot protocol used on realview/vexpress boards, with
  75  * some parameterisation to increase its flexibility.
  76  * QEMU platform models for which this code is not appropriate
  77  * should override write_secondary_boot and secondary_cpu_reset_hook
  78  * instead.
  79  *
  80  * This code enables the interrupt controllers for the secondary
  81  * CPUs and then puts all the secondary CPUs into a loop waiting
  82  * for an interprocessor interrupt and polling a configurable
  83  * location for the kernel secondary CPU entry point.
  84  */
  85 #define DSB_INSN 0xf57ff04f
  86 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
  87
  88 static const ARMInsnFixup smpboot[] = {
  89     { 0xe59f2028 }, /* ldr r2, gic_cpu_if */
  90     { 0xe59f0028 }, /* ldr r0, bootreg_addr */
  91     { 0xe3a01001 }, /* mov r1, #1 */
  92     { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */
  93     { 0xe3a010ff }, /* mov r1, #0xff */
  94     { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */
  95     { 0, FIXUP_DSB },   /* dsb */
  96     { 0xe320f003 }, /* wfi */
  97     { 0xe5901000 }, /* ldr     r1, [r0] */
  98     { 0xe1110001 }, /* tst     r1, r1 */
  99     { 0x0afffffb }, /* beq     <wfi> */
 100     { 0xe12fff11 }, /* bx      r1 */
 101     { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */
 102     { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */
 103     { 0, FIXUP_TERMINATOR }
 104 };
 105
 106 static void write_bootloader(const char *name, hwaddr addr,
 107                              const ARMInsnFixup *insns, uint32_t *fixupcontext)
 108 {
 109     /* Fix up the specified bootloader fragment and write it into
 110      * guest memory using rom_add_blob_fixed(). fixupcontext is
 111      * an array giving the values to write in for the fixup types
 112      * which write a value into the code array.
 113      */
 114     int i, len;
 115     uint32_t *code;
 116
 117     len = 0;
 118     while (insns[len].fixup != FIXUP_TERMINATOR) {
 119         len++;
 120     }
 121
 122     code = g_new0(uint32_t, len);
 123
 124     for (i = 0; i < len; i++) {
 125         uint32_t insn = insns[i].insn;
 126         FixupType fixup = insns[i].fixup;
 127
 128         switch (fixup) {
 129         case FIXUP_NONE:
 130             break;
 131         case FIXUP_BOARDID:
 132         case FIXUP_ARGPTR:
 133         case FIXUP_ENTRYPOINT:
 134         case FIXUP_GIC_CPU_IF:
 135         case FIXUP_BOOTREG:
 136         case FIXUP_DSB:
 137             insn = fixupcontext[fixup];
 138             break;
 139         default:
 140             abort();
 141         }
 142         code[i] = tswap32(insn);
 143     }
 144
 145     rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr);
 146
 147     g_free(code);
 148 }
 149
 150 static void default_write_secondary(ARMCPU *cpu,
 151                                     const struct arm_boot_info *info)
 152 {
 153     uint32_t fixupcontext[FIXUP_MAX];
 154
 155     fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;
 156     fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;
 157     if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 158         fixupcontext[FIXUP_DSB] = DSB_INSN;
 159     } else {
 160         fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
 161     }
 162
 163     write_bootloader("smpboot", info->smp_loader_start,
 164                      smpboot, fixupcontext);
 165 }
 166
 167 static void default_reset_secondary(ARMCPU *cpu,
 168                                     const struct arm_boot_info *info)
 169 {
 170     CPUARMState *env = &cpu->env;
 171
 172     stl_phys_notdirty(info->smp_bootreg_addr, 0);
 173     env->regs[15] = info->smp_loader_start;
 174 }
 175
 176 static inline bool have_dtb(const struct arm_boot_info *info)
 177 {
 178     return info->dtb_filename || info->get_dtb;
 179 }
 180
 181 #define WRITE_WORD(p, value) do { \
 182     stl_phys_notdirty(p, value);  \
 183     p += 4;                       \
 184 } while (0)
 185
 186 static void set_kernel_args(const struct arm_boot_info *info)
 187 {
 188     int initrd_size = info->initrd_size;
 189     hwaddr base = info->loader_start;
 190     hwaddr p;
 191
 192     p = base + KERNEL_ARGS_ADDR;
 193     /* ATAG_CORE */
 194     WRITE_WORD(p, 5);
 195     WRITE_WORD(p, 0x54410001);
 196     WRITE_WORD(p, 1);
 197     WRITE_WORD(p, 0x1000);
 198     WRITE_WORD(p, 0);
 199     /* ATAG_MEM */
 200     /* TODO: handle multiple chips on one ATAG list */
 201     WRITE_WORD(p, 4);
 202     WRITE_WORD(p, 0x54410002);
 203     WRITE_WORD(p, info->ram_size);
 204     WRITE_WORD(p, info->loader_start);
 205     if (initrd_size) {
 206         /* ATAG_INITRD2 */
 207         WRITE_WORD(p, 4);
 208         WRITE_WORD(p, 0x54420005);
 209         WRITE_WORD(p, info->initrd_start);
 210         WRITE_WORD(p, initrd_size);
 211     }
 212     if (info->kernel_cmdline && *info->kernel_cmdline) {
 213         /* ATAG_CMDLINE */
 214         int cmdline_size;
 215
 216         cmdline_size = strlen(info->kernel_cmdline);
 217         cpu_physical_memory_write(p + 8, info->kernel_cmdline,
 218                                   cmdline_size + 1);
 219         cmdline_size = (cmdline_size >> 2) + 1;
 220         WRITE_WORD(p, cmdline_size + 2);
 221         WRITE_WORD(p, 0x54410009);
 222         p += cmdline_size * 4;
 223     }
 224     if (info->atag_board) {
 225         /* ATAG_BOARD */
 226         int atag_board_len;
 227         uint8_t atag_board_buf[0x1000];
 228
 229         atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
 230         WRITE_WORD(p, (atag_board_len + 8) >> 2);
 231         WRITE_WORD(p, 0x414f4d50);
 232         cpu_physical_memory_write(p, atag_board_buf, atag_board_len);
 233         p += atag_board_len;
 234     }
 235     /* ATAG_END */
 236     WRITE_WORD(p, 0);
 237     WRITE_WORD(p, 0);
 238 }
 239
 240 static void set_kernel_args_old(const struct arm_boot_info *info)
 241 {
 242     hwaddr p;
 243     const char *s;
 244     int initrd_size = info->initrd_size;
 245     hwaddr base = info->loader_start;
 246
 247     /* see linux/include/asm-arm/setup.h */
 248     p = base + KERNEL_ARGS_ADDR;
 249     /* page_size */
 250     WRITE_WORD(p, 4096);
 251     /* nr_pages */
 252     WRITE_WORD(p, info->ram_size / 4096);
 253     /* ramdisk_size */
 254     WRITE_WORD(p, 0);
 255 #define FLAG_READONLY   1
 256 #define FLAG_RDLOAD     4
 257 #define FLAG_RDPROMPT   8
 258     /* flags */
 259     WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
 260     /* rootdev */
 261     WRITE_WORD(p, (31 << 8) | 0);       /* /dev/mtdblock0 */
 262     /* video_num_cols */
 263     WRITE_WORD(p, 0);
 264     /* video_num_rows */
 265     WRITE_WORD(p, 0);
 266     /* video_x */
 267     WRITE_WORD(p, 0);
 268     /* video_y */
 269     WRITE_WORD(p, 0);
 270     /* memc_control_reg */
 271     WRITE_WORD(p, 0);
 272     /* unsigned char sounddefault */
 273     /* unsigned char adfsdrives */
 274     /* unsigned char bytes_per_char_h */
 275     /* unsigned char bytes_per_char_v */
 276     WRITE_WORD(p, 0);
 277     /* pages_in_bank[4] */
 278     WRITE_WORD(p, 0);
 279     WRITE_WORD(p, 0);
 280     WRITE_WORD(p, 0);
 281     WRITE_WORD(p, 0);
 282     /* pages_in_vram */
 283     WRITE_WORD(p, 0);
 284     /* initrd_start */
 285     if (initrd_size) {
 286         WRITE_WORD(p, info->initrd_start);
 287     } else {
 288         WRITE_WORD(p, 0);
 289     }
 290     /* initrd_size */
 291     WRITE_WORD(p, initrd_size);
 292     /* rd_start */
 293     WRITE_WORD(p, 0);
 294     /* system_rev */
 295     WRITE_WORD(p, 0);
 296     /* system_serial_low */
 297     WRITE_WORD(p, 0);
 298     /* system_serial_high */
 299     WRITE_WORD(p, 0);
 300     /* mem_fclk_21285 */
 301     WRITE_WORD(p, 0);
 302     /* zero unused fields */
 303     while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
 304         WRITE_WORD(p, 0);
 305     }
 306     s = info->kernel_cmdline;
 307     if (s) {
 308         cpu_physical_memory_write(p, s, strlen(s) + 1);
 309     } else {
 310         WRITE_WORD(p, 0);
 311     }
 312 }
 313
 314 static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo)
 315 {
 316     void *fdt = NULL;
 317     int size, rc;
 318     uint32_t acells, scells;
 319
 320     if (binfo->dtb_filename) {
 321         char *filename;
 322         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
 323         if (!filename) {
 324             fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
 325             goto fail;
 326         }
 327
 328         fdt = load_device_tree(filename, &size);
 329         if (!fdt) {
 330             fprintf(stderr, "Couldn't open dtb file %s\n", filename);
 331             g_free(filename);
 332             goto fail;
 333         }
 334         g_free(filename);
 335     } else if (binfo->get_dtb) {
 336         fdt = binfo->get_dtb(binfo, &size);
 337         if (!fdt) {
 338             fprintf(stderr, "Board was unable to create a dtb blob\n");
 339             goto fail;
 340         }
 341     }
 342
 343     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells");
 344     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells");
 345     if (acells == 0 || scells == 0) {
 346         fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
 347         goto fail;
 348     }
 349
 350     if (scells < 2 && binfo->ram_size >= (1ULL << 32)) {
 351         /* This is user error so deserves a friendlier error message
 352          * than the failure of setprop_sized_cells would provide
 353          */
 354         fprintf(stderr, "qemu: dtb file not compatible with "
 355                 "RAM size > 4GB\n");
 356         goto fail;
 357     }
 358
 359     rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg",
 360                                       acells, binfo->loader_start,
 361                                       scells, binfo->ram_size);
 362     if (rc < 0) {
 363         fprintf(stderr, "couldn't set /memory/reg\n");
 364         goto fail;
 365     }
 366
 367     if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
 368         rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
 369                                      binfo->kernel_cmdline);
 370         if (rc < 0) {
 371             fprintf(stderr, "couldn't set /chosen/bootargs\n");
 372             goto fail;
 373         }
 374     }
 375
 376     if (binfo->initrd_size) {
 377         rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 378                                    binfo->initrd_start);
 379         if (rc < 0) {
 380             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 381             goto fail;
 382         }
 383
 384         rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 385                                    binfo->initrd_start + binfo->initrd_size);
 386         if (rc < 0) {
 387             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 388             goto fail;
 389         }
 390     }
 391
 392     if (binfo->modify_dtb) {
 393         binfo->modify_dtb(binfo, fdt);
 394     }
 395
 396     qemu_fdt_dumpdtb(fdt, size);
 397
 398     cpu_physical_memory_write(addr, fdt, size);
 399
 400     g_free(fdt);
 401
 402     return 0;
 403
 404 fail:
 405     g_free(fdt);
 406     return -1;
 407 }
 408
 409 static void do_cpu_reset(void *opaque)
 410 {
 411     ARMCPU *cpu = opaque;
 412     CPUARMState *env = &cpu->env;
 413     const struct arm_boot_info *info = env->boot_info;
 414
 415     cpu_reset(CPU(cpu));
 416     if (info) {
 417         if (!info->is_linux) {
 418             /* Jump to the entry point.  */
 419             env->regs[15] = info->entry & 0xfffffffe;
 420             env->thumb = info->entry & 1;
 421         } else {
 422             if (CPU(cpu) == first_cpu) {
 423                 if (env->aarch64) {
 424                     env->pc = info->loader_start;
 425                 } else {
 426                     env->regs[15] = info->loader_start;
 427                 }
 428
 429                 if (!have_dtb(info)) {
 430                     if (old_param) {
 431                         set_kernel_args_old(info);
 432                     } else {
 433                         set_kernel_args(info);
 434                     }
 435                 }
 436             } else {
 437                 info->secondary_cpu_reset_hook(cpu, info);
 438             }
 439         }
 440     }
 441 }
 442
 443 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
 444 {
 445     CPUState *cs = CPU(cpu);
 446     int kernel_size;
 447     int initrd_size;
 448     int is_linux = 0;
 449     uint64_t elf_entry;
 450     hwaddr entry, kernel_load_offset;
 451     int big_endian;
 452     static const ARMInsnFixup *primary_loader;
 453
 454     /* Load the kernel.  */
 455     if (!info->kernel_filename) {
 456         /* If no kernel specified, do nothing; we will start from address 0
 457          * (typically a boot ROM image) in the same way as hardware.
 458          */
 459         return;
 460     }
 461
 462     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 463         primary_loader = bootloader_aarch64;
 464         kernel_load_offset = KERNEL64_LOAD_ADDR;
 465     } else {
 466         primary_loader = bootloader;
 467         kernel_load_offset = KERNEL_LOAD_ADDR;
 468     }
 469
 470     info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
 471
 472     if (!info->secondary_cpu_reset_hook) {
 473         info->secondary_cpu_reset_hook = default_reset_secondary;
 474     }
 475     if (!info->write_secondary_boot) {
 476         info->write_secondary_boot = default_write_secondary;
 477     }
 478
 479     if (info->nb_cpus == 0)
 480         info->nb_cpus = 1;
 481
 482 #ifdef TARGET_WORDS_BIGENDIAN
 483     big_endian = 1;
 484 #else
 485     big_endian = 0;
 486 #endif
 487
 488     /* We want to put the initrd far enough into RAM that when the
 489      * kernel is uncompressed it will not clobber the initrd. However
 490      * on boards without much RAM we must ensure that we still leave
 491      * enough room for a decent sized initrd, and on boards with large
 492      * amounts of RAM we must avoid the initrd being so far up in RAM
 493      * that it is outside lowmem and inaccessible to the kernel.
 494      * So for boards with less  than 256MB of RAM we put the initrd
 495      * halfway into RAM, and for boards with 256MB of RAM or more we put
 496      * the initrd at 128MB.
 497      */
 498     info->initrd_start = info->loader_start +
 499         MIN(info->ram_size / 2, 128 * 1024 * 1024);
 500
 501     /* Assume that raw images are linux kernels, and ELF images are not.  */
 502     kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
 503                            NULL, NULL, big_endian, ELF_MACHINE, 1);
 504     entry = elf_entry;
 505     if (kernel_size < 0) {
 506         kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
 507                                   &is_linux);
 508     }
 509     if (kernel_size < 0) {
 510         entry = info->loader_start + kernel_load_offset;
 511         kernel_size = load_image_targphys(info->kernel_filename, entry,
 512                                           info->ram_size - kernel_load_offset);
 513         is_linux = 1;
 514     }
 515     if (kernel_size < 0) {
 516         fprintf(stderr, "qemu: could not load kernel '%s'\n",
 517                 info->kernel_filename);
 518         exit(1);
 519     }
 520     info->entry = entry;
 521     if (is_linux) {
 522         uint32_t fixupcontext[FIXUP_MAX];
 523
 524         if (info->initrd_filename) {
 525             initrd_size = load_ramdisk(info->initrd_filename,
 526                                        info->initrd_start,
 527                                        info->ram_size -
 528                                        info->initrd_start);
 529             if (initrd_size < 0) {
 530                 initrd_size = load_image_targphys(info->initrd_filename,
 531                                                   info->initrd_start,
 532                                                   info->ram_size -
 533                                                   info->initrd_start);
 534             }
 535             if (initrd_size < 0) {
 536                 fprintf(stderr, "qemu: could not load initrd '%s'\n",
 537                         info->initrd_filename);
 538                 exit(1);
 539             }
 540         } else {
 541             initrd_size = 0;
 542         }
 543         info->initrd_size = initrd_size;
 544
 545         fixupcontext[FIXUP_BOARDID] = info->board_id;
 546
 547         /* for device tree boot, we pass the DTB directly in r2. Otherwise
 548          * we point to the kernel args.
 549          */
 550         if (have_dtb(info)) {
 551             /* Place the DTB after the initrd in memory. Note that some
 552              * kernels will trash anything in the 4K page the initrd
 553              * ends in, so make sure the DTB isn't caught up in that.
 554              */
 555             hwaddr dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
 556                                              4096);
 557             if (load_dtb(dtb_start, info)) {
 558                 exit(1);
 559             }
 560             fixupcontext[FIXUP_ARGPTR] = dtb_start;
 561         } else {
 562             fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR;
 563             if (info->ram_size >= (1ULL << 32)) {
 564                 fprintf(stderr, "qemu: RAM size must be less than 4GB to boot"
 565                         " Linux kernel using ATAGS (try passing a device tree"
 566                         " using -dtb)\n");
 567                 exit(1);
 568             }
 569         }
 570         fixupcontext[FIXUP_ENTRYPOINT] = entry;
 571
 572         write_bootloader("bootloader", info->loader_start,
 573                          primary_loader, fixupcontext);
 574
 575         if (info->nb_cpus > 1) {
 576             info->write_secondary_boot(cpu, info);
 577         }
 578     }
 579     info->is_linux = is_linux;
 580
 581     for (; cs; cs = CPU_NEXT(cs)) {
 582         cpu = ARM_CPU(cs);
 583         cpu->env.boot_info = info;
 584         qemu_register_reset(do_cpu_reset, cpu);
 585     }
 586 }