2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "qemu-common.h"
32 #include "qemu-option.h"
33 #include "qemu-config.h"
35 /* feature flags taken from "Intel Processor Identification and the CPUID
36 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
37 * between feature naming conventions, aliases may be added.
39 static const char *feature_name
[] = {
40 "fpu", "vme", "de", "pse",
41 "tsc", "msr", "pae", "mce",
42 "cx8", "apic", NULL
, "sep",
43 "mtrr", "pge", "mca", "cmov",
44 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
45 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
46 "fxsr", "sse", "sse2", "ss",
47 "ht" /* Intel htt */, "tm", "ia64", "pbe",
49 static const char *ext_feature_name
[] = {
50 "pni|sse3" /* Intel,AMD sse3 */, NULL
, NULL
, "monitor",
51 "ds_cpl", "vmx", NULL
/* Linux smx */, "est",
52 "tm2", "ssse3", "cid", NULL
,
53 NULL
, "cx16", "xtpr", NULL
,
54 NULL
, NULL
, "dca", "sse4.1|sse4_1",
55 "sse4.2|sse4_2", "x2apic", NULL
, "popcnt",
56 NULL
, NULL
, NULL
, NULL
,
57 NULL
, NULL
, NULL
, "hypervisor",
59 static const char *ext2_feature_name
[] = {
60 "fpu", "vme", "de", "pse",
61 "tsc", "msr", "pae", "mce",
62 "cx8" /* AMD CMPXCHG8B */, "apic", NULL
, "syscall",
63 "mtrr", "pge", "mca", "cmov",
64 "pat", "pse36", NULL
, NULL
/* Linux mp */,
65 "nx" /* Intel xd */, NULL
, "mmxext", "mmx",
66 "fxsr", "fxsr_opt" /* AMD ffxsr */, "pdpe1gb" /* AMD Page1GB */, "rdtscp",
67 NULL
, "lm" /* Intel 64 */, "3dnowext", "3dnow",
69 static const char *ext3_feature_name
[] = {
70 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
71 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
72 "3dnowprefetch", "osvw", NULL
/* Linux ibs */, NULL
,
73 "skinit", "wdt", NULL
, NULL
,
74 NULL
, NULL
, NULL
, NULL
,
75 NULL
, NULL
, NULL
, NULL
,
76 NULL
, NULL
, NULL
, NULL
,
77 NULL
, NULL
, NULL
, NULL
,
80 static const char *kvm_feature_name
[] = {
81 "kvmclock", "kvm_nopiodelay", "kvm_mmu", NULL
, NULL
, NULL
, NULL
, NULL
,
82 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
83 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
84 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
87 /* collects per-function cpuid data
89 typedef struct model_features_t
{
93 const char **flag_names
;
98 int enforce_cpuid
= 0;
100 static void host_cpuid(uint32_t function
, uint32_t count
, uint32_t *eax
,
101 uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
);
103 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
105 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
106 * a substring. ex if !NULL points to the first char after a substring,
107 * otherwise the string is assumed to sized by a terminating nul.
108 * Return lexical ordering of *s1:*s2.
110 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
114 if (!*s1
|| !*s2
|| *s1
!= *s2
)
117 if (s1
== e1
&& s2
== e2
)
126 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
127 * '|' delimited (possibly empty) strings in which case search for a match
128 * within the alternatives proceeds left to right. Return 0 for success,
129 * non-zero otherwise.
131 static int altcmp(const char *s
, const char *e
, const char *altstr
)
135 for (q
= p
= altstr
; ; ) {
136 while (*p
&& *p
!= '|')
138 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
147 /* search featureset for flag *[s..e), if found set corresponding bit in
148 * *pval and return success, otherwise return zero
150 static int lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
151 const char **featureset
)
156 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
)
157 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
161 return (mask
? 1 : 0);
164 static void add_flagname_to_bitmaps(const char *flagname
, uint32_t *features
,
165 uint32_t *ext_features
,
166 uint32_t *ext2_features
,
167 uint32_t *ext3_features
,
168 uint32_t *kvm_features
)
170 if (!lookup_feature(features
, flagname
, NULL
, feature_name
) &&
171 !lookup_feature(ext_features
, flagname
, NULL
, ext_feature_name
) &&
172 !lookup_feature(ext2_features
, flagname
, NULL
, ext2_feature_name
) &&
173 !lookup_feature(ext3_features
, flagname
, NULL
, ext3_feature_name
) &&
174 !lookup_feature(kvm_features
, flagname
, NULL
, kvm_feature_name
))
175 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
178 typedef struct x86_def_t
{
179 struct x86_def_t
*next
;
182 uint32_t vendor1
, vendor2
, vendor3
;
186 uint32_t features
, ext_features
, ext2_features
, ext3_features
, kvm_features
;
193 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
194 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
195 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
196 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
197 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
198 CPUID_PSE36 | CPUID_FXSR)
199 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
200 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
201 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
202 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
203 CPUID_PAE | CPUID_SEP | CPUID_APIC)
205 /* maintains list of cpu model definitions
207 static x86_def_t
*x86_defs
= {NULL
};
209 /* built-in cpu model definitions (deprecated)
211 static x86_def_t builtin_x86_defs
[] = {
216 .vendor1
= CPUID_VENDOR_AMD_1
,
217 .vendor2
= CPUID_VENDOR_AMD_2
,
218 .vendor3
= CPUID_VENDOR_AMD_3
,
222 .features
= PPRO_FEATURES
|
223 /* these features are needed for Win64 and aren't fully implemented */
224 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
225 /* this feature is needed for Solaris and isn't fully implemented */
227 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
228 .ext2_features
= (PPRO_FEATURES
& 0x0183F3FF) |
229 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
230 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
231 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
232 .xlevel
= 0x8000000A,
233 .model_id
= "QEMU Virtual CPU version " QEMU_VERSION
,
238 .vendor1
= CPUID_VENDOR_AMD_1
,
239 .vendor2
= CPUID_VENDOR_AMD_2
,
240 .vendor3
= CPUID_VENDOR_AMD_3
,
244 /* Missing: CPUID_VME, CPUID_HT */
245 .features
= PPRO_FEATURES
|
246 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
248 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
250 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
251 .ext2_features
= (PPRO_FEATURES
& 0x0183F3FF) |
252 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
253 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
255 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
257 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
258 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
259 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
260 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
261 .xlevel
= 0x8000001A,
262 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
270 /* The original CPU also implements these features:
271 CPUID_VME, CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT,
272 CPUID_TM, CPUID_PBE */
273 .features
= PPRO_FEATURES
|
274 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
276 /* The original CPU also implements these ext features:
277 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
278 CPUID_EXT_TM2, CPUID_EXT_CX16, CPUID_EXT_XTPR, CPUID_EXT_PDCM */
279 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
,
280 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
281 .ext3_features
= CPUID_EXT3_LAHF_LM
,
282 .xlevel
= 0x80000008,
283 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
288 .vendor1
= CPUID_VENDOR_INTEL_1
,
289 .vendor2
= CPUID_VENDOR_INTEL_2
,
290 .vendor3
= CPUID_VENDOR_INTEL_3
,
294 /* Missing: CPUID_VME, CPUID_HT */
295 .features
= PPRO_FEATURES
|
296 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
298 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
299 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
300 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
301 .ext2_features
= (PPRO_FEATURES
& 0x0183F3FF) |
302 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
303 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
304 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
305 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
306 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
308 .xlevel
= 0x80000008,
309 .model_id
= "Common KVM processor"
318 .features
= PPRO_FEATURES
,
319 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
321 .model_id
= "QEMU Virtual CPU version " QEMU_VERSION
,
329 /* The original CPU also implements these features:
330 CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT,
331 CPUID_TM, CPUID_PBE */
332 .features
= PPRO_FEATURES
| CPUID_VME
|
333 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
,
334 /* The original CPU also implements these ext features:
335 CPUID_EXT_VMX, CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_XTPR,
337 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
338 .ext2_features
= CPUID_EXT2_NX
,
339 .xlevel
= 0x80000008,
340 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
348 .features
= I486_FEATURES
,
357 .features
= PENTIUM_FEATURES
,
366 .features
= PENTIUM2_FEATURES
,
375 .features
= PENTIUM3_FEATURES
,
381 .vendor1
= CPUID_VENDOR_AMD_1
,
382 .vendor2
= CPUID_VENDOR_AMD_2
,
383 .vendor3
= CPUID_VENDOR_AMD_3
,
387 .features
= PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
| CPUID_MCA
,
388 .ext2_features
= (PPRO_FEATURES
& 0x0183F3FF) | CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
389 .xlevel
= 0x80000008,
390 /* XXX: put another string ? */
391 .model_id
= "QEMU Virtual CPU version " QEMU_VERSION
,
395 /* original is on level 10 */
400 .features
= PPRO_FEATURES
|
401 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
,
402 /* Missing: CPUID_DTS | CPUID_ACPI | CPUID_SS |
403 * CPUID_HT | CPUID_TM | CPUID_PBE */
404 /* Some CPUs got no CPUID_SEP */
405 .ext_features
= CPUID_EXT_MONITOR
|
406 CPUID_EXT_SSE3
/* PNI */ | CPUID_EXT_SSSE3
,
407 /* Missing: CPUID_EXT_DSCPL | CPUID_EXT_EST |
408 * CPUID_EXT_TM2 | CPUID_EXT_XTPR */
409 .ext2_features
= (PPRO_FEATURES
& 0x0183F3FF) | CPUID_EXT2_NX
,
410 /* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */
411 .xlevel
= 0x8000000A,
412 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
416 static int cpu_x86_fill_model_id(char *str
)
418 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
421 for (i
= 0; i
< 3; i
++) {
422 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
423 memcpy(str
+ i
* 16 + 0, &eax
, 4);
424 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
425 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
426 memcpy(str
+ i
* 16 + 12, &edx
, 4);
431 static int cpu_x86_fill_host(x86_def_t
*x86_cpu_def
)
433 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
435 x86_cpu_def
->name
= "host";
436 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
437 x86_cpu_def
->level
= eax
;
438 x86_cpu_def
->vendor1
= ebx
;
439 x86_cpu_def
->vendor2
= edx
;
440 x86_cpu_def
->vendor3
= ecx
;
442 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
443 x86_cpu_def
->family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
444 x86_cpu_def
->model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
445 x86_cpu_def
->stepping
= eax
& 0x0F;
446 x86_cpu_def
->ext_features
= ecx
;
447 x86_cpu_def
->features
= edx
;
449 host_cpuid(0x80000000, 0, &eax
, &ebx
, &ecx
, &edx
);
450 x86_cpu_def
->xlevel
= eax
;
452 host_cpuid(0x80000001, 0, &eax
, &ebx
, &ecx
, &edx
);
453 x86_cpu_def
->ext2_features
= edx
;
454 x86_cpu_def
->ext3_features
= ecx
;
455 cpu_x86_fill_model_id(x86_cpu_def
->model_id
);
456 x86_cpu_def
->vendor_override
= 0;
461 static int unavailable_host_feature(struct model_features_t
*f
, uint32_t mask
)
465 for (i
= 0; i
< 32; ++i
)
467 fprintf(stderr
, "warning: host cpuid %04x_%04x lacks requested"
468 " flag '%s' [0x%08x]\n",
469 f
->cpuid
>> 16, f
->cpuid
& 0xffff,
470 f
->flag_names
[i
] ? f
->flag_names
[i
] : "[reserved]", mask
);
476 /* best effort attempt to inform user requested cpu flags aren't making
477 * their way to the guest. Note: ft[].check_feat ideally should be
478 * specified via a guest_def field to suppress report of extraneous flags.
480 static int check_features_against_host(x86_def_t
*guest_def
)
485 struct model_features_t ft
[] = {
486 {&guest_def
->features
, &host_def
.features
,
487 ~0, feature_name
, 0x00000000},
488 {&guest_def
->ext_features
, &host_def
.ext_features
,
489 ~CPUID_EXT_HYPERVISOR
, ext_feature_name
, 0x00000001},
490 {&guest_def
->ext2_features
, &host_def
.ext2_features
,
491 ~PPRO_FEATURES
, ext2_feature_name
, 0x80000000},
492 {&guest_def
->ext3_features
, &host_def
.ext3_features
,
493 ~CPUID_EXT3_SVM
, ext3_feature_name
, 0x80000001}};
495 cpu_x86_fill_host(&host_def
);
496 for (rv
= 0, i
= 0; i
< sizeof (ft
) / sizeof (ft
[0]); ++i
)
497 for (mask
= 1; mask
; mask
<<= 1)
498 if (ft
[i
].check_feat
& mask
&& *ft
[i
].guest_feat
& mask
&&
499 !(*ft
[i
].host_feat
& mask
)) {
500 unavailable_host_feature(&ft
[i
], mask
);
506 static int cpu_x86_find_by_name(x86_def_t
*x86_cpu_def
, const char *cpu_model
)
511 char *s
= strdup(cpu_model
);
512 char *featurestr
, *name
= strtok(s
, ",");
513 uint32_t plus_features
= 0, plus_ext_features
= 0, plus_ext2_features
= 0, plus_ext3_features
= 0, plus_kvm_features
= 0;
514 uint32_t minus_features
= 0, minus_ext_features
= 0, minus_ext2_features
= 0, minus_ext3_features
= 0, minus_kvm_features
= 0;
517 for (def
= x86_defs
; def
; def
= def
->next
)
518 if (!strcmp(name
, def
->name
))
520 if (kvm_enabled() && strcmp(name
, "host") == 0) {
521 cpu_x86_fill_host(x86_cpu_def
);
525 memcpy(x86_cpu_def
, def
, sizeof(*def
));
528 plus_kvm_features
= ~0; /* not supported bits will be filtered out later */
530 add_flagname_to_bitmaps("hypervisor", &plus_features
,
531 &plus_ext_features
, &plus_ext2_features
, &plus_ext3_features
,
534 featurestr
= strtok(NULL
, ",");
538 if (featurestr
[0] == '+') {
539 add_flagname_to_bitmaps(featurestr
+ 1, &plus_features
, &plus_ext_features
, &plus_ext2_features
, &plus_ext3_features
, &plus_kvm_features
);
540 } else if (featurestr
[0] == '-') {
541 add_flagname_to_bitmaps(featurestr
+ 1, &minus_features
, &minus_ext_features
, &minus_ext2_features
, &minus_ext3_features
, &minus_kvm_features
);
542 } else if ((val
= strchr(featurestr
, '='))) {
544 if (!strcmp(featurestr
, "family")) {
546 numvalue
= strtoul(val
, &err
, 0);
548 fprintf(stderr
, "bad numerical value %s\n", val
);
551 x86_cpu_def
->family
= numvalue
;
552 } else if (!strcmp(featurestr
, "model")) {
554 numvalue
= strtoul(val
, &err
, 0);
555 if (!*val
|| *err
|| numvalue
> 0xff) {
556 fprintf(stderr
, "bad numerical value %s\n", val
);
559 x86_cpu_def
->model
= numvalue
;
560 } else if (!strcmp(featurestr
, "stepping")) {
562 numvalue
= strtoul(val
, &err
, 0);
563 if (!*val
|| *err
|| numvalue
> 0xf) {
564 fprintf(stderr
, "bad numerical value %s\n", val
);
567 x86_cpu_def
->stepping
= numvalue
;
568 } else if (!strcmp(featurestr
, "level")) {
570 numvalue
= strtoul(val
, &err
, 0);
572 fprintf(stderr
, "bad numerical value %s\n", val
);
575 x86_cpu_def
->level
= numvalue
;
576 } else if (!strcmp(featurestr
, "xlevel")) {
578 numvalue
= strtoul(val
, &err
, 0);
580 fprintf(stderr
, "bad numerical value %s\n", val
);
583 if (numvalue
< 0x80000000) {
584 numvalue
+= 0x80000000;
586 x86_cpu_def
->xlevel
= numvalue
;
587 } else if (!strcmp(featurestr
, "vendor")) {
588 if (strlen(val
) != 12) {
589 fprintf(stderr
, "vendor string must be 12 chars long\n");
592 x86_cpu_def
->vendor1
= 0;
593 x86_cpu_def
->vendor2
= 0;
594 x86_cpu_def
->vendor3
= 0;
595 for(i
= 0; i
< 4; i
++) {
596 x86_cpu_def
->vendor1
|= ((uint8_t)val
[i
]) << (8 * i
);
597 x86_cpu_def
->vendor2
|= ((uint8_t)val
[i
+ 4]) << (8 * i
);
598 x86_cpu_def
->vendor3
|= ((uint8_t)val
[i
+ 8]) << (8 * i
);
600 x86_cpu_def
->vendor_override
= 1;
601 } else if (!strcmp(featurestr
, "model_id")) {
602 pstrcpy(x86_cpu_def
->model_id
, sizeof(x86_cpu_def
->model_id
),
605 fprintf(stderr
, "unrecognized feature %s\n", featurestr
);
608 } else if (!strcmp(featurestr
, "check")) {
610 } else if (!strcmp(featurestr
, "enforce")) {
611 check_cpuid
= enforce_cpuid
= 1;
613 fprintf(stderr
, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr
);
616 featurestr
= strtok(NULL
, ",");
618 x86_cpu_def
->features
|= plus_features
;
619 x86_cpu_def
->ext_features
|= plus_ext_features
;
620 x86_cpu_def
->ext2_features
|= plus_ext2_features
;
621 x86_cpu_def
->ext3_features
|= plus_ext3_features
;
622 x86_cpu_def
->kvm_features
|= plus_kvm_features
;
623 x86_cpu_def
->features
&= ~minus_features
;
624 x86_cpu_def
->ext_features
&= ~minus_ext_features
;
625 x86_cpu_def
->ext2_features
&= ~minus_ext2_features
;
626 x86_cpu_def
->ext3_features
&= ~minus_ext3_features
;
627 x86_cpu_def
->kvm_features
&= ~minus_kvm_features
;
629 if (check_features_against_host(x86_cpu_def
) && enforce_cpuid
)
640 /* generate a composite string into buf of all cpuid names in featureset
641 * selected by fbits. indicate truncation at bufsize in the event of overflow.
642 * if flags, suppress names undefined in featureset.
644 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
645 const char **featureset
, uint32_t flags
)
647 const char **p
= &featureset
[31];
651 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
653 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
654 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
656 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
658 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
661 memcpy(b
, "...", sizeof("..."));
670 /* generate CPU information:
671 * -? list model names
672 * -?model list model names/IDs
673 * -?dump output all model (x86_def_t) data
674 * -?cpuid list all recognized cpuid flag names
676 void x86_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
679 unsigned char model
= !strcmp("?model", optarg
);
680 unsigned char dump
= !strcmp("?dump", optarg
);
681 unsigned char cpuid
= !strcmp("?cpuid", optarg
);
686 (*cpu_fprintf
)(f
, "Recognized CPUID flags:\n");
687 listflags(buf
, sizeof (buf
), (uint32_t)~0, feature_name
, 1);
688 (*cpu_fprintf
)(f
, " f_edx: %s\n", buf
);
689 listflags(buf
, sizeof (buf
), (uint32_t)~0, ext_feature_name
, 1);
690 (*cpu_fprintf
)(f
, " f_ecx: %s\n", buf
);
691 listflags(buf
, sizeof (buf
), (uint32_t)~0, ext2_feature_name
, 1);
692 (*cpu_fprintf
)(f
, " extf_edx: %s\n", buf
);
693 listflags(buf
, sizeof (buf
), (uint32_t)~0, ext3_feature_name
, 1);
694 (*cpu_fprintf
)(f
, " extf_ecx: %s\n", buf
);
697 for (def
= x86_defs
; def
; def
= def
->next
) {
698 snprintf(buf
, sizeof (buf
), def
->flags
? "[%s]": "%s", def
->name
);
700 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
702 (*cpu_fprintf
)(f
, "x86 %16s\n", buf
);
705 memcpy(buf
, &def
->vendor1
, sizeof (def
->vendor1
));
706 memcpy(buf
+ 4, &def
->vendor2
, sizeof (def
->vendor2
));
707 memcpy(buf
+ 8, &def
->vendor3
, sizeof (def
->vendor3
));
710 " family %d model %d stepping %d level %d xlevel 0x%x"
712 def
->family
, def
->model
, def
->stepping
, def
->level
,
714 listflags(buf
, sizeof (buf
), def
->features
, feature_name
, 0);
715 (*cpu_fprintf
)(f
, " feature_edx %08x (%s)\n", def
->features
,
717 listflags(buf
, sizeof (buf
), def
->ext_features
, ext_feature_name
,
719 (*cpu_fprintf
)(f
, " feature_ecx %08x (%s)\n", def
->ext_features
,
721 listflags(buf
, sizeof (buf
), def
->ext2_features
, ext2_feature_name
,
723 (*cpu_fprintf
)(f
, " extfeature_edx %08x (%s)\n",
724 def
->ext2_features
, buf
);
725 listflags(buf
, sizeof (buf
), def
->ext3_features
, ext3_feature_name
,
727 (*cpu_fprintf
)(f
, " extfeature_ecx %08x (%s)\n",
728 def
->ext3_features
, buf
);
729 (*cpu_fprintf
)(f
, "\n");
734 static int cpu_x86_register (CPUX86State
*env
, const char *cpu_model
)
736 x86_def_t def1
, *def
= &def1
;
738 if (cpu_x86_find_by_name(def
, cpu_model
) < 0)
741 env
->cpuid_vendor1
= def
->vendor1
;
742 env
->cpuid_vendor2
= def
->vendor2
;
743 env
->cpuid_vendor3
= def
->vendor3
;
745 env
->cpuid_vendor1
= CPUID_VENDOR_INTEL_1
;
746 env
->cpuid_vendor2
= CPUID_VENDOR_INTEL_2
;
747 env
->cpuid_vendor3
= CPUID_VENDOR_INTEL_3
;
749 env
->cpuid_vendor_override
= def
->vendor_override
;
750 env
->cpuid_level
= def
->level
;
751 if (def
->family
> 0x0f)
752 env
->cpuid_version
= 0xf00 | ((def
->family
- 0x0f) << 20);
754 env
->cpuid_version
= def
->family
<< 8;
755 env
->cpuid_version
|= ((def
->model
& 0xf) << 4) | ((def
->model
>> 4) << 16);
756 env
->cpuid_version
|= def
->stepping
;
757 env
->cpuid_features
= def
->features
;
758 env
->pat
= 0x0007040600070406ULL
;
759 env
->cpuid_ext_features
= def
->ext_features
;
760 env
->cpuid_ext2_features
= def
->ext2_features
;
761 env
->cpuid_xlevel
= def
->xlevel
;
762 env
->cpuid_kvm_features
= def
->kvm_features
;
764 const char *model_id
= def
->model_id
;
768 len
= strlen(model_id
);
769 for(i
= 0; i
< 48; i
++) {
773 c
= (uint8_t)model_id
[i
];
774 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
780 #if !defined(CONFIG_USER_ONLY)
781 /* copy vendor id string to 32 bit register, nul pad as needed
783 static void cpyid(const char *s
, uint32_t *id
)
785 char *d
= (char *)id
;
788 for (i
= sizeof (*id
); i
--; )
789 *d
++ = *s
? *s
++ : '\0';
792 /* interpret radix and convert from string to arbitrary scalar,
793 * otherwise flag failure
795 #define setscalar(pval, str, perr) \
800 ul = strtoul(str, &pend, 0); \
801 *str && !*pend ? (*pval = ul) : (*perr = 1); \
804 /* map cpuid options to feature bits, otherwise return failure
805 * (option tags in *str are delimited by whitespace)
807 static void setfeatures(uint32_t *pval
, const char *str
,
808 const char **featureset
, int *perr
)
812 for (q
= p
= str
; *p
|| *q
; q
= p
) {
815 while (*p
&& !iswhite(*p
))
819 if (!lookup_feature(pval
, q
, p
, featureset
)) {
820 fprintf(stderr
, "error: feature \"%.*s\" not available in set\n",
828 /* map config file options to x86_def_t form
830 static int cpudef_setfield(const char *name
, const char *str
, void *opaque
)
832 x86_def_t
*def
= opaque
;
835 if (!strcmp(name
, "name")) {
836 def
->name
= strdup(str
);
837 } else if (!strcmp(name
, "model_id")) {
838 strncpy(def
->model_id
, str
, sizeof (def
->model_id
));
839 } else if (!strcmp(name
, "level")) {
840 setscalar(&def
->level
, str
, &err
)
841 } else if (!strcmp(name
, "vendor")) {
842 cpyid(&str
[0], &def
->vendor1
);
843 cpyid(&str
[4], &def
->vendor2
);
844 cpyid(&str
[8], &def
->vendor3
);
845 } else if (!strcmp(name
, "family")) {
846 setscalar(&def
->family
, str
, &err
)
847 } else if (!strcmp(name
, "model")) {
848 setscalar(&def
->model
, str
, &err
)
849 } else if (!strcmp(name
, "stepping")) {
850 setscalar(&def
->stepping
, str
, &err
)
851 } else if (!strcmp(name
, "feature_edx")) {
852 setfeatures(&def
->features
, str
, feature_name
, &err
);
853 } else if (!strcmp(name
, "feature_ecx")) {
854 setfeatures(&def
->ext_features
, str
, ext_feature_name
, &err
);
855 } else if (!strcmp(name
, "extfeature_edx")) {
856 setfeatures(&def
->ext2_features
, str
, ext2_feature_name
, &err
);
857 } else if (!strcmp(name
, "extfeature_ecx")) {
858 setfeatures(&def
->ext3_features
, str
, ext3_feature_name
, &err
);
859 } else if (!strcmp(name
, "xlevel")) {
860 setscalar(&def
->xlevel
, str
, &err
)
862 fprintf(stderr
, "error: unknown option [%s = %s]\n", name
, str
);
866 fprintf(stderr
, "error: bad option value [%s = %s]\n", name
, str
);
872 /* register config file entry as x86_def_t
874 static int cpudef_register(QemuOpts
*opts
, void *opaque
)
876 x86_def_t
*def
= qemu_mallocz(sizeof (x86_def_t
));
878 qemu_opt_foreach(opts
, cpudef_setfield
, def
, 1);
879 def
->next
= x86_defs
;
883 #endif /* !CONFIG_USER_ONLY */
885 /* register "cpudef" models defined in configuration file. Here we first
886 * preload any built-in definitions
888 void x86_cpudef_setup(void)
892 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
893 builtin_x86_defs
[i
].next
= x86_defs
;
894 builtin_x86_defs
[i
].flags
= 1;
895 x86_defs
= &builtin_x86_defs
[i
];
897 #if !defined(CONFIG_USER_ONLY)
898 qemu_opts_foreach(&qemu_cpudef_opts
, cpudef_register
, NULL
, 0);
902 /* NOTE: must be called outside the CPU execute loop */
903 void cpu_reset(CPUX86State
*env
)
907 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
908 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
909 log_cpu_state(env
, X86_DUMP_FPU
| X86_DUMP_CCOP
);
912 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
916 env
->old_exception
= -1;
918 /* init to reset state */
920 #ifdef CONFIG_SOFTMMU
921 env
->hflags
|= HF_SOFTMMU_MASK
;
923 env
->hflags2
|= HF2_GIF_MASK
;
925 cpu_x86_update_cr0(env
, 0x60000010);
926 env
->a20_mask
= ~0x0;
927 env
->smbase
= 0x30000;
929 env
->idt
.limit
= 0xffff;
930 env
->gdt
.limit
= 0xffff;
931 env
->ldt
.limit
= 0xffff;
932 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
933 env
->tr
.limit
= 0xffff;
934 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
936 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
937 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
938 DESC_R_MASK
| DESC_A_MASK
);
939 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
940 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
942 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
943 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
945 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
946 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
948 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
949 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
951 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
952 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
956 env
->regs
[R_EDX
] = env
->cpuid_version
;
961 for(i
= 0;i
< 8; i
++)
967 memset(env
->dr
, 0, sizeof(env
->dr
));
968 env
->dr
[6] = DR6_FIXED_1
;
969 env
->dr
[7] = DR7_FIXED_1
;
970 cpu_breakpoint_remove_all(env
, BP_CPU
);
971 cpu_watchpoint_remove_all(env
, BP_CPU
);
976 void cpu_x86_close(CPUX86State
*env
)
981 /***********************************************************/
984 static const char *cc_op_str
[] = {
1040 cpu_x86_dump_seg_cache(CPUState
*env
, FILE *f
,
1041 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1042 const char *name
, struct SegmentCache
*sc
)
1044 #ifdef TARGET_X86_64
1045 if (env
->hflags
& HF_CS64_MASK
) {
1046 cpu_fprintf(f
, "%-3s=%04x %016" PRIx64
" %08x %08x", name
,
1047 sc
->selector
, sc
->base
, sc
->limit
, sc
->flags
);
1051 cpu_fprintf(f
, "%-3s=%04x %08x %08x %08x", name
, sc
->selector
,
1052 (uint32_t)sc
->base
, sc
->limit
, sc
->flags
);
1055 if (!(env
->hflags
& HF_PE_MASK
) || !(sc
->flags
& DESC_P_MASK
))
1058 cpu_fprintf(f
, " DPL=%d ", (sc
->flags
& DESC_DPL_MASK
) >> DESC_DPL_SHIFT
);
1059 if (sc
->flags
& DESC_S_MASK
) {
1060 if (sc
->flags
& DESC_CS_MASK
) {
1061 cpu_fprintf(f
, (sc
->flags
& DESC_L_MASK
) ? "CS64" :
1062 ((sc
->flags
& DESC_B_MASK
) ? "CS32" : "CS16"));
1063 cpu_fprintf(f
, " [%c%c", (sc
->flags
& DESC_C_MASK
) ? 'C' : '-',
1064 (sc
->flags
& DESC_R_MASK
) ? 'R' : '-');
1066 cpu_fprintf(f
, (sc
->flags
& DESC_B_MASK
) ? "DS " : "DS16");
1067 cpu_fprintf(f
, " [%c%c", (sc
->flags
& DESC_E_MASK
) ? 'E' : '-',
1068 (sc
->flags
& DESC_W_MASK
) ? 'W' : '-');
1070 cpu_fprintf(f
, "%c]", (sc
->flags
& DESC_A_MASK
) ? 'A' : '-');
1072 static const char *sys_type_name
[2][16] = {
1074 "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
1075 "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
1076 "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
1077 "CallGate32", "Reserved", "IntGate32", "TrapGate32"
1080 "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
1081 "Reserved", "Reserved", "Reserved", "Reserved",
1082 "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
1083 "Reserved", "IntGate64", "TrapGate64"
1086 cpu_fprintf(f
, sys_type_name
[(env
->hflags
& HF_LMA_MASK
) ? 1 : 0]
1087 [(sc
->flags
& DESC_TYPE_MASK
)
1088 >> DESC_TYPE_SHIFT
]);
1091 cpu_fprintf(f
, "\n");
1094 void cpu_dump_state(CPUState
*env
, FILE *f
,
1095 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1099 char cc_op_name
[32];
1100 static const char *seg_name
[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
1102 cpu_synchronize_state(env
);
1104 eflags
= env
->eflags
;
1105 #ifdef TARGET_X86_64
1106 if (env
->hflags
& HF_CS64_MASK
) {
1108 "RAX=%016" PRIx64
" RBX=%016" PRIx64
" RCX=%016" PRIx64
" RDX=%016" PRIx64
"\n"
1109 "RSI=%016" PRIx64
" RDI=%016" PRIx64
" RBP=%016" PRIx64
" RSP=%016" PRIx64
"\n"
1110 "R8 =%016" PRIx64
" R9 =%016" PRIx64
" R10=%016" PRIx64
" R11=%016" PRIx64
"\n"
1111 "R12=%016" PRIx64
" R13=%016" PRIx64
" R14=%016" PRIx64
" R15=%016" PRIx64
"\n"
1112 "RIP=%016" PRIx64
" RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
1130 eflags
& DF_MASK
? 'D' : '-',
1131 eflags
& CC_O
? 'O' : '-',
1132 eflags
& CC_S
? 'S' : '-',
1133 eflags
& CC_Z
? 'Z' : '-',
1134 eflags
& CC_A
? 'A' : '-',
1135 eflags
& CC_P
? 'P' : '-',
1136 eflags
& CC_C
? 'C' : '-',
1137 env
->hflags
& HF_CPL_MASK
,
1138 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
1139 (env
->a20_mask
>> 20) & 1,
1140 (env
->hflags
>> HF_SMM_SHIFT
) & 1,
1145 cpu_fprintf(f
, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
1146 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
1147 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
1148 (uint32_t)env
->regs
[R_EAX
],
1149 (uint32_t)env
->regs
[R_EBX
],
1150 (uint32_t)env
->regs
[R_ECX
],
1151 (uint32_t)env
->regs
[R_EDX
],
1152 (uint32_t)env
->regs
[R_ESI
],
1153 (uint32_t)env
->regs
[R_EDI
],
1154 (uint32_t)env
->regs
[R_EBP
],
1155 (uint32_t)env
->regs
[R_ESP
],
1156 (uint32_t)env
->eip
, eflags
,
1157 eflags
& DF_MASK
? 'D' : '-',
1158 eflags
& CC_O
? 'O' : '-',
1159 eflags
& CC_S
? 'S' : '-',
1160 eflags
& CC_Z
? 'Z' : '-',
1161 eflags
& CC_A
? 'A' : '-',
1162 eflags
& CC_P
? 'P' : '-',
1163 eflags
& CC_C
? 'C' : '-',
1164 env
->hflags
& HF_CPL_MASK
,
1165 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
1166 (env
->a20_mask
>> 20) & 1,
1167 (env
->hflags
>> HF_SMM_SHIFT
) & 1,
1171 for(i
= 0; i
< 6; i
++) {
1172 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, seg_name
[i
],
1175 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, "LDT", &env
->ldt
);
1176 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, "TR", &env
->tr
);
1178 #ifdef TARGET_X86_64
1179 if (env
->hflags
& HF_LMA_MASK
) {
1180 cpu_fprintf(f
, "GDT= %016" PRIx64
" %08x\n",
1181 env
->gdt
.base
, env
->gdt
.limit
);
1182 cpu_fprintf(f
, "IDT= %016" PRIx64
" %08x\n",
1183 env
->idt
.base
, env
->idt
.limit
);
1184 cpu_fprintf(f
, "CR0=%08x CR2=%016" PRIx64
" CR3=%016" PRIx64
" CR4=%08x\n",
1185 (uint32_t)env
->cr
[0],
1188 (uint32_t)env
->cr
[4]);
1189 for(i
= 0; i
< 4; i
++)
1190 cpu_fprintf(f
, "DR%d=%016" PRIx64
" ", i
, env
->dr
[i
]);
1191 cpu_fprintf(f
, "\nDR6=%016" PRIx64
" DR7=%016" PRIx64
"\n",
1192 env
->dr
[6], env
->dr
[7]);
1196 cpu_fprintf(f
, "GDT= %08x %08x\n",
1197 (uint32_t)env
->gdt
.base
, env
->gdt
.limit
);
1198 cpu_fprintf(f
, "IDT= %08x %08x\n",
1199 (uint32_t)env
->idt
.base
, env
->idt
.limit
);
1200 cpu_fprintf(f
, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
1201 (uint32_t)env
->cr
[0],
1202 (uint32_t)env
->cr
[2],
1203 (uint32_t)env
->cr
[3],
1204 (uint32_t)env
->cr
[4]);
1205 for(i
= 0; i
< 4; i
++)
1206 cpu_fprintf(f
, "DR%d=%08x ", i
, env
->dr
[i
]);
1207 cpu_fprintf(f
, "\nDR6=%08x DR7=%08x\n", env
->dr
[6], env
->dr
[7]);
1209 if (flags
& X86_DUMP_CCOP
) {
1210 if ((unsigned)env
->cc_op
< CC_OP_NB
)
1211 snprintf(cc_op_name
, sizeof(cc_op_name
), "%s", cc_op_str
[env
->cc_op
]);
1213 snprintf(cc_op_name
, sizeof(cc_op_name
), "[%d]", env
->cc_op
);
1214 #ifdef TARGET_X86_64
1215 if (env
->hflags
& HF_CS64_MASK
) {
1216 cpu_fprintf(f
, "CCS=%016" PRIx64
" CCD=%016" PRIx64
" CCO=%-8s\n",
1217 env
->cc_src
, env
->cc_dst
,
1222 cpu_fprintf(f
, "CCS=%08x CCD=%08x CCO=%-8s\n",
1223 (uint32_t)env
->cc_src
, (uint32_t)env
->cc_dst
,
1227 if (flags
& X86_DUMP_FPU
) {
1230 for(i
= 0; i
< 8; i
++) {
1231 fptag
|= ((!env
->fptags
[i
]) << i
);
1233 cpu_fprintf(f
, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
1235 (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11,
1240 #if defined(USE_X86LDOUBLE)
1248 tmp
.d
= env
->fpregs
[i
].d
;
1249 cpu_fprintf(f
, "FPR%d=%016" PRIx64
" %04x",
1250 i
, tmp
.l
.lower
, tmp
.l
.upper
);
1252 cpu_fprintf(f
, "FPR%d=%016" PRIx64
,
1253 i
, env
->fpregs
[i
].mmx
.q
);
1256 cpu_fprintf(f
, "\n");
1258 cpu_fprintf(f
, " ");
1260 if (env
->hflags
& HF_CS64_MASK
)
1265 cpu_fprintf(f
, "XMM%02d=%08x%08x%08x%08x",
1267 env
->xmm_regs
[i
].XMM_L(3),
1268 env
->xmm_regs
[i
].XMM_L(2),
1269 env
->xmm_regs
[i
].XMM_L(1),
1270 env
->xmm_regs
[i
].XMM_L(0));
1272 cpu_fprintf(f
, "\n");
1274 cpu_fprintf(f
, " ");
1279 /***********************************************************/
1281 /* XXX: add PGE support */
1283 void cpu_x86_set_a20(CPUX86State
*env
, int a20_state
)
1285 a20_state
= (a20_state
!= 0);
1286 if (a20_state
!= ((env
->a20_mask
>> 20) & 1)) {
1287 #if defined(DEBUG_MMU)
1288 printf("A20 update: a20=%d\n", a20_state
);
1290 /* if the cpu is currently executing code, we must unlink it and
1291 all the potentially executing TB */
1292 cpu_interrupt(env
, CPU_INTERRUPT_EXITTB
);
1294 /* when a20 is changed, all the MMU mappings are invalid, so
1295 we must flush everything */
1297 env
->a20_mask
= ~(1 << 20) | (a20_state
<< 20);
1301 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
)
1305 #if defined(DEBUG_MMU)
1306 printf("CR0 update: CR0=0x%08x\n", new_cr0
);
1308 if ((new_cr0
& (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
)) !=
1309 (env
->cr
[0] & (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
))) {
1313 #ifdef TARGET_X86_64
1314 if (!(env
->cr
[0] & CR0_PG_MASK
) && (new_cr0
& CR0_PG_MASK
) &&
1315 (env
->efer
& MSR_EFER_LME
)) {
1316 /* enter in long mode */
1317 /* XXX: generate an exception */
1318 if (!(env
->cr
[4] & CR4_PAE_MASK
))
1320 env
->efer
|= MSR_EFER_LMA
;
1321 env
->hflags
|= HF_LMA_MASK
;
1322 } else if ((env
->cr
[0] & CR0_PG_MASK
) && !(new_cr0
& CR0_PG_MASK
) &&
1323 (env
->efer
& MSR_EFER_LMA
)) {
1324 /* exit long mode */
1325 env
->efer
&= ~MSR_EFER_LMA
;
1326 env
->hflags
&= ~(HF_LMA_MASK
| HF_CS64_MASK
);
1327 env
->eip
&= 0xffffffff;
1330 env
->cr
[0] = new_cr0
| CR0_ET_MASK
;
1332 /* update PE flag in hidden flags */
1333 pe_state
= (env
->cr
[0] & CR0_PE_MASK
);
1334 env
->hflags
= (env
->hflags
& ~HF_PE_MASK
) | (pe_state
<< HF_PE_SHIFT
);
1335 /* ensure that ADDSEG is always set in real mode */
1336 env
->hflags
|= ((pe_state
^ 1) << HF_ADDSEG_SHIFT
);
1337 /* update FPU flags */
1338 env
->hflags
= (env
->hflags
& ~(HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
)) |
1339 ((new_cr0
<< (HF_MP_SHIFT
- 1)) & (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
));
1342 /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
1344 void cpu_x86_update_cr3(CPUX86State
*env
, target_ulong new_cr3
)
1346 env
->cr
[3] = new_cr3
;
1347 if (env
->cr
[0] & CR0_PG_MASK
) {
1348 #if defined(DEBUG_MMU)
1349 printf("CR3 update: CR3=" TARGET_FMT_lx
"\n", new_cr3
);
1355 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
)
1357 #if defined(DEBUG_MMU)
1358 printf("CR4 update: CR4=%08x\n", (uint32_t)env
->cr
[4]);
1360 if ((new_cr4
& (CR4_PGE_MASK
| CR4_PAE_MASK
| CR4_PSE_MASK
)) !=
1361 (env
->cr
[4] & (CR4_PGE_MASK
| CR4_PAE_MASK
| CR4_PSE_MASK
))) {
1365 if (!(env
->cpuid_features
& CPUID_SSE
))
1366 new_cr4
&= ~CR4_OSFXSR_MASK
;
1367 if (new_cr4
& CR4_OSFXSR_MASK
)
1368 env
->hflags
|= HF_OSFXSR_MASK
;
1370 env
->hflags
&= ~HF_OSFXSR_MASK
;
1372 env
->cr
[4] = new_cr4
;
1375 #if defined(CONFIG_USER_ONLY)
1377 int cpu_x86_handle_mmu_fault(CPUX86State
*env
, target_ulong addr
,
1378 int is_write
, int mmu_idx
, int is_softmmu
)
1380 /* user mode only emulation */
1383 env
->error_code
= (is_write
<< PG_ERROR_W_BIT
);
1384 env
->error_code
|= PG_ERROR_U_MASK
;
1385 env
->exception_index
= EXCP0E_PAGE
;
1389 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1396 /* XXX: This value should match the one returned by CPUID
1398 # if defined(TARGET_X86_64)
1399 # define PHYS_ADDR_MASK 0xfffffff000LL
1401 # define PHYS_ADDR_MASK 0xffffff000LL
1405 -1 = cannot handle fault
1406 0 = nothing more to do
1407 1 = generate PF fault
1408 2 = soft MMU activation required for this block
1410 int cpu_x86_handle_mmu_fault(CPUX86State
*env
, target_ulong addr
,
1411 int is_write1
, int mmu_idx
, int is_softmmu
)
1414 target_ulong pde_addr
, pte_addr
;
1415 int error_code
, is_dirty
, prot
, page_size
, ret
, is_write
, is_user
;
1416 target_phys_addr_t paddr
;
1417 uint32_t page_offset
;
1418 target_ulong vaddr
, virt_addr
;
1420 is_user
= mmu_idx
== MMU_USER_IDX
;
1421 #if defined(DEBUG_MMU)
1422 printf("MMU fault: addr=" TARGET_FMT_lx
" w=%d u=%d eip=" TARGET_FMT_lx
"\n",
1423 addr
, is_write1
, is_user
, env
->eip
);
1425 is_write
= is_write1
& 1;
1427 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
1429 virt_addr
= addr
& TARGET_PAGE_MASK
;
1430 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1435 if (env
->cr
[4] & CR4_PAE_MASK
) {
1437 target_ulong pdpe_addr
;
1439 #ifdef TARGET_X86_64
1440 if (env
->hflags
& HF_LMA_MASK
) {
1441 uint64_t pml4e_addr
, pml4e
;
1444 /* test virtual address sign extension */
1445 sext
= (int64_t)addr
>> 47;
1446 if (sext
!= 0 && sext
!= -1) {
1447 env
->error_code
= 0;
1448 env
->exception_index
= EXCP0D_GPF
;
1452 pml4e_addr
= ((env
->cr
[3] & ~0xfff) + (((addr
>> 39) & 0x1ff) << 3)) &
1454 pml4e
= ldq_phys(pml4e_addr
);
1455 if (!(pml4e
& PG_PRESENT_MASK
)) {
1459 if (!(env
->efer
& MSR_EFER_NXE
) && (pml4e
& PG_NX_MASK
)) {
1460 error_code
= PG_ERROR_RSVD_MASK
;
1463 if (!(pml4e
& PG_ACCESSED_MASK
)) {
1464 pml4e
|= PG_ACCESSED_MASK
;
1465 stl_phys_notdirty(pml4e_addr
, pml4e
);
1467 ptep
= pml4e
^ PG_NX_MASK
;
1468 pdpe_addr
= ((pml4e
& PHYS_ADDR_MASK
) + (((addr
>> 30) & 0x1ff) << 3)) &
1470 pdpe
= ldq_phys(pdpe_addr
);
1471 if (!(pdpe
& PG_PRESENT_MASK
)) {
1475 if (!(env
->efer
& MSR_EFER_NXE
) && (pdpe
& PG_NX_MASK
)) {
1476 error_code
= PG_ERROR_RSVD_MASK
;
1479 ptep
&= pdpe
^ PG_NX_MASK
;
1480 if (!(pdpe
& PG_ACCESSED_MASK
)) {
1481 pdpe
|= PG_ACCESSED_MASK
;
1482 stl_phys_notdirty(pdpe_addr
, pdpe
);
1487 /* XXX: load them when cr3 is loaded ? */
1488 pdpe_addr
= ((env
->cr
[3] & ~0x1f) + ((addr
>> 27) & 0x18)) &
1490 pdpe
= ldq_phys(pdpe_addr
);
1491 if (!(pdpe
& PG_PRESENT_MASK
)) {
1495 ptep
= PG_NX_MASK
| PG_USER_MASK
| PG_RW_MASK
;
1498 pde_addr
= ((pdpe
& PHYS_ADDR_MASK
) + (((addr
>> 21) & 0x1ff) << 3)) &
1500 pde
= ldq_phys(pde_addr
);
1501 if (!(pde
& PG_PRESENT_MASK
)) {
1505 if (!(env
->efer
& MSR_EFER_NXE
) && (pde
& PG_NX_MASK
)) {
1506 error_code
= PG_ERROR_RSVD_MASK
;
1509 ptep
&= pde
^ PG_NX_MASK
;
1510 if (pde
& PG_PSE_MASK
) {
1512 page_size
= 2048 * 1024;
1514 if ((ptep
& PG_NX_MASK
) && is_write1
== 2)
1515 goto do_fault_protect
;
1517 if (!(ptep
& PG_USER_MASK
))
1518 goto do_fault_protect
;
1519 if (is_write
&& !(ptep
& PG_RW_MASK
))
1520 goto do_fault_protect
;
1522 if ((env
->cr
[0] & CR0_WP_MASK
) &&
1523 is_write
&& !(ptep
& PG_RW_MASK
))
1524 goto do_fault_protect
;
1526 is_dirty
= is_write
&& !(pde
& PG_DIRTY_MASK
);
1527 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
1528 pde
|= PG_ACCESSED_MASK
;
1530 pde
|= PG_DIRTY_MASK
;
1531 stl_phys_notdirty(pde_addr
, pde
);
1533 /* align to page_size */
1534 pte
= pde
& ((PHYS_ADDR_MASK
& ~(page_size
- 1)) | 0xfff);
1535 virt_addr
= addr
& ~(page_size
- 1);
1538 if (!(pde
& PG_ACCESSED_MASK
)) {
1539 pde
|= PG_ACCESSED_MASK
;
1540 stl_phys_notdirty(pde_addr
, pde
);
1542 pte_addr
= ((pde
& PHYS_ADDR_MASK
) + (((addr
>> 12) & 0x1ff) << 3)) &
1544 pte
= ldq_phys(pte_addr
);
1545 if (!(pte
& PG_PRESENT_MASK
)) {
1549 if (!(env
->efer
& MSR_EFER_NXE
) && (pte
& PG_NX_MASK
)) {
1550 error_code
= PG_ERROR_RSVD_MASK
;
1553 /* combine pde and pte nx, user and rw protections */
1554 ptep
&= pte
^ PG_NX_MASK
;
1556 if ((ptep
& PG_NX_MASK
) && is_write1
== 2)
1557 goto do_fault_protect
;
1559 if (!(ptep
& PG_USER_MASK
))
1560 goto do_fault_protect
;
1561 if (is_write
&& !(ptep
& PG_RW_MASK
))
1562 goto do_fault_protect
;
1564 if ((env
->cr
[0] & CR0_WP_MASK
) &&
1565 is_write
&& !(ptep
& PG_RW_MASK
))
1566 goto do_fault_protect
;
1568 is_dirty
= is_write
&& !(pte
& PG_DIRTY_MASK
);
1569 if (!(pte
& PG_ACCESSED_MASK
) || is_dirty
) {
1570 pte
|= PG_ACCESSED_MASK
;
1572 pte
|= PG_DIRTY_MASK
;
1573 stl_phys_notdirty(pte_addr
, pte
);
1576 virt_addr
= addr
& ~0xfff;
1577 pte
= pte
& (PHYS_ADDR_MASK
| 0xfff);
1582 /* page directory entry */
1583 pde_addr
= ((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & 0xffc)) &
1585 pde
= ldl_phys(pde_addr
);
1586 if (!(pde
& PG_PRESENT_MASK
)) {
1590 /* if PSE bit is set, then we use a 4MB page */
1591 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
1592 page_size
= 4096 * 1024;
1594 if (!(pde
& PG_USER_MASK
))
1595 goto do_fault_protect
;
1596 if (is_write
&& !(pde
& PG_RW_MASK
))
1597 goto do_fault_protect
;
1599 if ((env
->cr
[0] & CR0_WP_MASK
) &&
1600 is_write
&& !(pde
& PG_RW_MASK
))
1601 goto do_fault_protect
;
1603 is_dirty
= is_write
&& !(pde
& PG_DIRTY_MASK
);
1604 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
1605 pde
|= PG_ACCESSED_MASK
;
1607 pde
|= PG_DIRTY_MASK
;
1608 stl_phys_notdirty(pde_addr
, pde
);
1611 pte
= pde
& ~( (page_size
- 1) & ~0xfff); /* align to page_size */
1613 virt_addr
= addr
& ~(page_size
- 1);
1615 if (!(pde
& PG_ACCESSED_MASK
)) {
1616 pde
|= PG_ACCESSED_MASK
;
1617 stl_phys_notdirty(pde_addr
, pde
);
1620 /* page directory entry */
1621 pte_addr
= ((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) &
1623 pte
= ldl_phys(pte_addr
);
1624 if (!(pte
& PG_PRESENT_MASK
)) {
1628 /* combine pde and pte user and rw protections */
1631 if (!(ptep
& PG_USER_MASK
))
1632 goto do_fault_protect
;
1633 if (is_write
&& !(ptep
& PG_RW_MASK
))
1634 goto do_fault_protect
;
1636 if ((env
->cr
[0] & CR0_WP_MASK
) &&
1637 is_write
&& !(ptep
& PG_RW_MASK
))
1638 goto do_fault_protect
;
1640 is_dirty
= is_write
&& !(pte
& PG_DIRTY_MASK
);
1641 if (!(pte
& PG_ACCESSED_MASK
) || is_dirty
) {
1642 pte
|= PG_ACCESSED_MASK
;
1644 pte
|= PG_DIRTY_MASK
;
1645 stl_phys_notdirty(pte_addr
, pte
);
1648 virt_addr
= addr
& ~0xfff;
1651 /* the page can be put in the TLB */
1653 if (!(ptep
& PG_NX_MASK
))
1655 if (pte
& PG_DIRTY_MASK
) {
1656 /* only set write access if already dirty... otherwise wait
1659 if (ptep
& PG_RW_MASK
)
1662 if (!(env
->cr
[0] & CR0_WP_MASK
) ||
1663 (ptep
& PG_RW_MASK
))
1668 pte
= pte
& env
->a20_mask
;
1670 /* Even if 4MB pages, we map only one 4KB page in the cache to
1671 avoid filling it too fast */
1672 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
1673 paddr
= (pte
& TARGET_PAGE_MASK
) + page_offset
;
1674 vaddr
= virt_addr
+ page_offset
;
1676 ret
= tlb_set_page_exec(env
, vaddr
, paddr
, prot
, mmu_idx
, is_softmmu
);
1679 error_code
= PG_ERROR_P_MASK
;
1681 error_code
|= (is_write
<< PG_ERROR_W_BIT
);
1683 error_code
|= PG_ERROR_U_MASK
;
1684 if (is_write1
== 2 &&
1685 (env
->efer
& MSR_EFER_NXE
) &&
1686 (env
->cr
[4] & CR4_PAE_MASK
))
1687 error_code
|= PG_ERROR_I_D_MASK
;
1688 if (env
->intercept_exceptions
& (1 << EXCP0E_PAGE
)) {
1689 /* cr2 is not modified in case of exceptions */
1690 stq_phys(env
->vm_vmcb
+ offsetof(struct vmcb
, control
.exit_info_2
),
1695 env
->error_code
= error_code
;
1696 env
->exception_index
= EXCP0E_PAGE
;
1700 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1702 target_ulong pde_addr
, pte_addr
;
1704 target_phys_addr_t paddr
;
1705 uint32_t page_offset
;
1708 if (env
->cr
[4] & CR4_PAE_MASK
) {
1709 target_ulong pdpe_addr
;
1712 #ifdef TARGET_X86_64
1713 if (env
->hflags
& HF_LMA_MASK
) {
1714 uint64_t pml4e_addr
, pml4e
;
1717 /* test virtual address sign extension */
1718 sext
= (int64_t)addr
>> 47;
1719 if (sext
!= 0 && sext
!= -1)
1722 pml4e_addr
= ((env
->cr
[3] & ~0xfff) + (((addr
>> 39) & 0x1ff) << 3)) &
1724 pml4e
= ldq_phys(pml4e_addr
);
1725 if (!(pml4e
& PG_PRESENT_MASK
))
1728 pdpe_addr
= ((pml4e
& ~0xfff) + (((addr
>> 30) & 0x1ff) << 3)) &
1730 pdpe
= ldq_phys(pdpe_addr
);
1731 if (!(pdpe
& PG_PRESENT_MASK
))
1736 pdpe_addr
= ((env
->cr
[3] & ~0x1f) + ((addr
>> 27) & 0x18)) &
1738 pdpe
= ldq_phys(pdpe_addr
);
1739 if (!(pdpe
& PG_PRESENT_MASK
))
1743 pde_addr
= ((pdpe
& ~0xfff) + (((addr
>> 21) & 0x1ff) << 3)) &
1745 pde
= ldq_phys(pde_addr
);
1746 if (!(pde
& PG_PRESENT_MASK
)) {
1749 if (pde
& PG_PSE_MASK
) {
1751 page_size
= 2048 * 1024;
1752 pte
= pde
& ~( (page_size
- 1) & ~0xfff); /* align to page_size */
1755 pte_addr
= ((pde
& ~0xfff) + (((addr
>> 12) & 0x1ff) << 3)) &
1758 pte
= ldq_phys(pte_addr
);
1760 if (!(pte
& PG_PRESENT_MASK
))
1765 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
1769 /* page directory entry */
1770 pde_addr
= ((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & 0xffc)) & env
->a20_mask
;
1771 pde
= ldl_phys(pde_addr
);
1772 if (!(pde
& PG_PRESENT_MASK
))
1774 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
1775 pte
= pde
& ~0x003ff000; /* align to 4MB */
1776 page_size
= 4096 * 1024;
1778 /* page directory entry */
1779 pte_addr
= ((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) & env
->a20_mask
;
1780 pte
= ldl_phys(pte_addr
);
1781 if (!(pte
& PG_PRESENT_MASK
))
1786 pte
= pte
& env
->a20_mask
;
1789 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
1790 paddr
= (pte
& TARGET_PAGE_MASK
) + page_offset
;
1794 void hw_breakpoint_insert(CPUState
*env
, int index
)
1798 switch (hw_breakpoint_type(env
->dr
[7], index
)) {
1800 if (hw_breakpoint_enabled(env
->dr
[7], index
))
1801 err
= cpu_breakpoint_insert(env
, env
->dr
[index
], BP_CPU
,
1802 &env
->cpu_breakpoint
[index
]);
1805 type
= BP_CPU
| BP_MEM_WRITE
;
1808 /* No support for I/O watchpoints yet */
1811 type
= BP_CPU
| BP_MEM_ACCESS
;
1813 err
= cpu_watchpoint_insert(env
, env
->dr
[index
],
1814 hw_breakpoint_len(env
->dr
[7], index
),
1815 type
, &env
->cpu_watchpoint
[index
]);
1819 env
->cpu_breakpoint
[index
] = NULL
;
1822 void hw_breakpoint_remove(CPUState
*env
, int index
)
1824 if (!env
->cpu_breakpoint
[index
])
1826 switch (hw_breakpoint_type(env
->dr
[7], index
)) {
1828 if (hw_breakpoint_enabled(env
->dr
[7], index
))
1829 cpu_breakpoint_remove_by_ref(env
, env
->cpu_breakpoint
[index
]);
1833 cpu_watchpoint_remove_by_ref(env
, env
->cpu_watchpoint
[index
]);
1836 /* No support for I/O watchpoints yet */
1841 int check_hw_breakpoints(CPUState
*env
, int force_dr6_update
)
1845 int hit_enabled
= 0;
1847 dr6
= env
->dr
[6] & ~0xf;
1848 for (reg
= 0; reg
< 4; reg
++) {
1849 type
= hw_breakpoint_type(env
->dr
[7], reg
);
1850 if ((type
== 0 && env
->dr
[reg
] == env
->eip
) ||
1851 ((type
& 1) && env
->cpu_watchpoint
[reg
] &&
1852 (env
->cpu_watchpoint
[reg
]->flags
& BP_WATCHPOINT_HIT
))) {
1854 if (hw_breakpoint_enabled(env
->dr
[7], reg
))
1858 if (hit_enabled
|| force_dr6_update
)
1863 static CPUDebugExcpHandler
*prev_debug_excp_handler
;
1865 void raise_exception_env(int exception_index
, CPUState
*env
);
1867 static void breakpoint_handler(CPUState
*env
)
1871 if (env
->watchpoint_hit
) {
1872 if (env
->watchpoint_hit
->flags
& BP_CPU
) {
1873 env
->watchpoint_hit
= NULL
;
1874 if (check_hw_breakpoints(env
, 0))
1875 raise_exception_env(EXCP01_DB
, env
);
1877 cpu_resume_from_signal(env
, NULL
);
1880 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
)
1881 if (bp
->pc
== env
->eip
) {
1882 if (bp
->flags
& BP_CPU
) {
1883 check_hw_breakpoints(env
, 1);
1884 raise_exception_env(EXCP01_DB
, env
);
1889 if (prev_debug_excp_handler
)
1890 prev_debug_excp_handler(env
);
1893 /* This should come from sysemu.h - if we could include it here... */
1894 void qemu_system_reset_request(void);
1896 void cpu_inject_x86_mce(CPUState
*cenv
, int bank
, uint64_t status
,
1897 uint64_t mcg_status
, uint64_t addr
, uint64_t misc
)
1899 uint64_t mcg_cap
= cenv
->mcg_cap
;
1900 unsigned bank_num
= mcg_cap
& 0xff;
1901 uint64_t *banks
= cenv
->mce_banks
;
1903 if (bank
>= bank_num
|| !(status
& MCI_STATUS_VAL
))
1907 * if MSR_MCG_CTL is not all 1s, the uncorrected error
1908 * reporting is disabled
1910 if ((status
& MCI_STATUS_UC
) && (mcg_cap
& MCG_CTL_P
) &&
1911 cenv
->mcg_ctl
!= ~(uint64_t)0)
1915 * if MSR_MCi_CTL is not all 1s, the uncorrected error
1916 * reporting is disabled for the bank
1918 if ((status
& MCI_STATUS_UC
) && banks
[0] != ~(uint64_t)0)
1920 if (status
& MCI_STATUS_UC
) {
1921 if ((cenv
->mcg_status
& MCG_STATUS_MCIP
) ||
1922 !(cenv
->cr
[4] & CR4_MCE_MASK
)) {
1923 fprintf(stderr
, "injects mce exception while previous "
1924 "one is in progress!\n");
1925 qemu_log_mask(CPU_LOG_RESET
, "Triple fault\n");
1926 qemu_system_reset_request();
1929 if (banks
[1] & MCI_STATUS_VAL
)
1930 status
|= MCI_STATUS_OVER
;
1933 cenv
->mcg_status
= mcg_status
;
1935 cpu_interrupt(cenv
, CPU_INTERRUPT_MCE
);
1936 } else if (!(banks
[1] & MCI_STATUS_VAL
)
1937 || !(banks
[1] & MCI_STATUS_UC
)) {
1938 if (banks
[1] & MCI_STATUS_VAL
)
1939 status
|= MCI_STATUS_OVER
;
1944 banks
[1] |= MCI_STATUS_OVER
;
1946 #endif /* !CONFIG_USER_ONLY */
1948 static void mce_init(CPUX86State
*cenv
)
1950 unsigned int bank
, bank_num
;
1952 if (((cenv
->cpuid_version
>> 8)&0xf) >= 6
1953 && (cenv
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)) {
1954 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
1955 cenv
->mcg_ctl
= ~(uint64_t)0;
1956 bank_num
= MCE_BANKS_DEF
;
1957 for (bank
= 0; bank
< bank_num
; bank
++)
1958 cenv
->mce_banks
[bank
*4] = ~(uint64_t)0;
1962 static void host_cpuid(uint32_t function
, uint32_t count
,
1963 uint32_t *eax
, uint32_t *ebx
,
1964 uint32_t *ecx
, uint32_t *edx
)
1966 #if defined(CONFIG_KVM)
1970 asm volatile("cpuid"
1971 : "=a"(vec
[0]), "=b"(vec
[1]),
1972 "=c"(vec
[2]), "=d"(vec
[3])
1973 : "0"(function
), "c"(count
) : "cc");
1975 asm volatile("pusha \n\t"
1977 "mov %%eax, 0(%2) \n\t"
1978 "mov %%ebx, 4(%2) \n\t"
1979 "mov %%ecx, 8(%2) \n\t"
1980 "mov %%edx, 12(%2) \n\t"
1982 : : "a"(function
), "c"(count
), "S"(vec
)
1997 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
1998 uint32_t *ecx
, uint32_t *edx
)
2000 *ebx
= env
->cpuid_vendor1
;
2001 *edx
= env
->cpuid_vendor2
;
2002 *ecx
= env
->cpuid_vendor3
;
2004 /* sysenter isn't supported on compatibility mode on AMD, syscall
2005 * isn't supported in compatibility mode on Intel.
2006 * Normally we advertise the actual cpu vendor, but you can override
2007 * this if you want to use KVM's sysenter/syscall emulation
2008 * in compatibility mode and when doing cross vendor migration
2010 if (kvm_enabled() && env
->cpuid_vendor_override
) {
2011 host_cpuid(0, 0, NULL
, ebx
, ecx
, edx
);
2015 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2016 uint32_t *eax
, uint32_t *ebx
,
2017 uint32_t *ecx
, uint32_t *edx
)
2019 /* test if maximum index reached */
2020 if (index
& 0x80000000) {
2021 if (index
> env
->cpuid_xlevel
)
2022 index
= env
->cpuid_level
;
2024 if (index
> env
->cpuid_level
)
2025 index
= env
->cpuid_level
;
2030 *eax
= env
->cpuid_level
;
2031 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
2034 *eax
= env
->cpuid_version
;
2035 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2036 *ecx
= env
->cpuid_ext_features
;
2037 *edx
= env
->cpuid_features
;
2038 if (env
->nr_cores
* env
->nr_threads
> 1) {
2039 *ebx
|= (env
->nr_cores
* env
->nr_threads
) << 16;
2040 *edx
|= 1 << 28; /* HTT bit */
2044 /* cache info: needed for Pentium Pro compatibility */
2051 /* cache info: needed for Core compatibility */
2052 if (env
->nr_cores
> 1) {
2053 *eax
= (env
->nr_cores
- 1) << 26;
2058 case 0: /* L1 dcache info */
2064 case 1: /* L1 icache info */
2070 case 2: /* L2 cache info */
2072 if (env
->nr_threads
> 1) {
2073 *eax
|= (env
->nr_threads
- 1) << 14;
2079 default: /* end of info */
2088 /* mwait info: needed for Core compatibility */
2089 *eax
= 0; /* Smallest monitor-line size in bytes */
2090 *ebx
= 0; /* Largest monitor-line size in bytes */
2091 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
2095 /* Thermal and Power Leaf */
2102 /* Direct Cache Access Information Leaf */
2103 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
2109 /* Architectural Performance Monitoring Leaf */
2116 *eax
= env
->cpuid_xlevel
;
2117 *ebx
= env
->cpuid_vendor1
;
2118 *edx
= env
->cpuid_vendor2
;
2119 *ecx
= env
->cpuid_vendor3
;
2122 *eax
= env
->cpuid_version
;
2124 *ecx
= env
->cpuid_ext3_features
;
2125 *edx
= env
->cpuid_ext2_features
;
2127 /* The Linux kernel checks for the CMPLegacy bit and
2128 * discards multiple thread information if it is set.
2129 * So dont set it here for Intel to make Linux guests happy.
2131 if (env
->nr_cores
* env
->nr_threads
> 1) {
2132 uint32_t tebx
, tecx
, tedx
;
2133 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
2134 if (tebx
!= CPUID_VENDOR_INTEL_1
||
2135 tedx
!= CPUID_VENDOR_INTEL_2
||
2136 tecx
!= CPUID_VENDOR_INTEL_3
) {
2137 *ecx
|= 1 << 1; /* CmpLegacy bit */
2141 if (kvm_enabled()) {
2142 /* Nested SVM not yet supported in upstream QEMU */
2143 *ecx
&= ~CPUID_EXT3_SVM
;
2149 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
2150 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
2151 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
2152 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
2155 /* cache info (L1 cache) */
2162 /* cache info (L2 cache) */
2169 /* virtual & phys address size in low 2 bytes. */
2170 /* XXX: This value must match the one used in the MMU code. */
2171 if (env
->cpuid_ext2_features
& CPUID_EXT2_LM
) {
2172 /* 64 bit processor */
2173 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2174 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
2176 if (env
->cpuid_features
& CPUID_PSE36
)
2177 *eax
= 0x00000024; /* 36 bits physical */
2179 *eax
= 0x00000020; /* 32 bits physical */
2184 if (env
->nr_cores
* env
->nr_threads
> 1) {
2185 *ecx
|= (env
->nr_cores
* env
->nr_threads
) - 1;
2189 *eax
= 0x00000001; /* SVM Revision */
2190 *ebx
= 0x00000010; /* nr of ASIDs */
2192 *edx
= 0; /* optional features */
2195 /* reserved values: zero */
2205 int cpu_x86_get_descr_debug(CPUX86State
*env
, unsigned int selector
,
2206 target_ulong
*base
, unsigned int *limit
,
2207 unsigned int *flags
)
2218 index
= selector
& ~7;
2219 ptr
= dt
->base
+ index
;
2220 if ((index
+ 7) > dt
->limit
2221 || cpu_memory_rw_debug(env
, ptr
, (uint8_t *)&e1
, sizeof(e1
), 0) != 0
2222 || cpu_memory_rw_debug(env
, ptr
+4, (uint8_t *)&e2
, sizeof(e2
), 0) != 0)
2225 *base
= ((e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000));
2226 *limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
2227 if (e2
& DESC_G_MASK
)
2228 *limit
= (*limit
<< 12) | 0xfff;
2234 CPUX86State
*cpu_x86_init(const char *cpu_model
)
2239 env
= qemu_mallocz(sizeof(CPUX86State
));
2241 env
->cpu_model_str
= cpu_model
;
2243 /* init various static tables */
2246 optimize_flags_init();
2247 #ifndef CONFIG_USER_ONLY
2248 prev_debug_excp_handler
=
2249 cpu_set_debug_excp_handler(breakpoint_handler
);
2252 if (cpu_x86_register(env
, cpu_model
) < 0) {
2258 qemu_init_vcpu(env
);
2263 #if !defined(CONFIG_USER_ONLY)
2264 void do_cpu_init(CPUState
*env
)
2266 int sipi
= env
->interrupt_request
& CPU_INTERRUPT_SIPI
;
2268 env
->interrupt_request
= sipi
;
2269 apic_init_reset(env
);
2272 void do_cpu_sipi(CPUState
*env
)
2277 void do_cpu_init(CPUState
*env
)
2280 void do_cpu_sipi(CPUState
*env
)