?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
block: Connect BlockBackend to BlockDriverState
[qemu/cris-port.git] / target-mips / op_helper.c
blobdf97b35f87014b5b6014bb768b15250875e79f36
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/cpu_ldst.h"
24 #include "sysemu/kvm.h"
25
26 #ifndef CONFIG_USER_ONLY
27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
28 #endif
29
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
32
33 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
34 uint32_t exception,
35 int error_code,
36 uintptr_t pc)
37 {
38 CPUState *cs = CPU(mips_env_get_cpu(env));
39
40 if (exception < EXCP_SC) {
41 qemu_log("%s: %d %d\n", __func__, exception, error_code);
42 }
43 cs->exception_index = exception;
44 env->error_code = error_code;
45
46 if (pc) {
47 /* now we have a real cpu fault */
48 cpu_restore_state(cs, pc);
49 }
50
51 cpu_loop_exit(cs);
52 }
53
54 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
55 uint32_t exception,
56 uintptr_t pc)
57 {
58 do_raise_exception_err(env, exception, 0, pc);
59 }
60
61 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
62 int error_code)
63 {
64 do_raise_exception_err(env, exception, error_code, 0);
65 }
66
67 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
68 {
69 do_raise_exception(env, exception, 0);
70 }
71
72 #if defined(CONFIG_USER_ONLY)
73 #define HELPER_LD(name, insn, type) \
74 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
75 int mem_idx) \
76 { \
77 return (type) insn##_raw(addr); \
78 }
79 #else
80 #define HELPER_LD(name, insn, type) \
81 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
82 int mem_idx) \
83 { \
84 switch (mem_idx) \
85 { \
86 case 0: return (type) cpu_##insn##_kernel(env, addr); break; \
87 case 1: return (type) cpu_##insn##_super(env, addr); break; \
88 default: \
89 case 2: return (type) cpu_##insn##_user(env, addr); break; \
90 } \
91 }
92 #endif
93 HELPER_LD(lbu, ldub, uint8_t)
94 HELPER_LD(lw, ldl, int32_t)
95 #ifdef TARGET_MIPS64
96 HELPER_LD(ld, ldq, int64_t)
97 #endif
98 #undef HELPER_LD
99
100 #if defined(CONFIG_USER_ONLY)
101 #define HELPER_ST(name, insn, type) \
102 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
103 type val, int mem_idx) \
104 { \
105 insn##_raw(addr, val); \
106 }
107 #else
108 #define HELPER_ST(name, insn, type) \
109 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
110 type val, int mem_idx) \
111 { \
112 switch (mem_idx) \
113 { \
114 case 0: cpu_##insn##_kernel(env, addr, val); break; \
115 case 1: cpu_##insn##_super(env, addr, val); break; \
116 default: \
117 case 2: cpu_##insn##_user(env, addr, val); break; \
118 } \
119 }
120 #endif
121 HELPER_ST(sb, stb, uint8_t)
122 HELPER_ST(sw, stl, uint32_t)
123 #ifdef TARGET_MIPS64
124 HELPER_ST(sd, stq, uint64_t)
125 #endif
126 #undef HELPER_ST
127
128 target_ulong helper_clo (target_ulong arg1)
129 {
130 return clo32(arg1);
131 }
132
133 target_ulong helper_clz (target_ulong arg1)
134 {
135 return clz32(arg1);
136 }
137
138 #if defined(TARGET_MIPS64)
139 target_ulong helper_dclo (target_ulong arg1)
140 {
141 return clo64(arg1);
142 }
143
144 target_ulong helper_dclz (target_ulong arg1)
145 {
146 return clz64(arg1);
147 }
148 #endif /* TARGET_MIPS64 */
149
150 /* 64 bits arithmetic for 32 bits hosts */
151 static inline uint64_t get_HILO(CPUMIPSState *env)
152 {
153 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
154 }
155
156 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
157 {
158 target_ulong tmp;
159 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
160 tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
161 return tmp;
162 }
163
164 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
165 {
166 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
167 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
168 return tmp;
169 }
170
171 /* Multiplication variants of the vr54xx. */
172 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
173 target_ulong arg2)
174 {
175 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
176 (int64_t)(int32_t)arg2));
177 }
178
179 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
180 target_ulong arg2)
181 {
182 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
183 (uint64_t)(uint32_t)arg2);
184 }
185
186 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
187 target_ulong arg2)
188 {
189 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
190 (int64_t)(int32_t)arg2);
191 }
192
193 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
194 target_ulong arg2)
195 {
196 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
197 (int64_t)(int32_t)arg2);
198 }
199
200 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
201 target_ulong arg2)
202 {
203 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
204 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
205 }
206
207 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
208 target_ulong arg2)
209 {
210 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
211 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
212 }
213
214 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
215 target_ulong arg2)
216 {
217 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
218 (int64_t)(int32_t)arg2);
219 }
220
221 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
222 target_ulong arg2)
223 {
224 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
225 (int64_t)(int32_t)arg2);
226 }
227
228 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
229 target_ulong arg2)
230 {
231 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
232 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
233 }
234
235 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
236 target_ulong arg2)
237 {
238 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
239 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
240 }
241
242 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
243 target_ulong arg2)
244 {
245 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
246 }
247
248 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
249 target_ulong arg2)
250 {
251 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
252 (uint64_t)(uint32_t)arg2);
253 }
254
255 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
256 target_ulong arg2)
257 {
258 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
259 (int64_t)(int32_t)arg2);
260 }
261
262 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
263 target_ulong arg2)
264 {
265 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
266 (uint64_t)(uint32_t)arg2);
267 }
268
269 #ifndef CONFIG_USER_ONLY
270
271 static inline hwaddr do_translate_address(CPUMIPSState *env,
272 target_ulong address,
273 int rw)
274 {
275 hwaddr lladdr;
276
277 lladdr = cpu_mips_translate_address(env, address, rw);
278
279 if (lladdr == -1LL) {
280 cpu_loop_exit(CPU(mips_env_get_cpu(env)));
281 } else {
282 return lladdr;
283 }
284 }
285
286 #define HELPER_LD_ATOMIC(name, insn) \
287 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
288 { \
289 env->lladdr = do_translate_address(env, arg, 0); \
290 env->llval = do_##insn(env, arg, mem_idx); \
291 return env->llval; \
292 }
293 HELPER_LD_ATOMIC(ll, lw)
294 #ifdef TARGET_MIPS64
295 HELPER_LD_ATOMIC(lld, ld)
296 #endif
297 #undef HELPER_LD_ATOMIC
298
299 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
300 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
301 target_ulong arg2, int mem_idx) \
302 { \
303 target_long tmp; \
304 \
305 if (arg2 & almask) { \
306 env->CP0_BadVAddr = arg2; \
307 helper_raise_exception(env, EXCP_AdES); \
308 } \
309 if (do_translate_address(env, arg2, 1) == env->lladdr) { \
310 tmp = do_##ld_insn(env, arg2, mem_idx); \
311 if (tmp == env->llval) { \
312 do_##st_insn(env, arg2, arg1, mem_idx); \
313 return 1; \
314 } \
315 } \
316 return 0; \
317 }
318 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
319 #ifdef TARGET_MIPS64
320 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
321 #endif
322 #undef HELPER_ST_ATOMIC
323 #endif
324
325 #ifdef TARGET_WORDS_BIGENDIAN
326 #define GET_LMASK(v) ((v) & 3)
327 #define GET_OFFSET(addr, offset) (addr + (offset))
328 #else
329 #define GET_LMASK(v) (((v) & 3) ^ 3)
330 #define GET_OFFSET(addr, offset) (addr - (offset))
331 #endif
332
333 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
334 int mem_idx)
335 {
336 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
337
338 if (GET_LMASK(arg2) <= 2)
339 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
340
341 if (GET_LMASK(arg2) <= 1)
342 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
343
344 if (GET_LMASK(arg2) == 0)
345 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
346 }
347
348 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
349 int mem_idx)
350 {
351 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
352
353 if (GET_LMASK(arg2) >= 1)
354 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
355
356 if (GET_LMASK(arg2) >= 2)
357 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
358
359 if (GET_LMASK(arg2) == 3)
360 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
361 }
362
363 #if defined(TARGET_MIPS64)
364 /* "half" load and stores. We must do the memory access inline,
365 or fault handling won't work. */
366
367 #ifdef TARGET_WORDS_BIGENDIAN
368 #define GET_LMASK64(v) ((v) & 7)
369 #else
370 #define GET_LMASK64(v) (((v) & 7) ^ 7)
371 #endif
372
373 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
374 int mem_idx)
375 {
376 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
377
378 if (GET_LMASK64(arg2) <= 6)
379 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
380
381 if (GET_LMASK64(arg2) <= 5)
382 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
383
384 if (GET_LMASK64(arg2) <= 4)
385 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
386
387 if (GET_LMASK64(arg2) <= 3)
388 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
389
390 if (GET_LMASK64(arg2) <= 2)
391 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
392
393 if (GET_LMASK64(arg2) <= 1)
394 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
395
396 if (GET_LMASK64(arg2) <= 0)
397 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
398 }
399
400 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
401 int mem_idx)
402 {
403 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
404
405 if (GET_LMASK64(arg2) >= 1)
406 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
407
408 if (GET_LMASK64(arg2) >= 2)
409 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
410
411 if (GET_LMASK64(arg2) >= 3)
412 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
413
414 if (GET_LMASK64(arg2) >= 4)
415 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
416
417 if (GET_LMASK64(arg2) >= 5)
418 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
419
420 if (GET_LMASK64(arg2) >= 6)
421 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
422
423 if (GET_LMASK64(arg2) == 7)
424 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
425 }
426 #endif /* TARGET_MIPS64 */
427
428 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
429
430 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
431 uint32_t mem_idx)
432 {
433 target_ulong base_reglist = reglist & 0xf;
434 target_ulong do_r31 = reglist & 0x10;
435
436 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
437 target_ulong i;
438
439 for (i = 0; i < base_reglist; i++) {
440 env->active_tc.gpr[multiple_regs[i]] =
441 (target_long)do_lw(env, addr, mem_idx);
442 addr += 4;
443 }
444 }
445
446 if (do_r31) {
447 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
448 }
449 }
450
451 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
452 uint32_t mem_idx)
453 {
454 target_ulong base_reglist = reglist & 0xf;
455 target_ulong do_r31 = reglist & 0x10;
456
457 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
458 target_ulong i;
459
460 for (i = 0; i < base_reglist; i++) {
461 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
462 addr += 4;
463 }
464 }
465
466 if (do_r31) {
467 do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
468 }
469 }
470
471 #if defined(TARGET_MIPS64)
472 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
473 uint32_t mem_idx)
474 {
475 target_ulong base_reglist = reglist & 0xf;
476 target_ulong do_r31 = reglist & 0x10;
477
478 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
479 target_ulong i;
480
481 for (i = 0; i < base_reglist; i++) {
482 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
483 addr += 8;
484 }
485 }
486
487 if (do_r31) {
488 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
489 }
490 }
491
492 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
493 uint32_t mem_idx)
494 {
495 target_ulong base_reglist = reglist & 0xf;
496 target_ulong do_r31 = reglist & 0x10;
497
498 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
499 target_ulong i;
500
501 for (i = 0; i < base_reglist; i++) {
502 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
503 addr += 8;
504 }
505 }
506
507 if (do_r31) {
508 do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
509 }
510 }
511 #endif
512
513 #ifndef CONFIG_USER_ONLY
514 /* SMP helpers. */
515 static bool mips_vpe_is_wfi(MIPSCPU *c)
516 {
517 CPUState *cpu = CPU(c);
518 CPUMIPSState *env = &c->env;
519
520 /* If the VPE is halted but otherwise active, it means it's waiting for
521 an interrupt. */
522 return cpu->halted && mips_vpe_active(env);
523 }
524
525 static inline void mips_vpe_wake(MIPSCPU *c)
526 {
527 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
528 because there might be other conditions that state that c should
529 be sleeping. */
530 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
531 }
532
533 static inline void mips_vpe_sleep(MIPSCPU *cpu)
534 {
535 CPUState *cs = CPU(cpu);
536
537 /* The VPE was shut off, really go to bed.
538 Reset any old _WAKE requests. */
539 cs->halted = 1;
540 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
541 }
542
543 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
544 {
545 CPUMIPSState *c = &cpu->env;
546
547 /* FIXME: TC reschedule. */
548 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
549 mips_vpe_wake(cpu);
550 }
551 }
552
553 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
554 {
555 CPUMIPSState *c = &cpu->env;
556
557 /* FIXME: TC reschedule. */
558 if (!mips_vpe_active(c)) {
559 mips_vpe_sleep(cpu);
560 }
561 }
562
563 /**
564 * mips_cpu_map_tc:
565 * @env: CPU from which mapping is performed.
566 * @tc: Should point to an int with the value of the global TC index.
567 *
568 * This function will transform @tc into a local index within the
569 * returned #CPUMIPSState.
570 */
571 /* FIXME: This code assumes that all VPEs have the same number of TCs,
572 which depends on runtime setup. Can probably be fixed by
573 walking the list of CPUMIPSStates. */
574 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
575 {
576 MIPSCPU *cpu;
577 CPUState *cs;
578 CPUState *other_cs;
579 int vpe_idx;
580 int tc_idx = *tc;
581
582 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
583 /* Not allowed to address other CPUs. */
584 *tc = env->current_tc;
585 return env;
586 }
587
588 cs = CPU(mips_env_get_cpu(env));
589 vpe_idx = tc_idx / cs->nr_threads;
590 *tc = tc_idx % cs->nr_threads;
591 other_cs = qemu_get_cpu(vpe_idx);
592 if (other_cs == NULL) {
593 return env;
594 }
595 cpu = MIPS_CPU(other_cs);
596 return &cpu->env;
597 }
598
599 /* The per VPE CP0_Status register shares some fields with the per TC
600 CP0_TCStatus registers. These fields are wired to the same registers,
601 so changes to either of them should be reflected on both registers.
602
603 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
604
605 These helper call synchronizes the regs for a given cpu. */
606
607 /* Called for updates to CP0_Status. */
608 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
609 {
610 int32_t tcstatus, *tcst;
611 uint32_t v = cpu->CP0_Status;
612 uint32_t cu, mx, asid, ksu;
613 uint32_t mask = ((1 << CP0TCSt_TCU3)
614 | (1 << CP0TCSt_TCU2)
615 | (1 << CP0TCSt_TCU1)
616 | (1 << CP0TCSt_TCU0)
617 | (1 << CP0TCSt_TMX)
618 | (3 << CP0TCSt_TKSU)
619 | (0xff << CP0TCSt_TASID));
620
621 cu = (v >> CP0St_CU0) & 0xf;
622 mx = (v >> CP0St_MX) & 0x1;
623 ksu = (v >> CP0St_KSU) & 0x3;
624 asid = env->CP0_EntryHi & 0xff;
625
626 tcstatus = cu << CP0TCSt_TCU0;
627 tcstatus |= mx << CP0TCSt_TMX;
628 tcstatus |= ksu << CP0TCSt_TKSU;
629 tcstatus |= asid;
630
631 if (tc == cpu->current_tc) {
632 tcst = &cpu->active_tc.CP0_TCStatus;
633 } else {
634 tcst = &cpu->tcs[tc].CP0_TCStatus;
635 }
636
637 *tcst &= ~mask;
638 *tcst |= tcstatus;
639 compute_hflags(cpu);
640 }
641
642 /* Called for updates to CP0_TCStatus. */
643 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
644 target_ulong v)
645 {
646 uint32_t status;
647 uint32_t tcu, tmx, tasid, tksu;
648 uint32_t mask = ((1U << CP0St_CU3)
649 | (1 << CP0St_CU2)
650 | (1 << CP0St_CU1)
651 | (1 << CP0St_CU0)
652 | (1 << CP0St_MX)
653 | (3 << CP0St_KSU));
654
655 tcu = (v >> CP0TCSt_TCU0) & 0xf;
656 tmx = (v >> CP0TCSt_TMX) & 0x1;
657 tasid = v & 0xff;
658 tksu = (v >> CP0TCSt_TKSU) & 0x3;
659
660 status = tcu << CP0St_CU0;
661 status |= tmx << CP0St_MX;
662 status |= tksu << CP0St_KSU;
663
664 cpu->CP0_Status &= ~mask;
665 cpu->CP0_Status |= status;
666
667 /* Sync the TASID with EntryHi. */
668 cpu->CP0_EntryHi &= ~0xff;
669 cpu->CP0_EntryHi = tasid;
670
671 compute_hflags(cpu);
672 }
673
674 /* Called for updates to CP0_EntryHi. */
675 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
676 {
677 int32_t *tcst;
678 uint32_t asid, v = cpu->CP0_EntryHi;
679
680 asid = v & 0xff;
681
682 if (tc == cpu->current_tc) {
683 tcst = &cpu->active_tc.CP0_TCStatus;
684 } else {
685 tcst = &cpu->tcs[tc].CP0_TCStatus;
686 }
687
688 *tcst &= ~0xff;
689 *tcst |= asid;
690 }
691
692 /* CP0 helpers */
693 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
694 {
695 return env->mvp->CP0_MVPControl;
696 }
697
698 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
699 {
700 return env->mvp->CP0_MVPConf0;
701 }
702
703 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
704 {
705 return env->mvp->CP0_MVPConf1;
706 }
707
708 target_ulong helper_mfc0_random(CPUMIPSState *env)
709 {
710 return (int32_t)cpu_mips_get_random(env);
711 }
712
713 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
714 {
715 return env->active_tc.CP0_TCStatus;
716 }
717
718 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
719 {
720 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
721 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
722
723 if (other_tc == other->current_tc)
724 return other->active_tc.CP0_TCStatus;
725 else
726 return other->tcs[other_tc].CP0_TCStatus;
727 }
728
729 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
730 {
731 return env->active_tc.CP0_TCBind;
732 }
733
734 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
735 {
736 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
737 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
738
739 if (other_tc == other->current_tc)
740 return other->active_tc.CP0_TCBind;
741 else
742 return other->tcs[other_tc].CP0_TCBind;
743 }
744
745 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
746 {
747 return env->active_tc.PC;
748 }
749
750 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
751 {
752 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
753 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
754
755 if (other_tc == other->current_tc)
756 return other->active_tc.PC;
757 else
758 return other->tcs[other_tc].PC;
759 }
760
761 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
762 {
763 return env->active_tc.CP0_TCHalt;
764 }
765
766 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
767 {
768 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
769 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
770
771 if (other_tc == other->current_tc)
772 return other->active_tc.CP0_TCHalt;
773 else
774 return other->tcs[other_tc].CP0_TCHalt;
775 }
776
777 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
778 {
779 return env->active_tc.CP0_TCContext;
780 }
781
782 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
783 {
784 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
785 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
786
787 if (other_tc == other->current_tc)
788 return other->active_tc.CP0_TCContext;
789 else
790 return other->tcs[other_tc].CP0_TCContext;
791 }
792
793 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
794 {
795 return env->active_tc.CP0_TCSchedule;
796 }
797
798 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
799 {
800 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
801 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
802
803 if (other_tc == other->current_tc)
804 return other->active_tc.CP0_TCSchedule;
805 else
806 return other->tcs[other_tc].CP0_TCSchedule;
807 }
808
809 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
810 {
811 return env->active_tc.CP0_TCScheFBack;
812 }
813
814 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
815 {
816 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
817 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
818
819 if (other_tc == other->current_tc)
820 return other->active_tc.CP0_TCScheFBack;
821 else
822 return other->tcs[other_tc].CP0_TCScheFBack;
823 }
824
825 target_ulong helper_mfc0_count(CPUMIPSState *env)
826 {
827 return (int32_t)cpu_mips_get_count(env);
828 }
829
830 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
831 {
832 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
833 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
834
835 return other->CP0_EntryHi;
836 }
837
838 target_ulong helper_mftc0_cause(CPUMIPSState *env)
839 {
840 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
841 int32_t tccause;
842 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
843
844 if (other_tc == other->current_tc) {
845 tccause = other->CP0_Cause;
846 } else {
847 tccause = other->CP0_Cause;
848 }
849
850 return tccause;
851 }
852
853 target_ulong helper_mftc0_status(CPUMIPSState *env)
854 {
855 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
856 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
857
858 return other->CP0_Status;
859 }
860
861 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
862 {
863 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
864 }
865
866 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
867 {
868 return (int32_t)env->CP0_WatchLo[sel];
869 }
870
871 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
872 {
873 return env->CP0_WatchHi[sel];
874 }
875
876 target_ulong helper_mfc0_debug(CPUMIPSState *env)
877 {
878 target_ulong t0 = env->CP0_Debug;
879 if (env->hflags & MIPS_HFLAG_DM)
880 t0 |= 1 << CP0DB_DM;
881
882 return t0;
883 }
884
885 target_ulong helper_mftc0_debug(CPUMIPSState *env)
886 {
887 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
888 int32_t tcstatus;
889 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
890
891 if (other_tc == other->current_tc)
892 tcstatus = other->active_tc.CP0_Debug_tcstatus;
893 else
894 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
895
896 /* XXX: Might be wrong, check with EJTAG spec. */
897 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
898 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
899 }
900
901 #if defined(TARGET_MIPS64)
902 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
903 {
904 return env->active_tc.PC;
905 }
906
907 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
908 {
909 return env->active_tc.CP0_TCHalt;
910 }
911
912 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
913 {
914 return env->active_tc.CP0_TCContext;
915 }
916
917 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
918 {
919 return env->active_tc.CP0_TCSchedule;
920 }
921
922 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
923 {
924 return env->active_tc.CP0_TCScheFBack;
925 }
926
927 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
928 {
929 return env->lladdr >> env->CP0_LLAddr_shift;
930 }
931
932 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
933 {
934 return env->CP0_WatchLo[sel];
935 }
936 #endif /* TARGET_MIPS64 */
937
938 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
939 {
940 int num = 1;
941 unsigned int tmp = env->tlb->nb_tlb;
942
943 do {
944 tmp >>= 1;
945 num <<= 1;
946 } while (tmp);
947 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
948 }
949
950 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
951 {
952 uint32_t mask = 0;
953 uint32_t newval;
954
955 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
956 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
957 (1 << CP0MVPCo_EVP);
958 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
959 mask |= (1 << CP0MVPCo_STLB);
960 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
961
962 // TODO: Enable/disable shared TLB, enable/disable VPEs.
963
964 env->mvp->CP0_MVPControl = newval;
965 }
966
967 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
968 {
969 uint32_t mask;
970 uint32_t newval;
971
972 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
973 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
974 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
975
976 /* Yield scheduler intercept not implemented. */
977 /* Gating storage scheduler intercept not implemented. */
978
979 // TODO: Enable/disable TCs.
980
981 env->CP0_VPEControl = newval;
982 }
983
984 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
985 {
986 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
987 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
988 uint32_t mask;
989 uint32_t newval;
990
991 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
992 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
993 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
994
995 /* TODO: Enable/disable TCs. */
996
997 other->CP0_VPEControl = newval;
998 }
999
1000 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1001 {
1002 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1003 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1004 /* FIXME: Mask away return zero on read bits. */
1005 return other->CP0_VPEControl;
1006 }
1007
1008 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1009 {
1010 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1011 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1012
1013 return other->CP0_VPEConf0;
1014 }
1015
1016 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1017 {
1018 uint32_t mask = 0;
1019 uint32_t newval;
1020
1021 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1022 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1023 mask |= (0xff << CP0VPEC0_XTC);
1024 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1025 }
1026 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1027
1028 // TODO: TC exclusive handling due to ERL/EXL.
1029
1030 env->CP0_VPEConf0 = newval;
1031 }
1032
1033 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1034 {
1035 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1036 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1037 uint32_t mask = 0;
1038 uint32_t newval;
1039
1040 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1041 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1042
1043 /* TODO: TC exclusive handling due to ERL/EXL. */
1044 other->CP0_VPEConf0 = newval;
1045 }
1046
1047 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1048 {
1049 uint32_t mask = 0;
1050 uint32_t newval;
1051
1052 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1053 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1054 (0xff << CP0VPEC1_NCP1);
1055 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1056
1057 /* UDI not implemented. */
1058 /* CP2 not implemented. */
1059
1060 // TODO: Handle FPU (CP1) binding.
1061
1062 env->CP0_VPEConf1 = newval;
1063 }
1064
1065 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1066 {
1067 /* Yield qualifier inputs not implemented. */
1068 env->CP0_YQMask = 0x00000000;
1069 }
1070
1071 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1072 {
1073 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1074 }
1075
1076 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1077 {
1078 /* Large physaddr (PABITS) not implemented */
1079 /* 1k pages not implemented */
1080 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1081 }
1082
1083 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1084 {
1085 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1086 uint32_t newval;
1087
1088 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1089
1090 env->active_tc.CP0_TCStatus = newval;
1091 sync_c0_tcstatus(env, env->current_tc, newval);
1092 }
1093
1094 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1095 {
1096 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1097 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1098
1099 if (other_tc == other->current_tc)
1100 other->active_tc.CP0_TCStatus = arg1;
1101 else
1102 other->tcs[other_tc].CP0_TCStatus = arg1;
1103 sync_c0_tcstatus(other, other_tc, arg1);
1104 }
1105
1106 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1107 {
1108 uint32_t mask = (1 << CP0TCBd_TBE);
1109 uint32_t newval;
1110
1111 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1112 mask |= (1 << CP0TCBd_CurVPE);
1113 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1114 env->active_tc.CP0_TCBind = newval;
1115 }
1116
1117 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1118 {
1119 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1120 uint32_t mask = (1 << CP0TCBd_TBE);
1121 uint32_t newval;
1122 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1123
1124 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1125 mask |= (1 << CP0TCBd_CurVPE);
1126 if (other_tc == other->current_tc) {
1127 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1128 other->active_tc.CP0_TCBind = newval;
1129 } else {
1130 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1131 other->tcs[other_tc].CP0_TCBind = newval;
1132 }
1133 }
1134
1135 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1136 {
1137 env->active_tc.PC = arg1;
1138 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1139 env->lladdr = 0ULL;
1140 /* MIPS16 not implemented. */
1141 }
1142
1143 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1144 {
1145 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1146 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1147
1148 if (other_tc == other->current_tc) {
1149 other->active_tc.PC = arg1;
1150 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1151 other->lladdr = 0ULL;
1152 /* MIPS16 not implemented. */
1153 } else {
1154 other->tcs[other_tc].PC = arg1;
1155 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1156 other->lladdr = 0ULL;
1157 /* MIPS16 not implemented. */
1158 }
1159 }
1160
1161 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1162 {
1163 MIPSCPU *cpu = mips_env_get_cpu(env);
1164
1165 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1166
1167 // TODO: Halt TC / Restart (if allocated+active) TC.
1168 if (env->active_tc.CP0_TCHalt & 1) {
1169 mips_tc_sleep(cpu, env->current_tc);
1170 } else {
1171 mips_tc_wake(cpu, env->current_tc);
1172 }
1173 }
1174
1175 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1176 {
1177 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1178 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1179 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1180
1181 // TODO: Halt TC / Restart (if allocated+active) TC.
1182
1183 if (other_tc == other->current_tc)
1184 other->active_tc.CP0_TCHalt = arg1;
1185 else
1186 other->tcs[other_tc].CP0_TCHalt = arg1;
1187
1188 if (arg1 & 1) {
1189 mips_tc_sleep(other_cpu, other_tc);
1190 } else {
1191 mips_tc_wake(other_cpu, other_tc);
1192 }
1193 }
1194
1195 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1196 {
1197 env->active_tc.CP0_TCContext = arg1;
1198 }
1199
1200 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1201 {
1202 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1203 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1204
1205 if (other_tc == other->current_tc)
1206 other->active_tc.CP0_TCContext = arg1;
1207 else
1208 other->tcs[other_tc].CP0_TCContext = arg1;
1209 }
1210
1211 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1212 {
1213 env->active_tc.CP0_TCSchedule = arg1;
1214 }
1215
1216 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1217 {
1218 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1219 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1220
1221 if (other_tc == other->current_tc)
1222 other->active_tc.CP0_TCSchedule = arg1;
1223 else
1224 other->tcs[other_tc].CP0_TCSchedule = arg1;
1225 }
1226
1227 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1228 {
1229 env->active_tc.CP0_TCScheFBack = arg1;
1230 }
1231
1232 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1233 {
1234 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1235 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1236
1237 if (other_tc == other->current_tc)
1238 other->active_tc.CP0_TCScheFBack = arg1;
1239 else
1240 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1241 }
1242
1243 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1244 {
1245 /* Large physaddr (PABITS) not implemented */
1246 /* 1k pages not implemented */
1247 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1248 }
1249
1250 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1251 {
1252 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1253 }
1254
1255 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1256 {
1257 /* 1k pages not implemented */
1258 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1259 }
1260
1261 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1262 {
1263 /* SmartMIPS not implemented */
1264 /* Large physaddr (PABITS) not implemented */
1265 /* 1k pages not implemented */
1266 env->CP0_PageGrain = 0;
1267 }
1268
1269 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1270 {
1271 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1272 }
1273
1274 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1275 {
1276 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1277 }
1278
1279 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1280 {
1281 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1282 }
1283
1284 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1285 {
1286 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1287 }
1288
1289 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1290 {
1291 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1292 }
1293
1294 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1295 {
1296 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1297 }
1298
1299 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1300 {
1301 uint32_t mask = 0x0000000F;
1302
1303 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1304 mask |= (1 << 29);
1305
1306 if (arg1 & (1 << 29)) {
1307 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1308 } else {
1309 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1310 }
1311 }
1312
1313 env->CP0_HWREna = arg1 & mask;
1314 }
1315
1316 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1317 {
1318 cpu_mips_store_count(env, arg1);
1319 }
1320
1321 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1322 {
1323 target_ulong old, val;
1324
1325 /* 1k pages not implemented */
1326 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1327 #if defined(TARGET_MIPS64)
1328 val &= env->SEGMask;
1329 #endif
1330 old = env->CP0_EntryHi;
1331 env->CP0_EntryHi = val;
1332 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1333 sync_c0_entryhi(env, env->current_tc);
1334 }
1335 /* If the ASID changes, flush qemu's TLB. */
1336 if ((old & 0xFF) != (val & 0xFF))
1337 cpu_mips_tlb_flush(env, 1);
1338 }
1339
1340 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1341 {
1342 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1343 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1344
1345 other->CP0_EntryHi = arg1;
1346 sync_c0_entryhi(other, other_tc);
1347 }
1348
1349 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1350 {
1351 cpu_mips_store_compare(env, arg1);
1352 }
1353
1354 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1355 {
1356 MIPSCPU *cpu = mips_env_get_cpu(env);
1357 uint32_t val, old;
1358 uint32_t mask = env->CP0_Status_rw_bitmask;
1359
1360 val = arg1 & mask;
1361 old = env->CP0_Status;
1362 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1363 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1364 sync_c0_status(env, env, env->current_tc);
1365 } else {
1366 compute_hflags(env);
1367 }
1368
1369 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1370 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1371 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1372 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1373 env->CP0_Cause);
1374 switch (env->hflags & MIPS_HFLAG_KSU) {
1375 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1376 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1377 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1378 default:
1379 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1380 break;
1381 }
1382 }
1383 }
1384
1385 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1386 {
1387 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1388 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1389
1390 other->CP0_Status = arg1 & ~0xf1000018;
1391 sync_c0_status(env, other, other_tc);
1392 }
1393
1394 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1395 {
1396 /* vectored interrupts not implemented, no performance counters. */
1397 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1398 }
1399
1400 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1401 {
1402 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1403 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1404 }
1405
1406 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1407 {
1408 uint32_t mask = 0x00C00300;
1409 uint32_t old = cpu->CP0_Cause;
1410 int i;
1411
1412 if (cpu->insn_flags & ISA_MIPS32R2) {
1413 mask |= 1 << CP0Ca_DC;
1414 }
1415
1416 cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1417
1418 if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1419 if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1420 cpu_mips_stop_count(cpu);
1421 } else {
1422 cpu_mips_start_count(cpu);
1423 }
1424 }
1425
1426 /* Set/reset software interrupts */
1427 for (i = 0 ; i < 2 ; i++) {
1428 if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1429 cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1430 }
1431 }
1432 }
1433
1434 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1435 {
1436 mtc0_cause(env, arg1);
1437 }
1438
1439 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1440 {
1441 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1442 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1443
1444 mtc0_cause(other, arg1);
1445 }
1446
1447 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1448 {
1449 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1450 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1451
1452 return other->CP0_EPC;
1453 }
1454
1455 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1456 {
1457 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1458 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1459
1460 return other->CP0_EBase;
1461 }
1462
1463 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1464 {
1465 /* vectored interrupts not implemented */
1466 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1467 }
1468
1469 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1470 {
1471 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1472 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1473 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1474 }
1475
1476 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1477 {
1478 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1479 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1480
1481 switch (idx) {
1482 case 0: return other->CP0_Config0;
1483 case 1: return other->CP0_Config1;
1484 case 2: return other->CP0_Config2;
1485 case 3: return other->CP0_Config3;
1486 /* 4 and 5 are reserved. */
1487 case 6: return other->CP0_Config6;
1488 case 7: return other->CP0_Config7;
1489 default:
1490 break;
1491 }
1492 return 0;
1493 }
1494
1495 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1496 {
1497 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1498 }
1499
1500 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1501 {
1502 /* tertiary/secondary caches not implemented */
1503 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1504 }
1505
1506 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1507 {
1508 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1509 (arg1 & env->CP0_Config4_rw_bitmask);
1510 }
1511
1512 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1513 {
1514 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1515 (arg1 & env->CP0_Config5_rw_bitmask);
1516 }
1517
1518 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1519 {
1520 target_long mask = env->CP0_LLAddr_rw_bitmask;
1521 arg1 = arg1 << env->CP0_LLAddr_shift;
1522 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1523 }
1524
1525 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1526 {
1527 /* Watch exceptions for instructions, data loads, data stores
1528 not implemented. */
1529 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1530 }
1531
1532 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1533 {
1534 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1535 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1536 }
1537
1538 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1539 {
1540 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1541 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1542 }
1543
1544 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1545 {
1546 env->CP0_Framemask = arg1; /* XXX */
1547 }
1548
1549 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1550 {
1551 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1552 if (arg1 & (1 << CP0DB_DM))
1553 env->hflags |= MIPS_HFLAG_DM;
1554 else
1555 env->hflags &= ~MIPS_HFLAG_DM;
1556 }
1557
1558 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1559 {
1560 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1561 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1562 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1563
1564 /* XXX: Might be wrong, check with EJTAG spec. */
1565 if (other_tc == other->current_tc)
1566 other->active_tc.CP0_Debug_tcstatus = val;
1567 else
1568 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1569 other->CP0_Debug = (other->CP0_Debug &
1570 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1571 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1572 }
1573
1574 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1575 {
1576 env->CP0_Performance0 = arg1 & 0x000007ff;
1577 }
1578
1579 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1580 {
1581 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1582 }
1583
1584 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1585 {
1586 env->CP0_DataLo = arg1; /* XXX */
1587 }
1588
1589 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1590 {
1591 env->CP0_TagHi = arg1; /* XXX */
1592 }
1593
1594 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1595 {
1596 env->CP0_DataHi = arg1; /* XXX */
1597 }
1598
1599 /* MIPS MT functions */
1600 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1601 {
1602 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1603 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1604
1605 if (other_tc == other->current_tc)
1606 return other->active_tc.gpr[sel];
1607 else
1608 return other->tcs[other_tc].gpr[sel];
1609 }
1610
1611 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1612 {
1613 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1614 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1615
1616 if (other_tc == other->current_tc)
1617 return other->active_tc.LO[sel];
1618 else
1619 return other->tcs[other_tc].LO[sel];
1620 }
1621
1622 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1623 {
1624 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1625 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1626
1627 if (other_tc == other->current_tc)
1628 return other->active_tc.HI[sel];
1629 else
1630 return other->tcs[other_tc].HI[sel];
1631 }
1632
1633 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1634 {
1635 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1636 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1637
1638 if (other_tc == other->current_tc)
1639 return other->active_tc.ACX[sel];
1640 else
1641 return other->tcs[other_tc].ACX[sel];
1642 }
1643
1644 target_ulong helper_mftdsp(CPUMIPSState *env)
1645 {
1646 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1647 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1648
1649 if (other_tc == other->current_tc)
1650 return other->active_tc.DSPControl;
1651 else
1652 return other->tcs[other_tc].DSPControl;
1653 }
1654
1655 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1656 {
1657 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1658 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1659
1660 if (other_tc == other->current_tc)
1661 other->active_tc.gpr[sel] = arg1;
1662 else
1663 other->tcs[other_tc].gpr[sel] = arg1;
1664 }
1665
1666 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1667 {
1668 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1669 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1670
1671 if (other_tc == other->current_tc)
1672 other->active_tc.LO[sel] = arg1;
1673 else
1674 other->tcs[other_tc].LO[sel] = arg1;
1675 }
1676
1677 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1678 {
1679 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1680 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1681
1682 if (other_tc == other->current_tc)
1683 other->active_tc.HI[sel] = arg1;
1684 else
1685 other->tcs[other_tc].HI[sel] = arg1;
1686 }
1687
1688 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1689 {
1690 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1691 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1692
1693 if (other_tc == other->current_tc)
1694 other->active_tc.ACX[sel] = arg1;
1695 else
1696 other->tcs[other_tc].ACX[sel] = arg1;
1697 }
1698
1699 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1700 {
1701 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1702 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1703
1704 if (other_tc == other->current_tc)
1705 other->active_tc.DSPControl = arg1;
1706 else
1707 other->tcs[other_tc].DSPControl = arg1;
1708 }
1709
1710 /* MIPS MT functions */
1711 target_ulong helper_dmt(void)
1712 {
1713 // TODO
1714 return 0;
1715 }
1716
1717 target_ulong helper_emt(void)
1718 {
1719 // TODO
1720 return 0;
1721 }
1722
1723 target_ulong helper_dvpe(CPUMIPSState *env)
1724 {
1725 CPUState *other_cs = first_cpu;
1726 target_ulong prev = env->mvp->CP0_MVPControl;
1727
1728 CPU_FOREACH(other_cs) {
1729 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1730 /* Turn off all VPEs except the one executing the dvpe. */
1731 if (&other_cpu->env != env) {
1732 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1733 mips_vpe_sleep(other_cpu);
1734 }
1735 }
1736 return prev;
1737 }
1738
1739 target_ulong helper_evpe(CPUMIPSState *env)
1740 {
1741 CPUState *other_cs = first_cpu;
1742 target_ulong prev = env->mvp->CP0_MVPControl;
1743
1744 CPU_FOREACH(other_cs) {
1745 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1746
1747 if (&other_cpu->env != env
1748 /* If the VPE is WFI, don't disturb its sleep. */
1749 && !mips_vpe_is_wfi(other_cpu)) {
1750 /* Enable the VPE. */
1751 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1752 mips_vpe_wake(other_cpu); /* And wake it up. */
1753 }
1754 }
1755 return prev;
1756 }
1757 #endif /* !CONFIG_USER_ONLY */
1758
1759 void helper_fork(target_ulong arg1, target_ulong arg2)
1760 {
1761 // arg1 = rt, arg2 = rs
1762 // TODO: store to TC register
1763 }
1764
1765 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1766 {
1767 target_long arg1 = arg;
1768
1769 if (arg1 < 0) {
1770 /* No scheduling policy implemented. */
1771 if (arg1 != -2) {
1772 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1773 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1774 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1775 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1776 helper_raise_exception(env, EXCP_THREAD);
1777 }
1778 }
1779 } else if (arg1 == 0) {
1780 if (0 /* TODO: TC underflow */) {
1781 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1782 helper_raise_exception(env, EXCP_THREAD);
1783 } else {
1784 // TODO: Deallocate TC
1785 }
1786 } else if (arg1 > 0) {
1787 /* Yield qualifier inputs not implemented. */
1788 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1789 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1790 helper_raise_exception(env, EXCP_THREAD);
1791 }
1792 return env->CP0_YQMask;
1793 }
1794
1795 #ifndef CONFIG_USER_ONLY
1796 /* TLB management */
1797 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1798 {
1799 MIPSCPU *cpu = mips_env_get_cpu(env);
1800
1801 /* Flush qemu's TLB and discard all shadowed entries. */
1802 tlb_flush(CPU(cpu), flush_global);
1803 env->tlb->tlb_in_use = env->tlb->nb_tlb;
1804 }
1805
1806 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1807 {
1808 /* Discard entries from env->tlb[first] onwards. */
1809 while (env->tlb->tlb_in_use > first) {
1810 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1811 }
1812 }
1813
1814 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1815 {
1816 r4k_tlb_t *tlb;
1817
1818 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1819 tlb = &env->tlb->mmu.r4k.tlb[idx];
1820 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1821 #if defined(TARGET_MIPS64)
1822 tlb->VPN &= env->SEGMask;
1823 #endif
1824 tlb->ASID = env->CP0_EntryHi & 0xFF;
1825 tlb->PageMask = env->CP0_PageMask;
1826 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1827 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1828 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1829 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1830 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1831 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1832 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1833 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1834 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1835 }
1836
1837 void r4k_helper_tlbwi(CPUMIPSState *env)
1838 {
1839 r4k_tlb_t *tlb;
1840 int idx;
1841 target_ulong VPN;
1842 uint8_t ASID;
1843 bool G, V0, D0, V1, D1;
1844
1845 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1846 tlb = &env->tlb->mmu.r4k.tlb[idx];
1847 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1848 #if defined(TARGET_MIPS64)
1849 VPN &= env->SEGMask;
1850 #endif
1851 ASID = env->CP0_EntryHi & 0xff;
1852 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1853 V0 = (env->CP0_EntryLo0 & 2) != 0;
1854 D0 = (env->CP0_EntryLo0 & 4) != 0;
1855 V1 = (env->CP0_EntryLo1 & 2) != 0;
1856 D1 = (env->CP0_EntryLo1 & 4) != 0;
1857
1858 /* Discard cached TLB entries, unless tlbwi is just upgrading access
1859 permissions on the current entry. */
1860 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1861 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1862 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1863 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1864 }
1865
1866 r4k_invalidate_tlb(env, idx, 0);
1867 r4k_fill_tlb(env, idx);
1868 }
1869
1870 void r4k_helper_tlbwr(CPUMIPSState *env)
1871 {
1872 int r = cpu_mips_get_random(env);
1873
1874 r4k_invalidate_tlb(env, r, 1);
1875 r4k_fill_tlb(env, r);
1876 }
1877
1878 void r4k_helper_tlbp(CPUMIPSState *env)
1879 {
1880 r4k_tlb_t *tlb;
1881 target_ulong mask;
1882 target_ulong tag;
1883 target_ulong VPN;
1884 uint8_t ASID;
1885 int i;
1886
1887 ASID = env->CP0_EntryHi & 0xFF;
1888 for (i = 0; i < env->tlb->nb_tlb; i++) {
1889 tlb = &env->tlb->mmu.r4k.tlb[i];
1890 /* 1k pages are not supported. */
1891 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1892 tag = env->CP0_EntryHi & ~mask;
1893 VPN = tlb->VPN & ~mask;
1894 #if defined(TARGET_MIPS64)
1895 tag &= env->SEGMask;
1896 #endif
1897 /* Check ASID, virtual page number & size */
1898 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1899 /* TLB match */
1900 env->CP0_Index = i;
1901 break;
1902 }
1903 }
1904 if (i == env->tlb->nb_tlb) {
1905 /* No match. Discard any shadow entries, if any of them match. */
1906 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1907 tlb = &env->tlb->mmu.r4k.tlb[i];
1908 /* 1k pages are not supported. */
1909 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1910 tag = env->CP0_EntryHi & ~mask;
1911 VPN = tlb->VPN & ~mask;
1912 #if defined(TARGET_MIPS64)
1913 tag &= env->SEGMask;
1914 #endif
1915 /* Check ASID, virtual page number & size */
1916 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1917 r4k_mips_tlb_flush_extra (env, i);
1918 break;
1919 }
1920 }
1921
1922 env->CP0_Index |= 0x80000000;
1923 }
1924 }
1925
1926 void r4k_helper_tlbr(CPUMIPSState *env)
1927 {
1928 r4k_tlb_t *tlb;
1929 uint8_t ASID;
1930 int idx;
1931
1932 ASID = env->CP0_EntryHi & 0xFF;
1933 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1934 tlb = &env->tlb->mmu.r4k.tlb[idx];
1935
1936 /* If this will change the current ASID, flush qemu's TLB. */
1937 if (ASID != tlb->ASID)
1938 cpu_mips_tlb_flush (env, 1);
1939
1940 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1941
1942 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1943 env->CP0_PageMask = tlb->PageMask;
1944 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1945 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1946 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1947 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1948 }
1949
1950 void helper_tlbwi(CPUMIPSState *env)
1951 {
1952 env->tlb->helper_tlbwi(env);
1953 }
1954
1955 void helper_tlbwr(CPUMIPSState *env)
1956 {
1957 env->tlb->helper_tlbwr(env);
1958 }
1959
1960 void helper_tlbp(CPUMIPSState *env)
1961 {
1962 env->tlb->helper_tlbp(env);
1963 }
1964
1965 void helper_tlbr(CPUMIPSState *env)
1966 {
1967 env->tlb->helper_tlbr(env);
1968 }
1969
1970 /* Specials */
1971 target_ulong helper_di(CPUMIPSState *env)
1972 {
1973 target_ulong t0 = env->CP0_Status;
1974
1975 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1976 return t0;
1977 }
1978
1979 target_ulong helper_ei(CPUMIPSState *env)
1980 {
1981 target_ulong t0 = env->CP0_Status;
1982
1983 env->CP0_Status = t0 | (1 << CP0St_IE);
1984 return t0;
1985 }
1986
1987 static void debug_pre_eret(CPUMIPSState *env)
1988 {
1989 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1990 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1991 env->active_tc.PC, env->CP0_EPC);
1992 if (env->CP0_Status & (1 << CP0St_ERL))
1993 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1994 if (env->hflags & MIPS_HFLAG_DM)
1995 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1996 qemu_log("\n");
1997 }
1998 }
1999
2000 static void debug_post_eret(CPUMIPSState *env)
2001 {
2002 MIPSCPU *cpu = mips_env_get_cpu(env);
2003
2004 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2005 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2006 env->active_tc.PC, env->CP0_EPC);
2007 if (env->CP0_Status & (1 << CP0St_ERL))
2008 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2009 if (env->hflags & MIPS_HFLAG_DM)
2010 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2011 switch (env->hflags & MIPS_HFLAG_KSU) {
2012 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2013 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2014 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2015 default:
2016 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2017 break;
2018 }
2019 }
2020 }
2021
2022 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2023 {
2024 env->active_tc.PC = error_pc & ~(target_ulong)1;
2025 if (error_pc & 1) {
2026 env->hflags |= MIPS_HFLAG_M16;
2027 } else {
2028 env->hflags &= ~(MIPS_HFLAG_M16);
2029 }
2030 }
2031
2032 void helper_eret(CPUMIPSState *env)
2033 {
2034 debug_pre_eret(env);
2035 if (env->CP0_Status & (1 << CP0St_ERL)) {
2036 set_pc(env, env->CP0_ErrorEPC);
2037 env->CP0_Status &= ~(1 << CP0St_ERL);
2038 } else {
2039 set_pc(env, env->CP0_EPC);
2040 env->CP0_Status &= ~(1 << CP0St_EXL);
2041 }
2042 compute_hflags(env);
2043 debug_post_eret(env);
2044 env->lladdr = 1;
2045 }
2046
2047 void helper_deret(CPUMIPSState *env)
2048 {
2049 debug_pre_eret(env);
2050 set_pc(env, env->CP0_DEPC);
2051
2052 env->hflags &= MIPS_HFLAG_DM;
2053 compute_hflags(env);
2054 debug_post_eret(env);
2055 env->lladdr = 1;
2056 }
2057 #endif /* !CONFIG_USER_ONLY */
2058
2059 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2060 {
2061 if ((env->hflags & MIPS_HFLAG_CP0) ||
2062 (env->CP0_HWREna & (1 << 0)))
2063 return env->CP0_EBase & 0x3ff;
2064 else
2065 helper_raise_exception(env, EXCP_RI);
2066
2067 return 0;
2068 }
2069
2070 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2071 {
2072 if ((env->hflags & MIPS_HFLAG_CP0) ||
2073 (env->CP0_HWREna & (1 << 1)))
2074 return env->SYNCI_Step;
2075 else
2076 helper_raise_exception(env, EXCP_RI);
2077
2078 return 0;
2079 }
2080
2081 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2082 {
2083 if ((env->hflags & MIPS_HFLAG_CP0) ||
2084 (env->CP0_HWREna & (1 << 2)))
2085 return env->CP0_Count;
2086 else
2087 helper_raise_exception(env, EXCP_RI);
2088
2089 return 0;
2090 }
2091
2092 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2093 {
2094 if ((env->hflags & MIPS_HFLAG_CP0) ||
2095 (env->CP0_HWREna & (1 << 3)))
2096 return env->CCRes;
2097 else
2098 helper_raise_exception(env, EXCP_RI);
2099
2100 return 0;
2101 }
2102
2103 void helper_pmon(CPUMIPSState *env, int function)
2104 {
2105 function /= 2;
2106 switch (function) {
2107 case 2: /* TODO: char inbyte(int waitflag); */
2108 if (env->active_tc.gpr[4] == 0)
2109 env->active_tc.gpr[2] = -1;
2110 /* Fall through */
2111 case 11: /* TODO: char inbyte (void); */
2112 env->active_tc.gpr[2] = -1;
2113 break;
2114 case 3:
2115 case 12:
2116 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2117 break;
2118 case 17:
2119 break;
2120 case 158:
2121 {
2122 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2123 printf("%s", fmt);
2124 }
2125 break;
2126 }
2127 }
2128
2129 void helper_wait(CPUMIPSState *env)
2130 {
2131 CPUState *cs = CPU(mips_env_get_cpu(env));
2132
2133 cs->halted = 1;
2134 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2135 helper_raise_exception(env, EXCP_HLT);
2136 }
2137
2138 #if !defined(CONFIG_USER_ONLY)
2139
2140 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2141 int is_write, int is_user, uintptr_t retaddr)
2142 {
2143 MIPSCPU *cpu = MIPS_CPU(cs);
2144 CPUMIPSState *env = &cpu->env;
2145
2146 env->CP0_BadVAddr = addr;
2147 do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2148 }
2149
2150 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2151 uintptr_t retaddr)
2152 {
2153 int ret;
2154
2155 ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2156 if (ret) {
2157 MIPSCPU *cpu = MIPS_CPU(cs);
2158 CPUMIPSState *env = &cpu->env;
2159
2160 do_raise_exception_err(env, cs->exception_index,
2161 env->error_code, retaddr);
2162 }
2163 }
2164
2165 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2166 bool is_write, bool is_exec, int unused,
2167 unsigned size)
2168 {
2169 MIPSCPU *cpu = MIPS_CPU(cs);
2170 CPUMIPSState *env = &cpu->env;
2171
2172 /*
2173 * Raising an exception with KVM enabled will crash because it won't be from
2174 * the main execution loop so the longjmp won't have a matching setjmp.
2175 * Until we can trigger a bus error exception through KVM lets just ignore
2176 * the access.
2177 */
2178 if (kvm_enabled()) {
2179 return;
2180 }
2181
2182 if (is_exec) {
2183 helper_raise_exception(env, EXCP_IBE);
2184 } else {
2185 helper_raise_exception(env, EXCP_DBE);
2186 }
2187 }
2188 #endif /* !CONFIG_USER_ONLY */
2189
2190 /* Complex FPU operations which may need stack space. */
2191
2192 #define FLOAT_TWO32 make_float32(1 << 30)
2193 #define FLOAT_TWO64 make_float64(1ULL << 62)
2194 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2195 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2196
2197 /* convert MIPS rounding mode in FCR31 to IEEE library */
2198 static unsigned int ieee_rm[] = {
2199 float_round_nearest_even,
2200 float_round_to_zero,
2201 float_round_up,
2202 float_round_down
2203 };
2204
2205 static inline void restore_rounding_mode(CPUMIPSState *env)
2206 {
2207 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2208 &env->active_fpu.fp_status);
2209 }
2210
2211 static inline void restore_flush_mode(CPUMIPSState *env)
2212 {
2213 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2214 &env->active_fpu.fp_status);
2215 }
2216
2217 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2218 {
2219 target_ulong arg1 = 0;
2220
2221 switch (reg) {
2222 case 0:
2223 arg1 = (int32_t)env->active_fpu.fcr0;
2224 break;
2225 case 1:
2226 /* UFR Support - Read Status FR */
2227 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2228 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2229 arg1 = (int32_t)
2230 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2231 } else {
2232 helper_raise_exception(env, EXCP_RI);
2233 }
2234 }
2235 break;
2236 case 25:
2237 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2238 break;
2239 case 26:
2240 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2241 break;
2242 case 28:
2243 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2244 break;
2245 default:
2246 arg1 = (int32_t)env->active_fpu.fcr31;
2247 break;
2248 }
2249
2250 return arg1;
2251 }
2252
2253 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2254 {
2255 switch (fs) {
2256 case 1:
2257 /* UFR Alias - Reset Status FR */
2258 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2259 return;
2260 }
2261 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2262 env->CP0_Status &= ~(1 << CP0St_FR);
2263 compute_hflags(env);
2264 } else {
2265 helper_raise_exception(env, EXCP_RI);
2266 }
2267 break;
2268 case 4:
2269 /* UNFR Alias - Set Status FR */
2270 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2271 return;
2272 }
2273 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2274 env->CP0_Status |= (1 << CP0St_FR);
2275 compute_hflags(env);
2276 } else {
2277 helper_raise_exception(env, EXCP_RI);
2278 }
2279 break;
2280 case 25:
2281 if (arg1 & 0xffffff00)
2282 return;
2283 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2284 ((arg1 & 0x1) << 23);
2285 break;
2286 case 26:
2287 if (arg1 & 0x007c0000)
2288 return;
2289 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2290 break;
2291 case 28:
2292 if (arg1 & 0x007c0000)
2293 return;
2294 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2295 ((arg1 & 0x4) << 22);
2296 break;
2297 case 31:
2298 if (arg1 & 0x007c0000)
2299 return;
2300 env->active_fpu.fcr31 = arg1;
2301 break;
2302 default:
2303 return;
2304 }
2305 /* set rounding mode */
2306 restore_rounding_mode(env);
2307 /* set flush-to-zero mode */
2308 restore_flush_mode(env);
2309 set_float_exception_flags(0, &env->active_fpu.fp_status);
2310 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2311 do_raise_exception(env, EXCP_FPE, GETPC());
2312 }
2313
2314 static inline int ieee_ex_to_mips(int xcpt)
2315 {
2316 int ret = 0;
2317 if (xcpt) {
2318 if (xcpt & float_flag_invalid) {
2319 ret |= FP_INVALID;
2320 }
2321 if (xcpt & float_flag_overflow) {
2322 ret |= FP_OVERFLOW;
2323 }
2324 if (xcpt & float_flag_underflow) {
2325 ret |= FP_UNDERFLOW;
2326 }
2327 if (xcpt & float_flag_divbyzero) {
2328 ret |= FP_DIV0;
2329 }
2330 if (xcpt & float_flag_inexact) {
2331 ret |= FP_INEXACT;
2332 }
2333 }
2334 return ret;
2335 }
2336
2337 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2338 {
2339 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2340
2341 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2342
2343 if (tmp) {
2344 set_float_exception_flags(0, &env->active_fpu.fp_status);
2345
2346 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2347 do_raise_exception(env, EXCP_FPE, pc);
2348 } else {
2349 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2350 }
2351 }
2352 }
2353
2354 /* Float support.
2355 Single precition routines have a "s" suffix, double precision a
2356 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2357 paired single lower "pl", paired single upper "pu". */
2358
2359 /* unary operations, modifying fp status */
2360 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2361 {
2362 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2363 update_fcr31(env, GETPC());
2364 return fdt0;
2365 }
2366
2367 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2368 {
2369 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2370 update_fcr31(env, GETPC());
2371 return fst0;
2372 }
2373
2374 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2375 {
2376 uint64_t fdt2;
2377
2378 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2379 update_fcr31(env, GETPC());
2380 return fdt2;
2381 }
2382
2383 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2384 {
2385 uint64_t fdt2;
2386
2387 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2388 update_fcr31(env, GETPC());
2389 return fdt2;
2390 }
2391
2392 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2393 {
2394 uint64_t fdt2;
2395
2396 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2397 update_fcr31(env, GETPC());
2398 return fdt2;
2399 }
2400
2401 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2402 {
2403 uint64_t dt2;
2404
2405 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2406 if (get_float_exception_flags(&env->active_fpu.fp_status)
2407 & (float_flag_invalid | float_flag_overflow)) {
2408 dt2 = FP_TO_INT64_OVERFLOW;
2409 }
2410 update_fcr31(env, GETPC());
2411 return dt2;
2412 }
2413
2414 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2415 {
2416 uint64_t dt2;
2417
2418 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2419 if (get_float_exception_flags(&env->active_fpu.fp_status)
2420 & (float_flag_invalid | float_flag_overflow)) {
2421 dt2 = FP_TO_INT64_OVERFLOW;
2422 }
2423 update_fcr31(env, GETPC());
2424 return dt2;
2425 }
2426
2427 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2428 {
2429 uint32_t fst2;
2430 uint32_t fsth2;
2431
2432 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2433 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2434 update_fcr31(env, GETPC());
2435 return ((uint64_t)fsth2 << 32) | fst2;
2436 }
2437
2438 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2439 {
2440 uint32_t wt2;
2441 uint32_t wth2;
2442 int excp, excph;
2443
2444 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2445 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2446 if (excp & (float_flag_overflow | float_flag_invalid)) {
2447 wt2 = FP_TO_INT32_OVERFLOW;
2448 }
2449
2450 set_float_exception_flags(0, &env->active_fpu.fp_status);
2451 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2452 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2453 if (excph & (float_flag_overflow | float_flag_invalid)) {
2454 wth2 = FP_TO_INT32_OVERFLOW;
2455 }
2456
2457 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2458 update_fcr31(env, GETPC());
2459
2460 return ((uint64_t)wth2 << 32) | wt2;
2461 }
2462
2463 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2464 {
2465 uint32_t fst2;
2466
2467 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2468 update_fcr31(env, GETPC());
2469 return fst2;
2470 }
2471
2472 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2473 {
2474 uint32_t fst2;
2475
2476 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2477 update_fcr31(env, GETPC());
2478 return fst2;
2479 }
2480
2481 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2482 {
2483 uint32_t fst2;
2484
2485 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2486 update_fcr31(env, GETPC());
2487 return fst2;
2488 }
2489
2490 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2491 {
2492 uint32_t wt2;
2493
2494 wt2 = wt0;
2495 update_fcr31(env, GETPC());
2496 return wt2;
2497 }
2498
2499 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2500 {
2501 uint32_t wt2;
2502
2503 wt2 = wth0;
2504 update_fcr31(env, GETPC());
2505 return wt2;
2506 }
2507
2508 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2509 {
2510 uint32_t wt2;
2511
2512 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2513 update_fcr31(env, GETPC());
2514 if (get_float_exception_flags(&env->active_fpu.fp_status)
2515 & (float_flag_invalid | float_flag_overflow)) {
2516 wt2 = FP_TO_INT32_OVERFLOW;
2517 }
2518 return wt2;
2519 }
2520
2521 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2522 {
2523 uint32_t wt2;
2524
2525 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2526 if (get_float_exception_flags(&env->active_fpu.fp_status)
2527 & (float_flag_invalid | float_flag_overflow)) {
2528 wt2 = FP_TO_INT32_OVERFLOW;
2529 }
2530 update_fcr31(env, GETPC());
2531 return wt2;
2532 }
2533
2534 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2535 {
2536 uint64_t dt2;
2537
2538 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2539 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2540 restore_rounding_mode(env);
2541 if (get_float_exception_flags(&env->active_fpu.fp_status)
2542 & (float_flag_invalid | float_flag_overflow)) {
2543 dt2 = FP_TO_INT64_OVERFLOW;
2544 }
2545 update_fcr31(env, GETPC());
2546 return dt2;
2547 }
2548
2549 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2550 {
2551 uint64_t dt2;
2552
2553 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2554 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2555 restore_rounding_mode(env);
2556 if (get_float_exception_flags(&env->active_fpu.fp_status)
2557 & (float_flag_invalid | float_flag_overflow)) {
2558 dt2 = FP_TO_INT64_OVERFLOW;
2559 }
2560 update_fcr31(env, GETPC());
2561 return dt2;
2562 }
2563
2564 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2565 {
2566 uint32_t wt2;
2567
2568 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2569 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2570 restore_rounding_mode(env);
2571 if (get_float_exception_flags(&env->active_fpu.fp_status)
2572 & (float_flag_invalid | float_flag_overflow)) {
2573 wt2 = FP_TO_INT32_OVERFLOW;
2574 }
2575 update_fcr31(env, GETPC());
2576 return wt2;
2577 }
2578
2579 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2580 {
2581 uint32_t wt2;
2582
2583 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2584 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2585 restore_rounding_mode(env);
2586 if (get_float_exception_flags(&env->active_fpu.fp_status)
2587 & (float_flag_invalid | float_flag_overflow)) {
2588 wt2 = FP_TO_INT32_OVERFLOW;
2589 }
2590 update_fcr31(env, GETPC());
2591 return wt2;
2592 }
2593
2594 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2595 {
2596 uint64_t dt2;
2597
2598 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2599 if (get_float_exception_flags(&env->active_fpu.fp_status)
2600 & (float_flag_invalid | float_flag_overflow)) {
2601 dt2 = FP_TO_INT64_OVERFLOW;
2602 }
2603 update_fcr31(env, GETPC());
2604 return dt2;
2605 }
2606
2607 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2608 {
2609 uint64_t dt2;
2610
2611 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2612 if (get_float_exception_flags(&env->active_fpu.fp_status)
2613 & (float_flag_invalid | float_flag_overflow)) {
2614 dt2 = FP_TO_INT64_OVERFLOW;
2615 }
2616 update_fcr31(env, GETPC());
2617 return dt2;
2618 }
2619
2620 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2621 {
2622 uint32_t wt2;
2623
2624 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2625 if (get_float_exception_flags(&env->active_fpu.fp_status)
2626 & (float_flag_invalid | float_flag_overflow)) {
2627 wt2 = FP_TO_INT32_OVERFLOW;
2628 }
2629 update_fcr31(env, GETPC());
2630 return wt2;
2631 }
2632
2633 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2634 {
2635 uint32_t wt2;
2636
2637 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2638 if (get_float_exception_flags(&env->active_fpu.fp_status)
2639 & (float_flag_invalid | float_flag_overflow)) {
2640 wt2 = FP_TO_INT32_OVERFLOW;
2641 }
2642 update_fcr31(env, GETPC());
2643 return wt2;
2644 }
2645
2646 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2647 {
2648 uint64_t dt2;
2649
2650 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2651 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2652 restore_rounding_mode(env);
2653 if (get_float_exception_flags(&env->active_fpu.fp_status)
2654 & (float_flag_invalid | float_flag_overflow)) {
2655 dt2 = FP_TO_INT64_OVERFLOW;
2656 }
2657 update_fcr31(env, GETPC());
2658 return dt2;
2659 }
2660
2661 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2662 {
2663 uint64_t dt2;
2664
2665 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2666 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2667 restore_rounding_mode(env);
2668 if (get_float_exception_flags(&env->active_fpu.fp_status)
2669 & (float_flag_invalid | float_flag_overflow)) {
2670 dt2 = FP_TO_INT64_OVERFLOW;
2671 }
2672 update_fcr31(env, GETPC());
2673 return dt2;
2674 }
2675
2676 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2677 {
2678 uint32_t wt2;
2679
2680 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2681 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2682 restore_rounding_mode(env);
2683 if (get_float_exception_flags(&env->active_fpu.fp_status)
2684 & (float_flag_invalid | float_flag_overflow)) {
2685 wt2 = FP_TO_INT32_OVERFLOW;
2686 }
2687 update_fcr31(env, GETPC());
2688 return wt2;
2689 }
2690
2691 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2692 {
2693 uint32_t wt2;
2694
2695 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2696 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2697 restore_rounding_mode(env);
2698 if (get_float_exception_flags(&env->active_fpu.fp_status)
2699 & (float_flag_invalid | float_flag_overflow)) {
2700 wt2 = FP_TO_INT32_OVERFLOW;
2701 }
2702 update_fcr31(env, GETPC());
2703 return wt2;
2704 }
2705
2706 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2707 {
2708 uint64_t dt2;
2709
2710 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2711 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2712 restore_rounding_mode(env);
2713 if (get_float_exception_flags(&env->active_fpu.fp_status)
2714 & (float_flag_invalid | float_flag_overflow)) {
2715 dt2 = FP_TO_INT64_OVERFLOW;
2716 }
2717 update_fcr31(env, GETPC());
2718 return dt2;
2719 }
2720
2721 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2722 {
2723 uint64_t dt2;
2724
2725 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2726 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2727 restore_rounding_mode(env);
2728 if (get_float_exception_flags(&env->active_fpu.fp_status)
2729 & (float_flag_invalid | float_flag_overflow)) {
2730 dt2 = FP_TO_INT64_OVERFLOW;
2731 }
2732 update_fcr31(env, GETPC());
2733 return dt2;
2734 }
2735
2736 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2737 {
2738 uint32_t wt2;
2739
2740 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2741 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2742 restore_rounding_mode(env);
2743 if (get_float_exception_flags(&env->active_fpu.fp_status)
2744 & (float_flag_invalid | float_flag_overflow)) {
2745 wt2 = FP_TO_INT32_OVERFLOW;
2746 }
2747 update_fcr31(env, GETPC());
2748 return wt2;
2749 }
2750
2751 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2752 {
2753 uint32_t wt2;
2754
2755 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2756 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2757 restore_rounding_mode(env);
2758 if (get_float_exception_flags(&env->active_fpu.fp_status)
2759 & (float_flag_invalid | float_flag_overflow)) {
2760 wt2 = FP_TO_INT32_OVERFLOW;
2761 }
2762 update_fcr31(env, GETPC());
2763 return wt2;
2764 }
2765
2766 /* unary operations, not modifying fp status */
2767 #define FLOAT_UNOP(name) \
2768 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2769 { \
2770 return float64_ ## name(fdt0); \
2771 } \
2772 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2773 { \
2774 return float32_ ## name(fst0); \
2775 } \
2776 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2777 { \
2778 uint32_t wt0; \
2779 uint32_t wth0; \
2780 \
2781 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2782 wth0 = float32_ ## name(fdt0 >> 32); \
2783 return ((uint64_t)wth0 << 32) | wt0; \
2784 }
2785 FLOAT_UNOP(abs)
2786 FLOAT_UNOP(chs)
2787 #undef FLOAT_UNOP
2788
2789 /* MIPS specific unary operations */
2790 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2791 {
2792 uint64_t fdt2;
2793
2794 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2795 update_fcr31(env, GETPC());
2796 return fdt2;
2797 }
2798
2799 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2800 {
2801 uint32_t fst2;
2802
2803 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2804 update_fcr31(env, GETPC());
2805 return fst2;
2806 }
2807
2808 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2809 {
2810 uint64_t fdt2;
2811
2812 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2813 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2814 update_fcr31(env, GETPC());
2815 return fdt2;
2816 }
2817
2818 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2819 {
2820 uint32_t fst2;
2821
2822 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2823 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2824 update_fcr31(env, GETPC());
2825 return fst2;
2826 }
2827
2828 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2829 {
2830 uint64_t fdt2;
2831
2832 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2833 update_fcr31(env, GETPC());
2834 return fdt2;
2835 }
2836
2837 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2838 {
2839 uint32_t fst2;
2840
2841 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2842 update_fcr31(env, GETPC());
2843 return fst2;
2844 }
2845
2846 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2847 {
2848 uint32_t fst2;
2849 uint32_t fsth2;
2850
2851 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2852 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2853 update_fcr31(env, GETPC());
2854 return ((uint64_t)fsth2 << 32) | fst2;
2855 }
2856
2857 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2858 {
2859 uint64_t fdt2;
2860
2861 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2862 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2863 update_fcr31(env, GETPC());
2864 return fdt2;
2865 }
2866
2867 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2868 {
2869 uint32_t fst2;
2870
2871 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2872 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2873 update_fcr31(env, GETPC());
2874 return fst2;
2875 }
2876
2877 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2878 {
2879 uint32_t fst2;
2880 uint32_t fsth2;
2881
2882 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2883 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2884 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2885 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2886 update_fcr31(env, GETPC());
2887 return ((uint64_t)fsth2 << 32) | fst2;
2888 }
2889
2890 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2891
2892 /* binary operations */
2893 #define FLOAT_BINOP(name) \
2894 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2895 uint64_t fdt0, uint64_t fdt1) \
2896 { \
2897 uint64_t dt2; \
2898 \
2899 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2900 update_fcr31(env, GETPC()); \
2901 return dt2; \
2902 } \
2903 \
2904 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2905 uint32_t fst0, uint32_t fst1) \
2906 { \
2907 uint32_t wt2; \
2908 \
2909 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2910 update_fcr31(env, GETPC()); \
2911 return wt2; \
2912 } \
2913 \
2914 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2915 uint64_t fdt0, \
2916 uint64_t fdt1) \
2917 { \
2918 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2919 uint32_t fsth0 = fdt0 >> 32; \
2920 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2921 uint32_t fsth1 = fdt1 >> 32; \
2922 uint32_t wt2; \
2923 uint32_t wth2; \
2924 \
2925 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2926 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2927 update_fcr31(env, GETPC()); \
2928 return ((uint64_t)wth2 << 32) | wt2; \
2929 }
2930
2931 FLOAT_BINOP(add)
2932 FLOAT_BINOP(sub)
2933 FLOAT_BINOP(mul)
2934 FLOAT_BINOP(div)
2935 #undef FLOAT_BINOP
2936
2937 #define UNFUSED_FMA(prefix, a, b, c, flags) \
2938 { \
2939 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
2940 if ((flags) & float_muladd_negate_c) { \
2941 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
2942 } else { \
2943 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
2944 } \
2945 if ((flags) & float_muladd_negate_result) { \
2946 a = prefix##_chs(a); \
2947 } \
2948 }
2949
2950 /* FMA based operations */
2951 #define FLOAT_FMA(name, type) \
2952 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2953 uint64_t fdt0, uint64_t fdt1, \
2954 uint64_t fdt2) \
2955 { \
2956 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
2957 update_fcr31(env, GETPC()); \
2958 return fdt0; \
2959 } \
2960 \
2961 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2962 uint32_t fst0, uint32_t fst1, \
2963 uint32_t fst2) \
2964 { \
2965 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
2966 update_fcr31(env, GETPC()); \
2967 return fst0; \
2968 } \
2969 \
2970 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2971 uint64_t fdt0, uint64_t fdt1, \
2972 uint64_t fdt2) \
2973 { \
2974 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2975 uint32_t fsth0 = fdt0 >> 32; \
2976 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2977 uint32_t fsth1 = fdt1 >> 32; \
2978 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2979 uint32_t fsth2 = fdt2 >> 32; \
2980 \
2981 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
2982 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
2983 update_fcr31(env, GETPC()); \
2984 return ((uint64_t)fsth0 << 32) | fst0; \
2985 }
2986 FLOAT_FMA(madd, 0)
2987 FLOAT_FMA(msub, float_muladd_negate_c)
2988 FLOAT_FMA(nmadd, float_muladd_negate_result)
2989 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2990 #undef FLOAT_FMA
2991
2992 /* MIPS specific binary operations */
2993 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2994 {
2995 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2996 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2997 update_fcr31(env, GETPC());
2998 return fdt2;
2999 }
3000
3001 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3002 {
3003 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3004 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3005 update_fcr31(env, GETPC());
3006 return fst2;
3007 }
3008
3009 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3010 {
3011 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3012 uint32_t fsth0 = fdt0 >> 32;
3013 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3014 uint32_t fsth2 = fdt2 >> 32;
3015
3016 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3017 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3018 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3019 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3020 update_fcr31(env, GETPC());
3021 return ((uint64_t)fsth2 << 32) | fst2;
3022 }
3023
3024 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3025 {
3026 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3027 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3028 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3029 update_fcr31(env, GETPC());
3030 return fdt2;
3031 }
3032
3033 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3034 {
3035 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3036 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3037 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3038 update_fcr31(env, GETPC());
3039 return fst2;
3040 }
3041
3042 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3043 {
3044 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3045 uint32_t fsth0 = fdt0 >> 32;
3046 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3047 uint32_t fsth2 = fdt2 >> 32;
3048
3049 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3050 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3051 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3052 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3053 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3054 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3055 update_fcr31(env, GETPC());
3056 return ((uint64_t)fsth2 << 32) | fst2;
3057 }
3058
3059 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3060 {
3061 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3062 uint32_t fsth0 = fdt0 >> 32;
3063 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3064 uint32_t fsth1 = fdt1 >> 32;
3065 uint32_t fst2;
3066 uint32_t fsth2;
3067
3068 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3069 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3070 update_fcr31(env, GETPC());
3071 return ((uint64_t)fsth2 << 32) | fst2;
3072 }
3073
3074 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3075 {
3076 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3077 uint32_t fsth0 = fdt0 >> 32;
3078 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3079 uint32_t fsth1 = fdt1 >> 32;
3080 uint32_t fst2;
3081 uint32_t fsth2;
3082
3083 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3084 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3085 update_fcr31(env, GETPC());
3086 return ((uint64_t)fsth2 << 32) | fst2;
3087 }
3088
3089 /* compare operations */
3090 #define FOP_COND_D(op, cond) \
3091 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3092 uint64_t fdt1, int cc) \
3093 { \
3094 int c; \
3095 c = cond; \
3096 update_fcr31(env, GETPC()); \
3097 if (c) \
3098 SET_FP_COND(cc, env->active_fpu); \
3099 else \
3100 CLEAR_FP_COND(cc, env->active_fpu); \
3101 } \
3102 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3103 uint64_t fdt1, int cc) \
3104 { \
3105 int c; \
3106 fdt0 = float64_abs(fdt0); \
3107 fdt1 = float64_abs(fdt1); \
3108 c = cond; \
3109 update_fcr31(env, GETPC()); \
3110 if (c) \
3111 SET_FP_COND(cc, env->active_fpu); \
3112 else \
3113 CLEAR_FP_COND(cc, env->active_fpu); \
3114 }
3115
3116 /* NOTE: the comma operator will make "cond" to eval to false,
3117 * but float64_unordered_quiet() is still called. */
3118 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3119 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3120 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3121 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3122 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3123 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3124 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3125 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3126 /* NOTE: the comma operator will make "cond" to eval to false,
3127 * but float64_unordered() is still called. */
3128 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3129 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3130 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3131 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3132 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3133 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3134 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3135 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3136
3137 #define FOP_COND_S(op, cond) \
3138 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3139 uint32_t fst1, int cc) \
3140 { \
3141 int c; \
3142 c = cond; \
3143 update_fcr31(env, GETPC()); \
3144 if (c) \
3145 SET_FP_COND(cc, env->active_fpu); \
3146 else \
3147 CLEAR_FP_COND(cc, env->active_fpu); \
3148 } \
3149 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3150 uint32_t fst1, int cc) \
3151 { \
3152 int c; \
3153 fst0 = float32_abs(fst0); \
3154 fst1 = float32_abs(fst1); \
3155 c = cond; \
3156 update_fcr31(env, GETPC()); \
3157 if (c) \
3158 SET_FP_COND(cc, env->active_fpu); \
3159 else \
3160 CLEAR_FP_COND(cc, env->active_fpu); \
3161 }
3162
3163 /* NOTE: the comma operator will make "cond" to eval to false,
3164 * but float32_unordered_quiet() is still called. */
3165 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3166 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3167 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3168 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3169 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3170 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3171 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3172 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3173 /* NOTE: the comma operator will make "cond" to eval to false,
3174 * but float32_unordered() is still called. */
3175 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3176 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3177 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3178 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3179 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3180 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3181 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
3182 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3183
3184 #define FOP_COND_PS(op, condl, condh) \
3185 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3186 uint64_t fdt1, int cc) \
3187 { \
3188 uint32_t fst0, fsth0, fst1, fsth1; \
3189 int ch, cl; \
3190 fst0 = fdt0 & 0XFFFFFFFF; \
3191 fsth0 = fdt0 >> 32; \
3192 fst1 = fdt1 & 0XFFFFFFFF; \
3193 fsth1 = fdt1 >> 32; \
3194 cl = condl; \
3195 ch = condh; \
3196 update_fcr31(env, GETPC()); \
3197 if (cl) \
3198 SET_FP_COND(cc, env->active_fpu); \
3199 else \
3200 CLEAR_FP_COND(cc, env->active_fpu); \
3201 if (ch) \
3202 SET_FP_COND(cc + 1, env->active_fpu); \
3203 else \
3204 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3205 } \
3206 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3207 uint64_t fdt1, int cc) \
3208 { \
3209 uint32_t fst0, fsth0, fst1, fsth1; \
3210 int ch, cl; \
3211 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3212 fsth0 = float32_abs(fdt0 >> 32); \
3213 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3214 fsth1 = float32_abs(fdt1 >> 32); \
3215 cl = condl; \
3216 ch = condh; \
3217 update_fcr31(env, GETPC()); \
3218 if (cl) \
3219 SET_FP_COND(cc, env->active_fpu); \
3220 else \
3221 CLEAR_FP_COND(cc, env->active_fpu); \
3222 if (ch) \
3223 SET_FP_COND(cc + 1, env->active_fpu); \
3224 else \
3225 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3226 }
3227
3228 /* NOTE: the comma operator will make "cond" to eval to false,
3229 * but float32_unordered_quiet() is still called. */
3230 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3231 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3232 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3233 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3234 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3235 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3236 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3237 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3238 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3239 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3240 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3241 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3242 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3243 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3244 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3245 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3246 /* NOTE: the comma operator will make "cond" to eval to false,
3247 * but float32_unordered() is still called. */
3248 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3249 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3250 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3251 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3252 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3253 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3254 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3255 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3256 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3257 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3258 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3259 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3260 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
3261 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3262 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3263 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
CRIS target port of Qemu