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ahci: Correct PIO/D2H FIS responses
[qemu/cris-port.git] / hw / ide / ahci.c
blob03df4623e978e95777210903441ebe3e64201509
1 /*
2 * QEMU AHCI Emulation
3 *
4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
24 #include <hw/hw.h>
25 #include <hw/pci/msi.h>
26 #include <hw/i386/pc.h>
27 #include <hw/pci/pci.h>
28 #include <hw/sysbus.h>
29
30 #include "monitor/monitor.h"
31 #include "sysemu/block-backend.h"
32 #include "sysemu/dma.h"
33 #include "internal.h"
34 #include <hw/ide/pci.h>
35 #include <hw/ide/ahci.h>
36
37 /* #define DEBUG_AHCI */
38
39 #ifdef DEBUG_AHCI
40 #define DPRINTF(port, fmt, ...) \
41 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \
42 fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
43 #else
44 #define DPRINTF(port, fmt, ...) do {} while(0)
45 #endif
46
47 static void check_cmd(AHCIState *s, int port);
48 static int handle_cmd(AHCIState *s,int port,int slot);
49 static void ahci_reset_port(AHCIState *s, int port);
50 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis);
51 static void ahci_init_d2h(AHCIDevice *ad);
52
53 static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
54 {
55 uint32_t val;
56 AHCIPortRegs *pr;
57 pr = &s->dev[port].port_regs;
58
59 switch (offset) {
60 case PORT_LST_ADDR:
61 val = pr->lst_addr;
62 break;
63 case PORT_LST_ADDR_HI:
64 val = pr->lst_addr_hi;
65 break;
66 case PORT_FIS_ADDR:
67 val = pr->fis_addr;
68 break;
69 case PORT_FIS_ADDR_HI:
70 val = pr->fis_addr_hi;
71 break;
72 case PORT_IRQ_STAT:
73 val = pr->irq_stat;
74 break;
75 case PORT_IRQ_MASK:
76 val = pr->irq_mask;
77 break;
78 case PORT_CMD:
79 val = pr->cmd;
80 break;
81 case PORT_TFDATA:
82 val = pr->tfdata;
83 break;
84 case PORT_SIG:
85 val = pr->sig;
86 break;
87 case PORT_SCR_STAT:
88 if (s->dev[port].port.ifs[0].blk) {
89 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP |
90 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE;
91 } else {
92 val = SATA_SCR_SSTATUS_DET_NODEV;
93 }
94 break;
95 case PORT_SCR_CTL:
96 val = pr->scr_ctl;
97 break;
98 case PORT_SCR_ERR:
99 val = pr->scr_err;
100 break;
101 case PORT_SCR_ACT:
102 pr->scr_act &= ~s->dev[port].finished;
103 s->dev[port].finished = 0;
104 val = pr->scr_act;
105 break;
106 case PORT_CMD_ISSUE:
107 val = pr->cmd_issue;
108 break;
109 case PORT_RESERVED:
110 default:
111 val = 0;
112 }
113 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
114 return val;
115
116 }
117
118 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
119 {
120 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
121 PCIDevice *pci_dev =
122 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE);
123
124 DPRINTF(0, "raise irq\n");
125
126 if (pci_dev && msi_enabled(pci_dev)) {
127 msi_notify(pci_dev, 0);
128 } else {
129 qemu_irq_raise(s->irq);
130 }
131 }
132
133 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
134 {
135 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
136 PCIDevice *pci_dev =
137 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE);
138
139 DPRINTF(0, "lower irq\n");
140
141 if (!pci_dev || !msi_enabled(pci_dev)) {
142 qemu_irq_lower(s->irq);
143 }
144 }
145
146 static void ahci_check_irq(AHCIState *s)
147 {
148 int i;
149
150 DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus);
151
152 s->control_regs.irqstatus = 0;
153 for (i = 0; i < s->ports; i++) {
154 AHCIPortRegs *pr = &s->dev[i].port_regs;
155 if (pr->irq_stat & pr->irq_mask) {
156 s->control_regs.irqstatus |= (1 << i);
157 }
158 }
159
160 if (s->control_regs.irqstatus &&
161 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
162 ahci_irq_raise(s, NULL);
163 } else {
164 ahci_irq_lower(s, NULL);
165 }
166 }
167
168 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
169 int irq_type)
170 {
171 DPRINTF(d->port_no, "trigger irq %#x -> %x\n",
172 irq_type, d->port_regs.irq_mask & irq_type);
173
174 d->port_regs.irq_stat |= irq_type;
175 ahci_check_irq(s);
176 }
177
178 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr,
179 uint32_t wanted)
180 {
181 hwaddr len = wanted;
182
183 if (*ptr) {
184 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len);
185 }
186
187 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE);
188 if (len < wanted) {
189 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len);
190 *ptr = NULL;
191 }
192 }
193
194 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
195 {
196 AHCIPortRegs *pr = &s->dev[port].port_regs;
197
198 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
199 switch (offset) {
200 case PORT_LST_ADDR:
201 pr->lst_addr = val;
202 map_page(s->as, &s->dev[port].lst,
203 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
204 s->dev[port].cur_cmd = NULL;
205 break;
206 case PORT_LST_ADDR_HI:
207 pr->lst_addr_hi = val;
208 map_page(s->as, &s->dev[port].lst,
209 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
210 s->dev[port].cur_cmd = NULL;
211 break;
212 case PORT_FIS_ADDR:
213 pr->fis_addr = val;
214 map_page(s->as, &s->dev[port].res_fis,
215 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
216 break;
217 case PORT_FIS_ADDR_HI:
218 pr->fis_addr_hi = val;
219 map_page(s->as, &s->dev[port].res_fis,
220 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
221 break;
222 case PORT_IRQ_STAT:
223 pr->irq_stat &= ~val;
224 ahci_check_irq(s);
225 break;
226 case PORT_IRQ_MASK:
227 pr->irq_mask = val & 0xfdc000ff;
228 ahci_check_irq(s);
229 break;
230 case PORT_CMD:
231 pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);
232
233 if (pr->cmd & PORT_CMD_START) {
234 pr->cmd |= PORT_CMD_LIST_ON;
235 }
236
237 if (pr->cmd & PORT_CMD_FIS_RX) {
238 pr->cmd |= PORT_CMD_FIS_ON;
239 }
240
241 /* XXX usually the FIS would be pending on the bus here and
242 issuing deferred until the OS enables FIS receival.
243 Instead, we only submit it once - which works in most
244 cases, but is a hack. */
245 if ((pr->cmd & PORT_CMD_FIS_ON) &&
246 !s->dev[port].init_d2h_sent) {
247 ahci_init_d2h(&s->dev[port]);
248 s->dev[port].init_d2h_sent = true;
249 }
250
251 check_cmd(s, port);
252 break;
253 case PORT_TFDATA:
254 /* Read Only. */
255 break;
256 case PORT_SIG:
257 /* Read Only */
258 break;
259 case PORT_SCR_STAT:
260 /* Read Only */
261 break;
262 case PORT_SCR_CTL:
263 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
264 ((val & AHCI_SCR_SCTL_DET) == 0)) {
265 ahci_reset_port(s, port);
266 }
267 pr->scr_ctl = val;
268 break;
269 case PORT_SCR_ERR:
270 pr->scr_err &= ~val;
271 break;
272 case PORT_SCR_ACT:
273 /* RW1 */
274 pr->scr_act |= val;
275 break;
276 case PORT_CMD_ISSUE:
277 pr->cmd_issue |= val;
278 check_cmd(s, port);
279 break;
280 default:
281 break;
282 }
283 }
284
285 static uint64_t ahci_mem_read(void *opaque, hwaddr addr,
286 unsigned size)
287 {
288 AHCIState *s = opaque;
289 uint32_t val = 0;
290
291 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
292 switch (addr) {
293 case HOST_CAP:
294 val = s->control_regs.cap;
295 break;
296 case HOST_CTL:
297 val = s->control_regs.ghc;
298 break;
299 case HOST_IRQ_STAT:
300 val = s->control_regs.irqstatus;
301 break;
302 case HOST_PORTS_IMPL:
303 val = s->control_regs.impl;
304 break;
305 case HOST_VERSION:
306 val = s->control_regs.version;
307 break;
308 }
309
310 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val);
311 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
312 (addr < (AHCI_PORT_REGS_START_ADDR +
313 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
314 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
315 addr & AHCI_PORT_ADDR_OFFSET_MASK);
316 }
317
318 return val;
319 }
320
321
322
323 static void ahci_mem_write(void *opaque, hwaddr addr,
324 uint64_t val, unsigned size)
325 {
326 AHCIState *s = opaque;
327
328 /* Only aligned reads are allowed on AHCI */
329 if (addr & 3) {
330 fprintf(stderr, "ahci: Mis-aligned write to addr 0x"
331 TARGET_FMT_plx "\n", addr);
332 return;
333 }
334
335 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
336 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val);
337
338 switch (addr) {
339 case HOST_CAP: /* R/WO, RO */
340 /* FIXME handle R/WO */
341 break;
342 case HOST_CTL: /* R/W */
343 if (val & HOST_CTL_RESET) {
344 DPRINTF(-1, "HBA Reset\n");
345 ahci_reset(s);
346 } else {
347 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
348 ahci_check_irq(s);
349 }
350 break;
351 case HOST_IRQ_STAT: /* R/WC, RO */
352 s->control_regs.irqstatus &= ~val;
353 ahci_check_irq(s);
354 break;
355 case HOST_PORTS_IMPL: /* R/WO, RO */
356 /* FIXME handle R/WO */
357 break;
358 case HOST_VERSION: /* RO */
359 /* FIXME report write? */
360 break;
361 default:
362 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr);
363 }
364 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
365 (addr < (AHCI_PORT_REGS_START_ADDR +
366 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
367 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
368 addr & AHCI_PORT_ADDR_OFFSET_MASK, val);
369 }
370
371 }
372
373 static const MemoryRegionOps ahci_mem_ops = {
374 .read = ahci_mem_read,
375 .write = ahci_mem_write,
376 .endianness = DEVICE_LITTLE_ENDIAN,
377 };
378
379 static uint64_t ahci_idp_read(void *opaque, hwaddr addr,
380 unsigned size)
381 {
382 AHCIState *s = opaque;
383
384 if (addr == s->idp_offset) {
385 /* index register */
386 return s->idp_index;
387 } else if (addr == s->idp_offset + 4) {
388 /* data register - do memory read at location selected by index */
389 return ahci_mem_read(opaque, s->idp_index, size);
390 } else {
391 return 0;
392 }
393 }
394
395 static void ahci_idp_write(void *opaque, hwaddr addr,
396 uint64_t val, unsigned size)
397 {
398 AHCIState *s = opaque;
399
400 if (addr == s->idp_offset) {
401 /* index register - mask off reserved bits */
402 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3);
403 } else if (addr == s->idp_offset + 4) {
404 /* data register - do memory write at location selected by index */
405 ahci_mem_write(opaque, s->idp_index, val, size);
406 }
407 }
408
409 static const MemoryRegionOps ahci_idp_ops = {
410 .read = ahci_idp_read,
411 .write = ahci_idp_write,
412 .endianness = DEVICE_LITTLE_ENDIAN,
413 };
414
415
416 static void ahci_reg_init(AHCIState *s)
417 {
418 int i;
419
420 s->control_regs.cap = (s->ports - 1) |
421 (AHCI_NUM_COMMAND_SLOTS << 8) |
422 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) |
423 HOST_CAP_NCQ | HOST_CAP_AHCI;
424
425 s->control_regs.impl = (1 << s->ports) - 1;
426
427 s->control_regs.version = AHCI_VERSION_1_0;
428
429 for (i = 0; i < s->ports; i++) {
430 s->dev[i].port_state = STATE_RUN;
431 }
432 }
433
434 static void check_cmd(AHCIState *s, int port)
435 {
436 AHCIPortRegs *pr = &s->dev[port].port_regs;
437 int slot;
438
439 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {
440 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {
441 if ((pr->cmd_issue & (1U << slot)) &&
442 !handle_cmd(s, port, slot)) {
443 pr->cmd_issue &= ~(1U << slot);
444 }
445 }
446 }
447 }
448
449 static void ahci_check_cmd_bh(void *opaque)
450 {
451 AHCIDevice *ad = opaque;
452
453 qemu_bh_delete(ad->check_bh);
454 ad->check_bh = NULL;
455
456 if ((ad->busy_slot != -1) &&
457 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) {
458 /* no longer busy */
459 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot);
460 ad->busy_slot = -1;
461 }
462
463 check_cmd(ad->hba, ad->port_no);
464 }
465
466 static void ahci_init_d2h(AHCIDevice *ad)
467 {
468 uint8_t init_fis[20];
469 IDEState *ide_state = &ad->port.ifs[0];
470
471 memset(init_fis, 0, sizeof(init_fis));
472
473 init_fis[4] = 1;
474 init_fis[12] = 1;
475
476 if (ide_state->drive_kind == IDE_CD) {
477 init_fis[5] = ide_state->lcyl;
478 init_fis[6] = ide_state->hcyl;
479 }
480
481 ahci_write_fis_d2h(ad, init_fis);
482 }
483
484 static void ahci_reset_port(AHCIState *s, int port)
485 {
486 AHCIDevice *d = &s->dev[port];
487 AHCIPortRegs *pr = &d->port_regs;
488 IDEState *ide_state = &d->port.ifs[0];
489 int i;
490
491 DPRINTF(port, "reset port\n");
492
493 ide_bus_reset(&d->port);
494 ide_state->ncq_queues = AHCI_MAX_CMDS;
495
496 pr->scr_stat = 0;
497 pr->scr_err = 0;
498 pr->scr_act = 0;
499 pr->tfdata = 0x7F;
500 pr->sig = 0xFFFFFFFF;
501 d->busy_slot = -1;
502 d->init_d2h_sent = false;
503
504 ide_state = &s->dev[port].port.ifs[0];
505 if (!ide_state->blk) {
506 return;
507 }
508
509 /* reset ncq queue */
510 for (i = 0; i < AHCI_MAX_CMDS; i++) {
511 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i];
512 if (!ncq_tfs->used) {
513 continue;
514 }
515
516 if (ncq_tfs->aiocb) {
517 blk_aio_cancel(ncq_tfs->aiocb);
518 ncq_tfs->aiocb = NULL;
519 }
520
521 /* Maybe we just finished the request thanks to blk_aio_cancel() */
522 if (!ncq_tfs->used) {
523 continue;
524 }
525
526 qemu_sglist_destroy(&ncq_tfs->sglist);
527 ncq_tfs->used = 0;
528 }
529
530 s->dev[port].port_state = STATE_RUN;
531 if (!ide_state->blk) {
532 pr->sig = 0;
533 ide_state->status = SEEK_STAT | WRERR_STAT;
534 } else if (ide_state->drive_kind == IDE_CD) {
535 pr->sig = SATA_SIGNATURE_CDROM;
536 ide_state->lcyl = 0x14;
537 ide_state->hcyl = 0xeb;
538 DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl);
539 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT;
540 } else {
541 pr->sig = SATA_SIGNATURE_DISK;
542 ide_state->status = SEEK_STAT | WRERR_STAT;
543 }
544
545 ide_state->error = 1;
546 ahci_init_d2h(d);
547 }
548
549 static void debug_print_fis(uint8_t *fis, int cmd_len)
550 {
551 #ifdef DEBUG_AHCI
552 int i;
553
554 fprintf(stderr, "fis:");
555 for (i = 0; i < cmd_len; i++) {
556 if ((i & 0xf) == 0) {
557 fprintf(stderr, "\n%02x:",i);
558 }
559 fprintf(stderr, "%02x ",fis[i]);
560 }
561 fprintf(stderr, "\n");
562 #endif
563 }
564
565 static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)
566 {
567 AHCIDevice *ad = &s->dev[port];
568 AHCIPortRegs *pr = &ad->port_regs;
569 IDEState *ide_state;
570 uint8_t *sdb_fis;
571
572 if (!s->dev[port].res_fis ||
573 !(pr->cmd & PORT_CMD_FIS_RX)) {
574 return;
575 }
576
577 sdb_fis = &ad->res_fis[RES_FIS_SDBFIS];
578 ide_state = &ad->port.ifs[0];
579
580 /* clear memory */
581 *(uint32_t*)sdb_fis = 0;
582
583 /* write values */
584 sdb_fis[0] = ide_state->error;
585 sdb_fis[2] = ide_state->status & 0x77;
586 s->dev[port].finished |= finished;
587 *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(ad->finished);
588
589 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */
590 pr->tfdata = (ad->port.ifs[0].error << 8) |
591 (ad->port.ifs[0].status & 0x77) |
592 (pr->tfdata & 0x88);
593
594 ahci_trigger_irq(s, ad, PORT_IRQ_SDB_FIS);
595 }
596
597 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len)
598 {
599 AHCIPortRegs *pr = &ad->port_regs;
600 uint8_t *pio_fis, *cmd_fis;
601 uint64_t tbl_addr;
602 dma_addr_t cmd_len = 0x80;
603 IDEState *s = &ad->port.ifs[0];
604
605 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
606 return;
607 }
608
609 /* map cmd_fis */
610 tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr);
611 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len,
612 DMA_DIRECTION_TO_DEVICE);
613
614 if (cmd_fis == NULL) {
615 DPRINTF(ad->port_no, "dma_memory_map failed in ahci_write_fis_pio");
616 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_HBUS_ERR);
617 return;
618 }
619
620 if (cmd_len != 0x80) {
621 DPRINTF(ad->port_no,
622 "dma_memory_map mapped too few bytes in ahci_write_fis_pio");
623 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len,
624 DMA_DIRECTION_TO_DEVICE, cmd_len);
625 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_HBUS_ERR);
626 return;
627 }
628
629 pio_fis = &ad->res_fis[RES_FIS_PSFIS];
630
631 pio_fis[0] = 0x5f;
632 pio_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
633 pio_fis[2] = s->status;
634 pio_fis[3] = s->error;
635
636 pio_fis[4] = s->sector;
637 pio_fis[5] = s->lcyl;
638 pio_fis[6] = s->hcyl;
639 pio_fis[7] = s->select;
640 pio_fis[8] = s->hob_sector;
641 pio_fis[9] = s->hob_lcyl;
642 pio_fis[10] = s->hob_hcyl;
643 pio_fis[11] = 0;
644 pio_fis[12] = cmd_fis[12];
645 pio_fis[13] = cmd_fis[13];
646 pio_fis[14] = 0;
647 pio_fis[15] = s->status;
648 pio_fis[16] = len & 255;
649 pio_fis[17] = len >> 8;
650 pio_fis[18] = 0;
651 pio_fis[19] = 0;
652
653 /* Update shadow registers: */
654 pr->tfdata = (ad->port.ifs[0].error << 8) |
655 ad->port.ifs[0].status;
656
657 if (pio_fis[2] & ERR_STAT) {
658 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);
659 }
660
661 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS);
662
663 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len,
664 DMA_DIRECTION_TO_DEVICE, cmd_len);
665 }
666
667 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis)
668 {
669 AHCIPortRegs *pr = &ad->port_regs;
670 uint8_t *d2h_fis;
671 int i;
672 dma_addr_t cmd_len = 0x80;
673 int cmd_mapped = 0;
674 IDEState *s = &ad->port.ifs[0];
675
676 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
677 return;
678 }
679
680 if (!cmd_fis) {
681 /* map cmd_fis */
682 uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr);
683 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len,
684 DMA_DIRECTION_TO_DEVICE);
685 cmd_mapped = 1;
686 }
687
688 d2h_fis = &ad->res_fis[RES_FIS_RFIS];
689
690 d2h_fis[0] = 0x34;
691 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
692 d2h_fis[2] = s->status;
693 d2h_fis[3] = s->error;
694
695 d2h_fis[4] = s->sector;
696 d2h_fis[5] = s->lcyl;
697 d2h_fis[6] = s->hcyl;
698 d2h_fis[7] = s->select;
699 d2h_fis[8] = s->hob_sector;
700 d2h_fis[9] = s->hob_lcyl;
701 d2h_fis[10] = s->hob_hcyl;
702 d2h_fis[11] = 0;
703 d2h_fis[12] = cmd_fis[12];
704 d2h_fis[13] = cmd_fis[13];
705 for (i = 14; i < 20; i++) {
706 d2h_fis[i] = 0;
707 }
708
709 /* Update shadow registers: */
710 pr->tfdata = (ad->port.ifs[0].error << 8) |
711 ad->port.ifs[0].status;
712
713 if (d2h_fis[2] & ERR_STAT) {
714 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);
715 }
716
717 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);
718
719 if (cmd_mapped) {
720 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len,
721 DMA_DIRECTION_TO_DEVICE, cmd_len);
722 }
723 }
724
725 static int prdt_tbl_entry_size(const AHCI_SG *tbl)
726 {
727 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1;
728 }
729
730 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset)
731 {
732 AHCICmdHdr *cmd = ad->cur_cmd;
733 uint32_t opts = le32_to_cpu(cmd->opts);
734 uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80;
735 int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN;
736 dma_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG));
737 dma_addr_t real_prdt_len = prdt_len;
738 uint8_t *prdt;
739 int i;
740 int r = 0;
741 int sum = 0;
742 int off_idx = -1;
743 int off_pos = -1;
744 int tbl_entry_size;
745 IDEBus *bus = &ad->port;
746 BusState *qbus = BUS(bus);
747
748 if (!sglist_alloc_hint) {
749 DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts);
750 return -1;
751 }
752
753 /* map PRDT */
754 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len,
755 DMA_DIRECTION_TO_DEVICE))){
756 DPRINTF(ad->port_no, "map failed\n");
757 return -1;
758 }
759
760 if (prdt_len < real_prdt_len) {
761 DPRINTF(ad->port_no, "mapped less than expected\n");
762 r = -1;
763 goto out;
764 }
765
766 /* Get entries in the PRDT, init a qemu sglist accordingly */
767 if (sglist_alloc_hint > 0) {
768 AHCI_SG *tbl = (AHCI_SG *)prdt;
769 sum = 0;
770 for (i = 0; i < sglist_alloc_hint; i++) {
771 /* flags_size is zero-based */
772 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]);
773 if (offset <= (sum + tbl_entry_size)) {
774 off_idx = i;
775 off_pos = offset - sum;
776 break;
777 }
778 sum += tbl_entry_size;
779 }
780 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) {
781 DPRINTF(ad->port_no, "%s: Incorrect offset! "
782 "off_idx: %d, off_pos: %d\n",
783 __func__, off_idx, off_pos);
784 r = -1;
785 goto out;
786 }
787
788 qemu_sglist_init(sglist, qbus->parent, (sglist_alloc_hint - off_idx),
789 ad->hba->as);
790 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos),
791 prdt_tbl_entry_size(&tbl[off_idx]) - off_pos);
792
793 for (i = off_idx + 1; i < sglist_alloc_hint; i++) {
794 /* flags_size is zero-based */
795 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
796 prdt_tbl_entry_size(&tbl[i]));
797 }
798 }
799
800 out:
801 dma_memory_unmap(ad->hba->as, prdt, prdt_len,
802 DMA_DIRECTION_TO_DEVICE, prdt_len);
803 return r;
804 }
805
806 static void ncq_cb(void *opaque, int ret)
807 {
808 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;
809 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];
810
811 if (ret == -ECANCELED) {
812 return;
813 }
814 /* Clear bit for this tag in SActive */
815 ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag);
816
817 if (ret < 0) {
818 /* error */
819 ide_state->error = ABRT_ERR;
820 ide_state->status = READY_STAT | ERR_STAT;
821 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag);
822 } else {
823 ide_state->status = READY_STAT | SEEK_STAT;
824 }
825
826 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,
827 (1 << ncq_tfs->tag));
828
829 DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n",
830 ncq_tfs->tag);
831
832 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk),
833 &ncq_tfs->acct);
834 qemu_sglist_destroy(&ncq_tfs->sglist);
835 ncq_tfs->used = 0;
836 }
837
838 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,
839 int slot)
840 {
841 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis;
842 uint8_t tag = ncq_fis->tag >> 3;
843 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag];
844
845 if (ncq_tfs->used) {
846 /* error - already in use */
847 fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag);
848 return;
849 }
850
851 ncq_tfs->used = 1;
852 ncq_tfs->drive = &s->dev[port];
853 ncq_tfs->slot = slot;
854 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) |
855 ((uint64_t)ncq_fis->lba4 << 32) |
856 ((uint64_t)ncq_fis->lba3 << 24) |
857 ((uint64_t)ncq_fis->lba2 << 16) |
858 ((uint64_t)ncq_fis->lba1 << 8) |
859 (uint64_t)ncq_fis->lba0;
860
861 /* Note: We calculate the sector count, but don't currently rely on it.
862 * The total size of the DMA buffer tells us the transfer size instead. */
863 ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) |
864 ncq_fis->sector_count_low;
865
866 DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", "
867 "drive max %"PRId64"\n",
868 ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2,
869 s->dev[port].port.ifs[0].nb_sectors - 1);
870
871 ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist, 0);
872 ncq_tfs->tag = tag;
873
874 switch(ncq_fis->command) {
875 case READ_FPDMA_QUEUED:
876 DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", "
877 "tag %d\n",
878 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);
879
880 DPRINTF(port, "tag %d aio read %"PRId64"\n",
881 ncq_tfs->tag, ncq_tfs->lba);
882
883 dma_acct_start(ncq_tfs->drive->port.ifs[0].blk, &ncq_tfs->acct,
884 &ncq_tfs->sglist, BLOCK_ACCT_READ);
885 ncq_tfs->aiocb = dma_blk_read(ncq_tfs->drive->port.ifs[0].blk,
886 &ncq_tfs->sglist, ncq_tfs->lba,
887 ncq_cb, ncq_tfs);
888 break;
889 case WRITE_FPDMA_QUEUED:
890 DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n",
891 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);
892
893 DPRINTF(port, "tag %d aio write %"PRId64"\n",
894 ncq_tfs->tag, ncq_tfs->lba);
895
896 dma_acct_start(ncq_tfs->drive->port.ifs[0].blk, &ncq_tfs->acct,
897 &ncq_tfs->sglist, BLOCK_ACCT_WRITE);
898 ncq_tfs->aiocb = dma_blk_write(ncq_tfs->drive->port.ifs[0].blk,
899 &ncq_tfs->sglist, ncq_tfs->lba,
900 ncq_cb, ncq_tfs);
901 break;
902 default:
903 DPRINTF(port, "error: tried to process non-NCQ command as NCQ\n");
904 qemu_sglist_destroy(&ncq_tfs->sglist);
905 break;
906 }
907 }
908
909 static int handle_cmd(AHCIState *s, int port, int slot)
910 {
911 IDEState *ide_state;
912 uint32_t opts;
913 uint64_t tbl_addr;
914 AHCICmdHdr *cmd;
915 uint8_t *cmd_fis;
916 dma_addr_t cmd_len;
917
918 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
919 /* Engine currently busy, try again later */
920 DPRINTF(port, "engine busy\n");
921 return -1;
922 }
923
924 cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot];
925
926 if (!s->dev[port].lst) {
927 DPRINTF(port, "error: lst not given but cmd handled");
928 return -1;
929 }
930
931 /* remember current slot handle for later */
932 s->dev[port].cur_cmd = cmd;
933
934 opts = le32_to_cpu(cmd->opts);
935 tbl_addr = le64_to_cpu(cmd->tbl_addr);
936
937 cmd_len = 0x80;
938 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len,
939 DMA_DIRECTION_FROM_DEVICE);
940
941 if (!cmd_fis) {
942 DPRINTF(port, "error: guest passed us an invalid cmd fis\n");
943 return -1;
944 }
945
946 /* The device we are working for */
947 ide_state = &s->dev[port].port.ifs[0];
948
949 if (!ide_state->blk) {
950 DPRINTF(port, "error: guest accessed unused port");
951 goto out;
952 }
953
954 debug_print_fis(cmd_fis, 0x90);
955 //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4);
956
957 switch (cmd_fis[0]) {
958 case SATA_FIS_TYPE_REGISTER_H2D:
959 break;
960 default:
961 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
962 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1],
963 cmd_fis[2]);
964 goto out;
965 break;
966 }
967
968 switch (cmd_fis[1]) {
969 case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER:
970 break;
971 case 0:
972 break;
973 default:
974 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
975 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1],
976 cmd_fis[2]);
977 goto out;
978 break;
979 }
980
981 switch (s->dev[port].port_state) {
982 case STATE_RUN:
983 if (cmd_fis[15] & ATA_SRST) {
984 s->dev[port].port_state = STATE_RESET;
985 }
986 break;
987 case STATE_RESET:
988 if (!(cmd_fis[15] & ATA_SRST)) {
989 ahci_reset_port(s, port);
990 }
991 break;
992 }
993
994 if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) {
995
996 /* Check for NCQ command */
997 if ((cmd_fis[2] == READ_FPDMA_QUEUED) ||
998 (cmd_fis[2] == WRITE_FPDMA_QUEUED)) {
999 process_ncq_command(s, port, cmd_fis, slot);
1000 goto out;
1001 }
1002
1003 /* Decompose the FIS */
1004 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]);
1005 ide_state->feature = cmd_fis[3];
1006 if (!ide_state->nsector) {
1007 ide_state->nsector = 256;
1008 }
1009
1010 if (ide_state->drive_kind != IDE_CD) {
1011 /*
1012 * We set the sector depending on the sector defined in the FIS.
1013 * Unfortunately, the spec isn't exactly obvious on this one.
1014 *
1015 * Apparently LBA48 commands set fis bytes 10,9,8,6,5,4 to the
1016 * 48 bit sector number. ATA_CMD_READ_DMA_EXT is an example for
1017 * such a command.
1018 *
1019 * Non-LBA48 commands however use 7[lower 4 bits],6,5,4 to define a
1020 * 28-bit sector number. ATA_CMD_READ_DMA is an example for such
1021 * a command.
1022 *
1023 * Since the spec doesn't explicitly state what each field should
1024 * do, I simply assume non-used fields as reserved and OR everything
1025 * together, independent of the command.
1026 */
1027 ide_set_sector(ide_state, ((uint64_t)cmd_fis[10] << 40)
1028 | ((uint64_t)cmd_fis[9] << 32)
1029 /* This is used for LBA48 commands */
1030 | ((uint64_t)cmd_fis[8] << 24)
1031 /* This is used for non-LBA48 commands */
1032 | ((uint64_t)(cmd_fis[7] & 0xf) << 24)
1033 | ((uint64_t)cmd_fis[6] << 16)
1034 | ((uint64_t)cmd_fis[5] << 8)
1035 | cmd_fis[4]);
1036 }
1037
1038 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1039 * table to ide_state->io_buffer
1040 */
1041 if (opts & AHCI_CMD_ATAPI) {
1042 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10);
1043 ide_state->lcyl = 0x14;
1044 ide_state->hcyl = 0xeb;
1045 debug_print_fis(ide_state->io_buffer, 0x10);
1046 ide_state->feature = IDE_FEATURE_DMA;
1047 s->dev[port].done_atapi_packet = false;
1048 /* XXX send PIO setup FIS */
1049 }
1050
1051 ide_state->error = 0;
1052
1053 /* Reset transferred byte counter */
1054 cmd->status = 0;
1055
1056 /* We're ready to process the command in FIS byte 2. */
1057 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]);
1058 }
1059
1060 out:
1061 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE,
1062 cmd_len);
1063
1064 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
1065 /* async command, complete later */
1066 s->dev[port].busy_slot = slot;
1067 return -1;
1068 }
1069
1070 /* done handling the command */
1071 return 0;
1072 }
1073
1074 /* DMA dev <-> ram */
1075 static void ahci_start_transfer(IDEDMA *dma)
1076 {
1077 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1078 IDEState *s = &ad->port.ifs[0];
1079 uint32_t size = (uint32_t)(s->data_end - s->data_ptr);
1080 /* write == ram -> device */
1081 uint32_t opts = le32_to_cpu(ad->cur_cmd->opts);
1082 int is_write = opts & AHCI_CMD_WRITE;
1083 int is_atapi = opts & AHCI_CMD_ATAPI;
1084 int has_sglist = 0;
1085
1086 if (is_atapi && !ad->done_atapi_packet) {
1087 /* already prepopulated iobuffer */
1088 ad->done_atapi_packet = true;
1089 goto out;
1090 }
1091
1092 if (!ahci_populate_sglist(ad, &s->sg, 0)) {
1093 has_sglist = 1;
1094 }
1095
1096 DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n",
1097 is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata",
1098 has_sglist ? "" : "o");
1099
1100 if (has_sglist && size) {
1101 if (is_write) {
1102 dma_buf_write(s->data_ptr, size, &s->sg);
1103 } else {
1104 dma_buf_read(s->data_ptr, size, &s->sg);
1105 }
1106 }
1107
1108 /* update number of transferred bytes */
1109 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + size);
1110
1111 out:
1112 /* declare that we processed everything */
1113 s->data_ptr = s->data_end;
1114
1115 if (has_sglist) {
1116 qemu_sglist_destroy(&s->sg);
1117 }
1118
1119 s->end_transfer_func(s);
1120
1121 if (!(s->status & DRQ_STAT)) {
1122 /* done with PIO send/receive */
1123 ahci_write_fis_pio(ad, le32_to_cpu(ad->cur_cmd->status));
1124 }
1125 }
1126
1127 static void ahci_start_dma(IDEDMA *dma, IDEState *s,
1128 BlockCompletionFunc *dma_cb)
1129 {
1130 #ifdef DEBUG_AHCI
1131 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1132 #endif
1133 DPRINTF(ad->port_no, "\n");
1134 s->io_buffer_offset = 0;
1135 dma_cb(s, 0);
1136 }
1137
1138 static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write)
1139 {
1140 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1141 IDEState *s = &ad->port.ifs[0];
1142
1143 ahci_populate_sglist(ad, &s->sg, 0);
1144 s->io_buffer_size = s->sg.size;
1145
1146 DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size);
1147 return s->io_buffer_size != 0;
1148 }
1149
1150 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write)
1151 {
1152 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1153 IDEState *s = &ad->port.ifs[0];
1154 uint8_t *p = s->io_buffer + s->io_buffer_index;
1155 int l = s->io_buffer_size - s->io_buffer_index;
1156
1157 if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset)) {
1158 return 0;
1159 }
1160
1161 if (is_write) {
1162 dma_buf_read(p, l, &s->sg);
1163 } else {
1164 dma_buf_write(p, l, &s->sg);
1165 }
1166
1167 /* free sglist that was created in ahci_populate_sglist() */
1168 qemu_sglist_destroy(&s->sg);
1169
1170 /* update number of transferred bytes */
1171 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + l);
1172 s->io_buffer_index += l;
1173 s->io_buffer_offset += l;
1174
1175 DPRINTF(ad->port_no, "len=%#x\n", l);
1176
1177 return 1;
1178 }
1179
1180 static int ahci_dma_set_unit(IDEDMA *dma, int unit)
1181 {
1182 /* only a single unit per link */
1183 return 0;
1184 }
1185
1186 static void ahci_cmd_done(IDEDMA *dma)
1187 {
1188 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1189
1190 DPRINTF(ad->port_no, "cmd done\n");
1191
1192 /* update d2h status */
1193 ahci_write_fis_d2h(ad, NULL);
1194
1195 if (!ad->check_bh) {
1196 /* maybe we still have something to process, check later */
1197 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad);
1198 qemu_bh_schedule(ad->check_bh);
1199 }
1200 }
1201
1202 static void ahci_irq_set(void *opaque, int n, int level)
1203 {
1204 }
1205
1206 static void ahci_dma_restart_cb(void *opaque, int running, RunState state)
1207 {
1208 }
1209
1210 static const IDEDMAOps ahci_dma_ops = {
1211 .start_dma = ahci_start_dma,
1212 .start_transfer = ahci_start_transfer,
1213 .prepare_buf = ahci_dma_prepare_buf,
1214 .rw_buf = ahci_dma_rw_buf,
1215 .set_unit = ahci_dma_set_unit,
1216 .cmd_done = ahci_cmd_done,
1217 .restart_cb = ahci_dma_restart_cb,
1218 };
1219
1220 void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
1221 {
1222 qemu_irq *irqs;
1223 int i;
1224
1225 s->as = as;
1226 s->ports = ports;
1227 s->dev = g_new0(AHCIDevice, ports);
1228 ahci_reg_init(s);
1229 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1230 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
1231 "ahci", AHCI_MEM_BAR_SIZE);
1232 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
1233 "ahci-idp", 32);
1234
1235 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
1236
1237 for (i = 0; i < s->ports; i++) {
1238 AHCIDevice *ad = &s->dev[i];
1239
1240 ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1);
1241 ide_init2(&ad->port, irqs[i]);
1242
1243 ad->hba = s;
1244 ad->port_no = i;
1245 ad->port.dma = &ad->dma;
1246 ad->port.dma->ops = &ahci_dma_ops;
1247 }
1248 }
1249
1250 void ahci_uninit(AHCIState *s)
1251 {
1252 g_free(s->dev);
1253 }
1254
1255 void ahci_reset(AHCIState *s)
1256 {
1257 AHCIPortRegs *pr;
1258 int i;
1259
1260 s->control_regs.irqstatus = 0;
1261 /* AHCI Enable (AE)
1262 * The implementation of this bit is dependent upon the value of the
1263 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and
1264 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be
1265 * read-only and shall have a reset value of '1'.
1266 *
1267 * We set HOST_CAP_AHCI so we must enable AHCI at reset.
1268 */
1269 s->control_regs.ghc = HOST_CTL_AHCI_EN;
1270
1271 for (i = 0; i < s->ports; i++) {
1272 pr = &s->dev[i].port_regs;
1273 pr->irq_stat = 0;
1274 pr->irq_mask = 0;
1275 pr->scr_ctl = 0;
1276 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;
1277 ahci_reset_port(s, i);
1278 }
1279 }
1280
1281 static const VMStateDescription vmstate_ahci_device = {
1282 .name = "ahci port",
1283 .version_id = 1,
1284 .fields = (VMStateField[]) {
1285 VMSTATE_IDE_BUS(port, AHCIDevice),
1286 VMSTATE_UINT32(port_state, AHCIDevice),
1287 VMSTATE_UINT32(finished, AHCIDevice),
1288 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice),
1289 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice),
1290 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice),
1291 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice),
1292 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice),
1293 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice),
1294 VMSTATE_UINT32(port_regs.cmd, AHCIDevice),
1295 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice),
1296 VMSTATE_UINT32(port_regs.sig, AHCIDevice),
1297 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice),
1298 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice),
1299 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice),
1300 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice),
1301 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice),
1302 VMSTATE_BOOL(done_atapi_packet, AHCIDevice),
1303 VMSTATE_INT32(busy_slot, AHCIDevice),
1304 VMSTATE_BOOL(init_d2h_sent, AHCIDevice),
1305 VMSTATE_END_OF_LIST()
1306 },
1307 };
1308
1309 static int ahci_state_post_load(void *opaque, int version_id)
1310 {
1311 int i;
1312 struct AHCIDevice *ad;
1313 AHCIState *s = opaque;
1314
1315 for (i = 0; i < s->ports; i++) {
1316 ad = &s->dev[i];
1317 AHCIPortRegs *pr = &ad->port_regs;
1318
1319 map_page(s->as, &ad->lst,
1320 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
1321 map_page(s->as, &ad->res_fis,
1322 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
1323 /*
1324 * All pending i/o should be flushed out on a migrate. However,
1325 * we might not have cleared the busy_slot since this is done
1326 * in a bh. Also, issue i/o against any slots that are pending.
1327 */
1328 if ((ad->busy_slot != -1) &&
1329 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) {
1330 pr->cmd_issue &= ~(1 << ad->busy_slot);
1331 ad->busy_slot = -1;
1332 }
1333 check_cmd(s, i);
1334 }
1335
1336 return 0;
1337 }
1338
1339 const VMStateDescription vmstate_ahci = {
1340 .name = "ahci",
1341 .version_id = 1,
1342 .post_load = ahci_state_post_load,
1343 .fields = (VMStateField[]) {
1344 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports,
1345 vmstate_ahci_device, AHCIDevice),
1346 VMSTATE_UINT32(control_regs.cap, AHCIState),
1347 VMSTATE_UINT32(control_regs.ghc, AHCIState),
1348 VMSTATE_UINT32(control_regs.irqstatus, AHCIState),
1349 VMSTATE_UINT32(control_regs.impl, AHCIState),
1350 VMSTATE_UINT32(control_regs.version, AHCIState),
1351 VMSTATE_UINT32(idp_index, AHCIState),
1352 VMSTATE_INT32_EQUAL(ports, AHCIState),
1353 VMSTATE_END_OF_LIST()
1354 },
1355 };
1356
1357 #define TYPE_SYSBUS_AHCI "sysbus-ahci"
1358 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
1359
1360 typedef struct SysbusAHCIState {
1361 /*< private >*/
1362 SysBusDevice parent_obj;
1363 /*< public >*/
1364
1365 AHCIState ahci;
1366 uint32_t num_ports;
1367 } SysbusAHCIState;
1368
1369 static const VMStateDescription vmstate_sysbus_ahci = {
1370 .name = "sysbus-ahci",
1371 .unmigratable = 1, /* Still buggy under I/O load */
1372 .fields = (VMStateField[]) {
1373 VMSTATE_AHCI(ahci, SysbusAHCIState),
1374 VMSTATE_END_OF_LIST()
1375 },
1376 };
1377
1378 static void sysbus_ahci_reset(DeviceState *dev)
1379 {
1380 SysbusAHCIState *s = SYSBUS_AHCI(dev);
1381
1382 ahci_reset(&s->ahci);
1383 }
1384
1385 static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
1386 {
1387 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1388 SysbusAHCIState *s = SYSBUS_AHCI(dev);
1389
1390 ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports);
1391
1392 sysbus_init_mmio(sbd, &s->ahci.mem);
1393 sysbus_init_irq(sbd, &s->ahci.irq);
1394 }
1395
1396 static Property sysbus_ahci_properties[] = {
1397 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
1398 DEFINE_PROP_END_OF_LIST(),
1399 };
1400
1401 static void sysbus_ahci_class_init(ObjectClass *klass, void *data)
1402 {
1403 DeviceClass *dc = DEVICE_CLASS(klass);
1404
1405 dc->realize = sysbus_ahci_realize;
1406 dc->vmsd = &vmstate_sysbus_ahci;
1407 dc->props = sysbus_ahci_properties;
1408 dc->reset = sysbus_ahci_reset;
1409 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1410 }
1411
1412 static const TypeInfo sysbus_ahci_info = {
1413 .name = TYPE_SYSBUS_AHCI,
1414 .parent = TYPE_SYS_BUS_DEVICE,
1415 .instance_size = sizeof(SysbusAHCIState),
1416 .class_init = sysbus_ahci_class_init,
1417 };
1418
1419 static void sysbus_ahci_register_types(void)
1420 {
1421 type_register_static(&sysbus_ahci_info);
1422 }
1423
1424 type_init(sysbus_ahci_register_types)
1425
1426 void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
1427 {
1428 AHCIPCIState *d = ICH_AHCI(dev);
1429 AHCIState *ahci = &d->ahci;
1430 int i;
1431
1432 for (i = 0; i < ahci->ports; i++) {
1433 if (hd[i] == NULL) {
1434 continue;
1435 }
1436 ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
1437 }
1438
1439 }
CRIS target port of Qemu