?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
qcow2: rename two QCowAIOCB members
[qemu/cris-port.git] / hw / omap2.c
bloba3fa89d3ee278295a89d4e0a9e689a5c3362e7ae
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #include "hw.h"
21 #include "arm-misc.h"
22 #include "omap.h"
23 #include "sysemu.h"
24 #include "qemu-timer.h"
25 #include "qemu-char.h"
26 #include "flash.h"
27 #include "soc_dma.h"
28 #include "audio/audio.h"
29
30 /* GP timers */
31 struct omap_gp_timer_s {
32 qemu_irq irq;
33 qemu_irq wkup;
34 qemu_irq in;
35 qemu_irq out;
36 omap_clk clk;
37 QEMUTimer *timer;
38 QEMUTimer *match;
39 struct omap_target_agent_s *ta;
40
41 int in_val;
42 int out_val;
43 int64_t time;
44 int64_t rate;
45 int64_t ticks_per_sec;
46
47 int16_t config;
48 int status;
49 int it_ena;
50 int wu_ena;
51 int enable;
52 int inout;
53 int capt2;
54 int pt;
55 enum {
56 gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both
57 } trigger;
58 enum {
59 gpt_capture_none, gpt_capture_rising,
60 gpt_capture_falling, gpt_capture_both
61 } capture;
62 int scpwm;
63 int ce;
64 int pre;
65 int ptv;
66 int ar;
67 int st;
68 int posted;
69 uint32_t val;
70 uint32_t load_val;
71 uint32_t capture_val[2];
72 uint32_t match_val;
73 int capt_num;
74
75 uint16_t writeh; /* LSB */
76 uint16_t readh; /* MSB */
77 };
78
79 #define GPT_TCAR_IT (1 << 2)
80 #define GPT_OVF_IT (1 << 1)
81 #define GPT_MAT_IT (1 << 0)
82
83 static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it)
84 {
85 if (timer->it_ena & it) {
86 if (!timer->status)
87 qemu_irq_raise(timer->irq);
88
89 timer->status |= it;
90 /* Or are the status bits set even when masked?
91 * i.e. is masking applied before or after the status register? */
92 }
93
94 if (timer->wu_ena & it)
95 qemu_irq_pulse(timer->wkup);
96 }
97
98 static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level)
99 {
100 if (!timer->inout && timer->out_val != level) {
101 timer->out_val = level;
102 qemu_set_irq(timer->out, level);
103 }
104 }
105
106 static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer)
107 {
108 uint64_t distance;
109
110 if (timer->st && timer->rate) {
111 distance = qemu_get_clock(vm_clock) - timer->time;
112 distance = muldiv64(distance, timer->rate, timer->ticks_per_sec);
113
114 if (distance >= 0xffffffff - timer->val)
115 return 0xffffffff;
116 else
117 return timer->val + distance;
118 } else
119 return timer->val;
120 }
121
122 static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer)
123 {
124 if (timer->st) {
125 timer->val = omap_gp_timer_read(timer);
126 timer->time = qemu_get_clock(vm_clock);
127 }
128 }
129
130 static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer)
131 {
132 int64_t expires, matches;
133
134 if (timer->st && timer->rate) {
135 expires = muldiv64(0x100000000ll - timer->val,
136 timer->ticks_per_sec, timer->rate);
137 qemu_mod_timer(timer->timer, timer->time + expires);
138
139 if (timer->ce && timer->match_val >= timer->val) {
140 matches = muldiv64(timer->match_val - timer->val,
141 timer->ticks_per_sec, timer->rate);
142 qemu_mod_timer(timer->match, timer->time + matches);
143 } else
144 qemu_del_timer(timer->match);
145 } else {
146 qemu_del_timer(timer->timer);
147 qemu_del_timer(timer->match);
148 omap_gp_timer_out(timer, timer->scpwm);
149 }
150 }
151
152 static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
153 {
154 if (timer->pt)
155 /* TODO in overflow-and-match mode if the first event to
156 * occur is the match, don't toggle. */
157 omap_gp_timer_out(timer, !timer->out_val);
158 else
159 /* TODO inverted pulse on timer->out_val == 1? */
160 qemu_irq_pulse(timer->out);
161 }
162
163 static void omap_gp_timer_tick(void *opaque)
164 {
165 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
166
167 if (!timer->ar) {
168 timer->st = 0;
169 timer->val = 0;
170 } else {
171 timer->val = timer->load_val;
172 timer->time = qemu_get_clock(vm_clock);
173 }
174
175 if (timer->trigger == gpt_trigger_overflow ||
176 timer->trigger == gpt_trigger_both)
177 omap_gp_timer_trigger(timer);
178
179 omap_gp_timer_intr(timer, GPT_OVF_IT);
180 omap_gp_timer_update(timer);
181 }
182
183 static void omap_gp_timer_match(void *opaque)
184 {
185 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
186
187 if (timer->trigger == gpt_trigger_both)
188 omap_gp_timer_trigger(timer);
189
190 omap_gp_timer_intr(timer, GPT_MAT_IT);
191 }
192
193 static void omap_gp_timer_input(void *opaque, int line, int on)
194 {
195 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
196 int trigger;
197
198 switch (s->capture) {
199 default:
200 case gpt_capture_none:
201 trigger = 0;
202 break;
203 case gpt_capture_rising:
204 trigger = !s->in_val && on;
205 break;
206 case gpt_capture_falling:
207 trigger = s->in_val && !on;
208 break;
209 case gpt_capture_both:
210 trigger = (s->in_val == !on);
211 break;
212 }
213 s->in_val = on;
214
215 if (s->inout && trigger && s->capt_num < 2) {
216 s->capture_val[s->capt_num] = omap_gp_timer_read(s);
217
218 if (s->capt2 == s->capt_num ++)
219 omap_gp_timer_intr(s, GPT_TCAR_IT);
220 }
221 }
222
223 static void omap_gp_timer_clk_update(void *opaque, int line, int on)
224 {
225 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
226
227 omap_gp_timer_sync(timer);
228 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
229 omap_gp_timer_update(timer);
230 }
231
232 static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer)
233 {
234 omap_clk_adduser(timer->clk,
235 qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]);
236 timer->rate = omap_clk_getrate(timer->clk);
237 }
238
239 static void omap_gp_timer_reset(struct omap_gp_timer_s *s)
240 {
241 s->config = 0x000;
242 s->status = 0;
243 s->it_ena = 0;
244 s->wu_ena = 0;
245 s->inout = 0;
246 s->capt2 = 0;
247 s->capt_num = 0;
248 s->pt = 0;
249 s->trigger = gpt_trigger_none;
250 s->capture = gpt_capture_none;
251 s->scpwm = 0;
252 s->ce = 0;
253 s->pre = 0;
254 s->ptv = 0;
255 s->ar = 0;
256 s->st = 0;
257 s->posted = 1;
258 s->val = 0x00000000;
259 s->load_val = 0x00000000;
260 s->capture_val[0] = 0x00000000;
261 s->capture_val[1] = 0x00000000;
262 s->match_val = 0x00000000;
263 omap_gp_timer_update(s);
264 }
265
266 static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
267 {
268 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
269
270 switch (addr) {
271 case 0x00: /* TIDR */
272 return 0x21;
273
274 case 0x10: /* TIOCP_CFG */
275 return s->config;
276
277 case 0x14: /* TISTAT */
278 /* ??? When's this bit reset? */
279 return 1; /* RESETDONE */
280
281 case 0x18: /* TISR */
282 return s->status;
283
284 case 0x1c: /* TIER */
285 return s->it_ena;
286
287 case 0x20: /* TWER */
288 return s->wu_ena;
289
290 case 0x24: /* TCLR */
291 return (s->inout << 14) |
292 (s->capt2 << 13) |
293 (s->pt << 12) |
294 (s->trigger << 10) |
295 (s->capture << 8) |
296 (s->scpwm << 7) |
297 (s->ce << 6) |
298 (s->pre << 5) |
299 (s->ptv << 2) |
300 (s->ar << 1) |
301 (s->st << 0);
302
303 case 0x28: /* TCRR */
304 return omap_gp_timer_read(s);
305
306 case 0x2c: /* TLDR */
307 return s->load_val;
308
309 case 0x30: /* TTGR */
310 return 0xffffffff;
311
312 case 0x34: /* TWPS */
313 return 0x00000000; /* No posted writes pending. */
314
315 case 0x38: /* TMAR */
316 return s->match_val;
317
318 case 0x3c: /* TCAR1 */
319 return s->capture_val[0];
320
321 case 0x40: /* TSICR */
322 return s->posted << 2;
323
324 case 0x44: /* TCAR2 */
325 return s->capture_val[1];
326 }
327
328 OMAP_BAD_REG(addr);
329 return 0;
330 }
331
332 static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
333 {
334 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
335 uint32_t ret;
336
337 if (addr & 2)
338 return s->readh;
339 else {
340 ret = omap_gp_timer_readw(opaque, addr);
341 s->readh = ret >> 16;
342 return ret & 0xffff;
343 }
344 }
345
346 static CPUReadMemoryFunc * const omap_gp_timer_readfn[] = {
347 omap_badwidth_read32,
348 omap_gp_timer_readh,
349 omap_gp_timer_readw,
350 };
351
352 static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
353 uint32_t value)
354 {
355 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
356
357 switch (addr) {
358 case 0x00: /* TIDR */
359 case 0x14: /* TISTAT */
360 case 0x34: /* TWPS */
361 case 0x3c: /* TCAR1 */
362 case 0x44: /* TCAR2 */
363 OMAP_RO_REG(addr);
364 break;
365
366 case 0x10: /* TIOCP_CFG */
367 s->config = value & 0x33d;
368 if (((value >> 3) & 3) == 3) /* IDLEMODE */
369 fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n",
370 __FUNCTION__);
371 if (value & 2) /* SOFTRESET */
372 omap_gp_timer_reset(s);
373 break;
374
375 case 0x18: /* TISR */
376 if (value & GPT_TCAR_IT)
377 s->capt_num = 0;
378 if (s->status && !(s->status &= ~value))
379 qemu_irq_lower(s->irq);
380 break;
381
382 case 0x1c: /* TIER */
383 s->it_ena = value & 7;
384 break;
385
386 case 0x20: /* TWER */
387 s->wu_ena = value & 7;
388 break;
389
390 case 0x24: /* TCLR */
391 omap_gp_timer_sync(s);
392 s->inout = (value >> 14) & 1;
393 s->capt2 = (value >> 13) & 1;
394 s->pt = (value >> 12) & 1;
395 s->trigger = (value >> 10) & 3;
396 if (s->capture == gpt_capture_none &&
397 ((value >> 8) & 3) != gpt_capture_none)
398 s->capt_num = 0;
399 s->capture = (value >> 8) & 3;
400 s->scpwm = (value >> 7) & 1;
401 s->ce = (value >> 6) & 1;
402 s->pre = (value >> 5) & 1;
403 s->ptv = (value >> 2) & 7;
404 s->ar = (value >> 1) & 1;
405 s->st = (value >> 0) & 1;
406 if (s->inout && s->trigger != gpt_trigger_none)
407 fprintf(stderr, "%s: GP timer pin must be an output "
408 "for this trigger mode\n", __FUNCTION__);
409 if (!s->inout && s->capture != gpt_capture_none)
410 fprintf(stderr, "%s: GP timer pin must be an input "
411 "for this capture mode\n", __FUNCTION__);
412 if (s->trigger == gpt_trigger_none)
413 omap_gp_timer_out(s, s->scpwm);
414 /* TODO: make sure this doesn't overflow 32-bits */
415 s->ticks_per_sec = get_ticks_per_sec() << (s->pre ? s->ptv + 1 : 0);
416 omap_gp_timer_update(s);
417 break;
418
419 case 0x28: /* TCRR */
420 s->time = qemu_get_clock(vm_clock);
421 s->val = value;
422 omap_gp_timer_update(s);
423 break;
424
425 case 0x2c: /* TLDR */
426 s->load_val = value;
427 break;
428
429 case 0x30: /* TTGR */
430 s->time = qemu_get_clock(vm_clock);
431 s->val = s->load_val;
432 omap_gp_timer_update(s);
433 break;
434
435 case 0x38: /* TMAR */
436 omap_gp_timer_sync(s);
437 s->match_val = value;
438 omap_gp_timer_update(s);
439 break;
440
441 case 0x40: /* TSICR */
442 s->posted = (value >> 2) & 1;
443 if (value & 2) /* How much exactly are we supposed to reset? */
444 omap_gp_timer_reset(s);
445 break;
446
447 default:
448 OMAP_BAD_REG(addr);
449 }
450 }
451
452 static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
453 uint32_t value)
454 {
455 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
456
457 if (addr & 2)
458 return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
459 else
460 s->writeh = (uint16_t) value;
461 }
462
463 static CPUWriteMemoryFunc * const omap_gp_timer_writefn[] = {
464 omap_badwidth_write32,
465 omap_gp_timer_writeh,
466 omap_gp_timer_write,
467 };
468
469 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
470 qemu_irq irq, omap_clk fclk, omap_clk iclk)
471 {
472 int iomemtype;
473 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *)
474 qemu_mallocz(sizeof(struct omap_gp_timer_s));
475
476 s->ta = ta;
477 s->irq = irq;
478 s->clk = fclk;
479 s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s);
480 s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s);
481 s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0];
482 omap_gp_timer_reset(s);
483 omap_gp_timer_clk_setup(s);
484
485 iomemtype = l4_register_io_memory(omap_gp_timer_readfn,
486 omap_gp_timer_writefn, s);
487 omap_l4_attach(ta, 0, iomemtype);
488
489 return s;
490 }
491
492 /* 32-kHz Sync Timer of the OMAP2 */
493 static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {
494 return muldiv64(qemu_get_clock(vm_clock), 0x8000, get_ticks_per_sec());
495 }
496
497 static void omap_synctimer_reset(struct omap_synctimer_s *s)
498 {
499 s->val = omap_synctimer_read(s);
500 }
501
502 static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
503 {
504 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
505
506 switch (addr) {
507 case 0x00: /* 32KSYNCNT_REV */
508 return 0x21;
509
510 case 0x10: /* CR */
511 return omap_synctimer_read(s) - s->val;
512 }
513
514 OMAP_BAD_REG(addr);
515 return 0;
516 }
517
518 static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
519 {
520 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
521 uint32_t ret;
522
523 if (addr & 2)
524 return s->readh;
525 else {
526 ret = omap_synctimer_readw(opaque, addr);
527 s->readh = ret >> 16;
528 return ret & 0xffff;
529 }
530 }
531
532 static CPUReadMemoryFunc * const omap_synctimer_readfn[] = {
533 omap_badwidth_read32,
534 omap_synctimer_readh,
535 omap_synctimer_readw,
536 };
537
538 static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
539 uint32_t value)
540 {
541 OMAP_BAD_REG(addr);
542 }
543
544 static CPUWriteMemoryFunc * const omap_synctimer_writefn[] = {
545 omap_badwidth_write32,
546 omap_synctimer_write,
547 omap_synctimer_write,
548 };
549
550 void omap_synctimer_init(struct omap_target_agent_s *ta,
551 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk)
552 {
553 struct omap_synctimer_s *s = &mpu->synctimer;
554
555 omap_synctimer_reset(s);
556 omap_l4_attach(ta, 0, l4_register_io_memory(
557 omap_synctimer_readfn, omap_synctimer_writefn, s));
558 }
559
560 /* General-Purpose Interface of OMAP2 */
561 struct omap2_gpio_s {
562 qemu_irq irq[2];
563 qemu_irq wkup;
564 qemu_irq *in;
565 qemu_irq handler[32];
566
567 uint8_t config[2];
568 uint32_t inputs;
569 uint32_t outputs;
570 uint32_t dir;
571 uint32_t level[2];
572 uint32_t edge[2];
573 uint32_t mask[2];
574 uint32_t wumask;
575 uint32_t ints[2];
576 uint32_t debounce;
577 uint8_t delay;
578 };
579
580 static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s,
581 int line)
582 {
583 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
584 }
585
586 static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line)
587 {
588 if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */
589 return;
590 if (!(s->config[0] & (3 << 3))) /* Force Idle */
591 return;
592 if (!(s->wumask & (1 << line)))
593 return;
594
595 qemu_irq_raise(s->wkup);
596 }
597
598 static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s,
599 uint32_t diff)
600 {
601 int ln;
602
603 s->outputs ^= diff;
604 diff &= ~s->dir;
605 while ((ln = ffs(diff))) {
606 ln --;
607 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
608 diff &= ~(1 << ln);
609 }
610 }
611
612 static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line)
613 {
614 s->ints[line] |= s->dir &
615 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
616 omap_gpio_module_int_update(s, line);
617 }
618
619 static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line)
620 {
621 s->ints[0] |= 1 << line;
622 omap_gpio_module_int_update(s, 0);
623 s->ints[1] |= 1 << line;
624 omap_gpio_module_int_update(s, 1);
625 omap_gpio_module_wake(s, line);
626 }
627
628 static void omap_gpio_module_set(void *opaque, int line, int level)
629 {
630 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
631
632 if (level) {
633 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
634 omap_gpio_module_int(s, line);
635 s->inputs |= 1 << line;
636 } else {
637 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
638 omap_gpio_module_int(s, line);
639 s->inputs &= ~(1 << line);
640 }
641 }
642
643 static void omap_gpio_module_reset(struct omap2_gpio_s *s)
644 {
645 s->config[0] = 0;
646 s->config[1] = 2;
647 s->ints[0] = 0;
648 s->ints[1] = 0;
649 s->mask[0] = 0;
650 s->mask[1] = 0;
651 s->wumask = 0;
652 s->dir = ~0;
653 s->level[0] = 0;
654 s->level[1] = 0;
655 s->edge[0] = 0;
656 s->edge[1] = 0;
657 s->debounce = 0;
658 s->delay = 0;
659 }
660
661 static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
662 {
663 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
664
665 switch (addr) {
666 case 0x00: /* GPIO_REVISION */
667 return 0x18;
668
669 case 0x10: /* GPIO_SYSCONFIG */
670 return s->config[0];
671
672 case 0x14: /* GPIO_SYSSTATUS */
673 return 0x01;
674
675 case 0x18: /* GPIO_IRQSTATUS1 */
676 return s->ints[0];
677
678 case 0x1c: /* GPIO_IRQENABLE1 */
679 case 0x60: /* GPIO_CLEARIRQENABLE1 */
680 case 0x64: /* GPIO_SETIRQENABLE1 */
681 return s->mask[0];
682
683 case 0x20: /* GPIO_WAKEUPENABLE */
684 case 0x80: /* GPIO_CLEARWKUENA */
685 case 0x84: /* GPIO_SETWKUENA */
686 return s->wumask;
687
688 case 0x28: /* GPIO_IRQSTATUS2 */
689 return s->ints[1];
690
691 case 0x2c: /* GPIO_IRQENABLE2 */
692 case 0x70: /* GPIO_CLEARIRQENABLE2 */
693 case 0x74: /* GPIO_SETIREQNEABLE2 */
694 return s->mask[1];
695
696 case 0x30: /* GPIO_CTRL */
697 return s->config[1];
698
699 case 0x34: /* GPIO_OE */
700 return s->dir;
701
702 case 0x38: /* GPIO_DATAIN */
703 return s->inputs;
704
705 case 0x3c: /* GPIO_DATAOUT */
706 case 0x90: /* GPIO_CLEARDATAOUT */
707 case 0x94: /* GPIO_SETDATAOUT */
708 return s->outputs;
709
710 case 0x40: /* GPIO_LEVELDETECT0 */
711 return s->level[0];
712
713 case 0x44: /* GPIO_LEVELDETECT1 */
714 return s->level[1];
715
716 case 0x48: /* GPIO_RISINGDETECT */
717 return s->edge[0];
718
719 case 0x4c: /* GPIO_FALLINGDETECT */
720 return s->edge[1];
721
722 case 0x50: /* GPIO_DEBOUNCENABLE */
723 return s->debounce;
724
725 case 0x54: /* GPIO_DEBOUNCINGTIME */
726 return s->delay;
727 }
728
729 OMAP_BAD_REG(addr);
730 return 0;
731 }
732
733 static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,
734 uint32_t value)
735 {
736 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
737 uint32_t diff;
738 int ln;
739
740 switch (addr) {
741 case 0x00: /* GPIO_REVISION */
742 case 0x14: /* GPIO_SYSSTATUS */
743 case 0x38: /* GPIO_DATAIN */
744 OMAP_RO_REG(addr);
745 break;
746
747 case 0x10: /* GPIO_SYSCONFIG */
748 if (((value >> 3) & 3) == 3)
749 fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
750 if (value & 2)
751 omap_gpio_module_reset(s);
752 s->config[0] = value & 0x1d;
753 break;
754
755 case 0x18: /* GPIO_IRQSTATUS1 */
756 if (s->ints[0] & value) {
757 s->ints[0] &= ~value;
758 omap_gpio_module_level_update(s, 0);
759 }
760 break;
761
762 case 0x1c: /* GPIO_IRQENABLE1 */
763 s->mask[0] = value;
764 omap_gpio_module_int_update(s, 0);
765 break;
766
767 case 0x20: /* GPIO_WAKEUPENABLE */
768 s->wumask = value;
769 break;
770
771 case 0x28: /* GPIO_IRQSTATUS2 */
772 if (s->ints[1] & value) {
773 s->ints[1] &= ~value;
774 omap_gpio_module_level_update(s, 1);
775 }
776 break;
777
778 case 0x2c: /* GPIO_IRQENABLE2 */
779 s->mask[1] = value;
780 omap_gpio_module_int_update(s, 1);
781 break;
782
783 case 0x30: /* GPIO_CTRL */
784 s->config[1] = value & 7;
785 break;
786
787 case 0x34: /* GPIO_OE */
788 diff = s->outputs & (s->dir ^ value);
789 s->dir = value;
790
791 value = s->outputs & ~s->dir;
792 while ((ln = ffs(diff))) {
793 diff &= ~(1 <<-- ln);
794 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
795 }
796
797 omap_gpio_module_level_update(s, 0);
798 omap_gpio_module_level_update(s, 1);
799 break;
800
801 case 0x3c: /* GPIO_DATAOUT */
802 omap_gpio_module_out_update(s, s->outputs ^ value);
803 break;
804
805 case 0x40: /* GPIO_LEVELDETECT0 */
806 s->level[0] = value;
807 omap_gpio_module_level_update(s, 0);
808 omap_gpio_module_level_update(s, 1);
809 break;
810
811 case 0x44: /* GPIO_LEVELDETECT1 */
812 s->level[1] = value;
813 omap_gpio_module_level_update(s, 0);
814 omap_gpio_module_level_update(s, 1);
815 break;
816
817 case 0x48: /* GPIO_RISINGDETECT */
818 s->edge[0] = value;
819 break;
820
821 case 0x4c: /* GPIO_FALLINGDETECT */
822 s->edge[1] = value;
823 break;
824
825 case 0x50: /* GPIO_DEBOUNCENABLE */
826 s->debounce = value;
827 break;
828
829 case 0x54: /* GPIO_DEBOUNCINGTIME */
830 s->delay = value;
831 break;
832
833 case 0x60: /* GPIO_CLEARIRQENABLE1 */
834 s->mask[0] &= ~value;
835 omap_gpio_module_int_update(s, 0);
836 break;
837
838 case 0x64: /* GPIO_SETIRQENABLE1 */
839 s->mask[0] |= value;
840 omap_gpio_module_int_update(s, 0);
841 break;
842
843 case 0x70: /* GPIO_CLEARIRQENABLE2 */
844 s->mask[1] &= ~value;
845 omap_gpio_module_int_update(s, 1);
846 break;
847
848 case 0x74: /* GPIO_SETIREQNEABLE2 */
849 s->mask[1] |= value;
850 omap_gpio_module_int_update(s, 1);
851 break;
852
853 case 0x80: /* GPIO_CLEARWKUENA */
854 s->wumask &= ~value;
855 break;
856
857 case 0x84: /* GPIO_SETWKUENA */
858 s->wumask |= value;
859 break;
860
861 case 0x90: /* GPIO_CLEARDATAOUT */
862 omap_gpio_module_out_update(s, s->outputs & value);
863 break;
864
865 case 0x94: /* GPIO_SETDATAOUT */
866 omap_gpio_module_out_update(s, ~s->outputs & value);
867 break;
868
869 default:
870 OMAP_BAD_REG(addr);
871 return;
872 }
873 }
874
875 static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr)
876 {
877 return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3);
878 }
879
880 static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,
881 uint32_t value)
882 {
883 uint32_t cur = 0;
884 uint32_t mask = 0xffff;
885
886 switch (addr & ~3) {
887 case 0x00: /* GPIO_REVISION */
888 case 0x14: /* GPIO_SYSSTATUS */
889 case 0x38: /* GPIO_DATAIN */
890 OMAP_RO_REG(addr);
891 break;
892
893 case 0x10: /* GPIO_SYSCONFIG */
894 case 0x1c: /* GPIO_IRQENABLE1 */
895 case 0x20: /* GPIO_WAKEUPENABLE */
896 case 0x2c: /* GPIO_IRQENABLE2 */
897 case 0x30: /* GPIO_CTRL */
898 case 0x34: /* GPIO_OE */
899 case 0x3c: /* GPIO_DATAOUT */
900 case 0x40: /* GPIO_LEVELDETECT0 */
901 case 0x44: /* GPIO_LEVELDETECT1 */
902 case 0x48: /* GPIO_RISINGDETECT */
903 case 0x4c: /* GPIO_FALLINGDETECT */
904 case 0x50: /* GPIO_DEBOUNCENABLE */
905 case 0x54: /* GPIO_DEBOUNCINGTIME */
906 cur = omap_gpio_module_read(opaque, addr & ~3) &
907 ~(mask << ((addr & 3) << 3));
908
909 /* Fall through. */
910 case 0x18: /* GPIO_IRQSTATUS1 */
911 case 0x28: /* GPIO_IRQSTATUS2 */
912 case 0x60: /* GPIO_CLEARIRQENABLE1 */
913 case 0x64: /* GPIO_SETIRQENABLE1 */
914 case 0x70: /* GPIO_CLEARIRQENABLE2 */
915 case 0x74: /* GPIO_SETIREQNEABLE2 */
916 case 0x80: /* GPIO_CLEARWKUENA */
917 case 0x84: /* GPIO_SETWKUENA */
918 case 0x90: /* GPIO_CLEARDATAOUT */
919 case 0x94: /* GPIO_SETDATAOUT */
920 value <<= (addr & 3) << 3;
921 omap_gpio_module_write(opaque, addr, cur | value);
922 break;
923
924 default:
925 OMAP_BAD_REG(addr);
926 return;
927 }
928 }
929
930 static CPUReadMemoryFunc * const omap_gpio_module_readfn[] = {
931 omap_gpio_module_readp,
932 omap_gpio_module_readp,
933 omap_gpio_module_read,
934 };
935
936 static CPUWriteMemoryFunc * const omap_gpio_module_writefn[] = {
937 omap_gpio_module_writep,
938 omap_gpio_module_writep,
939 omap_gpio_module_write,
940 };
941
942 static void omap_gpio_module_init(struct omap2_gpio_s *s,
943 struct omap_target_agent_s *ta, int region,
944 qemu_irq mpu, qemu_irq dsp, qemu_irq wkup,
945 omap_clk fclk, omap_clk iclk)
946 {
947 int iomemtype;
948
949 s->irq[0] = mpu;
950 s->irq[1] = dsp;
951 s->wkup = wkup;
952 s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);
953
954 iomemtype = l4_register_io_memory(omap_gpio_module_readfn,
955 omap_gpio_module_writefn, s);
956 omap_l4_attach(ta, region, iomemtype);
957 }
958
959 struct omap_gpif_s {
960 struct omap2_gpio_s module[5];
961 int modules;
962
963 int autoidle;
964 int gpo;
965 };
966
967 static void omap_gpif_reset(struct omap_gpif_s *s)
968 {
969 int i;
970
971 for (i = 0; i < s->modules; i ++)
972 omap_gpio_module_reset(s->module + i);
973
974 s->autoidle = 0;
975 s->gpo = 0;
976 }
977
978 static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
979 {
980 struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
981
982 switch (addr) {
983 case 0x00: /* IPGENERICOCPSPL_REVISION */
984 return 0x18;
985
986 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
987 return s->autoidle;
988
989 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
990 return 0x01;
991
992 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
993 return 0x00;
994
995 case 0x40: /* IPGENERICOCPSPL_GPO */
996 return s->gpo;
997
998 case 0x50: /* IPGENERICOCPSPL_GPI */
999 return 0x00;
1000 }
1001
1002 OMAP_BAD_REG(addr);
1003 return 0;
1004 }
1005
1006 static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,
1007 uint32_t value)
1008 {
1009 struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
1010
1011 switch (addr) {
1012 case 0x00: /* IPGENERICOCPSPL_REVISION */
1013 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
1014 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
1015 case 0x50: /* IPGENERICOCPSPL_GPI */
1016 OMAP_RO_REG(addr);
1017 break;
1018
1019 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
1020 if (value & (1 << 1)) /* SOFTRESET */
1021 omap_gpif_reset(s);
1022 s->autoidle = value & 1;
1023 break;
1024
1025 case 0x40: /* IPGENERICOCPSPL_GPO */
1026 s->gpo = value & 1;
1027 break;
1028
1029 default:
1030 OMAP_BAD_REG(addr);
1031 return;
1032 }
1033 }
1034
1035 static CPUReadMemoryFunc * const omap_gpif_top_readfn[] = {
1036 omap_gpif_top_read,
1037 omap_gpif_top_read,
1038 omap_gpif_top_read,
1039 };
1040
1041 static CPUWriteMemoryFunc * const omap_gpif_top_writefn[] = {
1042 omap_gpif_top_write,
1043 omap_gpif_top_write,
1044 omap_gpif_top_write,
1045 };
1046
1047 struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
1048 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules)
1049 {
1050 int iomemtype, i;
1051 struct omap_gpif_s *s = (struct omap_gpif_s *)
1052 qemu_mallocz(sizeof(struct omap_gpif_s));
1053 int region[4] = { 0, 2, 4, 5 };
1054
1055 s->modules = modules;
1056 for (i = 0; i < modules; i ++)
1057 omap_gpio_module_init(s->module + i, ta, region[i],
1058 irq[i], NULL, NULL, fclk[i], iclk);
1059
1060 omap_gpif_reset(s);
1061
1062 iomemtype = l4_register_io_memory(omap_gpif_top_readfn,
1063 omap_gpif_top_writefn, s);
1064 omap_l4_attach(ta, 1, iomemtype);
1065
1066 return s;
1067 }
1068
1069 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
1070 {
1071 if (start >= s->modules * 32 || start < 0)
1072 hw_error("%s: No GPIO line %i\n", __FUNCTION__, start);
1073 return s->module[start >> 5].in + (start & 31);
1074 }
1075
1076 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)
1077 {
1078 if (line >= s->modules * 32 || line < 0)
1079 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
1080 s->module[line >> 5].handler[line & 31] = handler;
1081 }
1082
1083 /* Multichannel SPI */
1084 struct omap_mcspi_s {
1085 qemu_irq irq;
1086 int chnum;
1087
1088 uint32_t sysconfig;
1089 uint32_t systest;
1090 uint32_t irqst;
1091 uint32_t irqen;
1092 uint32_t wken;
1093 uint32_t control;
1094
1095 struct omap_mcspi_ch_s {
1096 qemu_irq txdrq;
1097 qemu_irq rxdrq;
1098 uint32_t (*txrx)(void *opaque, uint32_t, int);
1099 void *opaque;
1100
1101 uint32_t tx;
1102 uint32_t rx;
1103
1104 uint32_t config;
1105 uint32_t status;
1106 uint32_t control;
1107 } ch[4];
1108 };
1109
1110 static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
1111 {
1112 qemu_set_irq(s->irq, s->irqst & s->irqen);
1113 }
1114
1115 static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
1116 {
1117 qemu_set_irq(ch->txdrq,
1118 (ch->control & 1) && /* EN */
1119 (ch->config & (1 << 14)) && /* DMAW */
1120 (ch->status & (1 << 1)) && /* TXS */
1121 ((ch->config >> 12) & 3) != 1); /* TRM */
1122 qemu_set_irq(ch->rxdrq,
1123 (ch->control & 1) && /* EN */
1124 (ch->config & (1 << 15)) && /* DMAW */
1125 (ch->status & (1 << 0)) && /* RXS */
1126 ((ch->config >> 12) & 3) != 2); /* TRM */
1127 }
1128
1129 static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
1130 {
1131 struct omap_mcspi_ch_s *ch = s->ch + chnum;
1132
1133 if (!(ch->control & 1)) /* EN */
1134 return;
1135 if ((ch->status & (1 << 0)) && /* RXS */
1136 ((ch->config >> 12) & 3) != 2 && /* TRM */
1137 !(ch->config & (1 << 19))) /* TURBO */
1138 goto intr_update;
1139 if ((ch->status & (1 << 1)) && /* TXS */
1140 ((ch->config >> 12) & 3) != 1) /* TRM */
1141 goto intr_update;
1142
1143 if (!(s->control & 1) || /* SINGLE */
1144 (ch->config & (1 << 20))) { /* FORCE */
1145 if (ch->txrx)
1146 ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
1147 1 + (0x1f & (ch->config >> 7)));
1148 }
1149
1150 ch->tx = 0;
1151 ch->status |= 1 << 2; /* EOT */
1152 ch->status |= 1 << 1; /* TXS */
1153 if (((ch->config >> 12) & 3) != 2) /* TRM */
1154 ch->status |= 1 << 0; /* RXS */
1155
1156 intr_update:
1157 if ((ch->status & (1 << 0)) && /* RXS */
1158 ((ch->config >> 12) & 3) != 2 && /* TRM */
1159 !(ch->config & (1 << 19))) /* TURBO */
1160 s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */
1161 if ((ch->status & (1 << 1)) && /* TXS */
1162 ((ch->config >> 12) & 3) != 1) /* TRM */
1163 s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */
1164 omap_mcspi_interrupt_update(s);
1165 omap_mcspi_dmarequest_update(ch);
1166 }
1167
1168 static void omap_mcspi_reset(struct omap_mcspi_s *s)
1169 {
1170 int ch;
1171
1172 s->sysconfig = 0;
1173 s->systest = 0;
1174 s->irqst = 0;
1175 s->irqen = 0;
1176 s->wken = 0;
1177 s->control = 4;
1178
1179 for (ch = 0; ch < 4; ch ++) {
1180 s->ch[ch].config = 0x060000;
1181 s->ch[ch].status = 2; /* TXS */
1182 s->ch[ch].control = 0;
1183
1184 omap_mcspi_dmarequest_update(s->ch + ch);
1185 }
1186
1187 omap_mcspi_interrupt_update(s);
1188 }
1189
1190 static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
1191 {
1192 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1193 int ch = 0;
1194 uint32_t ret;
1195
1196 switch (addr) {
1197 case 0x00: /* MCSPI_REVISION */
1198 return 0x91;
1199
1200 case 0x10: /* MCSPI_SYSCONFIG */
1201 return s->sysconfig;
1202
1203 case 0x14: /* MCSPI_SYSSTATUS */
1204 return 1; /* RESETDONE */
1205
1206 case 0x18: /* MCSPI_IRQSTATUS */
1207 return s->irqst;
1208
1209 case 0x1c: /* MCSPI_IRQENABLE */
1210 return s->irqen;
1211
1212 case 0x20: /* MCSPI_WAKEUPENABLE */
1213 return s->wken;
1214
1215 case 0x24: /* MCSPI_SYST */
1216 return s->systest;
1217
1218 case 0x28: /* MCSPI_MODULCTRL */
1219 return s->control;
1220
1221 case 0x68: ch ++;
1222 case 0x54: ch ++;
1223 case 0x40: ch ++;
1224 case 0x2c: /* MCSPI_CHCONF */
1225 return s->ch[ch].config;
1226
1227 case 0x6c: ch ++;
1228 case 0x58: ch ++;
1229 case 0x44: ch ++;
1230 case 0x30: /* MCSPI_CHSTAT */
1231 return s->ch[ch].status;
1232
1233 case 0x70: ch ++;
1234 case 0x5c: ch ++;
1235 case 0x48: ch ++;
1236 case 0x34: /* MCSPI_CHCTRL */
1237 return s->ch[ch].control;
1238
1239 case 0x74: ch ++;
1240 case 0x60: ch ++;
1241 case 0x4c: ch ++;
1242 case 0x38: /* MCSPI_TX */
1243 return s->ch[ch].tx;
1244
1245 case 0x78: ch ++;
1246 case 0x64: ch ++;
1247 case 0x50: ch ++;
1248 case 0x3c: /* MCSPI_RX */
1249 s->ch[ch].status &= ~(1 << 0); /* RXS */
1250 ret = s->ch[ch].rx;
1251 omap_mcspi_transfer_run(s, ch);
1252 return ret;
1253 }
1254
1255 OMAP_BAD_REG(addr);
1256 return 0;
1257 }
1258
1259 static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
1260 uint32_t value)
1261 {
1262 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1263 int ch = 0;
1264
1265 switch (addr) {
1266 case 0x00: /* MCSPI_REVISION */
1267 case 0x14: /* MCSPI_SYSSTATUS */
1268 case 0x30: /* MCSPI_CHSTAT0 */
1269 case 0x3c: /* MCSPI_RX0 */
1270 case 0x44: /* MCSPI_CHSTAT1 */
1271 case 0x50: /* MCSPI_RX1 */
1272 case 0x58: /* MCSPI_CHSTAT2 */
1273 case 0x64: /* MCSPI_RX2 */
1274 case 0x6c: /* MCSPI_CHSTAT3 */
1275 case 0x78: /* MCSPI_RX3 */
1276 OMAP_RO_REG(addr);
1277 return;
1278
1279 case 0x10: /* MCSPI_SYSCONFIG */
1280 if (value & (1 << 1)) /* SOFTRESET */
1281 omap_mcspi_reset(s);
1282 s->sysconfig = value & 0x31d;
1283 break;
1284
1285 case 0x18: /* MCSPI_IRQSTATUS */
1286 if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
1287 s->irqst &= ~value;
1288 omap_mcspi_interrupt_update(s);
1289 }
1290 break;
1291
1292 case 0x1c: /* MCSPI_IRQENABLE */
1293 s->irqen = value & 0x1777f;
1294 omap_mcspi_interrupt_update(s);
1295 break;
1296
1297 case 0x20: /* MCSPI_WAKEUPENABLE */
1298 s->wken = value & 1;
1299 break;
1300
1301 case 0x24: /* MCSPI_SYST */
1302 if (s->control & (1 << 3)) /* SYSTEM_TEST */
1303 if (value & (1 << 11)) { /* SSB */
1304 s->irqst |= 0x1777f;
1305 omap_mcspi_interrupt_update(s);
1306 }
1307 s->systest = value & 0xfff;
1308 break;
1309
1310 case 0x28: /* MCSPI_MODULCTRL */
1311 if (value & (1 << 3)) /* SYSTEM_TEST */
1312 if (s->systest & (1 << 11)) { /* SSB */
1313 s->irqst |= 0x1777f;
1314 omap_mcspi_interrupt_update(s);
1315 }
1316 s->control = value & 0xf;
1317 break;
1318
1319 case 0x68: ch ++;
1320 case 0x54: ch ++;
1321 case 0x40: ch ++;
1322 case 0x2c: /* MCSPI_CHCONF */
1323 if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
1324 omap_mcspi_dmarequest_update(s->ch + ch);
1325 if (((value >> 12) & 3) == 3) /* TRM */
1326 fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
1327 if (((value >> 7) & 0x1f) < 3) /* WL */
1328 fprintf(stderr, "%s: invalid WL value (%i)\n",
1329 __FUNCTION__, (value >> 7) & 0x1f);
1330 s->ch[ch].config = value & 0x7fffff;
1331 break;
1332
1333 case 0x70: ch ++;
1334 case 0x5c: ch ++;
1335 case 0x48: ch ++;
1336 case 0x34: /* MCSPI_CHCTRL */
1337 if (value & ~s->ch[ch].control & 1) { /* EN */
1338 s->ch[ch].control |= 1;
1339 omap_mcspi_transfer_run(s, ch);
1340 } else
1341 s->ch[ch].control = value & 1;
1342 break;
1343
1344 case 0x74: ch ++;
1345 case 0x60: ch ++;
1346 case 0x4c: ch ++;
1347 case 0x38: /* MCSPI_TX */
1348 s->ch[ch].tx = value;
1349 s->ch[ch].status &= ~(1 << 1); /* TXS */
1350 omap_mcspi_transfer_run(s, ch);
1351 break;
1352
1353 default:
1354 OMAP_BAD_REG(addr);
1355 return;
1356 }
1357 }
1358
1359 static CPUReadMemoryFunc * const omap_mcspi_readfn[] = {
1360 omap_badwidth_read32,
1361 omap_badwidth_read32,
1362 omap_mcspi_read,
1363 };
1364
1365 static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = {
1366 omap_badwidth_write32,
1367 omap_badwidth_write32,
1368 omap_mcspi_write,
1369 };
1370
1371 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
1372 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
1373 {
1374 int iomemtype;
1375 struct omap_mcspi_s *s = (struct omap_mcspi_s *)
1376 qemu_mallocz(sizeof(struct omap_mcspi_s));
1377 struct omap_mcspi_ch_s *ch = s->ch;
1378
1379 s->irq = irq;
1380 s->chnum = chnum;
1381 while (chnum --) {
1382 ch->txdrq = *drq ++;
1383 ch->rxdrq = *drq ++;
1384 ch ++;
1385 }
1386 omap_mcspi_reset(s);
1387
1388 iomemtype = l4_register_io_memory(omap_mcspi_readfn,
1389 omap_mcspi_writefn, s);
1390 omap_l4_attach(ta, 0, iomemtype);
1391
1392 return s;
1393 }
1394
1395 void omap_mcspi_attach(struct omap_mcspi_s *s,
1396 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
1397 int chipselect)
1398 {
1399 if (chipselect < 0 || chipselect >= s->chnum)
1400 hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
1401
1402 s->ch[chipselect].txrx = txrx;
1403 s->ch[chipselect].opaque = opaque;
1404 }
1405
1406 /* Enhanced Audio Controller (CODEC only) */
1407 struct omap_eac_s {
1408 qemu_irq irq;
1409
1410 uint16_t sysconfig;
1411 uint8_t config[4];
1412 uint8_t control;
1413 uint8_t address;
1414 uint16_t data;
1415 uint8_t vtol;
1416 uint8_t vtsl;
1417 uint16_t mixer;
1418 uint16_t gain[4];
1419 uint8_t att;
1420 uint16_t max[7];
1421
1422 struct {
1423 qemu_irq txdrq;
1424 qemu_irq rxdrq;
1425 uint32_t (*txrx)(void *opaque, uint32_t, int);
1426 void *opaque;
1427
1428 #define EAC_BUF_LEN 1024
1429 uint32_t rxbuf[EAC_BUF_LEN];
1430 int rxoff;
1431 int rxlen;
1432 int rxavail;
1433 uint32_t txbuf[EAC_BUF_LEN];
1434 int txlen;
1435 int txavail;
1436
1437 int enable;
1438 int rate;
1439
1440 uint16_t config[4];
1441
1442 /* These need to be moved to the actual codec */
1443 QEMUSoundCard card;
1444 SWVoiceIn *in_voice;
1445 SWVoiceOut *out_voice;
1446 int hw_enable;
1447 } codec;
1448
1449 struct {
1450 uint8_t control;
1451 uint16_t config;
1452 } modem, bt;
1453 };
1454
1455 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
1456 {
1457 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
1458 }
1459
1460 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
1461 {
1462 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
1463 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
1464 }
1465
1466 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
1467 {
1468 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
1469 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
1470 }
1471
1472 static inline void omap_eac_in_refill(struct omap_eac_s *s)
1473 {
1474 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
1475 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
1476 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
1477 int recv = 1;
1478 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
1479
1480 left -= leftwrap;
1481 start = 0;
1482 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
1483 leftwrap)) > 0) { /* Be defensive */
1484 start += recv;
1485 leftwrap -= recv;
1486 }
1487 if (recv <= 0)
1488 s->codec.rxavail = 0;
1489 else
1490 s->codec.rxavail -= start >> 2;
1491 s->codec.rxlen += start >> 2;
1492
1493 if (recv > 0 && left > 0) {
1494 start = 0;
1495 while (left && (recv = AUD_read(s->codec.in_voice,
1496 (uint8_t *) s->codec.rxbuf + start,
1497 left)) > 0) { /* Be defensive */
1498 start += recv;
1499 left -= recv;
1500 }
1501 if (recv <= 0)
1502 s->codec.rxavail = 0;
1503 else
1504 s->codec.rxavail -= start >> 2;
1505 s->codec.rxlen += start >> 2;
1506 }
1507 }
1508
1509 static inline void omap_eac_out_empty(struct omap_eac_s *s)
1510 {
1511 int left = s->codec.txlen << 2;
1512 int start = 0;
1513 int sent = 1;
1514
1515 while (left && (sent = AUD_write(s->codec.out_voice,
1516 (uint8_t *) s->codec.txbuf + start,
1517 left)) > 0) { /* Be defensive */
1518 start += sent;
1519 left -= sent;
1520 }
1521
1522 if (!sent) {
1523 s->codec.txavail = 0;
1524 omap_eac_out_dmarequest_update(s);
1525 }
1526
1527 if (start)
1528 s->codec.txlen = 0;
1529 }
1530
1531 static void omap_eac_in_cb(void *opaque, int avail_b)
1532 {
1533 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1534
1535 s->codec.rxavail = avail_b >> 2;
1536 omap_eac_in_refill(s);
1537 /* TODO: possibly discard current buffer if overrun */
1538 omap_eac_in_dmarequest_update(s);
1539 }
1540
1541 static void omap_eac_out_cb(void *opaque, int free_b)
1542 {
1543 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1544
1545 s->codec.txavail = free_b >> 2;
1546 if (s->codec.txlen)
1547 omap_eac_out_empty(s);
1548 else
1549 omap_eac_out_dmarequest_update(s);
1550 }
1551
1552 static void omap_eac_enable_update(struct omap_eac_s *s)
1553 {
1554 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
1555 (s->codec.config[1] & 2) && /* AUDEN */
1556 s->codec.hw_enable;
1557 }
1558
1559 static const int omap_eac_fsint[4] = {
1560 8000,
1561 11025,
1562 22050,
1563 44100,
1564 };
1565
1566 static const int omap_eac_fsint2[8] = {
1567 8000,
1568 11025,
1569 22050,
1570 44100,
1571 48000,
1572 0, 0, 0,
1573 };
1574
1575 static const int omap_eac_fsint3[16] = {
1576 8000,
1577 11025,
1578 16000,
1579 22050,
1580 24000,
1581 32000,
1582 44100,
1583 48000,
1584 0, 0, 0, 0, 0, 0, 0, 0,
1585 };
1586
1587 static void omap_eac_rate_update(struct omap_eac_s *s)
1588 {
1589 int fsint[3];
1590
1591 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
1592 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
1593 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
1594 if (fsint[2] < 0xf)
1595 s->codec.rate = omap_eac_fsint3[fsint[2]];
1596 else if (fsint[1] < 0x7)
1597 s->codec.rate = omap_eac_fsint2[fsint[1]];
1598 else
1599 s->codec.rate = omap_eac_fsint[fsint[0]];
1600 }
1601
1602 static void omap_eac_volume_update(struct omap_eac_s *s)
1603 {
1604 /* TODO */
1605 }
1606
1607 static void omap_eac_format_update(struct omap_eac_s *s)
1608 {
1609 struct audsettings fmt;
1610
1611 /* The hardware buffers at most one sample */
1612 if (s->codec.rxlen)
1613 s->codec.rxlen = 1;
1614
1615 if (s->codec.in_voice) {
1616 AUD_set_active_in(s->codec.in_voice, 0);
1617 AUD_close_in(&s->codec.card, s->codec.in_voice);
1618 s->codec.in_voice = NULL;
1619 }
1620 if (s->codec.out_voice) {
1621 omap_eac_out_empty(s);
1622 AUD_set_active_out(s->codec.out_voice, 0);
1623 AUD_close_out(&s->codec.card, s->codec.out_voice);
1624 s->codec.out_voice = NULL;
1625 s->codec.txavail = 0;
1626 }
1627 /* Discard what couldn't be written */
1628 s->codec.txlen = 0;
1629
1630 omap_eac_enable_update(s);
1631 if (!s->codec.enable)
1632 return;
1633
1634 omap_eac_rate_update(s);
1635 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
1636 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
1637 fmt.freq = s->codec.rate;
1638 /* TODO: signedness possibly depends on the CODEC hardware - or
1639 * does I2S specify it? */
1640 /* All register writes are 16 bits so we we store 16-bit samples
1641 * in the buffers regardless of AGCFR[B8_16] value. */
1642 fmt.fmt = AUD_FMT_U16;
1643
1644 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
1645 "eac.codec.in", s, omap_eac_in_cb, &fmt);
1646 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
1647 "eac.codec.out", s, omap_eac_out_cb, &fmt);
1648
1649 omap_eac_volume_update(s);
1650
1651 AUD_set_active_in(s->codec.in_voice, 1);
1652 AUD_set_active_out(s->codec.out_voice, 1);
1653 }
1654
1655 static void omap_eac_reset(struct omap_eac_s *s)
1656 {
1657 s->sysconfig = 0;
1658 s->config[0] = 0x0c;
1659 s->config[1] = 0x09;
1660 s->config[2] = 0xab;
1661 s->config[3] = 0x03;
1662 s->control = 0x00;
1663 s->address = 0x00;
1664 s->data = 0x0000;
1665 s->vtol = 0x00;
1666 s->vtsl = 0x00;
1667 s->mixer = 0x0000;
1668 s->gain[0] = 0xe7e7;
1669 s->gain[1] = 0x6767;
1670 s->gain[2] = 0x6767;
1671 s->gain[3] = 0x6767;
1672 s->att = 0xce;
1673 s->max[0] = 0;
1674 s->max[1] = 0;
1675 s->max[2] = 0;
1676 s->max[3] = 0;
1677 s->max[4] = 0;
1678 s->max[5] = 0;
1679 s->max[6] = 0;
1680
1681 s->modem.control = 0x00;
1682 s->modem.config = 0x0000;
1683 s->bt.control = 0x00;
1684 s->bt.config = 0x0000;
1685 s->codec.config[0] = 0x0649;
1686 s->codec.config[1] = 0x0000;
1687 s->codec.config[2] = 0x0007;
1688 s->codec.config[3] = 0x1ffc;
1689 s->codec.rxoff = 0;
1690 s->codec.rxlen = 0;
1691 s->codec.txlen = 0;
1692 s->codec.rxavail = 0;
1693 s->codec.txavail = 0;
1694
1695 omap_eac_format_update(s);
1696 omap_eac_interrupt_update(s);
1697 }
1698
1699 static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
1700 {
1701 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1702 uint32_t ret;
1703
1704 switch (addr) {
1705 case 0x000: /* CPCFR1 */
1706 return s->config[0];
1707 case 0x004: /* CPCFR2 */
1708 return s->config[1];
1709 case 0x008: /* CPCFR3 */
1710 return s->config[2];
1711 case 0x00c: /* CPCFR4 */
1712 return s->config[3];
1713
1714 case 0x010: /* CPTCTL */
1715 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
1716 ((s->codec.txlen < s->codec.txavail) << 5);
1717
1718 case 0x014: /* CPTTADR */
1719 return s->address;
1720 case 0x018: /* CPTDATL */
1721 return s->data & 0xff;
1722 case 0x01c: /* CPTDATH */
1723 return s->data >> 8;
1724 case 0x020: /* CPTVSLL */
1725 return s->vtol;
1726 case 0x024: /* CPTVSLH */
1727 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
1728 case 0x040: /* MPCTR */
1729 return s->modem.control;
1730 case 0x044: /* MPMCCFR */
1731 return s->modem.config;
1732 case 0x060: /* BPCTR */
1733 return s->bt.control;
1734 case 0x064: /* BPMCCFR */
1735 return s->bt.config;
1736 case 0x080: /* AMSCFR */
1737 return s->mixer;
1738 case 0x084: /* AMVCTR */
1739 return s->gain[0];
1740 case 0x088: /* AM1VCTR */
1741 return s->gain[1];
1742 case 0x08c: /* AM2VCTR */
1743 return s->gain[2];
1744 case 0x090: /* AM3VCTR */
1745 return s->gain[3];
1746 case 0x094: /* ASTCTR */
1747 return s->att;
1748 case 0x098: /* APD1LCR */
1749 return s->max[0];
1750 case 0x09c: /* APD1RCR */
1751 return s->max[1];
1752 case 0x0a0: /* APD2LCR */
1753 return s->max[2];
1754 case 0x0a4: /* APD2RCR */
1755 return s->max[3];
1756 case 0x0a8: /* APD3LCR */
1757 return s->max[4];
1758 case 0x0ac: /* APD3RCR */
1759 return s->max[5];
1760 case 0x0b0: /* APD4R */
1761 return s->max[6];
1762 case 0x0b4: /* ADWR */
1763 /* This should be write-only? Docs list it as read-only. */
1764 return 0x0000;
1765 case 0x0b8: /* ADRDR */
1766 if (likely(s->codec.rxlen > 1)) {
1767 ret = s->codec.rxbuf[s->codec.rxoff ++];
1768 s->codec.rxlen --;
1769 s->codec.rxoff &= EAC_BUF_LEN - 1;
1770 return ret;
1771 } else if (s->codec.rxlen) {
1772 ret = s->codec.rxbuf[s->codec.rxoff ++];
1773 s->codec.rxlen --;
1774 s->codec.rxoff &= EAC_BUF_LEN - 1;
1775 if (s->codec.rxavail)
1776 omap_eac_in_refill(s);
1777 omap_eac_in_dmarequest_update(s);
1778 return ret;
1779 }
1780 return 0x0000;
1781 case 0x0bc: /* AGCFR */
1782 return s->codec.config[0];
1783 case 0x0c0: /* AGCTR */
1784 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
1785 case 0x0c4: /* AGCFR2 */
1786 return s->codec.config[2];
1787 case 0x0c8: /* AGCFR3 */
1788 return s->codec.config[3];
1789 case 0x0cc: /* MBPDMACTR */
1790 case 0x0d0: /* MPDDMARR */
1791 case 0x0d8: /* MPUDMARR */
1792 case 0x0e4: /* BPDDMARR */
1793 case 0x0ec: /* BPUDMARR */
1794 return 0x0000;
1795
1796 case 0x100: /* VERSION_NUMBER */
1797 return 0x0010;
1798
1799 case 0x104: /* SYSCONFIG */
1800 return s->sysconfig;
1801
1802 case 0x108: /* SYSSTATUS */
1803 return 1 | 0xe; /* RESETDONE | stuff */
1804 }
1805
1806 OMAP_BAD_REG(addr);
1807 return 0;
1808 }
1809
1810 static void omap_eac_write(void *opaque, target_phys_addr_t addr,
1811 uint32_t value)
1812 {
1813 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1814
1815 switch (addr) {
1816 case 0x098: /* APD1LCR */
1817 case 0x09c: /* APD1RCR */
1818 case 0x0a0: /* APD2LCR */
1819 case 0x0a4: /* APD2RCR */
1820 case 0x0a8: /* APD3LCR */
1821 case 0x0ac: /* APD3RCR */
1822 case 0x0b0: /* APD4R */
1823 case 0x0b8: /* ADRDR */
1824 case 0x0d0: /* MPDDMARR */
1825 case 0x0d8: /* MPUDMARR */
1826 case 0x0e4: /* BPDDMARR */
1827 case 0x0ec: /* BPUDMARR */
1828 case 0x100: /* VERSION_NUMBER */
1829 case 0x108: /* SYSSTATUS */
1830 OMAP_RO_REG(addr);
1831 return;
1832
1833 case 0x000: /* CPCFR1 */
1834 s->config[0] = value & 0xff;
1835 omap_eac_format_update(s);
1836 break;
1837 case 0x004: /* CPCFR2 */
1838 s->config[1] = value & 0xff;
1839 omap_eac_format_update(s);
1840 break;
1841 case 0x008: /* CPCFR3 */
1842 s->config[2] = value & 0xff;
1843 omap_eac_format_update(s);
1844 break;
1845 case 0x00c: /* CPCFR4 */
1846 s->config[3] = value & 0xff;
1847 omap_eac_format_update(s);
1848 break;
1849
1850 case 0x010: /* CPTCTL */
1851 /* Assuming TXF and TXE bits are read-only... */
1852 s->control = value & 0x5f;
1853 omap_eac_interrupt_update(s);
1854 break;
1855
1856 case 0x014: /* CPTTADR */
1857 s->address = value & 0xff;
1858 break;
1859 case 0x018: /* CPTDATL */
1860 s->data &= 0xff00;
1861 s->data |= value & 0xff;
1862 break;
1863 case 0x01c: /* CPTDATH */
1864 s->data &= 0x00ff;
1865 s->data |= value << 8;
1866 break;
1867 case 0x020: /* CPTVSLL */
1868 s->vtol = value & 0xf8;
1869 break;
1870 case 0x024: /* CPTVSLH */
1871 s->vtsl = value & 0x9f;
1872 break;
1873 case 0x040: /* MPCTR */
1874 s->modem.control = value & 0x8f;
1875 break;
1876 case 0x044: /* MPMCCFR */
1877 s->modem.config = value & 0x7fff;
1878 break;
1879 case 0x060: /* BPCTR */
1880 s->bt.control = value & 0x8f;
1881 break;
1882 case 0x064: /* BPMCCFR */
1883 s->bt.config = value & 0x7fff;
1884 break;
1885 case 0x080: /* AMSCFR */
1886 s->mixer = value & 0x0fff;
1887 break;
1888 case 0x084: /* AMVCTR */
1889 s->gain[0] = value & 0xffff;
1890 break;
1891 case 0x088: /* AM1VCTR */
1892 s->gain[1] = value & 0xff7f;
1893 break;
1894 case 0x08c: /* AM2VCTR */
1895 s->gain[2] = value & 0xff7f;
1896 break;
1897 case 0x090: /* AM3VCTR */
1898 s->gain[3] = value & 0xff7f;
1899 break;
1900 case 0x094: /* ASTCTR */
1901 s->att = value & 0xff;
1902 break;
1903
1904 case 0x0b4: /* ADWR */
1905 s->codec.txbuf[s->codec.txlen ++] = value;
1906 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
1907 s->codec.txlen == s->codec.txavail)) {
1908 if (s->codec.txavail)
1909 omap_eac_out_empty(s);
1910 /* Discard what couldn't be written */
1911 s->codec.txlen = 0;
1912 }
1913 break;
1914
1915 case 0x0bc: /* AGCFR */
1916 s->codec.config[0] = value & 0x07ff;
1917 omap_eac_format_update(s);
1918 break;
1919 case 0x0c0: /* AGCTR */
1920 s->codec.config[1] = value & 0x780f;
1921 omap_eac_format_update(s);
1922 break;
1923 case 0x0c4: /* AGCFR2 */
1924 s->codec.config[2] = value & 0x003f;
1925 omap_eac_format_update(s);
1926 break;
1927 case 0x0c8: /* AGCFR3 */
1928 s->codec.config[3] = value & 0xffff;
1929 omap_eac_format_update(s);
1930 break;
1931 case 0x0cc: /* MBPDMACTR */
1932 case 0x0d4: /* MPDDMAWR */
1933 case 0x0e0: /* MPUDMAWR */
1934 case 0x0e8: /* BPDDMAWR */
1935 case 0x0f0: /* BPUDMAWR */
1936 break;
1937
1938 case 0x104: /* SYSCONFIG */
1939 if (value & (1 << 1)) /* SOFTRESET */
1940 omap_eac_reset(s);
1941 s->sysconfig = value & 0x31d;
1942 break;
1943
1944 default:
1945 OMAP_BAD_REG(addr);
1946 return;
1947 }
1948 }
1949
1950 static CPUReadMemoryFunc * const omap_eac_readfn[] = {
1951 omap_badwidth_read16,
1952 omap_eac_read,
1953 omap_badwidth_read16,
1954 };
1955
1956 static CPUWriteMemoryFunc * const omap_eac_writefn[] = {
1957 omap_badwidth_write16,
1958 omap_eac_write,
1959 omap_badwidth_write16,
1960 };
1961
1962 struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
1963 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
1964 {
1965 int iomemtype;
1966 struct omap_eac_s *s = (struct omap_eac_s *)
1967 qemu_mallocz(sizeof(struct omap_eac_s));
1968
1969 s->irq = irq;
1970 s->codec.rxdrq = *drq ++;
1971 s->codec.txdrq = *drq ++;
1972 omap_eac_reset(s);
1973
1974 #ifdef HAS_AUDIO
1975 AUD_register_card("OMAP EAC", &s->codec.card);
1976
1977 iomemtype = cpu_register_io_memory(omap_eac_readfn,
1978 omap_eac_writefn, s);
1979 omap_l4_attach(ta, 0, iomemtype);
1980 #endif
1981
1982 return s;
1983 }
1984
1985 /* STI/XTI (emulation interface) console - reverse engineered only */
1986 struct omap_sti_s {
1987 qemu_irq irq;
1988 CharDriverState *chr;
1989
1990 uint32_t sysconfig;
1991 uint32_t systest;
1992 uint32_t irqst;
1993 uint32_t irqen;
1994 uint32_t clkcontrol;
1995 uint32_t serial_config;
1996 };
1997
1998 #define STI_TRACE_CONSOLE_CHANNEL 239
1999 #define STI_TRACE_CONTROL_CHANNEL 253
2000
2001 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
2002 {
2003 qemu_set_irq(s->irq, s->irqst & s->irqen);
2004 }
2005
2006 static void omap_sti_reset(struct omap_sti_s *s)
2007 {
2008 s->sysconfig = 0;
2009 s->irqst = 0;
2010 s->irqen = 0;
2011 s->clkcontrol = 0;
2012 s->serial_config = 0;
2013
2014 omap_sti_interrupt_update(s);
2015 }
2016
2017 static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
2018 {
2019 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2020
2021 switch (addr) {
2022 case 0x00: /* STI_REVISION */
2023 return 0x10;
2024
2025 case 0x10: /* STI_SYSCONFIG */
2026 return s->sysconfig;
2027
2028 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
2029 return 0x00;
2030
2031 case 0x18: /* STI_IRQSTATUS */
2032 return s->irqst;
2033
2034 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
2035 return s->irqen;
2036
2037 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
2038 case 0x28: /* STI_RX_DR / XTI_RXDATA */
2039 /* TODO */
2040 return 0;
2041
2042 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
2043 return s->clkcontrol;
2044
2045 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
2046 return s->serial_config;
2047 }
2048
2049 OMAP_BAD_REG(addr);
2050 return 0;
2051 }
2052
2053 static void omap_sti_write(void *opaque, target_phys_addr_t addr,
2054 uint32_t value)
2055 {
2056 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2057
2058 switch (addr) {
2059 case 0x00: /* STI_REVISION */
2060 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
2061 OMAP_RO_REG(addr);
2062 return;
2063
2064 case 0x10: /* STI_SYSCONFIG */
2065 if (value & (1 << 1)) /* SOFTRESET */
2066 omap_sti_reset(s);
2067 s->sysconfig = value & 0xfe;
2068 break;
2069
2070 case 0x18: /* STI_IRQSTATUS */
2071 s->irqst &= ~value;
2072 omap_sti_interrupt_update(s);
2073 break;
2074
2075 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
2076 s->irqen = value & 0xffff;
2077 omap_sti_interrupt_update(s);
2078 break;
2079
2080 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
2081 s->clkcontrol = value & 0xff;
2082 break;
2083
2084 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
2085 s->serial_config = value & 0xff;
2086 break;
2087
2088 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
2089 case 0x28: /* STI_RX_DR / XTI_RXDATA */
2090 /* TODO */
2091 return;
2092
2093 default:
2094 OMAP_BAD_REG(addr);
2095 return;
2096 }
2097 }
2098
2099 static CPUReadMemoryFunc * const omap_sti_readfn[] = {
2100 omap_badwidth_read32,
2101 omap_badwidth_read32,
2102 omap_sti_read,
2103 };
2104
2105 static CPUWriteMemoryFunc * const omap_sti_writefn[] = {
2106 omap_badwidth_write32,
2107 omap_badwidth_write32,
2108 omap_sti_write,
2109 };
2110
2111 static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
2112 {
2113 OMAP_BAD_REG(addr);
2114 return 0;
2115 }
2116
2117 static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
2118 uint32_t value)
2119 {
2120 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2121 int ch = addr >> 6;
2122 uint8_t byte = value;
2123
2124 if (ch == STI_TRACE_CONTROL_CHANNEL) {
2125 /* Flush channel <i>value</i>. */
2126 qemu_chr_write(s->chr, (const uint8_t *) "\r", 1);
2127 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
2128 if (value == 0xc0 || value == 0xc3) {
2129 /* Open channel <i>ch</i>. */
2130 } else if (value == 0x00)
2131 qemu_chr_write(s->chr, (const uint8_t *) "\n", 1);
2132 else
2133 qemu_chr_write(s->chr, &byte, 1);
2134 }
2135 }
2136
2137 static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = {
2138 omap_sti_fifo_read,
2139 omap_badwidth_read8,
2140 omap_badwidth_read8,
2141 };
2142
2143 static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = {
2144 omap_sti_fifo_write,
2145 omap_badwidth_write8,
2146 omap_badwidth_write8,
2147 };
2148
2149 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
2150 target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
2151 CharDriverState *chr)
2152 {
2153 int iomemtype;
2154 struct omap_sti_s *s = (struct omap_sti_s *)
2155 qemu_mallocz(sizeof(struct omap_sti_s));
2156
2157 s->irq = irq;
2158 omap_sti_reset(s);
2159
2160 s->chr = chr ?: qemu_chr_open("null", "null", NULL);
2161
2162 iomemtype = l4_register_io_memory(omap_sti_readfn,
2163 omap_sti_writefn, s);
2164 omap_l4_attach(ta, 0, iomemtype);
2165
2166 iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn,
2167 omap_sti_fifo_writefn, s);
2168 cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
2169
2170 return s;
2171 }
2172
2173 /* L4 Interconnect */
2174 struct omap_target_agent_s {
2175 struct omap_l4_s *bus;
2176 int regions;
2177 struct omap_l4_region_s *start;
2178 target_phys_addr_t base;
2179 uint32_t component;
2180 uint32_t control;
2181 uint32_t status;
2182 };
2183
2184 struct omap_l4_s {
2185 target_phys_addr_t base;
2186 int ta_num;
2187 struct omap_target_agent_s ta[0];
2188 };
2189
2190 #ifdef L4_MUX_HACK
2191 static int omap_l4_io_entries;
2192 static int omap_cpu_io_entry;
2193 static struct omap_l4_entry {
2194 CPUReadMemoryFunc * const *mem_read;
2195 CPUWriteMemoryFunc * const *mem_write;
2196 void *opaque;
2197 } *omap_l4_io_entry;
2198 static CPUReadMemoryFunc * const *omap_l4_io_readb_fn;
2199 static CPUReadMemoryFunc * const *omap_l4_io_readh_fn;
2200 static CPUReadMemoryFunc * const *omap_l4_io_readw_fn;
2201 static CPUWriteMemoryFunc * const *omap_l4_io_writeb_fn;
2202 static CPUWriteMemoryFunc * const *omap_l4_io_writeh_fn;
2203 static CPUWriteMemoryFunc * const *omap_l4_io_writew_fn;
2204 static void **omap_l4_io_opaque;
2205
2206 int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
2207 CPUWriteMemoryFunc * const *mem_write, void *opaque)
2208 {
2209 omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
2210 omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
2211 omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
2212
2213 return omap_l4_io_entries ++;
2214 }
2215
2216 static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
2217 {
2218 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2219
2220 return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
2221 }
2222
2223 static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
2224 {
2225 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2226
2227 return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
2228 }
2229
2230 static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
2231 {
2232 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2233
2234 return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
2235 }
2236
2237 static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
2238 uint32_t value)
2239 {
2240 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2241
2242 return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
2243 }
2244
2245 static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
2246 uint32_t value)
2247 {
2248 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2249
2250 return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
2251 }
2252
2253 static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
2254 uint32_t value)
2255 {
2256 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2257
2258 return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
2259 }
2260
2261 static CPUReadMemoryFunc * const omap_l4_io_readfn[] = {
2262 omap_l4_io_readb,
2263 omap_l4_io_readh,
2264 omap_l4_io_readw,
2265 };
2266
2267 static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = {
2268 omap_l4_io_writeb,
2269 omap_l4_io_writeh,
2270 omap_l4_io_writew,
2271 };
2272 #endif
2273
2274 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
2275 {
2276 struct omap_l4_s *bus = qemu_mallocz(
2277 sizeof(*bus) + ta_num * sizeof(*bus->ta));
2278
2279 bus->ta_num = ta_num;
2280 bus->base = base;
2281
2282 #ifdef L4_MUX_HACK
2283 omap_l4_io_entries = 1;
2284 omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
2285
2286 omap_cpu_io_entry =
2287 cpu_register_io_memory(omap_l4_io_readfn,
2288 omap_l4_io_writefn, bus);
2289 # define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
2290 omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2291 omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2292 omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2293 omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2294 omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2295 omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2296 omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES);
2297 #endif
2298
2299 return bus;
2300 }
2301
2302 static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
2303 {
2304 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
2305
2306 switch (addr) {
2307 case 0x00: /* COMPONENT */
2308 return s->component;
2309
2310 case 0x20: /* AGENT_CONTROL */
2311 return s->control;
2312
2313 case 0x28: /* AGENT_STATUS */
2314 return s->status;
2315 }
2316
2317 OMAP_BAD_REG(addr);
2318 return 0;
2319 }
2320
2321 static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
2322 uint32_t value)
2323 {
2324 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
2325
2326 switch (addr) {
2327 case 0x00: /* COMPONENT */
2328 case 0x28: /* AGENT_STATUS */
2329 OMAP_RO_REG(addr);
2330 break;
2331
2332 case 0x20: /* AGENT_CONTROL */
2333 s->control = value & 0x01000700;
2334 if (value & 1) /* OCP_RESET */
2335 s->status &= ~1; /* REQ_TIMEOUT */
2336 break;
2337
2338 default:
2339 OMAP_BAD_REG(addr);
2340 }
2341 }
2342
2343 static CPUReadMemoryFunc * const omap_l4ta_readfn[] = {
2344 omap_badwidth_read16,
2345 omap_l4ta_read,
2346 omap_badwidth_read16,
2347 };
2348
2349 static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
2350 omap_badwidth_write32,
2351 omap_badwidth_write32,
2352 omap_l4ta_write,
2353 };
2354
2355 #define L4TA(n) (n)
2356 #define L4TAO(n) ((n) + 39)
2357
2358 static struct omap_l4_region_s {
2359 target_phys_addr_t offset;
2360 size_t size;
2361 int access;
2362 } omap_l4_region[125] = {
2363 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
2364 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
2365 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
2366 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
2367 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
2368 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
2369 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
2370 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
2371 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
2372 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
2373 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
2374 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
2375 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
2376 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
2377 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
2378 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
2379 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
2380 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
2381 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
2382 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
2383 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
2384 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
2385 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
2386 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
2387 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
2388 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
2389 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
2390 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
2391 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
2392 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
2393 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
2394 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
2395 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
2396 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
2397 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
2398 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
2399 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
2400 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
2401 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
2402 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
2403 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
2404 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
2405 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
2406 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
2407 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
2408 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
2409 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
2410 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
2411 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
2412 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
2413 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
2414 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
2415 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
2416 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
2417 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
2418 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
2419 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
2420 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
2421 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
2422 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
2423 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
2424 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
2425 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
2426 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
2427 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
2428 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
2429 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
2430 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
2431 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
2432 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
2433 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
2434 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
2435 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
2436 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
2437 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
2438 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
2439 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
2440 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
2441 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
2442 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
2443 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
2444 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
2445 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
2446 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
2447 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
2448 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
2449 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
2450 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
2451 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
2452 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
2453 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
2454 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
2455 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
2456 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
2457 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
2458 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
2459 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
2460 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
2461 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
2462 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
2463 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
2464 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
2465 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
2466 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
2467 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
2468 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
2469 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
2470 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
2471 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
2472 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
2473 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
2474 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
2475 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
2476 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
2477 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
2478 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
2479 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
2480 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
2481 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
2482 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
2483 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
2484 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
2485 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
2486 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
2487 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
2488 };
2489
2490 static struct omap_l4_agent_info_s {
2491 int ta;
2492 int region;
2493 int regions;
2494 int ta_region;
2495 } omap_l4_agent_info[54] = {
2496 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
2497 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
2498 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
2499 { L4TAO(3), 7, 3, 2 }, /* PRCM */
2500 { L4TA(1), 10, 2, 1 }, /* BCM */
2501 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
2502 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
2503 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
2504 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
2505 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
2506 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
2507 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
2508 { L4TA(12), 38, 2, 1 }, /* sDMA */
2509 { L4TA(13), 40, 5, 4 }, /* SSI */
2510 { L4TAO(4), 45, 2, 1 }, /* USB */
2511 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
2512 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
2513 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
2514 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
2515 { L4TA(18), 55, 2, 1 }, /* XTI */
2516 { L4TA(19), 57, 2, 1 }, /* UART1 */
2517 { L4TA(20), 59, 2, 1 }, /* UART2 */
2518 { L4TA(21), 61, 2, 1 }, /* UART3 */
2519 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
2520 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
2521 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
2522 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
2523 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
2524 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
2525 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
2526 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
2527 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
2528 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
2529 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
2530 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
2531 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
2532 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
2533 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
2534 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
2535 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
2536 { L4TA(32), 97, 2, 1 }, /* EAC */
2537 { L4TA(33), 99, 2, 1 }, /* FAC */
2538 { L4TA(34), 101, 2, 1 }, /* IPC */
2539 { L4TA(35), 103, 2, 1 }, /* SPI1 */
2540 { L4TA(36), 105, 2, 1 }, /* SPI2 */
2541 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
2542 { L4TAO(10), 109, 2, 1 },
2543 { L4TAO(11), 111, 2, 1 }, /* RNG */
2544 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
2545 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
2546 { L4TA(37), 117, 2, 1 }, /* AES */
2547 { L4TA(38), 119, 2, 1 }, /* PKA */
2548 { -1, 121, 2, 1 },
2549 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
2550 };
2551
2552 #define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
2553 #define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
2554
2555 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
2556 {
2557 int i, iomemtype;
2558 struct omap_target_agent_s *ta = NULL;
2559 struct omap_l4_agent_info_s *info = NULL;
2560
2561 for (i = 0; i < bus->ta_num; i ++)
2562 if (omap_l4_agent_info[i].ta == cs) {
2563 ta = &bus->ta[i];
2564 info = &omap_l4_agent_info[i];
2565 break;
2566 }
2567 if (!ta) {
2568 fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
2569 exit(-1);
2570 }
2571
2572 ta->bus = bus;
2573 ta->start = &omap_l4_region[info->region];
2574 ta->regions = info->regions;
2575
2576 ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2577 ta->status = 0x00000000;
2578 ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
2579
2580 iomemtype = l4_register_io_memory(omap_l4ta_readfn,
2581 omap_l4ta_writefn, ta);
2582 ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
2583
2584 return ta;
2585 }
2586
2587 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
2588 int iotype)
2589 {
2590 target_phys_addr_t base;
2591 ssize_t size;
2592 #ifdef L4_MUX_HACK
2593 int i;
2594 #endif
2595
2596 if (region < 0 || region >= ta->regions) {
2597 fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
2598 exit(-1);
2599 }
2600
2601 base = ta->bus->base + ta->start[region].offset;
2602 size = ta->start[region].size;
2603 if (iotype) {
2604 #ifndef L4_MUX_HACK
2605 cpu_register_physical_memory(base, size, iotype);
2606 #else
2607 cpu_register_physical_memory(base, size, omap_cpu_io_entry);
2608 i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
2609 for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
2610 omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
2611 omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
2612 omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
2613 omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
2614 omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
2615 omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
2616 omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
2617 }
2618 #endif
2619 }
2620
2621 return base;
2622 }
2623
2624 /* TEST-Chip-level TAP */
2625 static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
2626 {
2627 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2628
2629 switch (addr) {
2630 case 0x204: /* IDCODE_reg */
2631 switch (s->mpu_model) {
2632 case omap2420:
2633 case omap2422:
2634 case omap2423:
2635 return 0x5b5d902f; /* ES 2.2 */
2636 case omap2430:
2637 return 0x5b68a02f; /* ES 2.2 */
2638 case omap3430:
2639 return 0x1b7ae02f; /* ES 2 */
2640 default:
2641 hw_error("%s: Bad mpu model\n", __FUNCTION__);
2642 }
2643
2644 case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
2645 case 0x210: /* PRODUCTION_ID_reg for OMAP3 */
2646 switch (s->mpu_model) {
2647 case omap2420:
2648 return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */
2649 case omap2422:
2650 return 0x000400f0;
2651 case omap2423:
2652 return 0x000800f0;
2653 case omap2430:
2654 return 0x000000f0;
2655 case omap3430:
2656 return 0x000000f0;
2657 default:
2658 hw_error("%s: Bad mpu model\n", __FUNCTION__);
2659 }
2660
2661 case 0x20c:
2662 switch (s->mpu_model) {
2663 case omap2420:
2664 case omap2422:
2665 case omap2423:
2666 return 0xcafeb5d9; /* ES 2.2 */
2667 case omap2430:
2668 return 0xcafeb68a; /* ES 2.2 */
2669 case omap3430:
2670 return 0xcafeb7ae; /* ES 2 */
2671 default:
2672 hw_error("%s: Bad mpu model\n", __FUNCTION__);
2673 }
2674
2675 case 0x218: /* DIE_ID_reg */
2676 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2677 case 0x21c: /* DIE_ID_reg */
2678 return 0x54 << 24;
2679 case 0x220: /* DIE_ID_reg */
2680 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2681 case 0x224: /* DIE_ID_reg */
2682 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2683 }
2684
2685 OMAP_BAD_REG(addr);
2686 return 0;
2687 }
2688
2689 static void omap_tap_write(void *opaque, target_phys_addr_t addr,
2690 uint32_t value)
2691 {
2692 OMAP_BAD_REG(addr);
2693 }
2694
2695 static CPUReadMemoryFunc * const omap_tap_readfn[] = {
2696 omap_badwidth_read32,
2697 omap_badwidth_read32,
2698 omap_tap_read,
2699 };
2700
2701 static CPUWriteMemoryFunc * const omap_tap_writefn[] = {
2702 omap_badwidth_write32,
2703 omap_badwidth_write32,
2704 omap_tap_write,
2705 };
2706
2707 void omap_tap_init(struct omap_target_agent_s *ta,
2708 struct omap_mpu_state_s *mpu)
2709 {
2710 omap_l4_attach(ta, 0, l4_register_io_memory(
2711 omap_tap_readfn, omap_tap_writefn, mpu));
2712 }
2713
2714 /* Power, Reset, and Clock Management */
2715 struct omap_prcm_s {
2716 qemu_irq irq[3];
2717 struct omap_mpu_state_s *mpu;
2718
2719 uint32_t irqst[3];
2720 uint32_t irqen[3];
2721
2722 uint32_t sysconfig;
2723 uint32_t voltctrl;
2724 uint32_t scratch[20];
2725
2726 uint32_t clksrc[1];
2727 uint32_t clkout[1];
2728 uint32_t clkemul[1];
2729 uint32_t clkpol[1];
2730 uint32_t clksel[8];
2731 uint32_t clken[12];
2732 uint32_t clkctrl[4];
2733 uint32_t clkidle[7];
2734 uint32_t setuptime[2];
2735
2736 uint32_t wkup[3];
2737 uint32_t wken[3];
2738 uint32_t wkst[3];
2739 uint32_t rst[4];
2740 uint32_t rstctrl[1];
2741 uint32_t power[4];
2742 uint32_t rsttime_wkup;
2743
2744 uint32_t ev;
2745 uint32_t evtime[2];
2746
2747 int dpll_lock, apll_lock[2];
2748 };
2749
2750 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
2751 {
2752 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
2753 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
2754 }
2755
2756 static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
2757 {
2758 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
2759 uint32_t ret;
2760
2761 switch (addr) {
2762 case 0x000: /* PRCM_REVISION */
2763 return 0x10;
2764
2765 case 0x010: /* PRCM_SYSCONFIG */
2766 return s->sysconfig;
2767
2768 case 0x018: /* PRCM_IRQSTATUS_MPU */
2769 return s->irqst[0];
2770
2771 case 0x01c: /* PRCM_IRQENABLE_MPU */
2772 return s->irqen[0];
2773
2774 case 0x050: /* PRCM_VOLTCTRL */
2775 return s->voltctrl;
2776 case 0x054: /* PRCM_VOLTST */
2777 return s->voltctrl & 3;
2778
2779 case 0x060: /* PRCM_CLKSRC_CTRL */
2780 return s->clksrc[0];
2781 case 0x070: /* PRCM_CLKOUT_CTRL */
2782 return s->clkout[0];
2783 case 0x078: /* PRCM_CLKEMUL_CTRL */
2784 return s->clkemul[0];
2785 case 0x080: /* PRCM_CLKCFG_CTRL */
2786 case 0x084: /* PRCM_CLKCFG_STATUS */
2787 return 0;
2788
2789 case 0x090: /* PRCM_VOLTSETUP */
2790 return s->setuptime[0];
2791
2792 case 0x094: /* PRCM_CLKSSETUP */
2793 return s->setuptime[1];
2794
2795 case 0x098: /* PRCM_POLCTRL */
2796 return s->clkpol[0];
2797
2798 case 0x0b0: /* GENERAL_PURPOSE1 */
2799 case 0x0b4: /* GENERAL_PURPOSE2 */
2800 case 0x0b8: /* GENERAL_PURPOSE3 */
2801 case 0x0bc: /* GENERAL_PURPOSE4 */
2802 case 0x0c0: /* GENERAL_PURPOSE5 */
2803 case 0x0c4: /* GENERAL_PURPOSE6 */
2804 case 0x0c8: /* GENERAL_PURPOSE7 */
2805 case 0x0cc: /* GENERAL_PURPOSE8 */
2806 case 0x0d0: /* GENERAL_PURPOSE9 */
2807 case 0x0d4: /* GENERAL_PURPOSE10 */
2808 case 0x0d8: /* GENERAL_PURPOSE11 */
2809 case 0x0dc: /* GENERAL_PURPOSE12 */
2810 case 0x0e0: /* GENERAL_PURPOSE13 */
2811 case 0x0e4: /* GENERAL_PURPOSE14 */
2812 case 0x0e8: /* GENERAL_PURPOSE15 */
2813 case 0x0ec: /* GENERAL_PURPOSE16 */
2814 case 0x0f0: /* GENERAL_PURPOSE17 */
2815 case 0x0f4: /* GENERAL_PURPOSE18 */
2816 case 0x0f8: /* GENERAL_PURPOSE19 */
2817 case 0x0fc: /* GENERAL_PURPOSE20 */
2818 return s->scratch[(addr - 0xb0) >> 2];
2819
2820 case 0x140: /* CM_CLKSEL_MPU */
2821 return s->clksel[0];
2822 case 0x148: /* CM_CLKSTCTRL_MPU */
2823 return s->clkctrl[0];
2824
2825 case 0x158: /* RM_RSTST_MPU */
2826 return s->rst[0];
2827 case 0x1c8: /* PM_WKDEP_MPU */
2828 return s->wkup[0];
2829 case 0x1d4: /* PM_EVGENCTRL_MPU */
2830 return s->ev;
2831 case 0x1d8: /* PM_EVEGENONTIM_MPU */
2832 return s->evtime[0];
2833 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
2834 return s->evtime[1];
2835 case 0x1e0: /* PM_PWSTCTRL_MPU */
2836 return s->power[0];
2837 case 0x1e4: /* PM_PWSTST_MPU */
2838 return 0;
2839
2840 case 0x200: /* CM_FCLKEN1_CORE */
2841 return s->clken[0];
2842 case 0x204: /* CM_FCLKEN2_CORE */
2843 return s->clken[1];
2844 case 0x210: /* CM_ICLKEN1_CORE */
2845 return s->clken[2];
2846 case 0x214: /* CM_ICLKEN2_CORE */
2847 return s->clken[3];
2848 case 0x21c: /* CM_ICLKEN4_CORE */
2849 return s->clken[4];
2850
2851 case 0x220: /* CM_IDLEST1_CORE */
2852 /* TODO: check the actual iclk status */
2853 return 0x7ffffff9;
2854 case 0x224: /* CM_IDLEST2_CORE */
2855 /* TODO: check the actual iclk status */
2856 return 0x00000007;
2857 case 0x22c: /* CM_IDLEST4_CORE */
2858 /* TODO: check the actual iclk status */
2859 return 0x0000001f;
2860
2861 case 0x230: /* CM_AUTOIDLE1_CORE */
2862 return s->clkidle[0];
2863 case 0x234: /* CM_AUTOIDLE2_CORE */
2864 return s->clkidle[1];
2865 case 0x238: /* CM_AUTOIDLE3_CORE */
2866 return s->clkidle[2];
2867 case 0x23c: /* CM_AUTOIDLE4_CORE */
2868 return s->clkidle[3];
2869
2870 case 0x240: /* CM_CLKSEL1_CORE */
2871 return s->clksel[1];
2872 case 0x244: /* CM_CLKSEL2_CORE */
2873 return s->clksel[2];
2874
2875 case 0x248: /* CM_CLKSTCTRL_CORE */
2876 return s->clkctrl[1];
2877
2878 case 0x2a0: /* PM_WKEN1_CORE */
2879 return s->wken[0];
2880 case 0x2a4: /* PM_WKEN2_CORE */
2881 return s->wken[1];
2882
2883 case 0x2b0: /* PM_WKST1_CORE */
2884 return s->wkst[0];
2885 case 0x2b4: /* PM_WKST2_CORE */
2886 return s->wkst[1];
2887 case 0x2c8: /* PM_WKDEP_CORE */
2888 return 0x1e;
2889
2890 case 0x2e0: /* PM_PWSTCTRL_CORE */
2891 return s->power[1];
2892 case 0x2e4: /* PM_PWSTST_CORE */
2893 return 0x000030 | (s->power[1] & 0xfc00);
2894
2895 case 0x300: /* CM_FCLKEN_GFX */
2896 return s->clken[5];
2897 case 0x310: /* CM_ICLKEN_GFX */
2898 return s->clken[6];
2899 case 0x320: /* CM_IDLEST_GFX */
2900 /* TODO: check the actual iclk status */
2901 return 0x00000001;
2902 case 0x340: /* CM_CLKSEL_GFX */
2903 return s->clksel[3];
2904 case 0x348: /* CM_CLKSTCTRL_GFX */
2905 return s->clkctrl[2];
2906 case 0x350: /* RM_RSTCTRL_GFX */
2907 return s->rstctrl[0];
2908 case 0x358: /* RM_RSTST_GFX */
2909 return s->rst[1];
2910 case 0x3c8: /* PM_WKDEP_GFX */
2911 return s->wkup[1];
2912
2913 case 0x3e0: /* PM_PWSTCTRL_GFX */
2914 return s->power[2];
2915 case 0x3e4: /* PM_PWSTST_GFX */
2916 return s->power[2] & 3;
2917
2918 case 0x400: /* CM_FCLKEN_WKUP */
2919 return s->clken[7];
2920 case 0x410: /* CM_ICLKEN_WKUP */
2921 return s->clken[8];
2922 case 0x420: /* CM_IDLEST_WKUP */
2923 /* TODO: check the actual iclk status */
2924 return 0x0000003f;
2925 case 0x430: /* CM_AUTOIDLE_WKUP */
2926 return s->clkidle[4];
2927 case 0x440: /* CM_CLKSEL_WKUP */
2928 return s->clksel[4];
2929 case 0x450: /* RM_RSTCTRL_WKUP */
2930 return 0;
2931 case 0x454: /* RM_RSTTIME_WKUP */
2932 return s->rsttime_wkup;
2933 case 0x458: /* RM_RSTST_WKUP */
2934 return s->rst[2];
2935 case 0x4a0: /* PM_WKEN_WKUP */
2936 return s->wken[2];
2937 case 0x4b0: /* PM_WKST_WKUP */
2938 return s->wkst[2];
2939
2940 case 0x500: /* CM_CLKEN_PLL */
2941 return s->clken[9];
2942 case 0x520: /* CM_IDLEST_CKGEN */
2943 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
2944 if (!(s->clksel[6] & 3))
2945 /* Core uses 32-kHz clock */
2946 ret |= 3 << 0;
2947 else if (!s->dpll_lock)
2948 /* DPLL not locked, core uses ref_clk */
2949 ret |= 1 << 0;
2950 else
2951 /* Core uses DPLL */
2952 ret |= 2 << 0;
2953 return ret;
2954 case 0x530: /* CM_AUTOIDLE_PLL */
2955 return s->clkidle[5];
2956 case 0x540: /* CM_CLKSEL1_PLL */
2957 return s->clksel[5];
2958 case 0x544: /* CM_CLKSEL2_PLL */
2959 return s->clksel[6];
2960
2961 case 0x800: /* CM_FCLKEN_DSP */
2962 return s->clken[10];
2963 case 0x810: /* CM_ICLKEN_DSP */
2964 return s->clken[11];
2965 case 0x820: /* CM_IDLEST_DSP */
2966 /* TODO: check the actual iclk status */
2967 return 0x00000103;
2968 case 0x830: /* CM_AUTOIDLE_DSP */
2969 return s->clkidle[6];
2970 case 0x840: /* CM_CLKSEL_DSP */
2971 return s->clksel[7];
2972 case 0x848: /* CM_CLKSTCTRL_DSP */
2973 return s->clkctrl[3];
2974 case 0x850: /* RM_RSTCTRL_DSP */
2975 return 0;
2976 case 0x858: /* RM_RSTST_DSP */
2977 return s->rst[3];
2978 case 0x8c8: /* PM_WKDEP_DSP */
2979 return s->wkup[2];
2980 case 0x8e0: /* PM_PWSTCTRL_DSP */
2981 return s->power[3];
2982 case 0x8e4: /* PM_PWSTST_DSP */
2983 return 0x008030 | (s->power[3] & 0x3003);
2984
2985 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
2986 return s->irqst[1];
2987 case 0x8f4: /* PRCM_IRQENABLE_DSP */
2988 return s->irqen[1];
2989
2990 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
2991 return s->irqst[2];
2992 case 0x8fc: /* PRCM_IRQENABLE_IVA */
2993 return s->irqen[2];
2994 }
2995
2996 OMAP_BAD_REG(addr);
2997 return 0;
2998 }
2999
3000 static void omap_prcm_apll_update(struct omap_prcm_s *s)
3001 {
3002 int mode[2];
3003
3004 mode[0] = (s->clken[9] >> 6) & 3;
3005 s->apll_lock[0] = (mode[0] == 3);
3006 mode[1] = (s->clken[9] >> 2) & 3;
3007 s->apll_lock[1] = (mode[1] == 3);
3008 /* TODO: update clocks */
3009
3010 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
3011 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
3012 __FUNCTION__);
3013 }
3014
3015 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
3016 {
3017 omap_clk dpll = omap_findclk(s->mpu, "dpll");
3018 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
3019 omap_clk core = omap_findclk(s->mpu, "core_clk");
3020 int mode = (s->clken[9] >> 0) & 3;
3021 int mult, div;
3022
3023 mult = (s->clksel[5] >> 12) & 0x3ff;
3024 div = (s->clksel[5] >> 8) & 0xf;
3025 if (mult == 0 || mult == 1)
3026 mode = 1; /* Bypass */
3027
3028 s->dpll_lock = 0;
3029 switch (mode) {
3030 case 0:
3031 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
3032 break;
3033 case 1: /* Low-power bypass mode (Default) */
3034 case 2: /* Fast-relock bypass mode */
3035 omap_clk_setrate(dpll, 1, 1);
3036 omap_clk_setrate(dpll_x2, 1, 1);
3037 break;
3038 case 3: /* Lock mode */
3039 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
3040
3041 omap_clk_setrate(dpll, div + 1, mult);
3042 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
3043 break;
3044 }
3045
3046 switch ((s->clksel[6] >> 0) & 3) {
3047 case 0:
3048 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
3049 break;
3050 case 1:
3051 omap_clk_reparent(core, dpll);
3052 break;
3053 case 2:
3054 /* Default */
3055 omap_clk_reparent(core, dpll_x2);
3056 break;
3057 case 3:
3058 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
3059 break;
3060 }
3061 }
3062
3063 static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
3064 uint32_t value)
3065 {
3066 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
3067
3068 switch (addr) {
3069 case 0x000: /* PRCM_REVISION */
3070 case 0x054: /* PRCM_VOLTST */
3071 case 0x084: /* PRCM_CLKCFG_STATUS */
3072 case 0x1e4: /* PM_PWSTST_MPU */
3073 case 0x220: /* CM_IDLEST1_CORE */
3074 case 0x224: /* CM_IDLEST2_CORE */
3075 case 0x22c: /* CM_IDLEST4_CORE */
3076 case 0x2c8: /* PM_WKDEP_CORE */
3077 case 0x2e4: /* PM_PWSTST_CORE */
3078 case 0x320: /* CM_IDLEST_GFX */
3079 case 0x3e4: /* PM_PWSTST_GFX */
3080 case 0x420: /* CM_IDLEST_WKUP */
3081 case 0x520: /* CM_IDLEST_CKGEN */
3082 case 0x820: /* CM_IDLEST_DSP */
3083 case 0x8e4: /* PM_PWSTST_DSP */
3084 OMAP_RO_REG(addr);
3085 return;
3086
3087 case 0x010: /* PRCM_SYSCONFIG */
3088 s->sysconfig = value & 1;
3089 break;
3090
3091 case 0x018: /* PRCM_IRQSTATUS_MPU */
3092 s->irqst[0] &= ~value;
3093 omap_prcm_int_update(s, 0);
3094 break;
3095 case 0x01c: /* PRCM_IRQENABLE_MPU */
3096 s->irqen[0] = value & 0x3f;
3097 omap_prcm_int_update(s, 0);
3098 break;
3099
3100 case 0x050: /* PRCM_VOLTCTRL */
3101 s->voltctrl = value & 0xf1c3;
3102 break;
3103
3104 case 0x060: /* PRCM_CLKSRC_CTRL */
3105 s->clksrc[0] = value & 0xdb;
3106 /* TODO update clocks */
3107 break;
3108
3109 case 0x070: /* PRCM_CLKOUT_CTRL */
3110 s->clkout[0] = value & 0xbbbb;
3111 /* TODO update clocks */
3112 break;
3113
3114 case 0x078: /* PRCM_CLKEMUL_CTRL */
3115 s->clkemul[0] = value & 1;
3116 /* TODO update clocks */
3117 break;
3118
3119 case 0x080: /* PRCM_CLKCFG_CTRL */
3120 break;
3121
3122 case 0x090: /* PRCM_VOLTSETUP */
3123 s->setuptime[0] = value & 0xffff;
3124 break;
3125 case 0x094: /* PRCM_CLKSSETUP */
3126 s->setuptime[1] = value & 0xffff;
3127 break;
3128
3129 case 0x098: /* PRCM_POLCTRL */
3130 s->clkpol[0] = value & 0x701;
3131 break;
3132
3133 case 0x0b0: /* GENERAL_PURPOSE1 */
3134 case 0x0b4: /* GENERAL_PURPOSE2 */
3135 case 0x0b8: /* GENERAL_PURPOSE3 */
3136 case 0x0bc: /* GENERAL_PURPOSE4 */
3137 case 0x0c0: /* GENERAL_PURPOSE5 */
3138 case 0x0c4: /* GENERAL_PURPOSE6 */
3139 case 0x0c8: /* GENERAL_PURPOSE7 */
3140 case 0x0cc: /* GENERAL_PURPOSE8 */
3141 case 0x0d0: /* GENERAL_PURPOSE9 */
3142 case 0x0d4: /* GENERAL_PURPOSE10 */
3143 case 0x0d8: /* GENERAL_PURPOSE11 */
3144 case 0x0dc: /* GENERAL_PURPOSE12 */
3145 case 0x0e0: /* GENERAL_PURPOSE13 */
3146 case 0x0e4: /* GENERAL_PURPOSE14 */
3147 case 0x0e8: /* GENERAL_PURPOSE15 */
3148 case 0x0ec: /* GENERAL_PURPOSE16 */
3149 case 0x0f0: /* GENERAL_PURPOSE17 */
3150 case 0x0f4: /* GENERAL_PURPOSE18 */
3151 case 0x0f8: /* GENERAL_PURPOSE19 */
3152 case 0x0fc: /* GENERAL_PURPOSE20 */
3153 s->scratch[(addr - 0xb0) >> 2] = value;
3154 break;
3155
3156 case 0x140: /* CM_CLKSEL_MPU */
3157 s->clksel[0] = value & 0x1f;
3158 /* TODO update clocks */
3159 break;
3160 case 0x148: /* CM_CLKSTCTRL_MPU */
3161 s->clkctrl[0] = value & 0x1f;
3162 break;
3163
3164 case 0x158: /* RM_RSTST_MPU */
3165 s->rst[0] &= ~value;
3166 break;
3167 case 0x1c8: /* PM_WKDEP_MPU */
3168 s->wkup[0] = value & 0x15;
3169 break;
3170
3171 case 0x1d4: /* PM_EVGENCTRL_MPU */
3172 s->ev = value & 0x1f;
3173 break;
3174 case 0x1d8: /* PM_EVEGENONTIM_MPU */
3175 s->evtime[0] = value;
3176 break;
3177 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
3178 s->evtime[1] = value;
3179 break;
3180
3181 case 0x1e0: /* PM_PWSTCTRL_MPU */
3182 s->power[0] = value & 0xc0f;
3183 break;
3184
3185 case 0x200: /* CM_FCLKEN1_CORE */
3186 s->clken[0] = value & 0xbfffffff;
3187 /* TODO update clocks */
3188 /* The EN_EAC bit only gets/puts func_96m_clk. */
3189 break;
3190 case 0x204: /* CM_FCLKEN2_CORE */
3191 s->clken[1] = value & 0x00000007;
3192 /* TODO update clocks */
3193 break;
3194 case 0x210: /* CM_ICLKEN1_CORE */
3195 s->clken[2] = value & 0xfffffff9;
3196 /* TODO update clocks */
3197 /* The EN_EAC bit only gets/puts core_l4_iclk. */
3198 break;
3199 case 0x214: /* CM_ICLKEN2_CORE */
3200 s->clken[3] = value & 0x00000007;
3201 /* TODO update clocks */
3202 break;
3203 case 0x21c: /* CM_ICLKEN4_CORE */
3204 s->clken[4] = value & 0x0000001f;
3205 /* TODO update clocks */
3206 break;
3207
3208 case 0x230: /* CM_AUTOIDLE1_CORE */
3209 s->clkidle[0] = value & 0xfffffff9;
3210 /* TODO update clocks */
3211 break;
3212 case 0x234: /* CM_AUTOIDLE2_CORE */
3213 s->clkidle[1] = value & 0x00000007;
3214 /* TODO update clocks */
3215 break;
3216 case 0x238: /* CM_AUTOIDLE3_CORE */
3217 s->clkidle[2] = value & 0x00000007;
3218 /* TODO update clocks */
3219 break;
3220 case 0x23c: /* CM_AUTOIDLE4_CORE */
3221 s->clkidle[3] = value & 0x0000001f;
3222 /* TODO update clocks */
3223 break;
3224
3225 case 0x240: /* CM_CLKSEL1_CORE */
3226 s->clksel[1] = value & 0x0fffbf7f;
3227 /* TODO update clocks */
3228 break;
3229
3230 case 0x244: /* CM_CLKSEL2_CORE */
3231 s->clksel[2] = value & 0x00fffffc;
3232 /* TODO update clocks */
3233 break;
3234
3235 case 0x248: /* CM_CLKSTCTRL_CORE */
3236 s->clkctrl[1] = value & 0x7;
3237 break;
3238
3239 case 0x2a0: /* PM_WKEN1_CORE */
3240 s->wken[0] = value & 0x04667ff8;
3241 break;
3242 case 0x2a4: /* PM_WKEN2_CORE */
3243 s->wken[1] = value & 0x00000005;
3244 break;
3245
3246 case 0x2b0: /* PM_WKST1_CORE */
3247 s->wkst[0] &= ~value;
3248 break;
3249 case 0x2b4: /* PM_WKST2_CORE */
3250 s->wkst[1] &= ~value;
3251 break;
3252
3253 case 0x2e0: /* PM_PWSTCTRL_CORE */
3254 s->power[1] = (value & 0x00fc3f) | (1 << 2);
3255 break;
3256
3257 case 0x300: /* CM_FCLKEN_GFX */
3258 s->clken[5] = value & 6;
3259 /* TODO update clocks */
3260 break;
3261 case 0x310: /* CM_ICLKEN_GFX */
3262 s->clken[6] = value & 1;
3263 /* TODO update clocks */
3264 break;
3265 case 0x340: /* CM_CLKSEL_GFX */
3266 s->clksel[3] = value & 7;
3267 /* TODO update clocks */
3268 break;
3269 case 0x348: /* CM_CLKSTCTRL_GFX */
3270 s->clkctrl[2] = value & 1;
3271 break;
3272 case 0x350: /* RM_RSTCTRL_GFX */
3273 s->rstctrl[0] = value & 1;
3274 /* TODO: reset */
3275 break;
3276 case 0x358: /* RM_RSTST_GFX */
3277 s->rst[1] &= ~value;
3278 break;
3279 case 0x3c8: /* PM_WKDEP_GFX */
3280 s->wkup[1] = value & 0x13;
3281 break;
3282 case 0x3e0: /* PM_PWSTCTRL_GFX */
3283 s->power[2] = (value & 0x00c0f) | (3 << 2);
3284 break;
3285
3286 case 0x400: /* CM_FCLKEN_WKUP */
3287 s->clken[7] = value & 0xd;
3288 /* TODO update clocks */
3289 break;
3290 case 0x410: /* CM_ICLKEN_WKUP */
3291 s->clken[8] = value & 0x3f;
3292 /* TODO update clocks */
3293 break;
3294 case 0x430: /* CM_AUTOIDLE_WKUP */
3295 s->clkidle[4] = value & 0x0000003f;
3296 /* TODO update clocks */
3297 break;
3298 case 0x440: /* CM_CLKSEL_WKUP */
3299 s->clksel[4] = value & 3;
3300 /* TODO update clocks */
3301 break;
3302 case 0x450: /* RM_RSTCTRL_WKUP */
3303 /* TODO: reset */
3304 if (value & 2)
3305 qemu_system_reset_request();
3306 break;
3307 case 0x454: /* RM_RSTTIME_WKUP */
3308 s->rsttime_wkup = value & 0x1fff;
3309 break;
3310 case 0x458: /* RM_RSTST_WKUP */
3311 s->rst[2] &= ~value;
3312 break;
3313 case 0x4a0: /* PM_WKEN_WKUP */
3314 s->wken[2] = value & 0x00000005;
3315 break;
3316 case 0x4b0: /* PM_WKST_WKUP */
3317 s->wkst[2] &= ~value;
3318 break;
3319
3320 case 0x500: /* CM_CLKEN_PLL */
3321 if (value & 0xffffff30)
3322 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
3323 "future compatiblity\n", __FUNCTION__);
3324 if ((s->clken[9] ^ value) & 0xcc) {
3325 s->clken[9] &= ~0xcc;
3326 s->clken[9] |= value & 0xcc;
3327 omap_prcm_apll_update(s);
3328 }
3329 if ((s->clken[9] ^ value) & 3) {
3330 s->clken[9] &= ~3;
3331 s->clken[9] |= value & 3;
3332 omap_prcm_dpll_update(s);
3333 }
3334 break;
3335 case 0x530: /* CM_AUTOIDLE_PLL */
3336 s->clkidle[5] = value & 0x000000cf;
3337 /* TODO update clocks */
3338 break;
3339 case 0x540: /* CM_CLKSEL1_PLL */
3340 if (value & 0xfc4000d7)
3341 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
3342 "future compatiblity\n", __FUNCTION__);
3343 if ((s->clksel[5] ^ value) & 0x003fff00) {
3344 s->clksel[5] = value & 0x03bfff28;
3345 omap_prcm_dpll_update(s);
3346 }
3347 /* TODO update the other clocks */
3348
3349 s->clksel[5] = value & 0x03bfff28;
3350 break;
3351 case 0x544: /* CM_CLKSEL2_PLL */
3352 if (value & ~3)
3353 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
3354 "future compatiblity\n", __FUNCTION__);
3355 if (s->clksel[6] != (value & 3)) {
3356 s->clksel[6] = value & 3;
3357 omap_prcm_dpll_update(s);
3358 }
3359 break;
3360
3361 case 0x800: /* CM_FCLKEN_DSP */
3362 s->clken[10] = value & 0x501;
3363 /* TODO update clocks */
3364 break;
3365 case 0x810: /* CM_ICLKEN_DSP */
3366 s->clken[11] = value & 0x2;
3367 /* TODO update clocks */
3368 break;
3369 case 0x830: /* CM_AUTOIDLE_DSP */
3370 s->clkidle[6] = value & 0x2;
3371 /* TODO update clocks */
3372 break;
3373 case 0x840: /* CM_CLKSEL_DSP */
3374 s->clksel[7] = value & 0x3fff;
3375 /* TODO update clocks */
3376 break;
3377 case 0x848: /* CM_CLKSTCTRL_DSP */
3378 s->clkctrl[3] = value & 0x101;
3379 break;
3380 case 0x850: /* RM_RSTCTRL_DSP */
3381 /* TODO: reset */
3382 break;
3383 case 0x858: /* RM_RSTST_DSP */
3384 s->rst[3] &= ~value;
3385 break;
3386 case 0x8c8: /* PM_WKDEP_DSP */
3387 s->wkup[2] = value & 0x13;
3388 break;
3389 case 0x8e0: /* PM_PWSTCTRL_DSP */
3390 s->power[3] = (value & 0x03017) | (3 << 2);
3391 break;
3392
3393 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
3394 s->irqst[1] &= ~value;
3395 omap_prcm_int_update(s, 1);
3396 break;
3397 case 0x8f4: /* PRCM_IRQENABLE_DSP */
3398 s->irqen[1] = value & 0x7;
3399 omap_prcm_int_update(s, 1);
3400 break;
3401
3402 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
3403 s->irqst[2] &= ~value;
3404 omap_prcm_int_update(s, 2);
3405 break;
3406 case 0x8fc: /* PRCM_IRQENABLE_IVA */
3407 s->irqen[2] = value & 0x7;
3408 omap_prcm_int_update(s, 2);
3409 break;
3410
3411 default:
3412 OMAP_BAD_REG(addr);
3413 return;
3414 }
3415 }
3416
3417 static CPUReadMemoryFunc * const omap_prcm_readfn[] = {
3418 omap_badwidth_read32,
3419 omap_badwidth_read32,
3420 omap_prcm_read,
3421 };
3422
3423 static CPUWriteMemoryFunc * const omap_prcm_writefn[] = {
3424 omap_badwidth_write32,
3425 omap_badwidth_write32,
3426 omap_prcm_write,
3427 };
3428
3429 static void omap_prcm_reset(struct omap_prcm_s *s)
3430 {
3431 s->sysconfig = 0;
3432 s->irqst[0] = 0;
3433 s->irqst[1] = 0;
3434 s->irqst[2] = 0;
3435 s->irqen[0] = 0;
3436 s->irqen[1] = 0;
3437 s->irqen[2] = 0;
3438 s->voltctrl = 0x1040;
3439 s->ev = 0x14;
3440 s->evtime[0] = 0;
3441 s->evtime[1] = 0;
3442 s->clkctrl[0] = 0;
3443 s->clkctrl[1] = 0;
3444 s->clkctrl[2] = 0;
3445 s->clkctrl[3] = 0;
3446 s->clken[1] = 7;
3447 s->clken[3] = 7;
3448 s->clken[4] = 0;
3449 s->clken[5] = 0;
3450 s->clken[6] = 0;
3451 s->clken[7] = 0xc;
3452 s->clken[8] = 0x3e;
3453 s->clken[9] = 0x0d;
3454 s->clken[10] = 0;
3455 s->clken[11] = 0;
3456 s->clkidle[0] = 0;
3457 s->clkidle[2] = 7;
3458 s->clkidle[3] = 0;
3459 s->clkidle[4] = 0;
3460 s->clkidle[5] = 0x0c;
3461 s->clkidle[6] = 0;
3462 s->clksel[0] = 0x01;
3463 s->clksel[1] = 0x02100121;
3464 s->clksel[2] = 0x00000000;
3465 s->clksel[3] = 0x01;
3466 s->clksel[4] = 0;
3467 s->clksel[7] = 0x0121;
3468 s->wkup[0] = 0x15;
3469 s->wkup[1] = 0x13;
3470 s->wkup[2] = 0x13;
3471 s->wken[0] = 0x04667ff8;
3472 s->wken[1] = 0x00000005;
3473 s->wken[2] = 5;
3474 s->wkst[0] = 0;
3475 s->wkst[1] = 0;
3476 s->wkst[2] = 0;
3477 s->power[0] = 0x00c;
3478 s->power[1] = 4;
3479 s->power[2] = 0x0000c;
3480 s->power[3] = 0x14;
3481 s->rstctrl[0] = 1;
3482 s->rst[3] = 1;
3483 omap_prcm_apll_update(s);
3484 omap_prcm_dpll_update(s);
3485 }
3486
3487 static void omap_prcm_coldreset(struct omap_prcm_s *s)
3488 {
3489 s->setuptime[0] = 0;
3490 s->setuptime[1] = 0;
3491 memset(&s->scratch, 0, sizeof(s->scratch));
3492 s->rst[0] = 0x01;
3493 s->rst[1] = 0x00;
3494 s->rst[2] = 0x01;
3495 s->clken[0] = 0;
3496 s->clken[2] = 0;
3497 s->clkidle[1] = 0;
3498 s->clksel[5] = 0;
3499 s->clksel[6] = 2;
3500 s->clksrc[0] = 0x43;
3501 s->clkout[0] = 0x0303;
3502 s->clkemul[0] = 0;
3503 s->clkpol[0] = 0x100;
3504 s->rsttime_wkup = 0x1002;
3505
3506 omap_prcm_reset(s);
3507 }
3508
3509 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
3510 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
3511 struct omap_mpu_state_s *mpu)
3512 {
3513 int iomemtype;
3514 struct omap_prcm_s *s = (struct omap_prcm_s *)
3515 qemu_mallocz(sizeof(struct omap_prcm_s));
3516
3517 s->irq[0] = mpu_int;
3518 s->irq[1] = dsp_int;
3519 s->irq[2] = iva_int;
3520 s->mpu = mpu;
3521 omap_prcm_coldreset(s);
3522
3523 iomemtype = l4_register_io_memory(omap_prcm_readfn,
3524 omap_prcm_writefn, s);
3525 omap_l4_attach(ta, 0, iomemtype);
3526 omap_l4_attach(ta, 1, iomemtype);
3527
3528 return s;
3529 }
3530
3531 /* System and Pinout control */
3532 struct omap_sysctl_s {
3533 struct omap_mpu_state_s *mpu;
3534
3535 uint32_t sysconfig;
3536 uint32_t devconfig;
3537 uint32_t psaconfig;
3538 uint32_t padconf[0x45];
3539 uint8_t obs;
3540 uint32_t msuspendmux[5];
3541 };
3542
3543 static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
3544 {
3545
3546 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3547 int pad_offset, byte_offset;
3548 int value;
3549
3550 switch (addr) {
3551 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3552 pad_offset = (addr - 0x30) >> 2;
3553 byte_offset = (addr - 0x30) & (4 - 1);
3554
3555 value = s->padconf[pad_offset];
3556 value = (value >> (byte_offset * 8)) & 0xff;
3557
3558 return value;
3559
3560 default:
3561 break;
3562 }
3563
3564 OMAP_BAD_REG(addr);
3565 return 0;
3566 }
3567
3568 static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
3569 {
3570 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3571
3572 switch (addr) {
3573 case 0x000: /* CONTROL_REVISION */
3574 return 0x20;
3575
3576 case 0x010: /* CONTROL_SYSCONFIG */
3577 return s->sysconfig;
3578
3579 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3580 return s->padconf[(addr - 0x30) >> 2];
3581
3582 case 0x270: /* CONTROL_DEBOBS */
3583 return s->obs;
3584
3585 case 0x274: /* CONTROL_DEVCONF */
3586 return s->devconfig;
3587
3588 case 0x28c: /* CONTROL_EMU_SUPPORT */
3589 return 0;
3590
3591 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
3592 return s->msuspendmux[0];
3593 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
3594 return s->msuspendmux[1];
3595 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
3596 return s->msuspendmux[2];
3597 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
3598 return s->msuspendmux[3];
3599 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
3600 return s->msuspendmux[4];
3601 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
3602 return 0;
3603
3604 case 0x2b8: /* CONTROL_PSA_CTRL */
3605 return s->psaconfig;
3606 case 0x2bc: /* CONTROL_PSA_CMD */
3607 case 0x2c0: /* CONTROL_PSA_VALUE */
3608 return 0;
3609
3610 case 0x2b0: /* CONTROL_SEC_CTRL */
3611 return 0x800000f1;
3612 case 0x2d0: /* CONTROL_SEC_EMU */
3613 return 0x80000015;
3614 case 0x2d4: /* CONTROL_SEC_TAP */
3615 return 0x8000007f;
3616 case 0x2b4: /* CONTROL_SEC_TEST */
3617 case 0x2f0: /* CONTROL_SEC_STATUS */
3618 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
3619 /* Secure mode is not present on general-pusrpose device. Outside
3620 * secure mode these values cannot be read or written. */
3621 return 0;
3622
3623 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
3624 return 0xff;
3625 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
3626 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
3627 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
3628 /* No secure mode so no Extended Secure RAM present. */
3629 return 0;
3630
3631 case 0x2f8: /* CONTROL_STATUS */
3632 /* Device Type => General-purpose */
3633 return 0x0300;
3634 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
3635
3636 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
3637 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
3638 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
3639 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
3640 return 0xdecafbad;
3641
3642 case 0x310: /* CONTROL_RAND_KEY_0 */
3643 case 0x314: /* CONTROL_RAND_KEY_1 */
3644 case 0x318: /* CONTROL_RAND_KEY_2 */
3645 case 0x31c: /* CONTROL_RAND_KEY_3 */
3646 case 0x320: /* CONTROL_CUST_KEY_0 */
3647 case 0x324: /* CONTROL_CUST_KEY_1 */
3648 case 0x330: /* CONTROL_TEST_KEY_0 */
3649 case 0x334: /* CONTROL_TEST_KEY_1 */
3650 case 0x338: /* CONTROL_TEST_KEY_2 */
3651 case 0x33c: /* CONTROL_TEST_KEY_3 */
3652 case 0x340: /* CONTROL_TEST_KEY_4 */
3653 case 0x344: /* CONTROL_TEST_KEY_5 */
3654 case 0x348: /* CONTROL_TEST_KEY_6 */
3655 case 0x34c: /* CONTROL_TEST_KEY_7 */
3656 case 0x350: /* CONTROL_TEST_KEY_8 */
3657 case 0x354: /* CONTROL_TEST_KEY_9 */
3658 /* Can only be accessed in secure mode and when C_FieldAccEnable
3659 * bit is set in CONTROL_SEC_CTRL.
3660 * TODO: otherwise an interconnect access error is generated. */
3661 return 0;
3662 }
3663
3664 OMAP_BAD_REG(addr);
3665 return 0;
3666 }
3667
3668 static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
3669 uint32_t value)
3670 {
3671 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3672 int pad_offset, byte_offset;
3673 int prev_value;
3674
3675 switch (addr) {
3676 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3677 pad_offset = (addr - 0x30) >> 2;
3678 byte_offset = (addr - 0x30) & (4 - 1);
3679
3680 prev_value = s->padconf[pad_offset];
3681 prev_value &= ~(0xff << (byte_offset * 8));
3682 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
3683 s->padconf[pad_offset] = prev_value;
3684 break;
3685
3686 default:
3687 OMAP_BAD_REG(addr);
3688 break;
3689 }
3690 }
3691
3692 static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
3693 uint32_t value)
3694 {
3695 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3696
3697 switch (addr) {
3698 case 0x000: /* CONTROL_REVISION */
3699 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
3700 case 0x2c0: /* CONTROL_PSA_VALUE */
3701 case 0x2f8: /* CONTROL_STATUS */
3702 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
3703 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
3704 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
3705 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
3706 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
3707 case 0x310: /* CONTROL_RAND_KEY_0 */
3708 case 0x314: /* CONTROL_RAND_KEY_1 */
3709 case 0x318: /* CONTROL_RAND_KEY_2 */
3710 case 0x31c: /* CONTROL_RAND_KEY_3 */
3711 case 0x320: /* CONTROL_CUST_KEY_0 */
3712 case 0x324: /* CONTROL_CUST_KEY_1 */
3713 case 0x330: /* CONTROL_TEST_KEY_0 */
3714 case 0x334: /* CONTROL_TEST_KEY_1 */
3715 case 0x338: /* CONTROL_TEST_KEY_2 */
3716 case 0x33c: /* CONTROL_TEST_KEY_3 */
3717 case 0x340: /* CONTROL_TEST_KEY_4 */
3718 case 0x344: /* CONTROL_TEST_KEY_5 */
3719 case 0x348: /* CONTROL_TEST_KEY_6 */
3720 case 0x34c: /* CONTROL_TEST_KEY_7 */
3721 case 0x350: /* CONTROL_TEST_KEY_8 */
3722 case 0x354: /* CONTROL_TEST_KEY_9 */
3723 OMAP_RO_REG(addr);
3724 return;
3725
3726 case 0x010: /* CONTROL_SYSCONFIG */
3727 s->sysconfig = value & 0x1e;
3728 break;
3729
3730 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3731 /* XXX: should check constant bits */
3732 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
3733 break;
3734
3735 case 0x270: /* CONTROL_DEBOBS */
3736 s->obs = value & 0xff;
3737 break;
3738
3739 case 0x274: /* CONTROL_DEVCONF */
3740 s->devconfig = value & 0xffffc7ff;
3741 break;
3742
3743 case 0x28c: /* CONTROL_EMU_SUPPORT */
3744 break;
3745
3746 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
3747 s->msuspendmux[0] = value & 0x3fffffff;
3748 break;
3749 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
3750 s->msuspendmux[1] = value & 0x3fffffff;
3751 break;
3752 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
3753 s->msuspendmux[2] = value & 0x3fffffff;
3754 break;
3755 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
3756 s->msuspendmux[3] = value & 0x3fffffff;
3757 break;
3758 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
3759 s->msuspendmux[4] = value & 0x3fffffff;
3760 break;
3761
3762 case 0x2b8: /* CONTROL_PSA_CTRL */
3763 s->psaconfig = value & 0x1c;
3764 s->psaconfig |= (value & 0x20) ? 2 : 1;
3765 break;
3766 case 0x2bc: /* CONTROL_PSA_CMD */
3767 break;
3768
3769 case 0x2b0: /* CONTROL_SEC_CTRL */
3770 case 0x2b4: /* CONTROL_SEC_TEST */
3771 case 0x2d0: /* CONTROL_SEC_EMU */
3772 case 0x2d4: /* CONTROL_SEC_TAP */
3773 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
3774 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
3775 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
3776 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
3777 case 0x2f0: /* CONTROL_SEC_STATUS */
3778 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
3779 break;
3780
3781 default:
3782 OMAP_BAD_REG(addr);
3783 return;
3784 }
3785 }
3786
3787 static CPUReadMemoryFunc * const omap_sysctl_readfn[] = {
3788 omap_sysctl_read8,
3789 omap_badwidth_read32, /* TODO */
3790 omap_sysctl_read,
3791 };
3792
3793 static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = {
3794 omap_sysctl_write8,
3795 omap_badwidth_write32, /* TODO */
3796 omap_sysctl_write,
3797 };
3798
3799 static void omap_sysctl_reset(struct omap_sysctl_s *s)
3800 {
3801 /* (power-on reset) */
3802 s->sysconfig = 0;
3803 s->obs = 0;
3804 s->devconfig = 0x0c000000;
3805 s->msuspendmux[0] = 0x00000000;
3806 s->msuspendmux[1] = 0x00000000;
3807 s->msuspendmux[2] = 0x00000000;
3808 s->msuspendmux[3] = 0x00000000;
3809 s->msuspendmux[4] = 0x00000000;
3810 s->psaconfig = 1;
3811
3812 s->padconf[0x00] = 0x000f0f0f;
3813 s->padconf[0x01] = 0x00000000;
3814 s->padconf[0x02] = 0x00000000;
3815 s->padconf[0x03] = 0x00000000;
3816 s->padconf[0x04] = 0x00000000;
3817 s->padconf[0x05] = 0x00000000;
3818 s->padconf[0x06] = 0x00000000;
3819 s->padconf[0x07] = 0x00000000;
3820 s->padconf[0x08] = 0x08080800;
3821 s->padconf[0x09] = 0x08080808;
3822 s->padconf[0x0a] = 0x08080808;
3823 s->padconf[0x0b] = 0x08080808;
3824 s->padconf[0x0c] = 0x08080808;
3825 s->padconf[0x0d] = 0x08080800;
3826 s->padconf[0x0e] = 0x08080808;
3827 s->padconf[0x0f] = 0x08080808;
3828 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
3829 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
3830 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
3831 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
3832 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
3833 s->padconf[0x15] = 0x18181818;
3834 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
3835 s->padconf[0x17] = 0x1f001f00;
3836 s->padconf[0x18] = 0x1f1f1f1f;
3837 s->padconf[0x19] = 0x00000000;
3838 s->padconf[0x1a] = 0x1f180000;
3839 s->padconf[0x1b] = 0x00001f1f;
3840 s->padconf[0x1c] = 0x1f001f00;
3841 s->padconf[0x1d] = 0x00000000;
3842 s->padconf[0x1e] = 0x00000000;
3843 s->padconf[0x1f] = 0x08000000;
3844 s->padconf[0x20] = 0x08080808;
3845 s->padconf[0x21] = 0x08080808;
3846 s->padconf[0x22] = 0x0f080808;
3847 s->padconf[0x23] = 0x0f0f0f0f;
3848 s->padconf[0x24] = 0x000f0f0f;
3849 s->padconf[0x25] = 0x1f1f1f0f;
3850 s->padconf[0x26] = 0x080f0f1f;
3851 s->padconf[0x27] = 0x070f1808;
3852 s->padconf[0x28] = 0x0f070707;
3853 s->padconf[0x29] = 0x000f0f1f;
3854 s->padconf[0x2a] = 0x0f0f0f1f;
3855 s->padconf[0x2b] = 0x08000000;
3856 s->padconf[0x2c] = 0x0000001f;
3857 s->padconf[0x2d] = 0x0f0f1f00;
3858 s->padconf[0x2e] = 0x1f1f0f0f;
3859 s->padconf[0x2f] = 0x0f1f1f1f;
3860 s->padconf[0x30] = 0x0f0f0f0f;
3861 s->padconf[0x31] = 0x0f1f0f1f;
3862 s->padconf[0x32] = 0x0f0f0f0f;
3863 s->padconf[0x33] = 0x0f1f0f1f;
3864 s->padconf[0x34] = 0x1f1f0f0f;
3865 s->padconf[0x35] = 0x0f0f1f1f;
3866 s->padconf[0x36] = 0x0f0f1f0f;
3867 s->padconf[0x37] = 0x0f0f0f0f;
3868 s->padconf[0x38] = 0x1f18180f;
3869 s->padconf[0x39] = 0x1f1f1f1f;
3870 s->padconf[0x3a] = 0x00001f1f;
3871 s->padconf[0x3b] = 0x00000000;
3872 s->padconf[0x3c] = 0x00000000;
3873 s->padconf[0x3d] = 0x0f0f0f0f;
3874 s->padconf[0x3e] = 0x18000f0f;
3875 s->padconf[0x3f] = 0x00070000;
3876 s->padconf[0x40] = 0x00000707;
3877 s->padconf[0x41] = 0x0f1f0700;
3878 s->padconf[0x42] = 0x1f1f070f;
3879 s->padconf[0x43] = 0x0008081f;
3880 s->padconf[0x44] = 0x00000800;
3881 }
3882
3883 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
3884 omap_clk iclk, struct omap_mpu_state_s *mpu)
3885 {
3886 int iomemtype;
3887 struct omap_sysctl_s *s = (struct omap_sysctl_s *)
3888 qemu_mallocz(sizeof(struct omap_sysctl_s));
3889
3890 s->mpu = mpu;
3891 omap_sysctl_reset(s);
3892
3893 iomemtype = l4_register_io_memory(omap_sysctl_readfn,
3894 omap_sysctl_writefn, s);
3895 omap_l4_attach(ta, 0, iomemtype);
3896
3897 return s;
3898 }
3899
3900 /* SDRAM Controller Subsystem */
3901 struct omap_sdrc_s {
3902 uint8_t config;
3903 };
3904
3905 static void omap_sdrc_reset(struct omap_sdrc_s *s)
3906 {
3907 s->config = 0x10;
3908 }
3909
3910 static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
3911 {
3912 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3913
3914 switch (addr) {
3915 case 0x00: /* SDRC_REVISION */
3916 return 0x20;
3917
3918 case 0x10: /* SDRC_SYSCONFIG */
3919 return s->config;
3920
3921 case 0x14: /* SDRC_SYSSTATUS */
3922 return 1; /* RESETDONE */
3923
3924 case 0x40: /* SDRC_CS_CFG */
3925 case 0x44: /* SDRC_SHARING */
3926 case 0x48: /* SDRC_ERR_ADDR */
3927 case 0x4c: /* SDRC_ERR_TYPE */
3928 case 0x60: /* SDRC_DLLA_SCTRL */
3929 case 0x64: /* SDRC_DLLA_STATUS */
3930 case 0x68: /* SDRC_DLLB_CTRL */
3931 case 0x6c: /* SDRC_DLLB_STATUS */
3932 case 0x70: /* SDRC_POWER */
3933 case 0x80: /* SDRC_MCFG_0 */
3934 case 0x84: /* SDRC_MR_0 */
3935 case 0x88: /* SDRC_EMR1_0 */
3936 case 0x8c: /* SDRC_EMR2_0 */
3937 case 0x90: /* SDRC_EMR3_0 */
3938 case 0x94: /* SDRC_DCDL1_CTRL */
3939 case 0x98: /* SDRC_DCDL2_CTRL */
3940 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
3941 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
3942 case 0xa4: /* SDRC_RFR_CTRL_0 */
3943 case 0xa8: /* SDRC_MANUAL_0 */
3944 case 0xb0: /* SDRC_MCFG_1 */
3945 case 0xb4: /* SDRC_MR_1 */
3946 case 0xb8: /* SDRC_EMR1_1 */
3947 case 0xbc: /* SDRC_EMR2_1 */
3948 case 0xc0: /* SDRC_EMR3_1 */
3949 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
3950 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
3951 case 0xd4: /* SDRC_RFR_CTRL_1 */
3952 case 0xd8: /* SDRC_MANUAL_1 */
3953 return 0x00;
3954 }
3955
3956 OMAP_BAD_REG(addr);
3957 return 0;
3958 }
3959
3960 static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
3961 uint32_t value)
3962 {
3963 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3964
3965 switch (addr) {
3966 case 0x00: /* SDRC_REVISION */
3967 case 0x14: /* SDRC_SYSSTATUS */
3968 case 0x48: /* SDRC_ERR_ADDR */
3969 case 0x64: /* SDRC_DLLA_STATUS */
3970 case 0x6c: /* SDRC_DLLB_STATUS */
3971 OMAP_RO_REG(addr);
3972 return;
3973
3974 case 0x10: /* SDRC_SYSCONFIG */
3975 if ((value >> 3) != 0x2)
3976 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
3977 __FUNCTION__, value >> 3);
3978 if (value & 2)
3979 omap_sdrc_reset(s);
3980 s->config = value & 0x18;
3981 break;
3982
3983 case 0x40: /* SDRC_CS_CFG */
3984 case 0x44: /* SDRC_SHARING */
3985 case 0x4c: /* SDRC_ERR_TYPE */
3986 case 0x60: /* SDRC_DLLA_SCTRL */
3987 case 0x68: /* SDRC_DLLB_CTRL */
3988 case 0x70: /* SDRC_POWER */
3989 case 0x80: /* SDRC_MCFG_0 */
3990 case 0x84: /* SDRC_MR_0 */
3991 case 0x88: /* SDRC_EMR1_0 */
3992 case 0x8c: /* SDRC_EMR2_0 */
3993 case 0x90: /* SDRC_EMR3_0 */
3994 case 0x94: /* SDRC_DCDL1_CTRL */
3995 case 0x98: /* SDRC_DCDL2_CTRL */
3996 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
3997 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
3998 case 0xa4: /* SDRC_RFR_CTRL_0 */
3999 case 0xa8: /* SDRC_MANUAL_0 */
4000 case 0xb0: /* SDRC_MCFG_1 */
4001 case 0xb4: /* SDRC_MR_1 */
4002 case 0xb8: /* SDRC_EMR1_1 */
4003 case 0xbc: /* SDRC_EMR2_1 */
4004 case 0xc0: /* SDRC_EMR3_1 */
4005 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
4006 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
4007 case 0xd4: /* SDRC_RFR_CTRL_1 */
4008 case 0xd8: /* SDRC_MANUAL_1 */
4009 break;
4010
4011 default:
4012 OMAP_BAD_REG(addr);
4013 return;
4014 }
4015 }
4016
4017 static CPUReadMemoryFunc * const omap_sdrc_readfn[] = {
4018 omap_badwidth_read32,
4019 omap_badwidth_read32,
4020 omap_sdrc_read,
4021 };
4022
4023 static CPUWriteMemoryFunc * const omap_sdrc_writefn[] = {
4024 omap_badwidth_write32,
4025 omap_badwidth_write32,
4026 omap_sdrc_write,
4027 };
4028
4029 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
4030 {
4031 int iomemtype;
4032 struct omap_sdrc_s *s = (struct omap_sdrc_s *)
4033 qemu_mallocz(sizeof(struct omap_sdrc_s));
4034
4035 omap_sdrc_reset(s);
4036
4037 iomemtype = cpu_register_io_memory(omap_sdrc_readfn,
4038 omap_sdrc_writefn, s);
4039 cpu_register_physical_memory(base, 0x1000, iomemtype);
4040
4041 return s;
4042 }
4043
4044 /* General-Purpose Memory Controller */
4045 struct omap_gpmc_s {
4046 qemu_irq irq;
4047
4048 uint8_t sysconfig;
4049 uint16_t irqst;
4050 uint16_t irqen;
4051 uint16_t timeout;
4052 uint16_t config;
4053 uint32_t prefconfig[2];
4054 int prefcontrol;
4055 int preffifo;
4056 int prefcount;
4057 struct omap_gpmc_cs_file_s {
4058 uint32_t config[7];
4059 target_phys_addr_t base;
4060 size_t size;
4061 int iomemtype;
4062 void (*base_update)(void *opaque, target_phys_addr_t new);
4063 void (*unmap)(void *opaque);
4064 void *opaque;
4065 } cs_file[8];
4066 int ecc_cs;
4067 int ecc_ptr;
4068 uint32_t ecc_cfg;
4069 ECCState ecc[9];
4070 };
4071
4072 static void omap_gpmc_int_update(struct omap_gpmc_s *s)
4073 {
4074 qemu_set_irq(s->irq, s->irqen & s->irqst);
4075 }
4076
4077 static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
4078 {
4079 /* TODO: check for overlapping regions and report access errors */
4080 if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) ||
4081 (base < 0 || base >= 0x40) ||
4082 (base & 0x0f & ~mask)) {
4083 fprintf(stderr, "%s: wrong cs address mapping/decoding!\n",
4084 __FUNCTION__);
4085 return;
4086 }
4087
4088 if (!f->opaque)
4089 return;
4090
4091 f->base = base << 24;
4092 f->size = (0x0fffffff & ~(mask << 24)) + 1;
4093 /* TODO: rather than setting the size of the mapping (which should be
4094 * constant), the mask should cause wrapping of the address space, so
4095 * that the same memory becomes accessible at every <i>size</i> bytes
4096 * starting from <i>base</i>. */
4097 if (f->iomemtype)
4098 cpu_register_physical_memory(f->base, f->size, f->iomemtype);
4099
4100 if (f->base_update)
4101 f->base_update(f->opaque, f->base);
4102 }
4103
4104 static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
4105 {
4106 if (f->size) {
4107 if (f->unmap)
4108 f->unmap(f->opaque);
4109 if (f->iomemtype)
4110 cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
4111 f->base = 0;
4112 f->size = 0;
4113 }
4114 }
4115
4116 static void omap_gpmc_reset(struct omap_gpmc_s *s)
4117 {
4118 int i;
4119
4120 s->sysconfig = 0;
4121 s->irqst = 0;
4122 s->irqen = 0;
4123 omap_gpmc_int_update(s);
4124 s->timeout = 0;
4125 s->config = 0xa00;
4126 s->prefconfig[0] = 0x00004000;
4127 s->prefconfig[1] = 0x00000000;
4128 s->prefcontrol = 0;
4129 s->preffifo = 0;
4130 s->prefcount = 0;
4131 for (i = 0; i < 8; i ++) {
4132 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
4133 omap_gpmc_cs_unmap(s->cs_file + i);
4134 s->cs_file[i].config[0] = i ? 1 << 12 : 0;
4135 s->cs_file[i].config[1] = 0x101001;
4136 s->cs_file[i].config[2] = 0x020201;
4137 s->cs_file[i].config[3] = 0x10031003;
4138 s->cs_file[i].config[4] = 0x10f1111;
4139 s->cs_file[i].config[5] = 0;
4140 s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
4141 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
4142 omap_gpmc_cs_map(&s->cs_file[i],
4143 s->cs_file[i].config[6] & 0x1f, /* MASKADDR */
4144 (s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */
4145 }
4146 omap_gpmc_cs_map(s->cs_file, 0, 0xf);
4147 s->ecc_cs = 0;
4148 s->ecc_ptr = 0;
4149 s->ecc_cfg = 0x3fcff000;
4150 for (i = 0; i < 9; i ++)
4151 ecc_reset(&s->ecc[i]);
4152 }
4153
4154 static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
4155 {
4156 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
4157 int cs;
4158 struct omap_gpmc_cs_file_s *f;
4159
4160 switch (addr) {
4161 case 0x000: /* GPMC_REVISION */
4162 return 0x20;
4163
4164 case 0x010: /* GPMC_SYSCONFIG */
4165 return s->sysconfig;
4166
4167 case 0x014: /* GPMC_SYSSTATUS */
4168 return 1; /* RESETDONE */
4169
4170 case 0x018: /* GPMC_IRQSTATUS */
4171 return s->irqst;
4172
4173 case 0x01c: /* GPMC_IRQENABLE */
4174 return s->irqen;
4175
4176 case 0x040: /* GPMC_TIMEOUT_CONTROL */
4177 return s->timeout;
4178
4179 case 0x044: /* GPMC_ERR_ADDRESS */
4180 case 0x048: /* GPMC_ERR_TYPE */
4181 return 0;
4182
4183 case 0x050: /* GPMC_CONFIG */
4184 return s->config;
4185
4186 case 0x054: /* GPMC_STATUS */
4187 return 0x001;
4188
4189 case 0x060 ... 0x1d4:
4190 cs = (addr - 0x060) / 0x30;
4191 addr -= cs * 0x30;
4192 f = s->cs_file + cs;
4193 switch (addr) {
4194 case 0x60: /* GPMC_CONFIG1 */
4195 return f->config[0];
4196 case 0x64: /* GPMC_CONFIG2 */
4197 return f->config[1];
4198 case 0x68: /* GPMC_CONFIG3 */
4199 return f->config[2];
4200 case 0x6c: /* GPMC_CONFIG4 */
4201 return f->config[3];
4202 case 0x70: /* GPMC_CONFIG5 */
4203 return f->config[4];
4204 case 0x74: /* GPMC_CONFIG6 */
4205 return f->config[5];
4206 case 0x78: /* GPMC_CONFIG7 */
4207 return f->config[6];
4208 case 0x84: /* GPMC_NAND_DATA */
4209 return 0;
4210 }
4211 break;
4212
4213 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
4214 return s->prefconfig[0];
4215 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
4216 return s->prefconfig[1];
4217 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
4218 return s->prefcontrol;
4219 case 0x1f0: /* GPMC_PREFETCH_STATUS */
4220 return (s->preffifo << 24) |
4221 ((s->preffifo >
4222 ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
4223 s->prefcount;
4224
4225 case 0x1f4: /* GPMC_ECC_CONFIG */
4226 return s->ecc_cs;
4227 case 0x1f8: /* GPMC_ECC_CONTROL */
4228 return s->ecc_ptr;
4229 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
4230 return s->ecc_cfg;
4231 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
4232 cs = (addr & 0x1f) >> 2;
4233 /* TODO: check correctness */
4234 return
4235 ((s->ecc[cs].cp & 0x07) << 0) |
4236 ((s->ecc[cs].cp & 0x38) << 13) |
4237 ((s->ecc[cs].lp[0] & 0x1ff) << 3) |
4238 ((s->ecc[cs].lp[1] & 0x1ff) << 19);
4239
4240 case 0x230: /* GPMC_TESTMODE_CTRL */
4241 return 0;
4242 case 0x234: /* GPMC_PSA_LSB */
4243 case 0x238: /* GPMC_PSA_MSB */
4244 return 0x00000000;
4245 }
4246
4247 OMAP_BAD_REG(addr);
4248 return 0;
4249 }
4250
4251 static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
4252 uint32_t value)
4253 {
4254 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
4255 int cs;
4256 struct omap_gpmc_cs_file_s *f;
4257
4258 switch (addr) {
4259 case 0x000: /* GPMC_REVISION */
4260 case 0x014: /* GPMC_SYSSTATUS */
4261 case 0x054: /* GPMC_STATUS */
4262 case 0x1f0: /* GPMC_PREFETCH_STATUS */
4263 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
4264 case 0x234: /* GPMC_PSA_LSB */
4265 case 0x238: /* GPMC_PSA_MSB */
4266 OMAP_RO_REG(addr);
4267 break;
4268
4269 case 0x010: /* GPMC_SYSCONFIG */
4270 if ((value >> 3) == 0x3)
4271 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
4272 __FUNCTION__, value >> 3);
4273 if (value & 2)
4274 omap_gpmc_reset(s);
4275 s->sysconfig = value & 0x19;
4276 break;
4277
4278 case 0x018: /* GPMC_IRQSTATUS */
4279 s->irqen = ~value;
4280 omap_gpmc_int_update(s);
4281 break;
4282
4283 case 0x01c: /* GPMC_IRQENABLE */
4284 s->irqen = value & 0xf03;
4285 omap_gpmc_int_update(s);
4286 break;
4287
4288 case 0x040: /* GPMC_TIMEOUT_CONTROL */
4289 s->timeout = value & 0x1ff1;
4290 break;
4291
4292 case 0x044: /* GPMC_ERR_ADDRESS */
4293 case 0x048: /* GPMC_ERR_TYPE */
4294 break;
4295
4296 case 0x050: /* GPMC_CONFIG */
4297 s->config = value & 0xf13;
4298 break;
4299
4300 case 0x060 ... 0x1d4:
4301 cs = (addr - 0x060) / 0x30;
4302 addr -= cs * 0x30;
4303 f = s->cs_file + cs;
4304 switch (addr) {
4305 case 0x60: /* GPMC_CONFIG1 */
4306 f->config[0] = value & 0xffef3e13;
4307 break;
4308 case 0x64: /* GPMC_CONFIG2 */
4309 f->config[1] = value & 0x001f1f8f;
4310 break;
4311 case 0x68: /* GPMC_CONFIG3 */
4312 f->config[2] = value & 0x001f1f8f;
4313 break;
4314 case 0x6c: /* GPMC_CONFIG4 */
4315 f->config[3] = value & 0x1f8f1f8f;
4316 break;
4317 case 0x70: /* GPMC_CONFIG5 */
4318 f->config[4] = value & 0x0f1f1f1f;
4319 break;
4320 case 0x74: /* GPMC_CONFIG6 */
4321 f->config[5] = value & 0x00000fcf;
4322 break;
4323 case 0x78: /* GPMC_CONFIG7 */
4324 if ((f->config[6] ^ value) & 0xf7f) {
4325 if (f->config[6] & (1 << 6)) /* CSVALID */
4326 omap_gpmc_cs_unmap(f);
4327 if (value & (1 << 6)) /* CSVALID */
4328 omap_gpmc_cs_map(f, value & 0x1f, /* MASKADDR */
4329 (value >> 8 & 0xf)); /* BASEADDR */
4330 }
4331 f->config[6] = value & 0x00000f7f;
4332 break;
4333 case 0x7c: /* GPMC_NAND_COMMAND */
4334 case 0x80: /* GPMC_NAND_ADDRESS */
4335 case 0x84: /* GPMC_NAND_DATA */
4336 break;
4337
4338 default:
4339 goto bad_reg;
4340 }
4341 break;
4342
4343 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
4344 s->prefconfig[0] = value & 0x7f8f7fbf;
4345 /* TODO: update interrupts, fifos, dmas */
4346 break;
4347
4348 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
4349 s->prefconfig[1] = value & 0x3fff;
4350 break;
4351
4352 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
4353 s->prefcontrol = value & 1;
4354 if (s->prefcontrol) {
4355 if (s->prefconfig[0] & 1)
4356 s->preffifo = 0x40;
4357 else
4358 s->preffifo = 0x00;
4359 }
4360 /* TODO: start */
4361 break;
4362
4363 case 0x1f4: /* GPMC_ECC_CONFIG */
4364 s->ecc_cs = 0x8f;
4365 break;
4366 case 0x1f8: /* GPMC_ECC_CONTROL */
4367 if (value & (1 << 8))
4368 for (cs = 0; cs < 9; cs ++)
4369 ecc_reset(&s->ecc[cs]);
4370 s->ecc_ptr = value & 0xf;
4371 if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
4372 s->ecc_ptr = 0;
4373 s->ecc_cs &= ~1;
4374 }
4375 break;
4376 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
4377 s->ecc_cfg = value & 0x3fcff1ff;
4378 break;
4379 case 0x230: /* GPMC_TESTMODE_CTRL */
4380 if (value & 7)
4381 fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
4382 break;
4383
4384 default:
4385 bad_reg:
4386 OMAP_BAD_REG(addr);
4387 return;
4388 }
4389 }
4390
4391 static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
4392 omap_badwidth_read32, /* TODO */
4393 omap_badwidth_read32, /* TODO */
4394 omap_gpmc_read,
4395 };
4396
4397 static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
4398 omap_badwidth_write32, /* TODO */
4399 omap_badwidth_write32, /* TODO */
4400 omap_gpmc_write,
4401 };
4402
4403 struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
4404 {
4405 int iomemtype;
4406 struct omap_gpmc_s *s = (struct omap_gpmc_s *)
4407 qemu_mallocz(sizeof(struct omap_gpmc_s));
4408
4409 omap_gpmc_reset(s);
4410
4411 iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
4412 omap_gpmc_writefn, s);
4413 cpu_register_physical_memory(base, 0x1000, iomemtype);
4414
4415 return s;
4416 }
4417
4418 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
4419 void (*base_upd)(void *opaque, target_phys_addr_t new),
4420 void (*unmap)(void *opaque), void *opaque)
4421 {
4422 struct omap_gpmc_cs_file_s *f;
4423
4424 if (cs < 0 || cs >= 8) {
4425 fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
4426 exit(-1);
4427 }
4428 f = &s->cs_file[cs];
4429
4430 f->iomemtype = iomemtype;
4431 f->base_update = base_upd;
4432 f->unmap = unmap;
4433 f->opaque = opaque;
4434
4435 if (f->config[6] & (1 << 6)) /* CSVALID */
4436 omap_gpmc_cs_map(f, f->config[6] & 0x1f, /* MASKADDR */
4437 (f->config[6] >> 8 & 0xf)); /* BASEADDR */
4438 }
4439
4440 /* General chip reset */
4441 static void omap2_mpu_reset(void *opaque)
4442 {
4443 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4444
4445 omap_inth_reset(mpu->ih[0]);
4446 omap_dma_reset(mpu->dma);
4447 omap_prcm_reset(mpu->prcm);
4448 omap_sysctl_reset(mpu->sysc);
4449 omap_gp_timer_reset(mpu->gptimer[0]);
4450 omap_gp_timer_reset(mpu->gptimer[1]);
4451 omap_gp_timer_reset(mpu->gptimer[2]);
4452 omap_gp_timer_reset(mpu->gptimer[3]);
4453 omap_gp_timer_reset(mpu->gptimer[4]);
4454 omap_gp_timer_reset(mpu->gptimer[5]);
4455 omap_gp_timer_reset(mpu->gptimer[6]);
4456 omap_gp_timer_reset(mpu->gptimer[7]);
4457 omap_gp_timer_reset(mpu->gptimer[8]);
4458 omap_gp_timer_reset(mpu->gptimer[9]);
4459 omap_gp_timer_reset(mpu->gptimer[10]);
4460 omap_gp_timer_reset(mpu->gptimer[11]);
4461 omap_synctimer_reset(&mpu->synctimer);
4462 omap_sdrc_reset(mpu->sdrc);
4463 omap_gpmc_reset(mpu->gpmc);
4464 omap_dss_reset(mpu->dss);
4465 omap_uart_reset(mpu->uart[0]);
4466 omap_uart_reset(mpu->uart[1]);
4467 omap_uart_reset(mpu->uart[2]);
4468 omap_mmc_reset(mpu->mmc);
4469 omap_gpif_reset(mpu->gpif);
4470 omap_mcspi_reset(mpu->mcspi[0]);
4471 omap_mcspi_reset(mpu->mcspi[1]);
4472 omap_i2c_reset(mpu->i2c[0]);
4473 omap_i2c_reset(mpu->i2c[1]);
4474 cpu_reset(mpu->env);
4475 }
4476
4477 static int omap2_validate_addr(struct omap_mpu_state_s *s,
4478 target_phys_addr_t addr)
4479 {
4480 return 1;
4481 }
4482
4483 static const struct dma_irq_map omap2_dma_irq_map[] = {
4484 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
4485 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
4486 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
4487 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
4488 };
4489
4490 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
4491 const char *core)
4492 {
4493 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4494 qemu_mallocz(sizeof(struct omap_mpu_state_s));
4495 ram_addr_t sram_base, q2_base;
4496 qemu_irq *cpu_irq;
4497 qemu_irq dma_irqs[4];
4498 omap_clk gpio_clks[4];
4499 DriveInfo *dinfo;
4500 int i;
4501
4502 /* Core */
4503 s->mpu_model = omap2420;
4504 s->env = cpu_init(core ?: "arm1136-r2");
4505 if (!s->env) {
4506 fprintf(stderr, "Unable to find CPU definition\n");
4507 exit(1);
4508 }
4509 s->sdram_size = sdram_size;
4510 s->sram_size = OMAP242X_SRAM_SIZE;
4511
4512 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4513
4514 /* Clocks */
4515 omap_clk_init(s);
4516
4517 /* Memory-mapped stuff */
4518 cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
4519 (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
4520 cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
4521 (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4522
4523 s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
4524
4525 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
4526 cpu_irq = arm_pic_init_cpu(s->env);
4527 s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
4528 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
4529 omap_findclk(s, "mpu_intc_fclk"),
4530 omap_findclk(s, "mpu_intc_iclk"));
4531
4532 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
4533 s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
4534
4535 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
4536 omap_findclk(s, "omapctrl_iclk"), s);
4537
4538 for (i = 0; i < 4; i ++)
4539 dma_irqs[i] =
4540 s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
4541 s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
4542 omap_findclk(s, "sdma_iclk"),
4543 omap_findclk(s, "sdma_fclk"));
4544 s->port->addr_valid = omap2_validate_addr;
4545
4546 /* Register SDRAM and SRAM ports for fast DMA transfers. */
4547 soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
4548 soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
4549
4550 s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
4551 s->irq[0][OMAP_INT_24XX_UART1_IRQ],
4552 omap_findclk(s, "uart1_fclk"),
4553 omap_findclk(s, "uart1_iclk"),
4554 s->drq[OMAP24XX_DMA_UART1_TX],
4555 s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
4556 s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
4557 s->irq[0][OMAP_INT_24XX_UART2_IRQ],
4558 omap_findclk(s, "uart2_fclk"),
4559 omap_findclk(s, "uart2_iclk"),
4560 s->drq[OMAP24XX_DMA_UART2_TX],
4561 s->drq[OMAP24XX_DMA_UART2_RX],
4562 serial_hds[0] ? serial_hds[1] : NULL);
4563 s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
4564 s->irq[0][OMAP_INT_24XX_UART3_IRQ],
4565 omap_findclk(s, "uart3_fclk"),
4566 omap_findclk(s, "uart3_iclk"),
4567 s->drq[OMAP24XX_DMA_UART3_TX],
4568 s->drq[OMAP24XX_DMA_UART3_RX],
4569 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
4570
4571 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
4572 s->irq[0][OMAP_INT_24XX_GPTIMER1],
4573 omap_findclk(s, "wu_gpt1_clk"),
4574 omap_findclk(s, "wu_l4_iclk"));
4575 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
4576 s->irq[0][OMAP_INT_24XX_GPTIMER2],
4577 omap_findclk(s, "core_gpt2_clk"),
4578 omap_findclk(s, "core_l4_iclk"));
4579 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
4580 s->irq[0][OMAP_INT_24XX_GPTIMER3],
4581 omap_findclk(s, "core_gpt3_clk"),
4582 omap_findclk(s, "core_l4_iclk"));
4583 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
4584 s->irq[0][OMAP_INT_24XX_GPTIMER4],
4585 omap_findclk(s, "core_gpt4_clk"),
4586 omap_findclk(s, "core_l4_iclk"));
4587 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
4588 s->irq[0][OMAP_INT_24XX_GPTIMER5],
4589 omap_findclk(s, "core_gpt5_clk"),
4590 omap_findclk(s, "core_l4_iclk"));
4591 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
4592 s->irq[0][OMAP_INT_24XX_GPTIMER6],
4593 omap_findclk(s, "core_gpt6_clk"),
4594 omap_findclk(s, "core_l4_iclk"));
4595 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
4596 s->irq[0][OMAP_INT_24XX_GPTIMER7],
4597 omap_findclk(s, "core_gpt7_clk"),
4598 omap_findclk(s, "core_l4_iclk"));
4599 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
4600 s->irq[0][OMAP_INT_24XX_GPTIMER8],
4601 omap_findclk(s, "core_gpt8_clk"),
4602 omap_findclk(s, "core_l4_iclk"));
4603 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
4604 s->irq[0][OMAP_INT_24XX_GPTIMER9],
4605 omap_findclk(s, "core_gpt9_clk"),
4606 omap_findclk(s, "core_l4_iclk"));
4607 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
4608 s->irq[0][OMAP_INT_24XX_GPTIMER10],
4609 omap_findclk(s, "core_gpt10_clk"),
4610 omap_findclk(s, "core_l4_iclk"));
4611 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
4612 s->irq[0][OMAP_INT_24XX_GPTIMER11],
4613 omap_findclk(s, "core_gpt11_clk"),
4614 omap_findclk(s, "core_l4_iclk"));
4615 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
4616 s->irq[0][OMAP_INT_24XX_GPTIMER12],
4617 omap_findclk(s, "core_gpt12_clk"),
4618 omap_findclk(s, "core_l4_iclk"));
4619
4620 omap_tap_init(omap_l4ta(s->l4, 2), s);
4621
4622 omap_synctimer_init(omap_l4tao(s->l4, 2), s,
4623 omap_findclk(s, "clk32-kHz"),
4624 omap_findclk(s, "core_l4_iclk"));
4625
4626 s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
4627 s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
4628 &s->drq[OMAP24XX_DMA_I2C1_TX],
4629 omap_findclk(s, "i2c1.fclk"),
4630 omap_findclk(s, "i2c1.iclk"));
4631 s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
4632 s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
4633 &s->drq[OMAP24XX_DMA_I2C2_TX],
4634 omap_findclk(s, "i2c2.fclk"),
4635 omap_findclk(s, "i2c2.iclk"));
4636
4637 gpio_clks[0] = omap_findclk(s, "gpio1_dbclk");
4638 gpio_clks[1] = omap_findclk(s, "gpio2_dbclk");
4639 gpio_clks[2] = omap_findclk(s, "gpio3_dbclk");
4640 gpio_clks[3] = omap_findclk(s, "gpio4_dbclk");
4641 s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
4642 &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
4643 gpio_clks, omap_findclk(s, "gpio_iclk"), 4);
4644
4645 s->sdrc = omap_sdrc_init(0x68009000);
4646 s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]);
4647
4648 dinfo = drive_get(IF_SD, 0, 0);
4649 if (!dinfo) {
4650 fprintf(stderr, "qemu: missing SecureDigital device\n");
4651 exit(1);
4652 }
4653 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
4654 s->irq[0][OMAP_INT_24XX_MMC_IRQ],
4655 &s->drq[OMAP24XX_DMA_MMC1_TX],
4656 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
4657
4658 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
4659 s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
4660 &s->drq[OMAP24XX_DMA_SPI1_TX0],
4661 omap_findclk(s, "spi1_fclk"),
4662 omap_findclk(s, "spi1_iclk"));
4663 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
4664 s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
4665 &s->drq[OMAP24XX_DMA_SPI2_TX0],
4666 omap_findclk(s, "spi2_fclk"),
4667 omap_findclk(s, "spi2_iclk"));
4668
4669 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
4670 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
4671 s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
4672 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
4673 omap_findclk(s, "dss_54m_clk"),
4674 omap_findclk(s, "dss_l3_iclk"),
4675 omap_findclk(s, "dss_l4_iclk"));
4676
4677 omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
4678 s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
4679 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
4680 serial_hds[3] : NULL);
4681
4682 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
4683 s->irq[0][OMAP_INT_24XX_EAC_IRQ],
4684 /* Ten consecutive lines */
4685 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
4686 omap_findclk(s, "func_96m_clk"),
4687 omap_findclk(s, "core_l4_iclk"));
4688
4689 /* All register mappings (includin those not currenlty implemented):
4690 * SystemControlMod 48000000 - 48000fff
4691 * SystemControlL4 48001000 - 48001fff
4692 * 32kHz Timer Mod 48004000 - 48004fff
4693 * 32kHz Timer L4 48005000 - 48005fff
4694 * PRCM ModA 48008000 - 480087ff
4695 * PRCM ModB 48008800 - 48008fff
4696 * PRCM L4 48009000 - 48009fff
4697 * TEST-BCM Mod 48012000 - 48012fff
4698 * TEST-BCM L4 48013000 - 48013fff
4699 * TEST-TAP Mod 48014000 - 48014fff
4700 * TEST-TAP L4 48015000 - 48015fff
4701 * GPIO1 Mod 48018000 - 48018fff
4702 * GPIO Top 48019000 - 48019fff
4703 * GPIO2 Mod 4801a000 - 4801afff
4704 * GPIO L4 4801b000 - 4801bfff
4705 * GPIO3 Mod 4801c000 - 4801cfff
4706 * GPIO4 Mod 4801e000 - 4801efff
4707 * WDTIMER1 Mod 48020000 - 48010fff
4708 * WDTIMER Top 48021000 - 48011fff
4709 * WDTIMER2 Mod 48022000 - 48012fff
4710 * WDTIMER L4 48023000 - 48013fff
4711 * WDTIMER3 Mod 48024000 - 48014fff
4712 * WDTIMER3 L4 48025000 - 48015fff
4713 * WDTIMER4 Mod 48026000 - 48016fff
4714 * WDTIMER4 L4 48027000 - 48017fff
4715 * GPTIMER1 Mod 48028000 - 48018fff
4716 * GPTIMER1 L4 48029000 - 48019fff
4717 * GPTIMER2 Mod 4802a000 - 4801afff
4718 * GPTIMER2 L4 4802b000 - 4801bfff
4719 * L4-Config AP 48040000 - 480407ff
4720 * L4-Config IP 48040800 - 48040fff
4721 * L4-Config LA 48041000 - 48041fff
4722 * ARM11ETB Mod 48048000 - 48049fff
4723 * ARM11ETB L4 4804a000 - 4804afff
4724 * DISPLAY Top 48050000 - 480503ff
4725 * DISPLAY DISPC 48050400 - 480507ff
4726 * DISPLAY RFBI 48050800 - 48050bff
4727 * DISPLAY VENC 48050c00 - 48050fff
4728 * DISPLAY L4 48051000 - 48051fff
4729 * CAMERA Top 48052000 - 480523ff
4730 * CAMERA core 48052400 - 480527ff
4731 * CAMERA DMA 48052800 - 48052bff
4732 * CAMERA MMU 48052c00 - 48052fff
4733 * CAMERA L4 48053000 - 48053fff
4734 * SDMA Mod 48056000 - 48056fff
4735 * SDMA L4 48057000 - 48057fff
4736 * SSI Top 48058000 - 48058fff
4737 * SSI GDD 48059000 - 48059fff
4738 * SSI Port1 4805a000 - 4805afff
4739 * SSI Port2 4805b000 - 4805bfff
4740 * SSI L4 4805c000 - 4805cfff
4741 * USB Mod 4805e000 - 480fefff
4742 * USB L4 4805f000 - 480fffff
4743 * WIN_TRACER1 Mod 48060000 - 48060fff
4744 * WIN_TRACER1 L4 48061000 - 48061fff
4745 * WIN_TRACER2 Mod 48062000 - 48062fff
4746 * WIN_TRACER2 L4 48063000 - 48063fff
4747 * WIN_TRACER3 Mod 48064000 - 48064fff
4748 * WIN_TRACER3 L4 48065000 - 48065fff
4749 * WIN_TRACER4 Top 48066000 - 480660ff
4750 * WIN_TRACER4 ETT 48066100 - 480661ff
4751 * WIN_TRACER4 WT 48066200 - 480662ff
4752 * WIN_TRACER4 L4 48067000 - 48067fff
4753 * XTI Mod 48068000 - 48068fff
4754 * XTI L4 48069000 - 48069fff
4755 * UART1 Mod 4806a000 - 4806afff
4756 * UART1 L4 4806b000 - 4806bfff
4757 * UART2 Mod 4806c000 - 4806cfff
4758 * UART2 L4 4806d000 - 4806dfff
4759 * UART3 Mod 4806e000 - 4806efff
4760 * UART3 L4 4806f000 - 4806ffff
4761 * I2C1 Mod 48070000 - 48070fff
4762 * I2C1 L4 48071000 - 48071fff
4763 * I2C2 Mod 48072000 - 48072fff
4764 * I2C2 L4 48073000 - 48073fff
4765 * McBSP1 Mod 48074000 - 48074fff
4766 * McBSP1 L4 48075000 - 48075fff
4767 * McBSP2 Mod 48076000 - 48076fff
4768 * McBSP2 L4 48077000 - 48077fff
4769 * GPTIMER3 Mod 48078000 - 48078fff
4770 * GPTIMER3 L4 48079000 - 48079fff
4771 * GPTIMER4 Mod 4807a000 - 4807afff
4772 * GPTIMER4 L4 4807b000 - 4807bfff
4773 * GPTIMER5 Mod 4807c000 - 4807cfff
4774 * GPTIMER5 L4 4807d000 - 4807dfff
4775 * GPTIMER6 Mod 4807e000 - 4807efff
4776 * GPTIMER6 L4 4807f000 - 4807ffff
4777 * GPTIMER7 Mod 48080000 - 48080fff
4778 * GPTIMER7 L4 48081000 - 48081fff
4779 * GPTIMER8 Mod 48082000 - 48082fff
4780 * GPTIMER8 L4 48083000 - 48083fff
4781 * GPTIMER9 Mod 48084000 - 48084fff
4782 * GPTIMER9 L4 48085000 - 48085fff
4783 * GPTIMER10 Mod 48086000 - 48086fff
4784 * GPTIMER10 L4 48087000 - 48087fff
4785 * GPTIMER11 Mod 48088000 - 48088fff
4786 * GPTIMER11 L4 48089000 - 48089fff
4787 * GPTIMER12 Mod 4808a000 - 4808afff
4788 * GPTIMER12 L4 4808b000 - 4808bfff
4789 * EAC Mod 48090000 - 48090fff
4790 * EAC L4 48091000 - 48091fff
4791 * FAC Mod 48092000 - 48092fff
4792 * FAC L4 48093000 - 48093fff
4793 * MAILBOX Mod 48094000 - 48094fff
4794 * MAILBOX L4 48095000 - 48095fff
4795 * SPI1 Mod 48098000 - 48098fff
4796 * SPI1 L4 48099000 - 48099fff
4797 * SPI2 Mod 4809a000 - 4809afff
4798 * SPI2 L4 4809b000 - 4809bfff
4799 * MMC/SDIO Mod 4809c000 - 4809cfff
4800 * MMC/SDIO L4 4809d000 - 4809dfff
4801 * MS_PRO Mod 4809e000 - 4809efff
4802 * MS_PRO L4 4809f000 - 4809ffff
4803 * RNG Mod 480a0000 - 480a0fff
4804 * RNG L4 480a1000 - 480a1fff
4805 * DES3DES Mod 480a2000 - 480a2fff
4806 * DES3DES L4 480a3000 - 480a3fff
4807 * SHA1MD5 Mod 480a4000 - 480a4fff
4808 * SHA1MD5 L4 480a5000 - 480a5fff
4809 * AES Mod 480a6000 - 480a6fff
4810 * AES L4 480a7000 - 480a7fff
4811 * PKA Mod 480a8000 - 480a9fff
4812 * PKA L4 480aa000 - 480aafff
4813 * MG Mod 480b0000 - 480b0fff
4814 * MG L4 480b1000 - 480b1fff
4815 * HDQ/1-wire Mod 480b2000 - 480b2fff
4816 * HDQ/1-wire L4 480b3000 - 480b3fff
4817 * MPU interrupt 480fe000 - 480fefff
4818 * STI channel base 54000000 - 5400ffff
4819 * IVA RAM 5c000000 - 5c01ffff
4820 * IVA ROM 5c020000 - 5c027fff
4821 * IMG_BUF_A 5c040000 - 5c040fff
4822 * IMG_BUF_B 5c042000 - 5c042fff
4823 * VLCDS 5c048000 - 5c0487ff
4824 * IMX_COEF 5c049000 - 5c04afff
4825 * IMX_CMD 5c051000 - 5c051fff
4826 * VLCDQ 5c053000 - 5c0533ff
4827 * VLCDH 5c054000 - 5c054fff
4828 * SEQ_CMD 5c055000 - 5c055fff
4829 * IMX_REG 5c056000 - 5c0560ff
4830 * VLCD_REG 5c056100 - 5c0561ff
4831 * SEQ_REG 5c056200 - 5c0562ff
4832 * IMG_BUF_REG 5c056300 - 5c0563ff
4833 * SEQIRQ_REG 5c056400 - 5c0564ff
4834 * OCP_REG 5c060000 - 5c060fff
4835 * SYSC_REG 5c070000 - 5c070fff
4836 * MMU_REG 5d000000 - 5d000fff
4837 * sDMA R 68000400 - 680005ff
4838 * sDMA W 68000600 - 680007ff
4839 * Display Control 68000800 - 680009ff
4840 * DSP subsystem 68000a00 - 68000bff
4841 * MPU subsystem 68000c00 - 68000dff
4842 * IVA subsystem 68001000 - 680011ff
4843 * USB 68001200 - 680013ff
4844 * Camera 68001400 - 680015ff
4845 * VLYNQ (firewall) 68001800 - 68001bff
4846 * VLYNQ 68001e00 - 68001fff
4847 * SSI 68002000 - 680021ff
4848 * L4 68002400 - 680025ff
4849 * DSP (firewall) 68002800 - 68002bff
4850 * DSP subsystem 68002e00 - 68002fff
4851 * IVA (firewall) 68003000 - 680033ff
4852 * IVA 68003600 - 680037ff
4853 * GFX 68003a00 - 68003bff
4854 * CMDWR emulation 68003c00 - 68003dff
4855 * SMS 68004000 - 680041ff
4856 * OCM 68004200 - 680043ff
4857 * GPMC 68004400 - 680045ff
4858 * RAM (firewall) 68005000 - 680053ff
4859 * RAM (err login) 68005400 - 680057ff
4860 * ROM (firewall) 68005800 - 68005bff
4861 * ROM (err login) 68005c00 - 68005fff
4862 * GPMC (firewall) 68006000 - 680063ff
4863 * GPMC (err login) 68006400 - 680067ff
4864 * SMS (err login) 68006c00 - 68006fff
4865 * SMS registers 68008000 - 68008fff
4866 * SDRC registers 68009000 - 68009fff
4867 * GPMC registers 6800a000 6800afff
4868 */
4869
4870 qemu_register_reset(omap2_mpu_reset, s);
4871
4872 return s;
4873 }
CRIS target port of Qemu