2 * QEMU PowerPC 405 embedded processors emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
26 #include "hw/ppc/ppc.h"
27 #include "hw/boards.h"
29 #include "hw/char/serial.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
33 #include "exec/address-spaces.h"
38 //#define DEBUG_SERIAL
43 //#define DEBUG_CLOCKS
44 //#define DEBUG_CLOCKS_LL
46 ram_addr_t
ppc405_set_bootinfo (CPUPPCState
*env
, ppc4xx_bd_info_t
*bd
,
49 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
53 /* We put the bd structure at the top of memory */
54 if (bd
->bi_memsize
>= 0x01000000UL
)
55 bdloc
= 0x01000000UL
- sizeof(struct ppc4xx_bd_info_t
);
57 bdloc
= bd
->bi_memsize
- sizeof(struct ppc4xx_bd_info_t
);
58 stl_be_phys(cs
->as
, bdloc
+ 0x00, bd
->bi_memstart
);
59 stl_be_phys(cs
->as
, bdloc
+ 0x04, bd
->bi_memsize
);
60 stl_be_phys(cs
->as
, bdloc
+ 0x08, bd
->bi_flashstart
);
61 stl_be_phys(cs
->as
, bdloc
+ 0x0C, bd
->bi_flashsize
);
62 stl_be_phys(cs
->as
, bdloc
+ 0x10, bd
->bi_flashoffset
);
63 stl_be_phys(cs
->as
, bdloc
+ 0x14, bd
->bi_sramstart
);
64 stl_be_phys(cs
->as
, bdloc
+ 0x18, bd
->bi_sramsize
);
65 stl_be_phys(cs
->as
, bdloc
+ 0x1C, bd
->bi_bootflags
);
66 stl_be_phys(cs
->as
, bdloc
+ 0x20, bd
->bi_ipaddr
);
67 for (i
= 0; i
< 6; i
++) {
68 stb_phys(cs
->as
, bdloc
+ 0x24 + i
, bd
->bi_enetaddr
[i
]);
70 stw_be_phys(cs
->as
, bdloc
+ 0x2A, bd
->bi_ethspeed
);
71 stl_be_phys(cs
->as
, bdloc
+ 0x2C, bd
->bi_intfreq
);
72 stl_be_phys(cs
->as
, bdloc
+ 0x30, bd
->bi_busfreq
);
73 stl_be_phys(cs
->as
, bdloc
+ 0x34, bd
->bi_baudrate
);
74 for (i
= 0; i
< 4; i
++) {
75 stb_phys(cs
->as
, bdloc
+ 0x38 + i
, bd
->bi_s_version
[i
]);
77 for (i
= 0; i
< 32; i
++) {
78 stb_phys(cs
->as
, bdloc
+ 0x3C + i
, bd
->bi_r_version
[i
]);
80 stl_be_phys(cs
->as
, bdloc
+ 0x5C, bd
->bi_plb_busfreq
);
81 stl_be_phys(cs
->as
, bdloc
+ 0x60, bd
->bi_pci_busfreq
);
82 for (i
= 0; i
< 6; i
++) {
83 stb_phys(cs
->as
, bdloc
+ 0x64 + i
, bd
->bi_pci_enetaddr
[i
]);
86 if (flags
& 0x00000001) {
87 for (i
= 0; i
< 6; i
++)
88 stb_phys(cs
->as
, bdloc
+ n
++, bd
->bi_pci_enetaddr2
[i
]);
90 stl_be_phys(cs
->as
, bdloc
+ n
, bd
->bi_opbfreq
);
92 for (i
= 0; i
< 2; i
++) {
93 stl_be_phys(cs
->as
, bdloc
+ n
, bd
->bi_iic_fast
[i
]);
100 /*****************************************************************************/
101 /* Shared peripherals */
103 /*****************************************************************************/
104 /* Peripheral local bus arbitrer */
111 typedef struct ppc4xx_plb_t ppc4xx_plb_t
;
112 struct ppc4xx_plb_t
{
118 static uint32_t dcr_read_plb (void *opaque
, int dcrn
)
135 /* Avoid gcc warning */
143 static void dcr_write_plb (void *opaque
, int dcrn
, uint32_t val
)
150 /* We don't care about the actual parameters written as
151 * we don't manage any priorities on the bus
153 plb
->acr
= val
& 0xF8000000;
165 static void ppc4xx_plb_reset (void *opaque
)
170 plb
->acr
= 0x00000000;
171 plb
->bear
= 0x00000000;
172 plb
->besr
= 0x00000000;
175 static void ppc4xx_plb_init(CPUPPCState
*env
)
179 plb
= g_malloc0(sizeof(ppc4xx_plb_t
));
180 ppc_dcr_register(env
, PLB0_ACR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
181 ppc_dcr_register(env
, PLB0_BEAR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
182 ppc_dcr_register(env
, PLB0_BESR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
183 qemu_register_reset(ppc4xx_plb_reset
, plb
);
186 /*****************************************************************************/
187 /* PLB to OPB bridge */
194 typedef struct ppc4xx_pob_t ppc4xx_pob_t
;
195 struct ppc4xx_pob_t
{
201 static uint32_t dcr_read_pob (void *opaque
, int dcrn
)
218 /* Avoid gcc warning */
226 static void dcr_write_pob (void *opaque
, int dcrn
, uint32_t val
)
246 static void ppc4xx_pob_reset (void *opaque
)
252 pob
->bear
= 0x00000000;
253 pob
->besr0
= 0x0000000;
254 pob
->besr1
= 0x0000000;
257 static void ppc4xx_pob_init(CPUPPCState
*env
)
261 pob
= g_malloc0(sizeof(ppc4xx_pob_t
));
262 ppc_dcr_register(env
, POB0_BEAR
, pob
, &dcr_read_pob
, &dcr_write_pob
);
263 ppc_dcr_register(env
, POB0_BESR0
, pob
, &dcr_read_pob
, &dcr_write_pob
);
264 ppc_dcr_register(env
, POB0_BESR1
, pob
, &dcr_read_pob
, &dcr_write_pob
);
265 qemu_register_reset(ppc4xx_pob_reset
, pob
);
268 /*****************************************************************************/
270 typedef struct ppc4xx_opba_t ppc4xx_opba_t
;
271 struct ppc4xx_opba_t
{
277 static uint32_t opba_readb (void *opaque
, hwaddr addr
)
283 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
301 static void opba_writeb (void *opaque
,
302 hwaddr addr
, uint32_t value
)
307 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
313 opba
->cr
= value
& 0xF8;
316 opba
->pr
= value
& 0xFF;
323 static uint32_t opba_readw (void *opaque
, hwaddr addr
)
328 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
330 ret
= opba_readb(opaque
, addr
) << 8;
331 ret
|= opba_readb(opaque
, addr
+ 1);
336 static void opba_writew (void *opaque
,
337 hwaddr addr
, uint32_t value
)
340 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
343 opba_writeb(opaque
, addr
, value
>> 8);
344 opba_writeb(opaque
, addr
+ 1, value
);
347 static uint32_t opba_readl (void *opaque
, hwaddr addr
)
352 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
354 ret
= opba_readb(opaque
, addr
) << 24;
355 ret
|= opba_readb(opaque
, addr
+ 1) << 16;
360 static void opba_writel (void *opaque
,
361 hwaddr addr
, uint32_t value
)
364 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
367 opba_writeb(opaque
, addr
, value
>> 24);
368 opba_writeb(opaque
, addr
+ 1, value
>> 16);
371 static const MemoryRegionOps opba_ops
= {
373 .read
= { opba_readb
, opba_readw
, opba_readl
, },
374 .write
= { opba_writeb
, opba_writew
, opba_writel
, },
376 .endianness
= DEVICE_NATIVE_ENDIAN
,
379 static void ppc4xx_opba_reset (void *opaque
)
384 opba
->cr
= 0x00; /* No dynamic priorities - park disabled */
388 static void ppc4xx_opba_init(hwaddr base
)
392 opba
= g_malloc0(sizeof(ppc4xx_opba_t
));
394 printf("%s: offset " TARGET_FMT_plx
"\n", __func__
, base
);
396 memory_region_init_io(&opba
->io
, NULL
, &opba_ops
, opba
, "opba", 0x002);
397 memory_region_add_subregion(get_system_memory(), base
, &opba
->io
);
398 qemu_register_reset(ppc4xx_opba_reset
, opba
);
401 /*****************************************************************************/
402 /* Code decompression controller */
405 /*****************************************************************************/
406 /* Peripheral controller */
407 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t
;
408 struct ppc4xx_ebc_t
{
419 EBC0_CFGADDR
= 0x012,
420 EBC0_CFGDATA
= 0x013,
423 static uint32_t dcr_read_ebc (void *opaque
, int dcrn
)
435 case 0x00: /* B0CR */
438 case 0x01: /* B1CR */
441 case 0x02: /* B2CR */
444 case 0x03: /* B3CR */
447 case 0x04: /* B4CR */
450 case 0x05: /* B5CR */
453 case 0x06: /* B6CR */
456 case 0x07: /* B7CR */
459 case 0x10: /* B0AP */
462 case 0x11: /* B1AP */
465 case 0x12: /* B2AP */
468 case 0x13: /* B3AP */
471 case 0x14: /* B4AP */
474 case 0x15: /* B5AP */
477 case 0x16: /* B6AP */
480 case 0x17: /* B7AP */
483 case 0x20: /* BEAR */
486 case 0x21: /* BESR0 */
489 case 0x22: /* BESR1 */
508 static void dcr_write_ebc (void *opaque
, int dcrn
, uint32_t val
)
519 case 0x00: /* B0CR */
521 case 0x01: /* B1CR */
523 case 0x02: /* B2CR */
525 case 0x03: /* B3CR */
527 case 0x04: /* B4CR */
529 case 0x05: /* B5CR */
531 case 0x06: /* B6CR */
533 case 0x07: /* B7CR */
535 case 0x10: /* B0AP */
537 case 0x11: /* B1AP */
539 case 0x12: /* B2AP */
541 case 0x13: /* B3AP */
543 case 0x14: /* B4AP */
545 case 0x15: /* B5AP */
547 case 0x16: /* B6AP */
549 case 0x17: /* B7AP */
551 case 0x20: /* BEAR */
553 case 0x21: /* BESR0 */
555 case 0x22: /* BESR1 */
568 static void ebc_reset (void *opaque
)
574 ebc
->addr
= 0x00000000;
575 ebc
->bap
[0] = 0x7F8FFE80;
576 ebc
->bcr
[0] = 0xFFE28000;
577 for (i
= 0; i
< 8; i
++) {
578 ebc
->bap
[i
] = 0x00000000;
579 ebc
->bcr
[i
] = 0x00000000;
581 ebc
->besr0
= 0x00000000;
582 ebc
->besr1
= 0x00000000;
583 ebc
->cfg
= 0x80400000;
586 static void ppc405_ebc_init(CPUPPCState
*env
)
590 ebc
= g_malloc0(sizeof(ppc4xx_ebc_t
));
591 qemu_register_reset(&ebc_reset
, ebc
);
592 ppc_dcr_register(env
, EBC0_CFGADDR
,
593 ebc
, &dcr_read_ebc
, &dcr_write_ebc
);
594 ppc_dcr_register(env
, EBC0_CFGDATA
,
595 ebc
, &dcr_read_ebc
, &dcr_write_ebc
);
598 /*****************************************************************************/
627 typedef struct ppc405_dma_t ppc405_dma_t
;
628 struct ppc405_dma_t
{
641 static uint32_t dcr_read_dma (void *opaque
, int dcrn
)
646 static void dcr_write_dma (void *opaque
, int dcrn
, uint32_t val
)
650 static void ppc405_dma_reset (void *opaque
)
656 for (i
= 0; i
< 4; i
++) {
657 dma
->cr
[i
] = 0x00000000;
658 dma
->ct
[i
] = 0x00000000;
659 dma
->da
[i
] = 0x00000000;
660 dma
->sa
[i
] = 0x00000000;
661 dma
->sg
[i
] = 0x00000000;
663 dma
->sr
= 0x00000000;
664 dma
->sgc
= 0x00000000;
665 dma
->slp
= 0x7C000000;
666 dma
->pol
= 0x00000000;
669 static void ppc405_dma_init(CPUPPCState
*env
, qemu_irq irqs
[4])
673 dma
= g_malloc0(sizeof(ppc405_dma_t
));
674 memcpy(dma
->irqs
, irqs
, 4 * sizeof(qemu_irq
));
675 qemu_register_reset(&ppc405_dma_reset
, dma
);
676 ppc_dcr_register(env
, DMA0_CR0
,
677 dma
, &dcr_read_dma
, &dcr_write_dma
);
678 ppc_dcr_register(env
, DMA0_CT0
,
679 dma
, &dcr_read_dma
, &dcr_write_dma
);
680 ppc_dcr_register(env
, DMA0_DA0
,
681 dma
, &dcr_read_dma
, &dcr_write_dma
);
682 ppc_dcr_register(env
, DMA0_SA0
,
683 dma
, &dcr_read_dma
, &dcr_write_dma
);
684 ppc_dcr_register(env
, DMA0_SG0
,
685 dma
, &dcr_read_dma
, &dcr_write_dma
);
686 ppc_dcr_register(env
, DMA0_CR1
,
687 dma
, &dcr_read_dma
, &dcr_write_dma
);
688 ppc_dcr_register(env
, DMA0_CT1
,
689 dma
, &dcr_read_dma
, &dcr_write_dma
);
690 ppc_dcr_register(env
, DMA0_DA1
,
691 dma
, &dcr_read_dma
, &dcr_write_dma
);
692 ppc_dcr_register(env
, DMA0_SA1
,
693 dma
, &dcr_read_dma
, &dcr_write_dma
);
694 ppc_dcr_register(env
, DMA0_SG1
,
695 dma
, &dcr_read_dma
, &dcr_write_dma
);
696 ppc_dcr_register(env
, DMA0_CR2
,
697 dma
, &dcr_read_dma
, &dcr_write_dma
);
698 ppc_dcr_register(env
, DMA0_CT2
,
699 dma
, &dcr_read_dma
, &dcr_write_dma
);
700 ppc_dcr_register(env
, DMA0_DA2
,
701 dma
, &dcr_read_dma
, &dcr_write_dma
);
702 ppc_dcr_register(env
, DMA0_SA2
,
703 dma
, &dcr_read_dma
, &dcr_write_dma
);
704 ppc_dcr_register(env
, DMA0_SG2
,
705 dma
, &dcr_read_dma
, &dcr_write_dma
);
706 ppc_dcr_register(env
, DMA0_CR3
,
707 dma
, &dcr_read_dma
, &dcr_write_dma
);
708 ppc_dcr_register(env
, DMA0_CT3
,
709 dma
, &dcr_read_dma
, &dcr_write_dma
);
710 ppc_dcr_register(env
, DMA0_DA3
,
711 dma
, &dcr_read_dma
, &dcr_write_dma
);
712 ppc_dcr_register(env
, DMA0_SA3
,
713 dma
, &dcr_read_dma
, &dcr_write_dma
);
714 ppc_dcr_register(env
, DMA0_SG3
,
715 dma
, &dcr_read_dma
, &dcr_write_dma
);
716 ppc_dcr_register(env
, DMA0_SR
,
717 dma
, &dcr_read_dma
, &dcr_write_dma
);
718 ppc_dcr_register(env
, DMA0_SGC
,
719 dma
, &dcr_read_dma
, &dcr_write_dma
);
720 ppc_dcr_register(env
, DMA0_SLP
,
721 dma
, &dcr_read_dma
, &dcr_write_dma
);
722 ppc_dcr_register(env
, DMA0_POL
,
723 dma
, &dcr_read_dma
, &dcr_write_dma
);
726 /*****************************************************************************/
728 typedef struct ppc405_gpio_t ppc405_gpio_t
;
729 struct ppc405_gpio_t
{
744 static uint32_t ppc405_gpio_readb (void *opaque
, hwaddr addr
)
747 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
753 static void ppc405_gpio_writeb (void *opaque
,
754 hwaddr addr
, uint32_t value
)
757 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
762 static uint32_t ppc405_gpio_readw (void *opaque
, hwaddr addr
)
765 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
771 static void ppc405_gpio_writew (void *opaque
,
772 hwaddr addr
, uint32_t value
)
775 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
780 static uint32_t ppc405_gpio_readl (void *opaque
, hwaddr addr
)
783 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
789 static void ppc405_gpio_writel (void *opaque
,
790 hwaddr addr
, uint32_t value
)
793 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
798 static const MemoryRegionOps ppc405_gpio_ops
= {
800 .read
= { ppc405_gpio_readb
, ppc405_gpio_readw
, ppc405_gpio_readl
, },
801 .write
= { ppc405_gpio_writeb
, ppc405_gpio_writew
, ppc405_gpio_writel
, },
803 .endianness
= DEVICE_NATIVE_ENDIAN
,
806 static void ppc405_gpio_reset (void *opaque
)
810 static void ppc405_gpio_init(hwaddr base
)
814 gpio
= g_malloc0(sizeof(ppc405_gpio_t
));
816 printf("%s: offset " TARGET_FMT_plx
"\n", __func__
, base
);
818 memory_region_init_io(&gpio
->io
, NULL
, &ppc405_gpio_ops
, gpio
, "pgio", 0x038);
819 memory_region_add_subregion(get_system_memory(), base
, &gpio
->io
);
820 qemu_register_reset(&ppc405_gpio_reset
, gpio
);
823 /*****************************************************************************/
827 OCM0_ISACNTL
= 0x019,
829 OCM0_DSACNTL
= 0x01B,
832 typedef struct ppc405_ocm_t ppc405_ocm_t
;
833 struct ppc405_ocm_t
{
835 MemoryRegion isarc_ram
;
836 MemoryRegion dsarc_ram
;
843 static void ocm_update_mappings (ppc405_ocm_t
*ocm
,
844 uint32_t isarc
, uint32_t isacntl
,
845 uint32_t dsarc
, uint32_t dsacntl
)
848 printf("OCM update ISA %08" PRIx32
" %08" PRIx32
" (%08" PRIx32
849 " %08" PRIx32
") DSA %08" PRIx32
" %08" PRIx32
850 " (%08" PRIx32
" %08" PRIx32
")\n",
851 isarc
, isacntl
, dsarc
, dsacntl
,
852 ocm
->isarc
, ocm
->isacntl
, ocm
->dsarc
, ocm
->dsacntl
);
854 if (ocm
->isarc
!= isarc
||
855 (ocm
->isacntl
& 0x80000000) != (isacntl
& 0x80000000)) {
856 if (ocm
->isacntl
& 0x80000000) {
857 /* Unmap previously assigned memory region */
858 printf("OCM unmap ISA %08" PRIx32
"\n", ocm
->isarc
);
859 memory_region_del_subregion(get_system_memory(), &ocm
->isarc_ram
);
861 if (isacntl
& 0x80000000) {
862 /* Map new instruction memory region */
864 printf("OCM map ISA %08" PRIx32
"\n", isarc
);
866 memory_region_add_subregion(get_system_memory(), isarc
,
870 if (ocm
->dsarc
!= dsarc
||
871 (ocm
->dsacntl
& 0x80000000) != (dsacntl
& 0x80000000)) {
872 if (ocm
->dsacntl
& 0x80000000) {
873 /* Beware not to unmap the region we just mapped */
874 if (!(isacntl
& 0x80000000) || ocm
->dsarc
!= isarc
) {
875 /* Unmap previously assigned memory region */
877 printf("OCM unmap DSA %08" PRIx32
"\n", ocm
->dsarc
);
879 memory_region_del_subregion(get_system_memory(),
883 if (dsacntl
& 0x80000000) {
884 /* Beware not to remap the region we just mapped */
885 if (!(isacntl
& 0x80000000) || dsarc
!= isarc
) {
886 /* Map new data memory region */
888 printf("OCM map DSA %08" PRIx32
"\n", dsarc
);
890 memory_region_add_subregion(get_system_memory(), dsarc
,
897 static uint32_t dcr_read_ocm (void *opaque
, int dcrn
)
924 static void dcr_write_ocm (void *opaque
, int dcrn
, uint32_t val
)
927 uint32_t isarc
, dsarc
, isacntl
, dsacntl
;
932 isacntl
= ocm
->isacntl
;
933 dsacntl
= ocm
->dsacntl
;
936 isarc
= val
& 0xFC000000;
939 isacntl
= val
& 0xC0000000;
942 isarc
= val
& 0xFC000000;
945 isacntl
= val
& 0xC0000000;
948 ocm_update_mappings(ocm
, isarc
, isacntl
, dsarc
, dsacntl
);
951 ocm
->isacntl
= isacntl
;
952 ocm
->dsacntl
= dsacntl
;
955 static void ocm_reset (void *opaque
)
958 uint32_t isarc
, dsarc
, isacntl
, dsacntl
;
962 isacntl
= 0x00000000;
964 dsacntl
= 0x00000000;
965 ocm_update_mappings(ocm
, isarc
, isacntl
, dsarc
, dsacntl
);
968 ocm
->isacntl
= isacntl
;
969 ocm
->dsacntl
= dsacntl
;
972 static void ppc405_ocm_init(CPUPPCState
*env
)
976 ocm
= g_malloc0(sizeof(ppc405_ocm_t
));
977 /* XXX: Size is 4096 or 0x04000000 */
978 memory_region_init_ram(&ocm
->isarc_ram
, NULL
, "ppc405.ocm", 4096,
980 vmstate_register_ram_global(&ocm
->isarc_ram
);
981 memory_region_init_alias(&ocm
->dsarc_ram
, NULL
, "ppc405.dsarc", &ocm
->isarc_ram
,
983 qemu_register_reset(&ocm_reset
, ocm
);
984 ppc_dcr_register(env
, OCM0_ISARC
,
985 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
986 ppc_dcr_register(env
, OCM0_ISACNTL
,
987 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
988 ppc_dcr_register(env
, OCM0_DSARC
,
989 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
990 ppc_dcr_register(env
, OCM0_DSACNTL
,
991 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
994 /*****************************************************************************/
996 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t
;
997 struct ppc4xx_i2c_t
{
1017 static uint32_t ppc4xx_i2c_readb (void *opaque
, hwaddr addr
)
1023 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1028 // i2c_readbyte(&i2c->mdata);
1068 ret
= i2c
->xtcntlss
;
1071 ret
= i2c
->directcntl
;
1078 printf("%s: addr " TARGET_FMT_plx
" %02" PRIx32
"\n", __func__
, addr
, ret
);
1084 static void ppc4xx_i2c_writeb (void *opaque
,
1085 hwaddr addr
, uint32_t value
)
1090 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1097 // i2c_sendbyte(&i2c->mdata);
1112 i2c
->mdcntl
= value
& 0xDF;
1115 i2c
->sts
&= ~(value
& 0x0A);
1118 i2c
->extsts
&= ~(value
& 0x8F);
1127 i2c
->clkdiv
= value
;
1130 i2c
->intrmsk
= value
;
1133 i2c
->xfrcnt
= value
& 0x77;
1136 i2c
->xtcntlss
= value
;
1139 i2c
->directcntl
= value
& 0x7;
1144 static uint32_t ppc4xx_i2c_readw (void *opaque
, hwaddr addr
)
1149 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1151 ret
= ppc4xx_i2c_readb(opaque
, addr
) << 8;
1152 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 1);
1157 static void ppc4xx_i2c_writew (void *opaque
,
1158 hwaddr addr
, uint32_t value
)
1161 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1164 ppc4xx_i2c_writeb(opaque
, addr
, value
>> 8);
1165 ppc4xx_i2c_writeb(opaque
, addr
+ 1, value
);
1168 static uint32_t ppc4xx_i2c_readl (void *opaque
, hwaddr addr
)
1173 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1175 ret
= ppc4xx_i2c_readb(opaque
, addr
) << 24;
1176 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 1) << 16;
1177 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 2) << 8;
1178 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 3);
1183 static void ppc4xx_i2c_writel (void *opaque
,
1184 hwaddr addr
, uint32_t value
)
1187 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1190 ppc4xx_i2c_writeb(opaque
, addr
, value
>> 24);
1191 ppc4xx_i2c_writeb(opaque
, addr
+ 1, value
>> 16);
1192 ppc4xx_i2c_writeb(opaque
, addr
+ 2, value
>> 8);
1193 ppc4xx_i2c_writeb(opaque
, addr
+ 3, value
);
1196 static const MemoryRegionOps i2c_ops
= {
1198 .read
= { ppc4xx_i2c_readb
, ppc4xx_i2c_readw
, ppc4xx_i2c_readl
, },
1199 .write
= { ppc4xx_i2c_writeb
, ppc4xx_i2c_writew
, ppc4xx_i2c_writel
, },
1201 .endianness
= DEVICE_NATIVE_ENDIAN
,
1204 static void ppc4xx_i2c_reset (void *opaque
)
1217 i2c
->directcntl
= 0x0F;
1220 static void ppc405_i2c_init(hwaddr base
, qemu_irq irq
)
1224 i2c
= g_malloc0(sizeof(ppc4xx_i2c_t
));
1227 printf("%s: offset " TARGET_FMT_plx
"\n", __func__
, base
);
1229 memory_region_init_io(&i2c
->iomem
, NULL
, &i2c_ops
, i2c
, "i2c", 0x011);
1230 memory_region_add_subregion(get_system_memory(), base
, &i2c
->iomem
);
1231 qemu_register_reset(ppc4xx_i2c_reset
, i2c
);
1234 /*****************************************************************************/
1235 /* General purpose timers */
1236 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t
;
1237 struct ppc4xx_gpt_t
{
1252 static uint32_t ppc4xx_gpt_readb (void *opaque
, hwaddr addr
)
1255 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1257 /* XXX: generate a bus fault */
1261 static void ppc4xx_gpt_writeb (void *opaque
,
1262 hwaddr addr
, uint32_t value
)
1265 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1268 /* XXX: generate a bus fault */
1271 static uint32_t ppc4xx_gpt_readw (void *opaque
, hwaddr addr
)
1274 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1276 /* XXX: generate a bus fault */
1280 static void ppc4xx_gpt_writew (void *opaque
,
1281 hwaddr addr
, uint32_t value
)
1284 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1287 /* XXX: generate a bus fault */
1290 static int ppc4xx_gpt_compare (ppc4xx_gpt_t
*gpt
, int n
)
1296 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t
*gpt
, int n
, int level
)
1301 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t
*gpt
)
1307 for (i
= 0; i
< 5; i
++) {
1308 if (gpt
->oe
& mask
) {
1309 /* Output is enabled */
1310 if (ppc4xx_gpt_compare(gpt
, i
)) {
1311 /* Comparison is OK */
1312 ppc4xx_gpt_set_output(gpt
, i
, gpt
->ol
& mask
);
1314 /* Comparison is KO */
1315 ppc4xx_gpt_set_output(gpt
, i
, gpt
->ol
& mask
? 0 : 1);
1322 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t
*gpt
)
1328 for (i
= 0; i
< 5; i
++) {
1329 if (gpt
->is
& gpt
->im
& mask
)
1330 qemu_irq_raise(gpt
->irqs
[i
]);
1332 qemu_irq_lower(gpt
->irqs
[i
]);
1337 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t
*gpt
)
1342 static uint32_t ppc4xx_gpt_readl (void *opaque
, hwaddr addr
)
1349 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1354 /* Time base counter */
1355 ret
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + gpt
->tb_offset
,
1356 gpt
->tb_freq
, get_ticks_per_sec());
1367 /* Interrupt mask */
1372 /* Interrupt status */
1376 /* Interrupt enable */
1381 idx
= (addr
- 0x80) >> 2;
1382 ret
= gpt
->comp
[idx
];
1386 idx
= (addr
- 0xC0) >> 2;
1387 ret
= gpt
->mask
[idx
];
1397 static void ppc4xx_gpt_writel (void *opaque
,
1398 hwaddr addr
, uint32_t value
)
1404 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1410 /* Time base counter */
1411 gpt
->tb_offset
= muldiv64(value
, get_ticks_per_sec(), gpt
->tb_freq
)
1412 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1413 ppc4xx_gpt_compute_timer(gpt
);
1417 gpt
->oe
= value
& 0xF8000000;
1418 ppc4xx_gpt_set_outputs(gpt
);
1422 gpt
->ol
= value
& 0xF8000000;
1423 ppc4xx_gpt_set_outputs(gpt
);
1426 /* Interrupt mask */
1427 gpt
->im
= value
& 0x0000F800;
1430 /* Interrupt status set */
1431 gpt
->is
|= value
& 0x0000F800;
1432 ppc4xx_gpt_set_irqs(gpt
);
1435 /* Interrupt status clear */
1436 gpt
->is
&= ~(value
& 0x0000F800);
1437 ppc4xx_gpt_set_irqs(gpt
);
1440 /* Interrupt enable */
1441 gpt
->ie
= value
& 0x0000F800;
1442 ppc4xx_gpt_set_irqs(gpt
);
1446 idx
= (addr
- 0x80) >> 2;
1447 gpt
->comp
[idx
] = value
& 0xF8000000;
1448 ppc4xx_gpt_compute_timer(gpt
);
1452 idx
= (addr
- 0xC0) >> 2;
1453 gpt
->mask
[idx
] = value
& 0xF8000000;
1454 ppc4xx_gpt_compute_timer(gpt
);
1459 static const MemoryRegionOps gpt_ops
= {
1461 .read
= { ppc4xx_gpt_readb
, ppc4xx_gpt_readw
, ppc4xx_gpt_readl
, },
1462 .write
= { ppc4xx_gpt_writeb
, ppc4xx_gpt_writew
, ppc4xx_gpt_writel
, },
1464 .endianness
= DEVICE_NATIVE_ENDIAN
,
1467 static void ppc4xx_gpt_cb (void *opaque
)
1472 ppc4xx_gpt_set_irqs(gpt
);
1473 ppc4xx_gpt_set_outputs(gpt
);
1474 ppc4xx_gpt_compute_timer(gpt
);
1477 static void ppc4xx_gpt_reset (void *opaque
)
1483 timer_del(gpt
->timer
);
1484 gpt
->oe
= 0x00000000;
1485 gpt
->ol
= 0x00000000;
1486 gpt
->im
= 0x00000000;
1487 gpt
->is
= 0x00000000;
1488 gpt
->ie
= 0x00000000;
1489 for (i
= 0; i
< 5; i
++) {
1490 gpt
->comp
[i
] = 0x00000000;
1491 gpt
->mask
[i
] = 0x00000000;
1495 static void ppc4xx_gpt_init(hwaddr base
, qemu_irq irqs
[5])
1500 gpt
= g_malloc0(sizeof(ppc4xx_gpt_t
));
1501 for (i
= 0; i
< 5; i
++) {
1502 gpt
->irqs
[i
] = irqs
[i
];
1504 gpt
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &ppc4xx_gpt_cb
, gpt
);
1506 printf("%s: offset " TARGET_FMT_plx
"\n", __func__
, base
);
1508 memory_region_init_io(&gpt
->iomem
, NULL
, &gpt_ops
, gpt
, "gpt", 0x0d4);
1509 memory_region_add_subregion(get_system_memory(), base
, &gpt
->iomem
);
1510 qemu_register_reset(ppc4xx_gpt_reset
, gpt
);
1513 /*****************************************************************************/
1519 MAL0_TXCASR
= 0x184,
1520 MAL0_TXCARR
= 0x185,
1521 MAL0_TXEOBISR
= 0x186,
1522 MAL0_TXDEIR
= 0x187,
1523 MAL0_RXCASR
= 0x190,
1524 MAL0_RXCARR
= 0x191,
1525 MAL0_RXEOBISR
= 0x192,
1526 MAL0_RXDEIR
= 0x193,
1527 MAL0_TXCTP0R
= 0x1A0,
1528 MAL0_TXCTP1R
= 0x1A1,
1529 MAL0_TXCTP2R
= 0x1A2,
1530 MAL0_TXCTP3R
= 0x1A3,
1531 MAL0_RXCTP0R
= 0x1C0,
1532 MAL0_RXCTP1R
= 0x1C1,
1537 typedef struct ppc40x_mal_t ppc40x_mal_t
;
1538 struct ppc40x_mal_t
{
1556 static void ppc40x_mal_reset (void *opaque
);
1558 static uint32_t dcr_read_mal (void *opaque
, int dcrn
)
1581 ret
= mal
->txeobisr
;
1593 ret
= mal
->rxeobisr
;
1599 ret
= mal
->txctpr
[0];
1602 ret
= mal
->txctpr
[1];
1605 ret
= mal
->txctpr
[2];
1608 ret
= mal
->txctpr
[3];
1611 ret
= mal
->rxctpr
[0];
1614 ret
= mal
->rxctpr
[1];
1630 static void dcr_write_mal (void *opaque
, int dcrn
, uint32_t val
)
1638 if (val
& 0x80000000)
1639 ppc40x_mal_reset(mal
);
1640 mal
->cfg
= val
& 0x00FFC087;
1647 mal
->ier
= val
& 0x0000001F;
1650 mal
->txcasr
= val
& 0xF0000000;
1653 mal
->txcarr
= val
& 0xF0000000;
1657 mal
->txeobisr
&= ~val
;
1661 mal
->txdeir
&= ~val
;
1664 mal
->rxcasr
= val
& 0xC0000000;
1667 mal
->rxcarr
= val
& 0xC0000000;
1671 mal
->rxeobisr
&= ~val
;
1675 mal
->rxdeir
&= ~val
;
1689 mal
->txctpr
[idx
] = val
;
1697 mal
->rxctpr
[idx
] = val
;
1701 goto update_rx_size
;
1705 mal
->rcbs
[idx
] = val
& 0x000000FF;
1710 static void ppc40x_mal_reset (void *opaque
)
1715 mal
->cfg
= 0x0007C000;
1716 mal
->esr
= 0x00000000;
1717 mal
->ier
= 0x00000000;
1718 mal
->rxcasr
= 0x00000000;
1719 mal
->rxdeir
= 0x00000000;
1720 mal
->rxeobisr
= 0x00000000;
1721 mal
->txcasr
= 0x00000000;
1722 mal
->txdeir
= 0x00000000;
1723 mal
->txeobisr
= 0x00000000;
1726 static void ppc405_mal_init(CPUPPCState
*env
, qemu_irq irqs
[4])
1731 mal
= g_malloc0(sizeof(ppc40x_mal_t
));
1732 for (i
= 0; i
< 4; i
++)
1733 mal
->irqs
[i
] = irqs
[i
];
1734 qemu_register_reset(&ppc40x_mal_reset
, mal
);
1735 ppc_dcr_register(env
, MAL0_CFG
,
1736 mal
, &dcr_read_mal
, &dcr_write_mal
);
1737 ppc_dcr_register(env
, MAL0_ESR
,
1738 mal
, &dcr_read_mal
, &dcr_write_mal
);
1739 ppc_dcr_register(env
, MAL0_IER
,
1740 mal
, &dcr_read_mal
, &dcr_write_mal
);
1741 ppc_dcr_register(env
, MAL0_TXCASR
,
1742 mal
, &dcr_read_mal
, &dcr_write_mal
);
1743 ppc_dcr_register(env
, MAL0_TXCARR
,
1744 mal
, &dcr_read_mal
, &dcr_write_mal
);
1745 ppc_dcr_register(env
, MAL0_TXEOBISR
,
1746 mal
, &dcr_read_mal
, &dcr_write_mal
);
1747 ppc_dcr_register(env
, MAL0_TXDEIR
,
1748 mal
, &dcr_read_mal
, &dcr_write_mal
);
1749 ppc_dcr_register(env
, MAL0_RXCASR
,
1750 mal
, &dcr_read_mal
, &dcr_write_mal
);
1751 ppc_dcr_register(env
, MAL0_RXCARR
,
1752 mal
, &dcr_read_mal
, &dcr_write_mal
);
1753 ppc_dcr_register(env
, MAL0_RXEOBISR
,
1754 mal
, &dcr_read_mal
, &dcr_write_mal
);
1755 ppc_dcr_register(env
, MAL0_RXDEIR
,
1756 mal
, &dcr_read_mal
, &dcr_write_mal
);
1757 ppc_dcr_register(env
, MAL0_TXCTP0R
,
1758 mal
, &dcr_read_mal
, &dcr_write_mal
);
1759 ppc_dcr_register(env
, MAL0_TXCTP1R
,
1760 mal
, &dcr_read_mal
, &dcr_write_mal
);
1761 ppc_dcr_register(env
, MAL0_TXCTP2R
,
1762 mal
, &dcr_read_mal
, &dcr_write_mal
);
1763 ppc_dcr_register(env
, MAL0_TXCTP3R
,
1764 mal
, &dcr_read_mal
, &dcr_write_mal
);
1765 ppc_dcr_register(env
, MAL0_RXCTP0R
,
1766 mal
, &dcr_read_mal
, &dcr_write_mal
);
1767 ppc_dcr_register(env
, MAL0_RXCTP1R
,
1768 mal
, &dcr_read_mal
, &dcr_write_mal
);
1769 ppc_dcr_register(env
, MAL0_RCBS0
,
1770 mal
, &dcr_read_mal
, &dcr_write_mal
);
1771 ppc_dcr_register(env
, MAL0_RCBS1
,
1772 mal
, &dcr_read_mal
, &dcr_write_mal
);
1775 /*****************************************************************************/
1777 void ppc40x_core_reset(PowerPCCPU
*cpu
)
1779 CPUPPCState
*env
= &cpu
->env
;
1782 printf("Reset PowerPC core\n");
1783 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_RESET
);
1784 dbsr
= env
->spr
[SPR_40x_DBSR
];
1785 dbsr
&= ~0x00000300;
1787 env
->spr
[SPR_40x_DBSR
] = dbsr
;
1790 void ppc40x_chip_reset(PowerPCCPU
*cpu
)
1792 CPUPPCState
*env
= &cpu
->env
;
1795 printf("Reset PowerPC chip\n");
1796 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_RESET
);
1797 /* XXX: TODO reset all internal peripherals */
1798 dbsr
= env
->spr
[SPR_40x_DBSR
];
1799 dbsr
&= ~0x00000300;
1801 env
->spr
[SPR_40x_DBSR
] = dbsr
;
1804 void ppc40x_system_reset(PowerPCCPU
*cpu
)
1806 printf("Reset PowerPC system\n");
1807 qemu_system_reset_request();
1810 void store_40x_dbcr0 (CPUPPCState
*env
, uint32_t val
)
1812 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
1814 switch ((val
>> 28) & 0x3) {
1820 ppc40x_core_reset(cpu
);
1824 ppc40x_chip_reset(cpu
);
1828 ppc40x_system_reset(cpu
);
1833 /*****************************************************************************/
1836 PPC405CR_CPC0_PLLMR
= 0x0B0,
1837 PPC405CR_CPC0_CR0
= 0x0B1,
1838 PPC405CR_CPC0_CR1
= 0x0B2,
1839 PPC405CR_CPC0_PSR
= 0x0B4,
1840 PPC405CR_CPC0_JTAGID
= 0x0B5,
1841 PPC405CR_CPC0_ER
= 0x0B9,
1842 PPC405CR_CPC0_FR
= 0x0BA,
1843 PPC405CR_CPC0_SR
= 0x0BB,
1847 PPC405CR_CPU_CLK
= 0,
1848 PPC405CR_TMR_CLK
= 1,
1849 PPC405CR_PLB_CLK
= 2,
1850 PPC405CR_SDRAM_CLK
= 3,
1851 PPC405CR_OPB_CLK
= 4,
1852 PPC405CR_EXT_CLK
= 5,
1853 PPC405CR_UART_CLK
= 6,
1854 PPC405CR_CLK_NB
= 7,
1857 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t
;
1858 struct ppc405cr_cpc_t
{
1859 clk_setup_t clk_setup
[PPC405CR_CLK_NB
];
1870 static void ppc405cr_clk_setup (ppc405cr_cpc_t
*cpc
)
1872 uint64_t VCO_out
, PLL_out
;
1873 uint32_t CPU_clk
, TMR_clk
, SDRAM_clk
, PLB_clk
, OPB_clk
, EXT_clk
, UART_clk
;
1876 D0
= ((cpc
->pllmr
>> 26) & 0x3) + 1; /* CBDV */
1877 if (cpc
->pllmr
& 0x80000000) {
1878 D1
= (((cpc
->pllmr
>> 20) - 1) & 0xF) + 1; /* FBDV */
1879 D2
= 8 - ((cpc
->pllmr
>> 16) & 0x7); /* FWDVA */
1881 VCO_out
= cpc
->sysclk
* M
;
1882 if (VCO_out
< 400000000 || VCO_out
> 800000000) {
1883 /* PLL cannot lock */
1884 cpc
->pllmr
&= ~0x80000000;
1887 PLL_out
= VCO_out
/ D2
;
1892 PLL_out
= cpc
->sysclk
* M
;
1895 if (cpc
->cr1
& 0x00800000)
1896 TMR_clk
= cpc
->sysclk
; /* Should have a separate clock */
1899 PLB_clk
= CPU_clk
/ D0
;
1900 SDRAM_clk
= PLB_clk
;
1901 D0
= ((cpc
->pllmr
>> 10) & 0x3) + 1;
1902 OPB_clk
= PLB_clk
/ D0
;
1903 D0
= ((cpc
->pllmr
>> 24) & 0x3) + 2;
1904 EXT_clk
= PLB_clk
/ D0
;
1905 D0
= ((cpc
->cr0
>> 1) & 0x1F) + 1;
1906 UART_clk
= CPU_clk
/ D0
;
1907 /* Setup CPU clocks */
1908 clk_setup(&cpc
->clk_setup
[PPC405CR_CPU_CLK
], CPU_clk
);
1909 /* Setup time-base clock */
1910 clk_setup(&cpc
->clk_setup
[PPC405CR_TMR_CLK
], TMR_clk
);
1911 /* Setup PLB clock */
1912 clk_setup(&cpc
->clk_setup
[PPC405CR_PLB_CLK
], PLB_clk
);
1913 /* Setup SDRAM clock */
1914 clk_setup(&cpc
->clk_setup
[PPC405CR_SDRAM_CLK
], SDRAM_clk
);
1915 /* Setup OPB clock */
1916 clk_setup(&cpc
->clk_setup
[PPC405CR_OPB_CLK
], OPB_clk
);
1917 /* Setup external clock */
1918 clk_setup(&cpc
->clk_setup
[PPC405CR_EXT_CLK
], EXT_clk
);
1919 /* Setup UART clock */
1920 clk_setup(&cpc
->clk_setup
[PPC405CR_UART_CLK
], UART_clk
);
1923 static uint32_t dcr_read_crcpc (void *opaque
, int dcrn
)
1925 ppc405cr_cpc_t
*cpc
;
1930 case PPC405CR_CPC0_PLLMR
:
1933 case PPC405CR_CPC0_CR0
:
1936 case PPC405CR_CPC0_CR1
:
1939 case PPC405CR_CPC0_PSR
:
1942 case PPC405CR_CPC0_JTAGID
:
1945 case PPC405CR_CPC0_ER
:
1948 case PPC405CR_CPC0_FR
:
1951 case PPC405CR_CPC0_SR
:
1952 ret
= ~(cpc
->er
| cpc
->fr
) & 0xFFFF0000;
1955 /* Avoid gcc warning */
1963 static void dcr_write_crcpc (void *opaque
, int dcrn
, uint32_t val
)
1965 ppc405cr_cpc_t
*cpc
;
1969 case PPC405CR_CPC0_PLLMR
:
1970 cpc
->pllmr
= val
& 0xFFF77C3F;
1972 case PPC405CR_CPC0_CR0
:
1973 cpc
->cr0
= val
& 0x0FFFFFFE;
1975 case PPC405CR_CPC0_CR1
:
1976 cpc
->cr1
= val
& 0x00800000;
1978 case PPC405CR_CPC0_PSR
:
1981 case PPC405CR_CPC0_JTAGID
:
1984 case PPC405CR_CPC0_ER
:
1985 cpc
->er
= val
& 0xBFFC0000;
1987 case PPC405CR_CPC0_FR
:
1988 cpc
->fr
= val
& 0xBFFC0000;
1990 case PPC405CR_CPC0_SR
:
1996 static void ppc405cr_cpc_reset (void *opaque
)
1998 ppc405cr_cpc_t
*cpc
;
2002 /* Compute PLLMR value from PSR settings */
2003 cpc
->pllmr
= 0x80000000;
2005 switch ((cpc
->psr
>> 30) & 3) {
2008 cpc
->pllmr
&= ~0x80000000;
2012 cpc
->pllmr
|= 5 << 16;
2016 cpc
->pllmr
|= 4 << 16;
2020 cpc
->pllmr
|= 2 << 16;
2024 D
= (cpc
->psr
>> 28) & 3;
2025 cpc
->pllmr
|= (D
+ 1) << 20;
2027 D
= (cpc
->psr
>> 25) & 7;
2042 D
= (cpc
->psr
>> 23) & 3;
2043 cpc
->pllmr
|= D
<< 26;
2045 D
= (cpc
->psr
>> 21) & 3;
2046 cpc
->pllmr
|= D
<< 10;
2048 D
= (cpc
->psr
>> 17) & 3;
2049 cpc
->pllmr
|= D
<< 24;
2050 cpc
->cr0
= 0x0000003C;
2051 cpc
->cr1
= 0x2B0D8800;
2052 cpc
->er
= 0x00000000;
2053 cpc
->fr
= 0x00000000;
2054 ppc405cr_clk_setup(cpc
);
2057 static void ppc405cr_clk_init (ppc405cr_cpc_t
*cpc
)
2061 /* XXX: this should be read from IO pins */
2062 cpc
->psr
= 0x00000000; /* 8 bits ROM */
2064 D
= 0x2; /* Divide by 4 */
2065 cpc
->psr
|= D
<< 30;
2067 D
= 0x1; /* Divide by 2 */
2068 cpc
->psr
|= D
<< 28;
2070 D
= 0x1; /* Divide by 2 */
2071 cpc
->psr
|= D
<< 23;
2073 D
= 0x5; /* M = 16 */
2074 cpc
->psr
|= D
<< 25;
2076 D
= 0x1; /* Divide by 2 */
2077 cpc
->psr
|= D
<< 21;
2079 D
= 0x2; /* Divide by 4 */
2080 cpc
->psr
|= D
<< 17;
2083 static void ppc405cr_cpc_init (CPUPPCState
*env
, clk_setup_t clk_setup
[7],
2086 ppc405cr_cpc_t
*cpc
;
2088 cpc
= g_malloc0(sizeof(ppc405cr_cpc_t
));
2089 memcpy(cpc
->clk_setup
, clk_setup
,
2090 PPC405CR_CLK_NB
* sizeof(clk_setup_t
));
2091 cpc
->sysclk
= sysclk
;
2092 cpc
->jtagid
= 0x42051049;
2093 ppc_dcr_register(env
, PPC405CR_CPC0_PSR
, cpc
,
2094 &dcr_read_crcpc
, &dcr_write_crcpc
);
2095 ppc_dcr_register(env
, PPC405CR_CPC0_CR0
, cpc
,
2096 &dcr_read_crcpc
, &dcr_write_crcpc
);
2097 ppc_dcr_register(env
, PPC405CR_CPC0_CR1
, cpc
,
2098 &dcr_read_crcpc
, &dcr_write_crcpc
);
2099 ppc_dcr_register(env
, PPC405CR_CPC0_JTAGID
, cpc
,
2100 &dcr_read_crcpc
, &dcr_write_crcpc
);
2101 ppc_dcr_register(env
, PPC405CR_CPC0_PLLMR
, cpc
,
2102 &dcr_read_crcpc
, &dcr_write_crcpc
);
2103 ppc_dcr_register(env
, PPC405CR_CPC0_ER
, cpc
,
2104 &dcr_read_crcpc
, &dcr_write_crcpc
);
2105 ppc_dcr_register(env
, PPC405CR_CPC0_FR
, cpc
,
2106 &dcr_read_crcpc
, &dcr_write_crcpc
);
2107 ppc_dcr_register(env
, PPC405CR_CPC0_SR
, cpc
,
2108 &dcr_read_crcpc
, &dcr_write_crcpc
);
2109 ppc405cr_clk_init(cpc
);
2110 qemu_register_reset(ppc405cr_cpc_reset
, cpc
);
2113 CPUPPCState
*ppc405cr_init(MemoryRegion
*address_space_mem
,
2114 MemoryRegion ram_memories
[4],
2115 hwaddr ram_bases
[4],
2116 hwaddr ram_sizes
[4],
2117 uint32_t sysclk
, qemu_irq
**picp
,
2120 clk_setup_t clk_setup
[PPC405CR_CLK_NB
];
2121 qemu_irq dma_irqs
[4];
2124 qemu_irq
*pic
, *irqs
;
2126 memset(clk_setup
, 0, sizeof(clk_setup
));
2127 cpu
= ppc4xx_init("405cr", &clk_setup
[PPC405CR_CPU_CLK
],
2128 &clk_setup
[PPC405CR_TMR_CLK
], sysclk
);
2130 /* Memory mapped devices registers */
2132 ppc4xx_plb_init(env
);
2133 /* PLB to OPB bridge */
2134 ppc4xx_pob_init(env
);
2136 ppc4xx_opba_init(0xef600600);
2137 /* Universal interrupt controller */
2138 irqs
= g_malloc0(sizeof(qemu_irq
) * PPCUIC_OUTPUT_NB
);
2139 irqs
[PPCUIC_OUTPUT_INT
] =
2140 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_INT
];
2141 irqs
[PPCUIC_OUTPUT_CINT
] =
2142 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_CINT
];
2143 pic
= ppcuic_init(env
, irqs
, 0x0C0, 0, 1);
2145 /* SDRAM controller */
2146 ppc4xx_sdram_init(env
, pic
[14], 1, ram_memories
,
2147 ram_bases
, ram_sizes
, do_init
);
2148 /* External bus controller */
2149 ppc405_ebc_init(env
);
2150 /* DMA controller */
2151 dma_irqs
[0] = pic
[26];
2152 dma_irqs
[1] = pic
[25];
2153 dma_irqs
[2] = pic
[24];
2154 dma_irqs
[3] = pic
[23];
2155 ppc405_dma_init(env
, dma_irqs
);
2157 if (serial_hds
[0] != NULL
) {
2158 serial_mm_init(address_space_mem
, 0xef600300, 0, pic
[0],
2159 PPC_SERIAL_MM_BAUDBASE
, serial_hds
[0],
2162 if (serial_hds
[1] != NULL
) {
2163 serial_mm_init(address_space_mem
, 0xef600400, 0, pic
[1],
2164 PPC_SERIAL_MM_BAUDBASE
, serial_hds
[1],
2167 /* IIC controller */
2168 ppc405_i2c_init(0xef600500, pic
[2]);
2170 ppc405_gpio_init(0xef600700);
2172 ppc405cr_cpc_init(env
, clk_setup
, sysclk
);
2177 /*****************************************************************************/
2181 PPC405EP_CPC0_PLLMR0
= 0x0F0,
2182 PPC405EP_CPC0_BOOT
= 0x0F1,
2183 PPC405EP_CPC0_EPCTL
= 0x0F3,
2184 PPC405EP_CPC0_PLLMR1
= 0x0F4,
2185 PPC405EP_CPC0_UCR
= 0x0F5,
2186 PPC405EP_CPC0_SRR
= 0x0F6,
2187 PPC405EP_CPC0_JTAGID
= 0x0F7,
2188 PPC405EP_CPC0_PCI
= 0x0F9,
2190 PPC405EP_CPC0_ER
= xxx
,
2191 PPC405EP_CPC0_FR
= xxx
,
2192 PPC405EP_CPC0_SR
= xxx
,
2197 PPC405EP_CPU_CLK
= 0,
2198 PPC405EP_PLB_CLK
= 1,
2199 PPC405EP_OPB_CLK
= 2,
2200 PPC405EP_EBC_CLK
= 3,
2201 PPC405EP_MAL_CLK
= 4,
2202 PPC405EP_PCI_CLK
= 5,
2203 PPC405EP_UART0_CLK
= 6,
2204 PPC405EP_UART1_CLK
= 7,
2205 PPC405EP_CLK_NB
= 8,
2208 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t
;
2209 struct ppc405ep_cpc_t
{
2211 clk_setup_t clk_setup
[PPC405EP_CLK_NB
];
2219 /* Clock and power management */
2225 static void ppc405ep_compute_clocks (ppc405ep_cpc_t
*cpc
)
2227 uint32_t CPU_clk
, PLB_clk
, OPB_clk
, EBC_clk
, MAL_clk
, PCI_clk
;
2228 uint32_t UART0_clk
, UART1_clk
;
2229 uint64_t VCO_out
, PLL_out
;
2233 if ((cpc
->pllmr
[1] & 0x80000000) && !(cpc
->pllmr
[1] & 0x40000000)) {
2234 M
= (((cpc
->pllmr
[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2235 #ifdef DEBUG_CLOCKS_LL
2236 printf("FBMUL %01" PRIx32
" %d\n", (cpc
->pllmr
[1] >> 20) & 0xF, M
);
2238 D
= 8 - ((cpc
->pllmr
[1] >> 16) & 0x7); /* FWDA */
2239 #ifdef DEBUG_CLOCKS_LL
2240 printf("FWDA %01" PRIx32
" %d\n", (cpc
->pllmr
[1] >> 16) & 0x7, D
);
2242 VCO_out
= cpc
->sysclk
* M
* D
;
2243 if (VCO_out
< 500000000UL || VCO_out
> 1000000000UL) {
2244 /* Error - unlock the PLL */
2245 printf("VCO out of range %" PRIu64
"\n", VCO_out
);
2247 cpc
->pllmr
[1] &= ~0x80000000;
2251 PLL_out
= VCO_out
/ D
;
2252 /* Pretend the PLL is locked */
2253 cpc
->boot
|= 0x00000001;
2258 PLL_out
= cpc
->sysclk
;
2259 if (cpc
->pllmr
[1] & 0x40000000) {
2260 /* Pretend the PLL is not locked */
2261 cpc
->boot
&= ~0x00000001;
2264 /* Now, compute all other clocks */
2265 D
= ((cpc
->pllmr
[0] >> 20) & 0x3) + 1; /* CCDV */
2266 #ifdef DEBUG_CLOCKS_LL
2267 printf("CCDV %01" PRIx32
" %d\n", (cpc
->pllmr
[0] >> 20) & 0x3, D
);
2269 CPU_clk
= PLL_out
/ D
;
2270 D
= ((cpc
->pllmr
[0] >> 16) & 0x3) + 1; /* CBDV */
2271 #ifdef DEBUG_CLOCKS_LL
2272 printf("CBDV %01" PRIx32
" %d\n", (cpc
->pllmr
[0] >> 16) & 0x3, D
);
2274 PLB_clk
= CPU_clk
/ D
;
2275 D
= ((cpc
->pllmr
[0] >> 12) & 0x3) + 1; /* OPDV */
2276 #ifdef DEBUG_CLOCKS_LL
2277 printf("OPDV %01" PRIx32
" %d\n", (cpc
->pllmr
[0] >> 12) & 0x3, D
);
2279 OPB_clk
= PLB_clk
/ D
;
2280 D
= ((cpc
->pllmr
[0] >> 8) & 0x3) + 2; /* EPDV */
2281 #ifdef DEBUG_CLOCKS_LL
2282 printf("EPDV %01" PRIx32
" %d\n", (cpc
->pllmr
[0] >> 8) & 0x3, D
);
2284 EBC_clk
= PLB_clk
/ D
;
2285 D
= ((cpc
->pllmr
[0] >> 4) & 0x3) + 1; /* MPDV */
2286 #ifdef DEBUG_CLOCKS_LL
2287 printf("MPDV %01" PRIx32
" %d\n", (cpc
->pllmr
[0] >> 4) & 0x3, D
);
2289 MAL_clk
= PLB_clk
/ D
;
2290 D
= (cpc
->pllmr
[0] & 0x3) + 1; /* PPDV */
2291 #ifdef DEBUG_CLOCKS_LL
2292 printf("PPDV %01" PRIx32
" %d\n", cpc
->pllmr
[0] & 0x3, D
);
2294 PCI_clk
= PLB_clk
/ D
;
2295 D
= ((cpc
->ucr
- 1) & 0x7F) + 1; /* U0DIV */
2296 #ifdef DEBUG_CLOCKS_LL
2297 printf("U0DIV %01" PRIx32
" %d\n", cpc
->ucr
& 0x7F, D
);
2299 UART0_clk
= PLL_out
/ D
;
2300 D
= (((cpc
->ucr
>> 8) - 1) & 0x7F) + 1; /* U1DIV */
2301 #ifdef DEBUG_CLOCKS_LL
2302 printf("U1DIV %01" PRIx32
" %d\n", (cpc
->ucr
>> 8) & 0x7F, D
);
2304 UART1_clk
= PLL_out
/ D
;
2306 printf("Setup PPC405EP clocks - sysclk %" PRIu32
" VCO %" PRIu64
2307 " PLL out %" PRIu64
" Hz\n", cpc
->sysclk
, VCO_out
, PLL_out
);
2308 printf("CPU %" PRIu32
" PLB %" PRIu32
" OPB %" PRIu32
" EBC %" PRIu32
2309 " MAL %" PRIu32
" PCI %" PRIu32
" UART0 %" PRIu32
2310 " UART1 %" PRIu32
"\n",
2311 CPU_clk
, PLB_clk
, OPB_clk
, EBC_clk
, MAL_clk
, PCI_clk
,
2312 UART0_clk
, UART1_clk
);
2314 /* Setup CPU clocks */
2315 clk_setup(&cpc
->clk_setup
[PPC405EP_CPU_CLK
], CPU_clk
);
2316 /* Setup PLB clock */
2317 clk_setup(&cpc
->clk_setup
[PPC405EP_PLB_CLK
], PLB_clk
);
2318 /* Setup OPB clock */
2319 clk_setup(&cpc
->clk_setup
[PPC405EP_OPB_CLK
], OPB_clk
);
2320 /* Setup external clock */
2321 clk_setup(&cpc
->clk_setup
[PPC405EP_EBC_CLK
], EBC_clk
);
2322 /* Setup MAL clock */
2323 clk_setup(&cpc
->clk_setup
[PPC405EP_MAL_CLK
], MAL_clk
);
2324 /* Setup PCI clock */
2325 clk_setup(&cpc
->clk_setup
[PPC405EP_PCI_CLK
], PCI_clk
);
2326 /* Setup UART0 clock */
2327 clk_setup(&cpc
->clk_setup
[PPC405EP_UART0_CLK
], UART0_clk
);
2328 /* Setup UART1 clock */
2329 clk_setup(&cpc
->clk_setup
[PPC405EP_UART1_CLK
], UART1_clk
);
2332 static uint32_t dcr_read_epcpc (void *opaque
, int dcrn
)
2334 ppc405ep_cpc_t
*cpc
;
2339 case PPC405EP_CPC0_BOOT
:
2342 case PPC405EP_CPC0_EPCTL
:
2345 case PPC405EP_CPC0_PLLMR0
:
2346 ret
= cpc
->pllmr
[0];
2348 case PPC405EP_CPC0_PLLMR1
:
2349 ret
= cpc
->pllmr
[1];
2351 case PPC405EP_CPC0_UCR
:
2354 case PPC405EP_CPC0_SRR
:
2357 case PPC405EP_CPC0_JTAGID
:
2360 case PPC405EP_CPC0_PCI
:
2364 /* Avoid gcc warning */
2372 static void dcr_write_epcpc (void *opaque
, int dcrn
, uint32_t val
)
2374 ppc405ep_cpc_t
*cpc
;
2378 case PPC405EP_CPC0_BOOT
:
2379 /* Read-only register */
2381 case PPC405EP_CPC0_EPCTL
:
2382 /* Don't care for now */
2383 cpc
->epctl
= val
& 0xC00000F3;
2385 case PPC405EP_CPC0_PLLMR0
:
2386 cpc
->pllmr
[0] = val
& 0x00633333;
2387 ppc405ep_compute_clocks(cpc
);
2389 case PPC405EP_CPC0_PLLMR1
:
2390 cpc
->pllmr
[1] = val
& 0xC0F73FFF;
2391 ppc405ep_compute_clocks(cpc
);
2393 case PPC405EP_CPC0_UCR
:
2394 /* UART control - don't care for now */
2395 cpc
->ucr
= val
& 0x003F7F7F;
2397 case PPC405EP_CPC0_SRR
:
2400 case PPC405EP_CPC0_JTAGID
:
2403 case PPC405EP_CPC0_PCI
:
2409 static void ppc405ep_cpc_reset (void *opaque
)
2411 ppc405ep_cpc_t
*cpc
= opaque
;
2413 cpc
->boot
= 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2414 cpc
->epctl
= 0x00000000;
2415 cpc
->pllmr
[0] = 0x00011010;
2416 cpc
->pllmr
[1] = 0x40000000;
2417 cpc
->ucr
= 0x00000000;
2418 cpc
->srr
= 0x00040000;
2419 cpc
->pci
= 0x00000000;
2420 cpc
->er
= 0x00000000;
2421 cpc
->fr
= 0x00000000;
2422 cpc
->sr
= 0x00000000;
2423 ppc405ep_compute_clocks(cpc
);
2426 /* XXX: sysclk should be between 25 and 100 MHz */
2427 static void ppc405ep_cpc_init (CPUPPCState
*env
, clk_setup_t clk_setup
[8],
2430 ppc405ep_cpc_t
*cpc
;
2432 cpc
= g_malloc0(sizeof(ppc405ep_cpc_t
));
2433 memcpy(cpc
->clk_setup
, clk_setup
,
2434 PPC405EP_CLK_NB
* sizeof(clk_setup_t
));
2435 cpc
->jtagid
= 0x20267049;
2436 cpc
->sysclk
= sysclk
;
2437 qemu_register_reset(&ppc405ep_cpc_reset
, cpc
);
2438 ppc_dcr_register(env
, PPC405EP_CPC0_BOOT
, cpc
,
2439 &dcr_read_epcpc
, &dcr_write_epcpc
);
2440 ppc_dcr_register(env
, PPC405EP_CPC0_EPCTL
, cpc
,
2441 &dcr_read_epcpc
, &dcr_write_epcpc
);
2442 ppc_dcr_register(env
, PPC405EP_CPC0_PLLMR0
, cpc
,
2443 &dcr_read_epcpc
, &dcr_write_epcpc
);
2444 ppc_dcr_register(env
, PPC405EP_CPC0_PLLMR1
, cpc
,
2445 &dcr_read_epcpc
, &dcr_write_epcpc
);
2446 ppc_dcr_register(env
, PPC405EP_CPC0_UCR
, cpc
,
2447 &dcr_read_epcpc
, &dcr_write_epcpc
);
2448 ppc_dcr_register(env
, PPC405EP_CPC0_SRR
, cpc
,
2449 &dcr_read_epcpc
, &dcr_write_epcpc
);
2450 ppc_dcr_register(env
, PPC405EP_CPC0_JTAGID
, cpc
,
2451 &dcr_read_epcpc
, &dcr_write_epcpc
);
2452 ppc_dcr_register(env
, PPC405EP_CPC0_PCI
, cpc
,
2453 &dcr_read_epcpc
, &dcr_write_epcpc
);
2455 ppc_dcr_register(env
, PPC405EP_CPC0_ER
, cpc
,
2456 &dcr_read_epcpc
, &dcr_write_epcpc
);
2457 ppc_dcr_register(env
, PPC405EP_CPC0_FR
, cpc
,
2458 &dcr_read_epcpc
, &dcr_write_epcpc
);
2459 ppc_dcr_register(env
, PPC405EP_CPC0_SR
, cpc
,
2460 &dcr_read_epcpc
, &dcr_write_epcpc
);
2464 CPUPPCState
*ppc405ep_init(MemoryRegion
*address_space_mem
,
2465 MemoryRegion ram_memories
[2],
2466 hwaddr ram_bases
[2],
2467 hwaddr ram_sizes
[2],
2468 uint32_t sysclk
, qemu_irq
**picp
,
2471 clk_setup_t clk_setup
[PPC405EP_CLK_NB
], tlb_clk_setup
;
2472 qemu_irq dma_irqs
[4], gpt_irqs
[5], mal_irqs
[4];
2475 qemu_irq
*pic
, *irqs
;
2477 memset(clk_setup
, 0, sizeof(clk_setup
));
2479 cpu
= ppc4xx_init("405ep", &clk_setup
[PPC405EP_CPU_CLK
],
2480 &tlb_clk_setup
, sysclk
);
2482 clk_setup
[PPC405EP_CPU_CLK
].cb
= tlb_clk_setup
.cb
;
2483 clk_setup
[PPC405EP_CPU_CLK
].opaque
= tlb_clk_setup
.opaque
;
2484 /* Internal devices init */
2485 /* Memory mapped devices registers */
2487 ppc4xx_plb_init(env
);
2488 /* PLB to OPB bridge */
2489 ppc4xx_pob_init(env
);
2491 ppc4xx_opba_init(0xef600600);
2492 /* Initialize timers */
2493 ppc_booke_timers_init(cpu
, sysclk
, 0);
2494 /* Universal interrupt controller */
2495 irqs
= g_malloc0(sizeof(qemu_irq
) * PPCUIC_OUTPUT_NB
);
2496 irqs
[PPCUIC_OUTPUT_INT
] =
2497 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_INT
];
2498 irqs
[PPCUIC_OUTPUT_CINT
] =
2499 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_CINT
];
2500 pic
= ppcuic_init(env
, irqs
, 0x0C0, 0, 1);
2502 /* SDRAM controller */
2503 /* XXX 405EP has no ECC interrupt */
2504 ppc4xx_sdram_init(env
, pic
[17], 2, ram_memories
,
2505 ram_bases
, ram_sizes
, do_init
);
2506 /* External bus controller */
2507 ppc405_ebc_init(env
);
2508 /* DMA controller */
2509 dma_irqs
[0] = pic
[5];
2510 dma_irqs
[1] = pic
[6];
2511 dma_irqs
[2] = pic
[7];
2512 dma_irqs
[3] = pic
[8];
2513 ppc405_dma_init(env
, dma_irqs
);
2514 /* IIC controller */
2515 ppc405_i2c_init(0xef600500, pic
[2]);
2517 ppc405_gpio_init(0xef600700);
2519 if (serial_hds
[0] != NULL
) {
2520 serial_mm_init(address_space_mem
, 0xef600300, 0, pic
[0],
2521 PPC_SERIAL_MM_BAUDBASE
, serial_hds
[0],
2524 if (serial_hds
[1] != NULL
) {
2525 serial_mm_init(address_space_mem
, 0xef600400, 0, pic
[1],
2526 PPC_SERIAL_MM_BAUDBASE
, serial_hds
[1],
2530 ppc405_ocm_init(env
);
2532 gpt_irqs
[0] = pic
[19];
2533 gpt_irqs
[1] = pic
[20];
2534 gpt_irqs
[2] = pic
[21];
2535 gpt_irqs
[3] = pic
[22];
2536 gpt_irqs
[4] = pic
[23];
2537 ppc4xx_gpt_init(0xef600000, gpt_irqs
);
2539 /* Uses pic[3], pic[16], pic[18] */
2541 mal_irqs
[0] = pic
[11];
2542 mal_irqs
[1] = pic
[12];
2543 mal_irqs
[2] = pic
[13];
2544 mal_irqs
[3] = pic
[14];
2545 ppc405_mal_init(env
, mal_irqs
);
2547 /* Uses pic[9], pic[15], pic[17] */
2549 ppc405ep_cpc_init(env
, clk_setup
, sysclk
);