hw/arm/strongarm.c

   1 /*
   2  * StrongARM SA-1100/SA-1110 emulation
   3  *
   4  * Copyright (C) 2011 Dmitry Eremin-Solenikov
   5  *
   6  * Largely based on StrongARM emulation:
   7  * Copyright (c) 2006 Openedhand Ltd.
   8  * Written by Andrzej Zaborowski <balrog@zabor.org>
   9  *
  10  * UART code based on QEMU 16550A UART emulation
  11  * Copyright (c) 2003-2004 Fabrice Bellard
  12  * Copyright (c) 2008 Citrix Systems, Inc.
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License version 2 as
  16  *  published by the Free Software Foundation.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License along
  24  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  25  *
  26  *  Contributions after 2012-01-13 are licensed under the terms of the
  27  *  GNU GPL, version 2 or (at your option) any later version.
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "cpu.h"
  32 #include "hw/boards.h"
  33 #include "hw/sysbus.h"
  34 #include "strongarm.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/arm/arm.h"
  37 #include "sysemu/char.h"
  38 #include "sysemu/sysemu.h"
  39 #include "hw/ssi/ssi.h"
  40
  41 //#define DEBUG
  42
  43 /*
  44  TODO
  45  - Implement cp15, c14 ?
  46  - Implement cp15, c15 !!! (idle used in L)
  47  - Implement idle mode handling/DIM
  48  - Implement sleep mode/Wake sources
  49  - Implement reset control
  50  - Implement memory control regs
  51  - PCMCIA handling
  52  - Maybe support MBGNT/MBREQ
  53  - DMA channels
  54  - GPCLK
  55  - IrDA
  56  - MCP
  57  - Enhance UART with modem signals
  58  */
  59
  60 #ifdef DEBUG
  61 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
  62 #else
  63 # define DPRINTF(format, ...) do { } while (0)
  64 #endif
  65
  66 static struct {
  67     hwaddr io_base;
  68     int irq;
  69 } sa_serial[] = {
  70     { 0x80010000, SA_PIC_UART1 },
  71     { 0x80030000, SA_PIC_UART2 },
  72     { 0x80050000, SA_PIC_UART3 },
  73     { 0, 0 }
  74 };
  75
  76 /* Interrupt Controller */
  77
  78 #define TYPE_STRONGARM_PIC "strongarm_pic"
  79 #define STRONGARM_PIC(obj) \
  80     OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
  81
  82 typedef struct StrongARMPICState {
  83     SysBusDevice parent_obj;
  84
  85     MemoryRegion iomem;
  86     qemu_irq    irq;
  87     qemu_irq    fiq;
  88
  89     uint32_t pending;
  90     uint32_t enabled;
  91     uint32_t is_fiq;
  92     uint32_t int_idle;
  93 } StrongARMPICState;
  94
  95 #define ICIP    0x00
  96 #define ICMR    0x04
  97 #define ICLR    0x08
  98 #define ICFP    0x10
  99 #define ICPR    0x20
 100 #define ICCR    0x0c
 101
 102 #define SA_PIC_SRCS     32
 103
 104
 105 static void strongarm_pic_update(void *opaque)
 106 {
 107     StrongARMPICState *s = opaque;
 108
 109     /* FIXME: reflect DIM */
 110     qemu_set_irq(s->fiq, s->pending & s->enabled &  s->is_fiq);
 111     qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
 112 }
 113
 114 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
 115 {
 116     StrongARMPICState *s = opaque;
 117
 118     if (level) {
 119         s->pending |= 1 << irq;
 120     } else {
 121         s->pending &= ~(1 << irq);
 122     }
 123
 124     strongarm_pic_update(s);
 125 }
 126
 127 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
 128                                        unsigned size)
 129 {
 130     StrongARMPICState *s = opaque;
 131
 132     switch (offset) {
 133     case ICIP:
 134         return s->pending & ~s->is_fiq & s->enabled;
 135     case ICMR:
 136         return s->enabled;
 137     case ICLR:
 138         return s->is_fiq;
 139     case ICCR:
 140         return s->int_idle == 0;
 141     case ICFP:
 142         return s->pending & s->is_fiq & s->enabled;
 143     case ICPR:
 144         return s->pending;
 145     default:
 146         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 147                         __func__, offset);
 148         return 0;
 149     }
 150 }
 151
 152 static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
 153                                     uint64_t value, unsigned size)
 154 {
 155     StrongARMPICState *s = opaque;
 156
 157     switch (offset) {
 158     case ICMR:
 159         s->enabled = value;
 160         break;
 161     case ICLR:
 162         s->is_fiq = value;
 163         break;
 164     case ICCR:
 165         s->int_idle = (value & 1) ? 0 : ~0;
 166         break;
 167     default:
 168         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 169                         __func__, offset);
 170         break;
 171     }
 172     strongarm_pic_update(s);
 173 }
 174
 175 static const MemoryRegionOps strongarm_pic_ops = {
 176     .read = strongarm_pic_mem_read,
 177     .write = strongarm_pic_mem_write,
 178     .endianness = DEVICE_NATIVE_ENDIAN,
 179 };
 180
 181 static int strongarm_pic_initfn(SysBusDevice *sbd)
 182 {
 183     DeviceState *dev = DEVICE(sbd);
 184     StrongARMPICState *s = STRONGARM_PIC(dev);
 185
 186     qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
 187     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s,
 188                           "pic", 0x1000);
 189     sysbus_init_mmio(sbd, &s->iomem);
 190     sysbus_init_irq(sbd, &s->irq);
 191     sysbus_init_irq(sbd, &s->fiq);
 192
 193     return 0;
 194 }
 195
 196 static int strongarm_pic_post_load(void *opaque, int version_id)
 197 {
 198     strongarm_pic_update(opaque);
 199     return 0;
 200 }
 201
 202 static VMStateDescription vmstate_strongarm_pic_regs = {
 203     .name = "strongarm_pic",
 204     .version_id = 0,
 205     .minimum_version_id = 0,
 206     .post_load = strongarm_pic_post_load,
 207     .fields = (VMStateField[]) {
 208         VMSTATE_UINT32(pending, StrongARMPICState),
 209         VMSTATE_UINT32(enabled, StrongARMPICState),
 210         VMSTATE_UINT32(is_fiq, StrongARMPICState),
 211         VMSTATE_UINT32(int_idle, StrongARMPICState),
 212         VMSTATE_END_OF_LIST(),
 213     },
 214 };
 215
 216 static void strongarm_pic_class_init(ObjectClass *klass, void *data)
 217 {
 218     DeviceClass *dc = DEVICE_CLASS(klass);
 219     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 220
 221     k->init = strongarm_pic_initfn;
 222     dc->desc = "StrongARM PIC";
 223     dc->vmsd = &vmstate_strongarm_pic_regs;
 224 }
 225
 226 static const TypeInfo strongarm_pic_info = {
 227     .name          = TYPE_STRONGARM_PIC,
 228     .parent        = TYPE_SYS_BUS_DEVICE,
 229     .instance_size = sizeof(StrongARMPICState),
 230     .class_init    = strongarm_pic_class_init,
 231 };
 232
 233 /* Real-Time Clock */
 234 #define RTAR 0x00 /* RTC Alarm register */
 235 #define RCNR 0x04 /* RTC Counter register */
 236 #define RTTR 0x08 /* RTC Timer Trim register */
 237 #define RTSR 0x10 /* RTC Status register */
 238
 239 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
 240 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
 241 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
 242 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
 243
 244 /* 16 LSB of RTTR are clockdiv for internal trim logic,
 245  * trim delete isn't emulated, so
 246  * f = 32 768 / (RTTR_trim + 1) */
 247
 248 #define TYPE_STRONGARM_RTC "strongarm-rtc"
 249 #define STRONGARM_RTC(obj) \
 250     OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
 251
 252 typedef struct StrongARMRTCState {
 253     SysBusDevice parent_obj;
 254
 255     MemoryRegion iomem;
 256     uint32_t rttr;
 257     uint32_t rtsr;
 258     uint32_t rtar;
 259     uint32_t last_rcnr;
 260     int64_t last_hz;
 261     QEMUTimer *rtc_alarm;
 262     QEMUTimer *rtc_hz;
 263     qemu_irq rtc_irq;
 264     qemu_irq rtc_hz_irq;
 265 } StrongARMRTCState;
 266
 267 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
 268 {
 269     qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
 270     qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
 271 }
 272
 273 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
 274 {
 275     int64_t rt = qemu_clock_get_ms(rtc_clock);
 276     s->last_rcnr += ((rt - s->last_hz) << 15) /
 277             (1000 * ((s->rttr & 0xffff) + 1));
 278     s->last_hz = rt;
 279 }
 280
 281 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
 282 {
 283     if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
 284         timer_mod(s->rtc_hz, s->last_hz + 1000);
 285     } else {
 286         timer_del(s->rtc_hz);
 287     }
 288
 289     if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
 290         timer_mod(s->rtc_alarm, s->last_hz +
 291                 (((s->rtar - s->last_rcnr) * 1000 *
 292                   ((s->rttr & 0xffff) + 1)) >> 15));
 293     } else {
 294         timer_del(s->rtc_alarm);
 295     }
 296 }
 297
 298 static inline void strongarm_rtc_alarm_tick(void *opaque)
 299 {
 300     StrongARMRTCState *s = opaque;
 301     s->rtsr |= RTSR_AL;
 302     strongarm_rtc_timer_update(s);
 303     strongarm_rtc_int_update(s);
 304 }
 305
 306 static inline void strongarm_rtc_hz_tick(void *opaque)
 307 {
 308     StrongARMRTCState *s = opaque;
 309     s->rtsr |= RTSR_HZ;
 310     strongarm_rtc_timer_update(s);
 311     strongarm_rtc_int_update(s);
 312 }
 313
 314 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
 315                                    unsigned size)
 316 {
 317     StrongARMRTCState *s = opaque;
 318
 319     switch (addr) {
 320     case RTTR:
 321         return s->rttr;
 322     case RTSR:
 323         return s->rtsr;
 324     case RTAR:
 325         return s->rtar;
 326     case RCNR:
 327         return s->last_rcnr +
 328                 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
 329                 (1000 * ((s->rttr & 0xffff) + 1));
 330     default:
 331         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 332         return 0;
 333     }
 334 }
 335
 336 static void strongarm_rtc_write(void *opaque, hwaddr addr,
 337                                 uint64_t value, unsigned size)
 338 {
 339     StrongARMRTCState *s = opaque;
 340     uint32_t old_rtsr;
 341
 342     switch (addr) {
 343     case RTTR:
 344         strongarm_rtc_hzupdate(s);
 345         s->rttr = value;
 346         strongarm_rtc_timer_update(s);
 347         break;
 348
 349     case RTSR:
 350         old_rtsr = s->rtsr;
 351         s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
 352                   (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
 353
 354         if (s->rtsr != old_rtsr) {
 355             strongarm_rtc_timer_update(s);
 356         }
 357
 358         strongarm_rtc_int_update(s);
 359         break;
 360
 361     case RTAR:
 362         s->rtar = value;
 363         strongarm_rtc_timer_update(s);
 364         break;
 365
 366     case RCNR:
 367         strongarm_rtc_hzupdate(s);
 368         s->last_rcnr = value;
 369         strongarm_rtc_timer_update(s);
 370         break;
 371
 372     default:
 373         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 374     }
 375 }
 376
 377 static const MemoryRegionOps strongarm_rtc_ops = {
 378     .read = strongarm_rtc_read,
 379     .write = strongarm_rtc_write,
 380     .endianness = DEVICE_NATIVE_ENDIAN,
 381 };
 382
 383 static int strongarm_rtc_init(SysBusDevice *dev)
 384 {
 385     StrongARMRTCState *s = STRONGARM_RTC(dev);
 386     struct tm tm;
 387
 388     s->rttr = 0x0;
 389     s->rtsr = 0;
 390
 391     qemu_get_timedate(&tm, 0);
 392
 393     s->last_rcnr = (uint32_t) mktimegm(&tm);
 394     s->last_hz = qemu_clock_get_ms(rtc_clock);
 395
 396     s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
 397     s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s);
 398
 399     sysbus_init_irq(dev, &s->rtc_irq);
 400     sysbus_init_irq(dev, &s->rtc_hz_irq);
 401
 402     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s,
 403                           "rtc", 0x10000);
 404     sysbus_init_mmio(dev, &s->iomem);
 405
 406     return 0;
 407 }
 408
 409 static void strongarm_rtc_pre_save(void *opaque)
 410 {
 411     StrongARMRTCState *s = opaque;
 412
 413     strongarm_rtc_hzupdate(s);
 414 }
 415
 416 static int strongarm_rtc_post_load(void *opaque, int version_id)
 417 {
 418     StrongARMRTCState *s = opaque;
 419
 420     strongarm_rtc_timer_update(s);
 421     strongarm_rtc_int_update(s);
 422
 423     return 0;
 424 }
 425
 426 static const VMStateDescription vmstate_strongarm_rtc_regs = {
 427     .name = "strongarm-rtc",
 428     .version_id = 0,
 429     .minimum_version_id = 0,
 430     .pre_save = strongarm_rtc_pre_save,
 431     .post_load = strongarm_rtc_post_load,
 432     .fields = (VMStateField[]) {
 433         VMSTATE_UINT32(rttr, StrongARMRTCState),
 434         VMSTATE_UINT32(rtsr, StrongARMRTCState),
 435         VMSTATE_UINT32(rtar, StrongARMRTCState),
 436         VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
 437         VMSTATE_INT64(last_hz, StrongARMRTCState),
 438         VMSTATE_END_OF_LIST(),
 439     },
 440 };
 441
 442 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
 443 {
 444     DeviceClass *dc = DEVICE_CLASS(klass);
 445     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 446
 447     k->init = strongarm_rtc_init;
 448     dc->desc = "StrongARM RTC Controller";
 449     dc->vmsd = &vmstate_strongarm_rtc_regs;
 450 }
 451
 452 static const TypeInfo strongarm_rtc_sysbus_info = {
 453     .name          = TYPE_STRONGARM_RTC,
 454     .parent        = TYPE_SYS_BUS_DEVICE,
 455     .instance_size = sizeof(StrongARMRTCState),
 456     .class_init    = strongarm_rtc_sysbus_class_init,
 457 };
 458
 459 /* GPIO */
 460 #define GPLR 0x00
 461 #define GPDR 0x04
 462 #define GPSR 0x08
 463 #define GPCR 0x0c
 464 #define GRER 0x10
 465 #define GFER 0x14
 466 #define GEDR 0x18
 467 #define GAFR 0x1c
 468
 469 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
 470 #define STRONGARM_GPIO(obj) \
 471     OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
 472
 473 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
 474 struct StrongARMGPIOInfo {
 475     SysBusDevice busdev;
 476     MemoryRegion iomem;
 477     qemu_irq handler[28];
 478     qemu_irq irqs[11];
 479     qemu_irq irqX;
 480
 481     uint32_t ilevel;
 482     uint32_t olevel;
 483     uint32_t dir;
 484     uint32_t rising;
 485     uint32_t falling;
 486     uint32_t status;
 487     uint32_t gafr;
 488
 489     uint32_t prev_level;
 490 };
 491
 492
 493 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
 494 {
 495     int i;
 496     for (i = 0; i < 11; i++) {
 497         qemu_set_irq(s->irqs[i], s->status & (1 << i));
 498     }
 499
 500     qemu_set_irq(s->irqX, (s->status & ~0x7ff));
 501 }
 502
 503 static void strongarm_gpio_set(void *opaque, int line, int level)
 504 {
 505     StrongARMGPIOInfo *s = opaque;
 506     uint32_t mask;
 507
 508     mask = 1 << line;
 509
 510     if (level) {
 511         s->status |= s->rising & mask &
 512                 ~s->ilevel & ~s->dir;
 513         s->ilevel |= mask;
 514     } else {
 515         s->status |= s->falling & mask &
 516                 s->ilevel & ~s->dir;
 517         s->ilevel &= ~mask;
 518     }
 519
 520     if (s->status & mask) {
 521         strongarm_gpio_irq_update(s);
 522     }
 523 }
 524
 525 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
 526 {
 527     uint32_t level, diff;
 528     int bit;
 529
 530     level = s->olevel & s->dir;
 531
 532     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 533         bit = ctz32(diff);
 534         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 535     }
 536
 537     s->prev_level = level;
 538 }
 539
 540 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
 541                                     unsigned size)
 542 {
 543     StrongARMGPIOInfo *s = opaque;
 544
 545     switch (offset) {
 546     case GPDR:        /* GPIO Pin-Direction registers */
 547         return s->dir;
 548
 549     case GPSR:        /* GPIO Pin-Output Set registers */
 550         qemu_log_mask(LOG_GUEST_ERROR,
 551                       "strongarm GPIO: read from write only register GPSR\n");
 552         return 0;
 553
 554     case GPCR:        /* GPIO Pin-Output Clear registers */
 555         qemu_log_mask(LOG_GUEST_ERROR,
 556                       "strongarm GPIO: read from write only register GPCR\n");
 557         return 0;
 558
 559     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 560         return s->rising;
 561
 562     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 563         return s->falling;
 564
 565     case GAFR:        /* GPIO Alternate Function registers */
 566         return s->gafr;
 567
 568     case GPLR:        /* GPIO Pin-Level registers */
 569         return (s->olevel & s->dir) |
 570                (s->ilevel & ~s->dir);
 571
 572     case GEDR:        /* GPIO Edge Detect Status registers */
 573         return s->status;
 574
 575     default:
 576         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 577     }
 578
 579     return 0;
 580 }
 581
 582 static void strongarm_gpio_write(void *opaque, hwaddr offset,
 583                                  uint64_t value, unsigned size)
 584 {
 585     StrongARMGPIOInfo *s = opaque;
 586
 587     switch (offset) {
 588     case GPDR:        /* GPIO Pin-Direction registers */
 589         s->dir = value;
 590         strongarm_gpio_handler_update(s);
 591         break;
 592
 593     case GPSR:        /* GPIO Pin-Output Set registers */
 594         s->olevel |= value;
 595         strongarm_gpio_handler_update(s);
 596         break;
 597
 598     case GPCR:        /* GPIO Pin-Output Clear registers */
 599         s->olevel &= ~value;
 600         strongarm_gpio_handler_update(s);
 601         break;
 602
 603     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 604         s->rising = value;
 605         break;
 606
 607     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 608         s->falling = value;
 609         break;
 610
 611     case GAFR:        /* GPIO Alternate Function registers */
 612         s->gafr = value;
 613         break;
 614
 615     case GEDR:        /* GPIO Edge Detect Status registers */
 616         s->status &= ~value;
 617         strongarm_gpio_irq_update(s);
 618         break;
 619
 620     default:
 621         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 622     }
 623 }
 624
 625 static const MemoryRegionOps strongarm_gpio_ops = {
 626     .read = strongarm_gpio_read,
 627     .write = strongarm_gpio_write,
 628     .endianness = DEVICE_NATIVE_ENDIAN,
 629 };
 630
 631 static DeviceState *strongarm_gpio_init(hwaddr base,
 632                 DeviceState *pic)
 633 {
 634     DeviceState *dev;
 635     int i;
 636
 637     dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
 638     qdev_init_nofail(dev);
 639
 640     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 641     for (i = 0; i < 12; i++)
 642         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 643                     qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
 644
 645     return dev;
 646 }
 647
 648 static int strongarm_gpio_initfn(SysBusDevice *sbd)
 649 {
 650     DeviceState *dev = DEVICE(sbd);
 651     StrongARMGPIOInfo *s = STRONGARM_GPIO(dev);
 652     int i;
 653
 654     qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
 655     qdev_init_gpio_out(dev, s->handler, 28);
 656
 657     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s,
 658                           "gpio", 0x1000);
 659
 660     sysbus_init_mmio(sbd, &s->iomem);
 661     for (i = 0; i < 11; i++) {
 662         sysbus_init_irq(sbd, &s->irqs[i]);
 663     }
 664     sysbus_init_irq(sbd, &s->irqX);
 665
 666     return 0;
 667 }
 668
 669 static const VMStateDescription vmstate_strongarm_gpio_regs = {
 670     .name = "strongarm-gpio",
 671     .version_id = 0,
 672     .minimum_version_id = 0,
 673     .fields = (VMStateField[]) {
 674         VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
 675         VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
 676         VMSTATE_UINT32(dir, StrongARMGPIOInfo),
 677         VMSTATE_UINT32(rising, StrongARMGPIOInfo),
 678         VMSTATE_UINT32(falling, StrongARMGPIOInfo),
 679         VMSTATE_UINT32(status, StrongARMGPIOInfo),
 680         VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
 681         VMSTATE_UINT32(prev_level, StrongARMGPIOInfo),
 682         VMSTATE_END_OF_LIST(),
 683     },
 684 };
 685
 686 static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
 687 {
 688     DeviceClass *dc = DEVICE_CLASS(klass);
 689     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 690
 691     k->init = strongarm_gpio_initfn;
 692     dc->desc = "StrongARM GPIO controller";
 693     dc->vmsd = &vmstate_strongarm_gpio_regs;
 694 }
 695
 696 static const TypeInfo strongarm_gpio_info = {
 697     .name          = TYPE_STRONGARM_GPIO,
 698     .parent        = TYPE_SYS_BUS_DEVICE,
 699     .instance_size = sizeof(StrongARMGPIOInfo),
 700     .class_init    = strongarm_gpio_class_init,
 701 };
 702
 703 /* Peripheral Pin Controller */
 704 #define PPDR 0x00
 705 #define PPSR 0x04
 706 #define PPAR 0x08
 707 #define PSDR 0x0c
 708 #define PPFR 0x10
 709
 710 #define TYPE_STRONGARM_PPC "strongarm-ppc"
 711 #define STRONGARM_PPC(obj) \
 712     OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
 713
 714 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
 715 struct StrongARMPPCInfo {
 716     SysBusDevice parent_obj;
 717
 718     MemoryRegion iomem;
 719     qemu_irq handler[28];
 720
 721     uint32_t ilevel;
 722     uint32_t olevel;
 723     uint32_t dir;
 724     uint32_t ppar;
 725     uint32_t psdr;
 726     uint32_t ppfr;
 727
 728     uint32_t prev_level;
 729 };
 730
 731 static void strongarm_ppc_set(void *opaque, int line, int level)
 732 {
 733     StrongARMPPCInfo *s = opaque;
 734
 735     if (level) {
 736         s->ilevel |= 1 << line;
 737     } else {
 738         s->ilevel &= ~(1 << line);
 739     }
 740 }
 741
 742 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
 743 {
 744     uint32_t level, diff;
 745     int bit;
 746
 747     level = s->olevel & s->dir;
 748
 749     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 750         bit = ctz32(diff);
 751         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 752     }
 753
 754     s->prev_level = level;
 755 }
 756
 757 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
 758                                    unsigned size)
 759 {
 760     StrongARMPPCInfo *s = opaque;
 761
 762     switch (offset) {
 763     case PPDR:        /* PPC Pin Direction registers */
 764         return s->dir | ~0x3fffff;
 765
 766     case PPSR:        /* PPC Pin State registers */
 767         return (s->olevel & s->dir) |
 768                (s->ilevel & ~s->dir) |
 769                ~0x3fffff;
 770
 771     case PPAR:
 772         return s->ppar | ~0x41000;
 773
 774     case PSDR:
 775         return s->psdr;
 776
 777     case PPFR:
 778         return s->ppfr | ~0x7f001;
 779
 780     default:
 781         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 782     }
 783
 784     return 0;
 785 }
 786
 787 static void strongarm_ppc_write(void *opaque, hwaddr offset,
 788                                 uint64_t value, unsigned size)
 789 {
 790     StrongARMPPCInfo *s = opaque;
 791
 792     switch (offset) {
 793     case PPDR:        /* PPC Pin Direction registers */
 794         s->dir = value & 0x3fffff;
 795         strongarm_ppc_handler_update(s);
 796         break;
 797
 798     case PPSR:        /* PPC Pin State registers */
 799         s->olevel = value & s->dir & 0x3fffff;
 800         strongarm_ppc_handler_update(s);
 801         break;
 802
 803     case PPAR:
 804         s->ppar = value & 0x41000;
 805         break;
 806
 807     case PSDR:
 808         s->psdr = value & 0x3fffff;
 809         break;
 810
 811     case PPFR:
 812         s->ppfr = value & 0x7f001;
 813         break;
 814
 815     default:
 816         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 817     }
 818 }
 819
 820 static const MemoryRegionOps strongarm_ppc_ops = {
 821     .read = strongarm_ppc_read,
 822     .write = strongarm_ppc_write,
 823     .endianness = DEVICE_NATIVE_ENDIAN,
 824 };
 825
 826 static int strongarm_ppc_init(SysBusDevice *sbd)
 827 {
 828     DeviceState *dev = DEVICE(sbd);
 829     StrongARMPPCInfo *s = STRONGARM_PPC(dev);
 830
 831     qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
 832     qdev_init_gpio_out(dev, s->handler, 22);
 833
 834     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s,
 835                           "ppc", 0x1000);
 836
 837     sysbus_init_mmio(sbd, &s->iomem);
 838
 839     return 0;
 840 }
 841
 842 static const VMStateDescription vmstate_strongarm_ppc_regs = {
 843     .name = "strongarm-ppc",
 844     .version_id = 0,
 845     .minimum_version_id = 0,
 846     .fields = (VMStateField[]) {
 847         VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
 848         VMSTATE_UINT32(olevel, StrongARMPPCInfo),
 849         VMSTATE_UINT32(dir, StrongARMPPCInfo),
 850         VMSTATE_UINT32(ppar, StrongARMPPCInfo),
 851         VMSTATE_UINT32(psdr, StrongARMPPCInfo),
 852         VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
 853         VMSTATE_UINT32(prev_level, StrongARMPPCInfo),
 854         VMSTATE_END_OF_LIST(),
 855     },
 856 };
 857
 858 static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
 859 {
 860     DeviceClass *dc = DEVICE_CLASS(klass);
 861     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 862
 863     k->init = strongarm_ppc_init;
 864     dc->desc = "StrongARM PPC controller";
 865     dc->vmsd = &vmstate_strongarm_ppc_regs;
 866 }
 867
 868 static const TypeInfo strongarm_ppc_info = {
 869     .name          = TYPE_STRONGARM_PPC,
 870     .parent        = TYPE_SYS_BUS_DEVICE,
 871     .instance_size = sizeof(StrongARMPPCInfo),
 872     .class_init    = strongarm_ppc_class_init,
 873 };
 874
 875 /* UART Ports */
 876 #define UTCR0 0x00
 877 #define UTCR1 0x04
 878 #define UTCR2 0x08
 879 #define UTCR3 0x0c
 880 #define UTDR  0x14
 881 #define UTSR0 0x1c
 882 #define UTSR1 0x20
 883
 884 #define UTCR0_PE  (1 << 0) /* Parity enable */
 885 #define UTCR0_OES (1 << 1) /* Even parity */
 886 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
 887 #define UTCR0_DSS (1 << 3) /* 8-bit data */
 888
 889 #define UTCR3_RXE (1 << 0) /* Rx enable */
 890 #define UTCR3_TXE (1 << 1) /* Tx enable */
 891 #define UTCR3_BRK (1 << 2) /* Force Break */
 892 #define UTCR3_RIE (1 << 3) /* Rx int enable */
 893 #define UTCR3_TIE (1 << 4) /* Tx int enable */
 894 #define UTCR3_LBM (1 << 5) /* Loopback */
 895
 896 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
 897 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
 898 #define UTSR0_RID (1 << 2) /* Receiver Idle */
 899 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
 900 #define UTSR0_REB (1 << 4) /* Receiver end break */
 901 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
 902
 903 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
 904 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
 905 #define UTSR1_PRE (1 << 3) /* Parity error */
 906 #define UTSR1_FRE (1 << 4) /* Frame error */
 907 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
 908
 909 #define RX_FIFO_PRE (1 << 8)
 910 #define RX_FIFO_FRE (1 << 9)
 911 #define RX_FIFO_ROR (1 << 10)
 912
 913 #define TYPE_STRONGARM_UART "strongarm-uart"
 914 #define STRONGARM_UART(obj) \
 915     OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
 916
 917 typedef struct StrongARMUARTState {
 918     SysBusDevice parent_obj;
 919
 920     MemoryRegion iomem;
 921     CharDriverState *chr;
 922     qemu_irq irq;
 923
 924     uint8_t utcr0;
 925     uint16_t brd;
 926     uint8_t utcr3;
 927     uint8_t utsr0;
 928     uint8_t utsr1;
 929
 930     uint8_t tx_fifo[8];
 931     uint8_t tx_start;
 932     uint8_t tx_len;
 933     uint16_t rx_fifo[12]; /* value + error flags in high bits */
 934     uint8_t rx_start;
 935     uint8_t rx_len;
 936
 937     uint64_t char_transmit_time; /* time to transmit a char in ticks*/
 938     bool wait_break_end;
 939     QEMUTimer *rx_timeout_timer;
 940     QEMUTimer *tx_timer;
 941 } StrongARMUARTState;
 942
 943 static void strongarm_uart_update_status(StrongARMUARTState *s)
 944 {
 945     uint16_t utsr1 = 0;
 946
 947     if (s->tx_len != 8) {
 948         utsr1 |= UTSR1_TNF;
 949     }
 950
 951     if (s->rx_len != 0) {
 952         uint16_t ent = s->rx_fifo[s->rx_start];
 953
 954         utsr1 |= UTSR1_RNE;
 955         if (ent & RX_FIFO_PRE) {
 956             s->utsr1 |= UTSR1_PRE;
 957         }
 958         if (ent & RX_FIFO_FRE) {
 959             s->utsr1 |= UTSR1_FRE;
 960         }
 961         if (ent & RX_FIFO_ROR) {
 962             s->utsr1 |= UTSR1_ROR;
 963         }
 964     }
 965
 966     s->utsr1 = utsr1;
 967 }
 968
 969 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
 970 {
 971     uint16_t utsr0 = s->utsr0 &
 972             (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
 973     int i;
 974
 975     if ((s->utcr3 & UTCR3_TXE) &&
 976                 (s->utcr3 & UTCR3_TIE) &&
 977                 s->tx_len <= 4) {
 978         utsr0 |= UTSR0_TFS;
 979     }
 980
 981     if ((s->utcr3 & UTCR3_RXE) &&
 982                 (s->utcr3 & UTCR3_RIE) &&
 983                 s->rx_len > 4) {
 984         utsr0 |= UTSR0_RFS;
 985     }
 986
 987     for (i = 0; i < s->rx_len && i < 4; i++)
 988         if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
 989             utsr0 |= UTSR0_EIF;
 990             break;
 991         }
 992
 993     s->utsr0 = utsr0;
 994     qemu_set_irq(s->irq, utsr0);
 995 }
 996
 997 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
 998 {
 999     int speed, parity, data_bits, stop_bits, frame_size;
1000     QEMUSerialSetParams ssp;
1001
1002     /* Start bit. */
1003     frame_size = 1;
1004     if (s->utcr0 & UTCR0_PE) {
1005         /* Parity bit. */
1006         frame_size++;
1007         if (s->utcr0 & UTCR0_OES) {
1008             parity = 'E';
1009         } else {
1010             parity = 'O';
1011         }
1012     } else {
1013             parity = 'N';
1014     }
1015     if (s->utcr0 & UTCR0_SBS) {
1016         stop_bits = 2;
1017     } else {
1018         stop_bits = 1;
1019     }
1020
1021     data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
1022     frame_size += data_bits + stop_bits;
1023     speed = 3686400 / 16 / (s->brd + 1);
1024     ssp.speed = speed;
1025     ssp.parity = parity;
1026     ssp.data_bits = data_bits;
1027     ssp.stop_bits = stop_bits;
1028     s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;
1029     if (s->chr) {
1030         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1031     }
1032
1033     DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1034             speed, parity, data_bits, stop_bits);
1035 }
1036
1037 static void strongarm_uart_rx_to(void *opaque)
1038 {
1039     StrongARMUARTState *s = opaque;
1040
1041     if (s->rx_len) {
1042         s->utsr0 |= UTSR0_RID;
1043         strongarm_uart_update_int_status(s);
1044     }
1045 }
1046
1047 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1048 {
1049     if ((s->utcr3 & UTCR3_RXE) == 0) {
1050         /* rx disabled */
1051         return;
1052     }
1053
1054     if (s->wait_break_end) {
1055         s->utsr0 |= UTSR0_REB;
1056         s->wait_break_end = false;
1057     }
1058
1059     if (s->rx_len < 12) {
1060         s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1061         s->rx_len++;
1062     } else
1063         s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1064 }
1065
1066 static int strongarm_uart_can_receive(void *opaque)
1067 {
1068     StrongARMUARTState *s = opaque;
1069
1070     if (s->rx_len == 12) {
1071         return 0;
1072     }
1073     /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1074     if (s->rx_len < 8) {
1075         return 8 - s->rx_len;
1076     }
1077     return 1;
1078 }
1079
1080 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1081 {
1082     StrongARMUARTState *s = opaque;
1083     int i;
1084
1085     for (i = 0; i < size; i++) {
1086         strongarm_uart_rx_push(s, buf[i]);
1087     }
1088
1089     /* call the timeout receive callback in 3 char transmit time */
1090     timer_mod(s->rx_timeout_timer,
1091                     qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1092
1093     strongarm_uart_update_status(s);
1094     strongarm_uart_update_int_status(s);
1095 }
1096
1097 static void strongarm_uart_event(void *opaque, int event)
1098 {
1099     StrongARMUARTState *s = opaque;
1100     if (event == CHR_EVENT_BREAK) {
1101         s->utsr0 |= UTSR0_RBB;
1102         strongarm_uart_rx_push(s, RX_FIFO_FRE);
1103         s->wait_break_end = true;
1104         strongarm_uart_update_status(s);
1105         strongarm_uart_update_int_status(s);
1106     }
1107 }
1108
1109 static void strongarm_uart_tx(void *opaque)
1110 {
1111     StrongARMUARTState *s = opaque;
1112     uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1113
1114     if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1115         strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1116     } else if (s->chr) {
1117         qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1118     }
1119
1120     s->tx_start = (s->tx_start + 1) % 8;
1121     s->tx_len--;
1122     if (s->tx_len) {
1123         timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1124     }
1125     strongarm_uart_update_status(s);
1126     strongarm_uart_update_int_status(s);
1127 }
1128
1129 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
1130                                     unsigned size)
1131 {
1132     StrongARMUARTState *s = opaque;
1133     uint16_t ret;
1134
1135     switch (addr) {
1136     case UTCR0:
1137         return s->utcr0;
1138
1139     case UTCR1:
1140         return s->brd >> 8;
1141
1142     case UTCR2:
1143         return s->brd & 0xff;
1144
1145     case UTCR3:
1146         return s->utcr3;
1147
1148     case UTDR:
1149         if (s->rx_len != 0) {
1150             ret = s->rx_fifo[s->rx_start];
1151             s->rx_start = (s->rx_start + 1) % 12;
1152             s->rx_len--;
1153             strongarm_uart_update_status(s);
1154             strongarm_uart_update_int_status(s);
1155             return ret;
1156         }
1157         return 0;
1158
1159     case UTSR0:
1160         return s->utsr0;
1161
1162     case UTSR1:
1163         return s->utsr1;
1164
1165     default:
1166         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1167         return 0;
1168     }
1169 }
1170
1171 static void strongarm_uart_write(void *opaque, hwaddr addr,
1172                                  uint64_t value, unsigned size)
1173 {
1174     StrongARMUARTState *s = opaque;
1175
1176     switch (addr) {
1177     case UTCR0:
1178         s->utcr0 = value & 0x7f;
1179         strongarm_uart_update_parameters(s);
1180         break;
1181
1182     case UTCR1:
1183         s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1184         strongarm_uart_update_parameters(s);
1185         break;
1186
1187     case UTCR2:
1188         s->brd = (s->brd & 0xf00) | (value & 0xff);
1189         strongarm_uart_update_parameters(s);
1190         break;
1191
1192     case UTCR3:
1193         s->utcr3 = value & 0x3f;
1194         if ((s->utcr3 & UTCR3_RXE) == 0) {
1195             s->rx_len = 0;
1196         }
1197         if ((s->utcr3 & UTCR3_TXE) == 0) {
1198             s->tx_len = 0;
1199         }
1200         strongarm_uart_update_status(s);
1201         strongarm_uart_update_int_status(s);
1202         break;
1203
1204     case UTDR:
1205         if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1206             s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1207             s->tx_len++;
1208             strongarm_uart_update_status(s);
1209             strongarm_uart_update_int_status(s);
1210             if (s->tx_len == 1) {
1211                 strongarm_uart_tx(s);
1212             }
1213         }
1214         break;
1215
1216     case UTSR0:
1217         s->utsr0 = s->utsr0 & ~(value &
1218                 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1219         strongarm_uart_update_int_status(s);
1220         break;
1221
1222     default:
1223         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1224     }
1225 }
1226
1227 static const MemoryRegionOps strongarm_uart_ops = {
1228     .read = strongarm_uart_read,
1229     .write = strongarm_uart_write,
1230     .endianness = DEVICE_NATIVE_ENDIAN,
1231 };
1232
1233 static int strongarm_uart_init(SysBusDevice *dev)
1234 {
1235     StrongARMUARTState *s = STRONGARM_UART(dev);
1236
1237     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s,
1238                           "uart", 0x10000);
1239     sysbus_init_mmio(dev, &s->iomem);
1240     sysbus_init_irq(dev, &s->irq);
1241
1242     s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);
1243     s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
1244
1245     if (s->chr) {
1246         qemu_chr_add_handlers(s->chr,
1247                         strongarm_uart_can_receive,
1248                         strongarm_uart_receive,
1249                         strongarm_uart_event,
1250                         s);
1251     }
1252
1253     return 0;
1254 }
1255
1256 static void strongarm_uart_reset(DeviceState *dev)
1257 {
1258     StrongARMUARTState *s = STRONGARM_UART(dev);
1259
1260     s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1261     s->brd = 23;    /* 9600 */
1262     /* enable send & recv - this actually violates spec */
1263     s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1264
1265     s->rx_len = s->tx_len = 0;
1266
1267     strongarm_uart_update_parameters(s);
1268     strongarm_uart_update_status(s);
1269     strongarm_uart_update_int_status(s);
1270 }
1271
1272 static int strongarm_uart_post_load(void *opaque, int version_id)
1273 {
1274     StrongARMUARTState *s = opaque;
1275
1276     strongarm_uart_update_parameters(s);
1277     strongarm_uart_update_status(s);
1278     strongarm_uart_update_int_status(s);
1279
1280     /* tx and restart timer */
1281     if (s->tx_len) {
1282         strongarm_uart_tx(s);
1283     }
1284
1285     /* restart rx timeout timer */
1286     if (s->rx_len) {
1287         timer_mod(s->rx_timeout_timer,
1288                 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1289     }
1290
1291     return 0;
1292 }
1293
1294 static const VMStateDescription vmstate_strongarm_uart_regs = {
1295     .name = "strongarm-uart",
1296     .version_id = 0,
1297     .minimum_version_id = 0,
1298     .post_load = strongarm_uart_post_load,
1299     .fields = (VMStateField[]) {
1300         VMSTATE_UINT8(utcr0, StrongARMUARTState),
1301         VMSTATE_UINT16(brd, StrongARMUARTState),
1302         VMSTATE_UINT8(utcr3, StrongARMUARTState),
1303         VMSTATE_UINT8(utsr0, StrongARMUARTState),
1304         VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1305         VMSTATE_UINT8(tx_start, StrongARMUARTState),
1306         VMSTATE_UINT8(tx_len, StrongARMUARTState),
1307         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1308         VMSTATE_UINT8(rx_start, StrongARMUARTState),
1309         VMSTATE_UINT8(rx_len, StrongARMUARTState),
1310         VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1311         VMSTATE_END_OF_LIST(),
1312     },
1313 };
1314
1315 static Property strongarm_uart_properties[] = {
1316     DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1317     DEFINE_PROP_END_OF_LIST(),
1318 };
1319
1320 static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1321 {
1322     DeviceClass *dc = DEVICE_CLASS(klass);
1323     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1324
1325     k->init = strongarm_uart_init;
1326     dc->desc = "StrongARM UART controller";
1327     dc->reset = strongarm_uart_reset;
1328     dc->vmsd = &vmstate_strongarm_uart_regs;
1329     dc->props = strongarm_uart_properties;
1330 }
1331
1332 static const TypeInfo strongarm_uart_info = {
1333     .name          = TYPE_STRONGARM_UART,
1334     .parent        = TYPE_SYS_BUS_DEVICE,
1335     .instance_size = sizeof(StrongARMUARTState),
1336     .class_init    = strongarm_uart_class_init,
1337 };
1338
1339 /* Synchronous Serial Ports */
1340
1341 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1342 #define STRONGARM_SSP(obj) \
1343     OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1344
1345 typedef struct StrongARMSSPState {
1346     SysBusDevice parent_obj;
1347
1348     MemoryRegion iomem;
1349     qemu_irq irq;
1350     SSIBus *bus;
1351
1352     uint16_t sscr[2];
1353     uint16_t sssr;
1354
1355     uint16_t rx_fifo[8];
1356     uint8_t rx_level;
1357     uint8_t rx_start;
1358 } StrongARMSSPState;
1359
1360 #define SSCR0 0x60 /* SSP Control register 0 */
1361 #define SSCR1 0x64 /* SSP Control register 1 */
1362 #define SSDR  0x6c /* SSP Data register */
1363 #define SSSR  0x74 /* SSP Status register */
1364
1365 /* Bitfields for above registers */
1366 #define SSCR0_SPI(x)    (((x) & 0x30) == 0x00)
1367 #define SSCR0_SSP(x)    (((x) & 0x30) == 0x10)
1368 #define SSCR0_UWIRE(x)  (((x) & 0x30) == 0x20)
1369 #define SSCR0_PSP(x)    (((x) & 0x30) == 0x30)
1370 #define SSCR0_SSE       (1 << 7)
1371 #define SSCR0_DSS(x)    (((x) & 0xf) + 1)
1372 #define SSCR1_RIE       (1 << 0)
1373 #define SSCR1_TIE       (1 << 1)
1374 #define SSCR1_LBM       (1 << 2)
1375 #define SSSR_TNF        (1 << 2)
1376 #define SSSR_RNE        (1 << 3)
1377 #define SSSR_TFS        (1 << 5)
1378 #define SSSR_RFS        (1 << 6)
1379 #define SSSR_ROR        (1 << 7)
1380 #define SSSR_RW         0x0080
1381
1382 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1383 {
1384     int level = 0;
1385
1386     level |= (s->sssr & SSSR_ROR);
1387     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
1388     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
1389     qemu_set_irq(s->irq, level);
1390 }
1391
1392 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1393 {
1394     s->sssr &= ~SSSR_TFS;
1395     s->sssr &= ~SSSR_TNF;
1396     if (s->sscr[0] & SSCR0_SSE) {
1397         if (s->rx_level >= 4) {
1398             s->sssr |= SSSR_RFS;
1399         } else {
1400             s->sssr &= ~SSSR_RFS;
1401         }
1402         if (s->rx_level) {
1403             s->sssr |= SSSR_RNE;
1404         } else {
1405             s->sssr &= ~SSSR_RNE;
1406         }
1407         /* TX FIFO is never filled, so it is always in underrun
1408            condition if SSP is enabled */
1409         s->sssr |= SSSR_TFS;
1410         s->sssr |= SSSR_TNF;
1411     }
1412
1413     strongarm_ssp_int_update(s);
1414 }
1415
1416 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
1417                                    unsigned size)
1418 {
1419     StrongARMSSPState *s = opaque;
1420     uint32_t retval;
1421
1422     switch (addr) {
1423     case SSCR0:
1424         return s->sscr[0];
1425     case SSCR1:
1426         return s->sscr[1];
1427     case SSSR:
1428         return s->sssr;
1429     case SSDR:
1430         if (~s->sscr[0] & SSCR0_SSE) {
1431             return 0xffffffff;
1432         }
1433         if (s->rx_level < 1) {
1434             printf("%s: SSP Rx Underrun\n", __func__);
1435             return 0xffffffff;
1436         }
1437         s->rx_level--;
1438         retval = s->rx_fifo[s->rx_start++];
1439         s->rx_start &= 0x7;
1440         strongarm_ssp_fifo_update(s);
1441         return retval;
1442     default:
1443         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1444         break;
1445     }
1446     return 0;
1447 }
1448
1449 static void strongarm_ssp_write(void *opaque, hwaddr addr,
1450                                 uint64_t value, unsigned size)
1451 {
1452     StrongARMSSPState *s = opaque;
1453
1454     switch (addr) {
1455     case SSCR0:
1456         s->sscr[0] = value & 0xffbf;
1457         if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1458             printf("%s: Wrong data size: %i bits\n", __func__,
1459                    (int)SSCR0_DSS(value));
1460         }
1461         if (!(value & SSCR0_SSE)) {
1462             s->sssr = 0;
1463             s->rx_level = 0;
1464         }
1465         strongarm_ssp_fifo_update(s);
1466         break;
1467
1468     case SSCR1:
1469         s->sscr[1] = value & 0x2f;
1470         if (value & SSCR1_LBM) {
1471             printf("%s: Attempt to use SSP LBM mode\n", __func__);
1472         }
1473         strongarm_ssp_fifo_update(s);
1474         break;
1475
1476     case SSSR:
1477         s->sssr &= ~(value & SSSR_RW);
1478         strongarm_ssp_int_update(s);
1479         break;
1480
1481     case SSDR:
1482         if (SSCR0_UWIRE(s->sscr[0])) {
1483             value &= 0xff;
1484         } else
1485             /* Note how 32bits overflow does no harm here */
1486             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1487
1488         /* Data goes from here to the Tx FIFO and is shifted out from
1489          * there directly to the slave, no need to buffer it.
1490          */
1491         if (s->sscr[0] & SSCR0_SSE) {
1492             uint32_t readval;
1493             if (s->sscr[1] & SSCR1_LBM) {
1494                 readval = value;
1495             } else {
1496                 readval = ssi_transfer(s->bus, value);
1497             }
1498
1499             if (s->rx_level < 0x08) {
1500                 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1501             } else {
1502                 s->sssr |= SSSR_ROR;
1503             }
1504         }
1505         strongarm_ssp_fifo_update(s);
1506         break;
1507
1508     default:
1509         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1510         break;
1511     }
1512 }
1513
1514 static const MemoryRegionOps strongarm_ssp_ops = {
1515     .read = strongarm_ssp_read,
1516     .write = strongarm_ssp_write,
1517     .endianness = DEVICE_NATIVE_ENDIAN,
1518 };
1519
1520 static int strongarm_ssp_post_load(void *opaque, int version_id)
1521 {
1522     StrongARMSSPState *s = opaque;
1523
1524     strongarm_ssp_fifo_update(s);
1525
1526     return 0;
1527 }
1528
1529 static int strongarm_ssp_init(SysBusDevice *sbd)
1530 {
1531     DeviceState *dev = DEVICE(sbd);
1532     StrongARMSSPState *s = STRONGARM_SSP(dev);
1533
1534     sysbus_init_irq(sbd, &s->irq);
1535
1536     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s,
1537                           "ssp", 0x1000);
1538     sysbus_init_mmio(sbd, &s->iomem);
1539
1540     s->bus = ssi_create_bus(dev, "ssi");
1541     return 0;
1542 }
1543
1544 static void strongarm_ssp_reset(DeviceState *dev)
1545 {
1546     StrongARMSSPState *s = STRONGARM_SSP(dev);
1547
1548     s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1549     s->rx_start = 0;
1550     s->rx_level = 0;
1551 }
1552
1553 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1554     .name = "strongarm-ssp",
1555     .version_id = 0,
1556     .minimum_version_id = 0,
1557     .post_load = strongarm_ssp_post_load,
1558     .fields = (VMStateField[]) {
1559         VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1560         VMSTATE_UINT16(sssr, StrongARMSSPState),
1561         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1562         VMSTATE_UINT8(rx_start, StrongARMSSPState),
1563         VMSTATE_UINT8(rx_level, StrongARMSSPState),
1564         VMSTATE_END_OF_LIST(),
1565     },
1566 };
1567
1568 static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1569 {
1570     DeviceClass *dc = DEVICE_CLASS(klass);
1571     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1572
1573     k->init = strongarm_ssp_init;
1574     dc->desc = "StrongARM SSP controller";
1575     dc->reset = strongarm_ssp_reset;
1576     dc->vmsd = &vmstate_strongarm_ssp_regs;
1577 }
1578
1579 static const TypeInfo strongarm_ssp_info = {
1580     .name          = TYPE_STRONGARM_SSP,
1581     .parent        = TYPE_SYS_BUS_DEVICE,
1582     .instance_size = sizeof(StrongARMSSPState),
1583     .class_init    = strongarm_ssp_class_init,
1584 };
1585
1586 /* Main CPU functions */
1587 StrongARMState *sa1110_init(MemoryRegion *sysmem,
1588                             unsigned int sdram_size, const char *rev)
1589 {
1590     StrongARMState *s;
1591     int i;
1592
1593     s = g_new0(StrongARMState, 1);
1594
1595     if (!rev) {
1596         rev = "sa1110-b5";
1597     }
1598
1599     if (strncmp(rev, "sa1110", 6)) {
1600         error_report("Machine requires a SA1110 processor.");
1601         exit(1);
1602     }
1603
1604     s->cpu = cpu_arm_init(rev);
1605
1606     if (!s->cpu) {
1607         error_report("Unable to find CPU definition");
1608         exit(1);
1609     }
1610
1611     memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
1612                                          sdram_size);
1613     memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1614
1615     s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1616                     qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ),
1617                     qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ),
1618                     NULL);
1619
1620     sysbus_create_varargs("pxa25x-timer", 0x90000000,
1621                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1622                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1623                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1624                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1625                     NULL);
1626
1627     sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000,
1628                     qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1629
1630     s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1631
1632     s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
1633
1634     for (i = 0; sa_serial[i].io_base; i++) {
1635         DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
1636         qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1637         qdev_init_nofail(dev);
1638         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
1639                 sa_serial[i].io_base);
1640         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
1641                 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1642     }
1643
1644     s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000,
1645                 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1646     s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1647
1648     return s;
1649 }
1650
1651 static void strongarm_register_types(void)
1652 {
1653     type_register_static(&strongarm_pic_info);
1654     type_register_static(&strongarm_rtc_sysbus_info);
1655     type_register_static(&strongarm_gpio_info);
1656     type_register_static(&strongarm_ppc_info);
1657     type_register_static(&strongarm_uart_info);
1658     type_register_static(&strongarm_ssp_info);
1659 }
1660
1661 type_init(strongarm_register_types)