target-microblaze/cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias
   5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  * Copyright (c) 2012 SUSE LINUX Products GmbH
   7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "cpu.h"
  25 #include "qemu-common.h"
  26 #include "hw/qdev-properties.h"
  27 #include "migration/vmstate.h"
  28
  29
  30 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
  31 {
  32     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  33
  34     cpu->env.sregs[SR_PC] = value;
  35 }
  36
  37 static bool mb_cpu_has_work(CPUState *cs)
  38 {
  39     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  40 }
  41
  42 #ifndef CONFIG_USER_ONLY
  43 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
  44 {
  45     MicroBlazeCPU *cpu = opaque;
  46     CPUState *cs = CPU(cpu);
  47     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
  48
  49     if (level) {
  50         cpu_interrupt(cs, type);
  51     } else {
  52         cpu_reset_interrupt(cs, type);
  53     }
  54 }
  55 #endif
  56
  57 /* CPUClass::reset() */
  58 static void mb_cpu_reset(CPUState *s)
  59 {
  60     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
  61     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
  62     CPUMBState *env = &cpu->env;
  63
  64     mcc->parent_reset(s);
  65
  66     memset(env, 0, offsetof(CPUMBState, pvr));
  67     env->res_addr = RES_ADDR_NONE;
  68     tlb_flush(s, 1);
  69
  70     /* Disable stack protector.  */
  71     env->shr = ~0;
  72
  73 #if defined(CONFIG_USER_ONLY)
  74     /* start in user mode with interrupts enabled.  */
  75     env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
  76 #else
  77     env->sregs[SR_MSR] = 0;
  78     mmu_init(&env->mmu);
  79     env->mmu.c_mmu = 3;
  80     env->mmu.c_mmu_tlb_access = 3;
  81     env->mmu.c_mmu_zones = 16;
  82 #endif
  83 }
  84
  85 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
  86 {
  87     CPUState *cs = CPU(dev);
  88     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
  89     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  90     CPUMBState *env = &cpu->env;
  91
  92     qemu_init_vcpu(cs);
  93
  94     env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
  95                        | PVR0_USE_BARREL_MASK \
  96                        | PVR0_USE_DIV_MASK \
  97                        | PVR0_USE_HW_MUL_MASK \
  98                        | PVR0_USE_EXC_MASK \
  99                        | PVR0_USE_ICACHE_MASK \
 100                        | PVR0_USE_DCACHE_MASK \
 101                        | (0xb << 8);
 102     env->pvr.regs[2] = PVR2_D_OPB_MASK \
 103                         | PVR2_D_LMB_MASK \
 104                         | PVR2_I_OPB_MASK \
 105                         | PVR2_I_LMB_MASK \
 106                         | PVR2_USE_MSR_INSTR \
 107                         | PVR2_USE_PCMP_INSTR \
 108                         | PVR2_USE_BARREL_MASK \
 109                         | PVR2_USE_DIV_MASK \
 110                         | PVR2_USE_HW_MUL_MASK \
 111                         | PVR2_USE_MUL64_MASK \
 112                         | PVR2_FPU_EXC_MASK \
 113                         | 0;
 114
 115     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
 116                         (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
 117                         (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
 118
 119     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
 120                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
 121
 122     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
 123     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
 124
 125     env->sregs[SR_PC] = cpu->cfg.base_vectors;
 126
 127 #if defined(CONFIG_USER_ONLY)
 128     env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp.  */
 129 #endif
 130
 131     mcc->parent_realize(dev, errp);
 132 }
 133
 134 static void mb_cpu_initfn(Object *obj)
 135 {
 136     CPUState *cs = CPU(obj);
 137     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
 138     CPUMBState *env = &cpu->env;
 139     static bool tcg_initialized;
 140
 141     cs->env_ptr = env;
 142     cpu_exec_init(env);
 143
 144     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 145
 146 #ifndef CONFIG_USER_ONLY
 147     /* Inbound IRQ and FIR lines */
 148     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
 149 #endif
 150
 151     if (tcg_enabled() && !tcg_initialized) {
 152         tcg_initialized = true;
 153         mb_tcg_init();
 154     }
 155 }
 156
 157 static const VMStateDescription vmstate_mb_cpu = {
 158     .name = "cpu",
 159     .unmigratable = 1,
 160 };
 161
 162 static Property mb_properties[] = {
 163     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
 164     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
 165                      false),
 166     /* If use-fpu > 0 - FPU is enabled
 167      * If use-fpu = 2 - Floating point conversion and square root instructions
 168      *                  are enabled
 169      */
 170     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
 171     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
 172     DEFINE_PROP_END_OF_LIST(),
 173 };
 174
 175 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 176 {
 177     DeviceClass *dc = DEVICE_CLASS(oc);
 178     CPUClass *cc = CPU_CLASS(oc);
 179     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 180
 181     mcc->parent_realize = dc->realize;
 182     dc->realize = mb_cpu_realizefn;
 183
 184     mcc->parent_reset = cc->reset;
 185     cc->reset = mb_cpu_reset;
 186
 187     cc->has_work = mb_cpu_has_work;
 188     cc->do_interrupt = mb_cpu_do_interrupt;
 189     cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
 190     cc->dump_state = mb_cpu_dump_state;
 191     cc->set_pc = mb_cpu_set_pc;
 192     cc->gdb_read_register = mb_cpu_gdb_read_register;
 193     cc->gdb_write_register = mb_cpu_gdb_write_register;
 194 #ifdef CONFIG_USER_ONLY
 195     cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
 196 #else
 197     cc->do_unassigned_access = mb_cpu_unassigned_access;
 198     cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
 199 #endif
 200     dc->vmsd = &vmstate_mb_cpu;
 201     dc->props = mb_properties;
 202     cc->gdb_num_core_regs = 32 + 5;
 203 }
 204
 205 static const TypeInfo mb_cpu_type_info = {
 206     .name = TYPE_MICROBLAZE_CPU,
 207     .parent = TYPE_CPU,
 208     .instance_size = sizeof(MicroBlazeCPU),
 209     .instance_init = mb_cpu_initfn,
 210     .class_size = sizeof(MicroBlazeCPUClass),
 211     .class_init = mb_cpu_class_init,
 212 };
 213
 214 static void mb_cpu_register_types(void)
 215 {
 216     type_register_static(&mb_cpu_type_info);
 217 }
 218
 219 type_init(mb_cpu_register_types)