include/qom/cpu.h

   1 /*
   2  * QEMU CPU model
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_CPU_H
  21 #define QEMU_CPU_H
  22
  23 #include <signal.h>
  24 #include <setjmp.h>
  25 #include "hw/qdev-core.h"
  26 #include "exec/hwaddr.h"
  27 #include "qemu/queue.h"
  28 #include "qemu/thread.h"
  29 #include "qemu/tls.h"
  30 #include "qemu/typedefs.h"
  31
  32 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
  33                                      void *opaque);
  34
  35 /**
  36  * vaddr:
  37  * Type wide enough to contain any #target_ulong virtual address.
  38  */
  39 typedef uint64_t vaddr;
  40 #define VADDR_PRId PRId64
  41 #define VADDR_PRIu PRIu64
  42 #define VADDR_PRIo PRIo64
  43 #define VADDR_PRIx PRIx64
  44 #define VADDR_PRIX PRIX64
  45 #define VADDR_MAX UINT64_MAX
  46
  47 /**
  48  * SECTION:cpu
  49  * @section_id: QEMU-cpu
  50  * @title: CPU Class
  51  * @short_description: Base class for all CPUs
  52  */
  53
  54 #define TYPE_CPU "cpu"
  55
  56 /* Since this macro is used a lot in hot code paths and in conjunction with
  57  * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
  58  * an unchecked cast.
  59  */
  60 #define CPU(obj) ((CPUState *)(obj))
  61
  62 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
  63 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
  64
  65 typedef struct CPUState CPUState;
  66
  67 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
  68                                     bool is_write, bool is_exec, int opaque,
  69                                     unsigned size);
  70
  71 struct TranslationBlock;
  72
  73 /**
  74  * CPUClass:
  75  * @class_by_name: Callback to map -cpu command line model name to an
  76  * instantiatable CPU type.
  77  * @parse_features: Callback to parse command line arguments.
  78  * @reset: Callback to reset the #CPUState to its initial state.
  79  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
  80  * @has_work: Callback for checking if there is work to do.
  81  * @do_interrupt: Callback for interrupt handling.
  82  * @do_unassigned_access: Callback for unassigned access handling.
  83  * @do_unaligned_access: Callback for unaligned access handling, if
  84  * the target defines #ALIGNED_ONLY.
  85  * @memory_rw_debug: Callback for GDB memory access.
  86  * @dump_state: Callback for dumping state.
  87  * @dump_statistics: Callback for dumping statistics.
  88  * @get_arch_id: Callback for getting architecture-dependent CPU ID.
  89  * @get_paging_enabled: Callback for inquiring whether paging is enabled.
  90  * @get_memory_mapping: Callback for obtaining the memory mappings.
  91  * @set_pc: Callback for setting the Program Counter register.
  92  * @synchronize_from_tb: Callback for synchronizing state from a TCG
  93  * #TranslationBlock.
  94  * @handle_mmu_fault: Callback for handling an MMU fault.
  95  * @get_phys_page_debug: Callback for obtaining a physical address.
  96  * @gdb_read_register: Callback for letting GDB read a register.
  97  * @gdb_write_register: Callback for letting GDB write a register.
  98  * @debug_excp_handler: Callback for handling debug exceptions.
  99  * @vmsd: State description for migration.
 100  * @gdb_num_core_regs: Number of core registers accessible to GDB.
 101  * @gdb_core_xml_file: File name for core registers GDB XML description.
 102  * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
 103  *           before the insn which triggers a watchpoint rather than after it.
 104  * @cpu_exec_enter: Callback for cpu_exec preparation.
 105  * @cpu_exec_exit: Callback for cpu_exec cleanup.
 106  * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
 107  *
 108  * Represents a CPU family or model.
 109  */
 110 typedef struct CPUClass {
 111     /*< private >*/
 112     DeviceClass parent_class;
 113     /*< public >*/
 114
 115     ObjectClass *(*class_by_name)(const char *cpu_model);
 116     void (*parse_features)(CPUState *cpu, char *str, Error **errp);
 117
 118     void (*reset)(CPUState *cpu);
 119     int reset_dump_flags;
 120     bool (*has_work)(CPUState *cpu);
 121     void (*do_interrupt)(CPUState *cpu);
 122     CPUUnassignedAccess do_unassigned_access;
 123     void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
 124                                 int is_write, int is_user, uintptr_t retaddr);
 125     bool (*virtio_is_big_endian)(CPUState *cpu);
 126     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
 127                            uint8_t *buf, int len, bool is_write);
 128     void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 129                        int flags);
 130     void (*dump_statistics)(CPUState *cpu, FILE *f,
 131                             fprintf_function cpu_fprintf, int flags);
 132     int64_t (*get_arch_id)(CPUState *cpu);
 133     bool (*get_paging_enabled)(const CPUState *cpu);
 134     void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
 135                                Error **errp);
 136     void (*set_pc)(CPUState *cpu, vaddr value);
 137     void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
 138     int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
 139                             int mmu_index);
 140     hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
 141     int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
 142     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
 143     void (*debug_excp_handler)(CPUState *cpu);
 144
 145     int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
 146                             int cpuid, void *opaque);
 147     int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 148                                 void *opaque);
 149     int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
 150                             int cpuid, void *opaque);
 151     int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 152                                 void *opaque);
 153
 154     const struct VMStateDescription *vmsd;
 155     int gdb_num_core_regs;
 156     const char *gdb_core_xml_file;
 157     bool gdb_stop_before_watchpoint;
 158
 159     void (*cpu_exec_enter)(CPUState *cpu);
 160     void (*cpu_exec_exit)(CPUState *cpu);
 161     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
 162 } CPUClass;
 163
 164 #ifdef HOST_WORDS_BIGENDIAN
 165 typedef struct icount_decr_u16 {
 166     uint16_t high;
 167     uint16_t low;
 168 } icount_decr_u16;
 169 #else
 170 typedef struct icount_decr_u16 {
 171     uint16_t low;
 172     uint16_t high;
 173 } icount_decr_u16;
 174 #endif
 175
 176 typedef struct CPUBreakpoint {
 177     vaddr pc;
 178     int flags; /* BP_* */
 179     QTAILQ_ENTRY(CPUBreakpoint) entry;
 180 } CPUBreakpoint;
 181
 182 typedef struct CPUWatchpoint {
 183     vaddr vaddr;
 184     vaddr len;
 185     vaddr hitaddr;
 186     int flags; /* BP_* */
 187     QTAILQ_ENTRY(CPUWatchpoint) entry;
 188 } CPUWatchpoint;
 189
 190 struct KVMState;
 191 struct kvm_run;
 192
 193 #define TB_JMP_CACHE_BITS 12
 194 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
 195
 196 /**
 197  * CPUState:
 198  * @cpu_index: CPU index (informative).
 199  * @nr_cores: Number of cores within this CPU package.
 200  * @nr_threads: Number of threads within this CPU.
 201  * @numa_node: NUMA node this CPU is belonging to.
 202  * @host_tid: Host thread ID.
 203  * @running: #true if CPU is currently running (usermode).
 204  * @created: Indicates whether the CPU thread has been successfully created.
 205  * @interrupt_request: Indicates a pending interrupt request.
 206  * @halted: Nonzero if the CPU is in suspended state.
 207  * @stop: Indicates a pending stop request.
 208  * @stopped: Indicates the CPU has been artificially stopped.
 209  * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
 210  *           CPU and return to its top level loop.
 211  * @singlestep_enabled: Flags for single-stepping.
 212  * @icount_extra: Instructions until next timer event.
 213  * @icount_decr: Number of cycles left, with interrupt flag in high bit.
 214  * This allows a single read-compare-cbranch-write sequence to test
 215  * for both decrementer underflow and exceptions.
 216  * @can_do_io: Nonzero if memory-mapped IO is safe.
 217  * @env_ptr: Pointer to subclass-specific CPUArchState field.
 218  * @current_tb: Currently executing TB.
 219  * @gdb_regs: Additional GDB registers.
 220  * @gdb_num_regs: Number of total registers accessible to GDB.
 221  * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
 222  * @next_cpu: Next CPU sharing TB cache.
 223  * @opaque: User data.
 224  * @mem_io_pc: Host Program Counter at which the memory was accessed.
 225  * @mem_io_vaddr: Target virtual address at which the memory was accessed.
 226  * @kvm_fd: vCPU file descriptor for KVM.
 227  *
 228  * State of one CPU core or thread.
 229  */
 230 struct CPUState {
 231     /*< private >*/
 232     DeviceState parent_obj;
 233     /*< public >*/
 234
 235     int nr_cores;
 236     int nr_threads;
 237     int numa_node;
 238
 239     struct QemuThread *thread;
 240 #ifdef _WIN32
 241     HANDLE hThread;
 242 #endif
 243     int thread_id;
 244     uint32_t host_tid;
 245     bool running;
 246     struct QemuCond *halt_cond;
 247     struct qemu_work_item *queued_work_first, *queued_work_last;
 248     bool thread_kicked;
 249     bool created;
 250     bool stop;
 251     bool stopped;
 252     volatile sig_atomic_t exit_request;
 253     uint32_t interrupt_request;
 254     int singlestep_enabled;
 255     int64_t icount_extra;
 256     sigjmp_buf jmp_env;
 257
 258     AddressSpace *as;
 259     struct AddressSpaceDispatch *memory_dispatch;
 260     MemoryListener *tcg_as_listener;
 261
 262     void *env_ptr; /* CPUArchState */
 263     struct TranslationBlock *current_tb;
 264     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
 265     struct GDBRegisterState *gdb_regs;
 266     int gdb_num_regs;
 267     int gdb_num_g_regs;
 268     QTAILQ_ENTRY(CPUState) node;
 269
 270     /* ice debug support */
 271     QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
 272
 273     QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
 274     CPUWatchpoint *watchpoint_hit;
 275
 276     void *opaque;
 277
 278     /* In order to avoid passing too many arguments to the MMIO helpers,
 279      * we store some rarely used information in the CPU context.
 280      */
 281     uintptr_t mem_io_pc;
 282     vaddr mem_io_vaddr;
 283
 284     int kvm_fd;
 285     bool kvm_vcpu_dirty;
 286     struct KVMState *kvm_state;
 287     struct kvm_run *kvm_run;
 288
 289     /* TODO Move common fields from CPUArchState here. */
 290     int cpu_index; /* used by alpha TCG */
 291     uint32_t halted; /* used by alpha, cris, ppc TCG */
 292     union {
 293         uint32_t u32;
 294         icount_decr_u16 u16;
 295     } icount_decr;
 296     uint32_t can_do_io;
 297     int32_t exception_index; /* used by m68k TCG */
 298
 299     /* Note that this is accessed at the start of every TB via a negative
 300        offset from AREG0.  Leave this field at the end so as to make the
 301        (absolute value) offset as small as possible.  This reduces code
 302        size, especially for hosts without large memory offsets.  */
 303     volatile sig_atomic_t tcg_exit_req;
 304 };
 305
 306 QTAILQ_HEAD(CPUTailQ, CPUState);
 307 extern struct CPUTailQ cpus;
 308 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
 309 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
 310 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
 311     QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
 312 #define first_cpu QTAILQ_FIRST(&cpus)
 313
 314 DECLARE_TLS(CPUState *, current_cpu);
 315 #define current_cpu tls_var(current_cpu)
 316
 317 /**
 318  * cpu_paging_enabled:
 319  * @cpu: The CPU whose state is to be inspected.
 320  *
 321  * Returns: %true if paging is enabled, %false otherwise.
 322  */
 323 bool cpu_paging_enabled(const CPUState *cpu);
 324
 325 /**
 326  * cpu_get_memory_mapping:
 327  * @cpu: The CPU whose memory mappings are to be obtained.
 328  * @list: Where to write the memory mappings to.
 329  * @errp: Pointer for reporting an #Error.
 330  */
 331 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
 332                             Error **errp);
 333
 334 /**
 335  * cpu_write_elf64_note:
 336  * @f: pointer to a function that writes memory to a file
 337  * @cpu: The CPU whose memory is to be dumped
 338  * @cpuid: ID number of the CPU
 339  * @opaque: pointer to the CPUState struct
 340  */
 341 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
 342                          int cpuid, void *opaque);
 343
 344 /**
 345  * cpu_write_elf64_qemunote:
 346  * @f: pointer to a function that writes memory to a file
 347  * @cpu: The CPU whose memory is to be dumped
 348  * @cpuid: ID number of the CPU
 349  * @opaque: pointer to the CPUState struct
 350  */
 351 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 352                              void *opaque);
 353
 354 /**
 355  * cpu_write_elf32_note:
 356  * @f: pointer to a function that writes memory to a file
 357  * @cpu: The CPU whose memory is to be dumped
 358  * @cpuid: ID number of the CPU
 359  * @opaque: pointer to the CPUState struct
 360  */
 361 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
 362                          int cpuid, void *opaque);
 363
 364 /**
 365  * cpu_write_elf32_qemunote:
 366  * @f: pointer to a function that writes memory to a file
 367  * @cpu: The CPU whose memory is to be dumped
 368  * @cpuid: ID number of the CPU
 369  * @opaque: pointer to the CPUState struct
 370  */
 371 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 372                              void *opaque);
 373
 374 /**
 375  * CPUDumpFlags:
 376  * @CPU_DUMP_CODE:
 377  * @CPU_DUMP_FPU: dump FPU register state, not just integer
 378  * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
 379  */
 380 enum CPUDumpFlags {
 381     CPU_DUMP_CODE = 0x00010000,
 382     CPU_DUMP_FPU  = 0x00020000,
 383     CPU_DUMP_CCOP = 0x00040000,
 384 };
 385
 386 /**
 387  * cpu_dump_state:
 388  * @cpu: The CPU whose state is to be dumped.
 389  * @f: File to dump to.
 390  * @cpu_fprintf: Function to dump with.
 391  * @flags: Flags what to dump.
 392  *
 393  * Dumps CPU state.
 394  */
 395 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 396                     int flags);
 397
 398 /**
 399  * cpu_dump_statistics:
 400  * @cpu: The CPU whose state is to be dumped.
 401  * @f: File to dump to.
 402  * @cpu_fprintf: Function to dump with.
 403  * @flags: Flags what to dump.
 404  *
 405  * Dumps CPU statistics.
 406  */
 407 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 408                          int flags);
 409
 410 #ifndef CONFIG_USER_ONLY
 411 /**
 412  * cpu_get_phys_page_debug:
 413  * @cpu: The CPU to obtain the physical page address for.
 414  * @addr: The virtual address.
 415  *
 416  * Obtains the physical page corresponding to a virtual one.
 417  * Use it only for debugging because no protection checks are done.
 418  *
 419  * Returns: Corresponding physical page address or -1 if no page found.
 420  */
 421 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
 422 {
 423     CPUClass *cc = CPU_GET_CLASS(cpu);
 424
 425     return cc->get_phys_page_debug(cpu, addr);
 426 }
 427 #endif
 428
 429 /**
 430  * cpu_reset:
 431  * @cpu: The CPU whose state is to be reset.
 432  */
 433 void cpu_reset(CPUState *cpu);
 434
 435 /**
 436  * cpu_class_by_name:
 437  * @typename: The CPU base type.
 438  * @cpu_model: The model string without any parameters.
 439  *
 440  * Looks up a CPU #ObjectClass matching name @cpu_model.
 441  *
 442  * Returns: A #CPUClass or %NULL if not matching class is found.
 443  */
 444 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
 445
 446 /**
 447  * cpu_generic_init:
 448  * @typename: The CPU base type.
 449  * @cpu_model: The model string including optional parameters.
 450  *
 451  * Instantiates a CPU, processes optional parameters and realizes the CPU.
 452  *
 453  * Returns: A #CPUState or %NULL if an error occurred.
 454  */
 455 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
 456
 457 /**
 458  * cpu_has_work:
 459  * @cpu: The vCPU to check.
 460  *
 461  * Checks whether the CPU has work to do.
 462  *
 463  * Returns: %true if the CPU has work, %false otherwise.
 464  */
 465 static inline bool cpu_has_work(CPUState *cpu)
 466 {
 467     CPUClass *cc = CPU_GET_CLASS(cpu);
 468
 469     g_assert(cc->has_work);
 470     return cc->has_work(cpu);
 471 }
 472
 473 /**
 474  * qemu_cpu_is_self:
 475  * @cpu: The vCPU to check against.
 476  *
 477  * Checks whether the caller is executing on the vCPU thread.
 478  *
 479  * Returns: %true if called from @cpu's thread, %false otherwise.
 480  */
 481 bool qemu_cpu_is_self(CPUState *cpu);
 482
 483 /**
 484  * qemu_cpu_kick:
 485  * @cpu: The vCPU to kick.
 486  *
 487  * Kicks @cpu's thread.
 488  */
 489 void qemu_cpu_kick(CPUState *cpu);
 490
 491 /**
 492  * cpu_is_stopped:
 493  * @cpu: The CPU to check.
 494  *
 495  * Checks whether the CPU is stopped.
 496  *
 497  * Returns: %true if run state is not running or if artificially stopped;
 498  * %false otherwise.
 499  */
 500 bool cpu_is_stopped(CPUState *cpu);
 501
 502 /**
 503  * run_on_cpu:
 504  * @cpu: The vCPU to run on.
 505  * @func: The function to be executed.
 506  * @data: Data to pass to the function.
 507  *
 508  * Schedules the function @func for execution on the vCPU @cpu.
 509  */
 510 void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 511
 512 /**
 513  * async_run_on_cpu:
 514  * @cpu: The vCPU to run on.
 515  * @func: The function to be executed.
 516  * @data: Data to pass to the function.
 517  *
 518  * Schedules the function @func for execution on the vCPU @cpu asynchronously.
 519  */
 520 void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 521
 522 /**
 523  * qemu_get_cpu:
 524  * @index: The CPUState@cpu_index value of the CPU to obtain.
 525  *
 526  * Gets a CPU matching @index.
 527  *
 528  * Returns: The CPU or %NULL if there is no matching CPU.
 529  */
 530 CPUState *qemu_get_cpu(int index);
 531
 532 /**
 533  * cpu_exists:
 534  * @id: Guest-exposed CPU ID to lookup.
 535  *
 536  * Search for CPU with specified ID.
 537  *
 538  * Returns: %true - CPU is found, %false - CPU isn't found.
 539  */
 540 bool cpu_exists(int64_t id);
 541
 542 #ifndef CONFIG_USER_ONLY
 543
 544 typedef void (*CPUInterruptHandler)(CPUState *, int);
 545
 546 extern CPUInterruptHandler cpu_interrupt_handler;
 547
 548 /**
 549  * cpu_interrupt:
 550  * @cpu: The CPU to set an interrupt on.
 551  * @mask: The interupts to set.
 552  *
 553  * Invokes the interrupt handler.
 554  */
 555 static inline void cpu_interrupt(CPUState *cpu, int mask)
 556 {
 557     cpu_interrupt_handler(cpu, mask);
 558 }
 559
 560 #else /* USER_ONLY */
 561
 562 void cpu_interrupt(CPUState *cpu, int mask);
 563
 564 #endif /* USER_ONLY */
 565
 566 #ifdef CONFIG_SOFTMMU
 567 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 568                                          bool is_write, bool is_exec,
 569                                          int opaque, unsigned size)
 570 {
 571     CPUClass *cc = CPU_GET_CLASS(cpu);
 572
 573     if (cc->do_unassigned_access) {
 574         cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
 575     }
 576 }
 577
 578 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
 579                                         int is_write, int is_user,
 580                                         uintptr_t retaddr)
 581 {
 582     CPUClass *cc = CPU_GET_CLASS(cpu);
 583
 584     return cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
 585 }
 586 #endif
 587
 588 /**
 589  * cpu_reset_interrupt:
 590  * @cpu: The CPU to clear the interrupt on.
 591  * @mask: The interrupt mask to clear.
 592  *
 593  * Resets interrupts on the vCPU @cpu.
 594  */
 595 void cpu_reset_interrupt(CPUState *cpu, int mask);
 596
 597 /**
 598  * cpu_exit:
 599  * @cpu: The CPU to exit.
 600  *
 601  * Requests the CPU @cpu to exit execution.
 602  */
 603 void cpu_exit(CPUState *cpu);
 604
 605 /**
 606  * cpu_resume:
 607  * @cpu: The CPU to resume.
 608  *
 609  * Resumes CPU, i.e. puts CPU into runnable state.
 610  */
 611 void cpu_resume(CPUState *cpu);
 612
 613 /**
 614  * qemu_init_vcpu:
 615  * @cpu: The vCPU to initialize.
 616  *
 617  * Initializes a vCPU.
 618  */
 619 void qemu_init_vcpu(CPUState *cpu);
 620
 621 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 622 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 623 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 624
 625 /**
 626  * cpu_single_step:
 627  * @cpu: CPU to the flags for.
 628  * @enabled: Flags to enable.
 629  *
 630  * Enables or disables single-stepping for @cpu.
 631  */
 632 void cpu_single_step(CPUState *cpu, int enabled);
 633
 634 /* Breakpoint/watchpoint flags */
 635 #define BP_MEM_READ           0x01
 636 #define BP_MEM_WRITE          0x02
 637 #define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
 638 #define BP_STOP_BEFORE_ACCESS 0x04
 639 /* 0x08 currently unused */
 640 #define BP_GDB                0x10
 641 #define BP_CPU                0x20
 642 #define BP_WATCHPOINT_HIT_READ 0x40
 643 #define BP_WATCHPOINT_HIT_WRITE 0x80
 644 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
 645
 646 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
 647                           CPUBreakpoint **breakpoint);
 648 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
 649 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
 650 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
 651
 652 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
 653                           int flags, CPUWatchpoint **watchpoint);
 654 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
 655                           vaddr len, int flags);
 656 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
 657 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
 658
 659 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
 660     GCC_FMT_ATTR(2, 3);
 661
 662 #ifdef CONFIG_SOFTMMU
 663 extern const struct VMStateDescription vmstate_cpu_common;
 664 #else
 665 #define vmstate_cpu_common vmstate_dummy
 666 #endif
 667
 668 #define VMSTATE_CPU() {                                                     \
 669     .name = "parent_obj",                                                   \
 670     .size = sizeof(CPUState),                                               \
 671     .vmsd = &vmstate_cpu_common,                                            \
 672     .flags = VMS_STRUCT,                                                    \
 673     .offset = 0,                                                            \
 674 }
 675
 676 #endif