4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
22 #include "internals.h"
23 #include "qemu-common.h"
24 #include "hw/qdev-properties.h"
25 #include "qapi/qmp/qerror.h"
26 #if !defined(CONFIG_USER_ONLY)
27 #include "hw/loader.h"
29 #include "hw/arm/arm.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/kvm.h"
34 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
36 ARMCPU
*cpu
= ARM_CPU(cs
);
38 cpu
->env
.regs
[15] = value
;
41 static bool arm_cpu_has_work(CPUState
*cs
)
43 ARMCPU
*cpu
= ARM_CPU(cs
);
45 return !cpu
->powered_off
46 && cs
->interrupt_request
&
47 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
48 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
49 | CPU_INTERRUPT_EXITTB
);
52 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
54 /* Reset a single ARMCPRegInfo register */
55 ARMCPRegInfo
*ri
= value
;
58 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
63 ri
->resetfn(&cpu
->env
, ri
);
67 /* A zero offset is never possible as it would be regs[0]
68 * so we use it to indicate that reset is being handled elsewhere.
69 * This is basically only used for fields in non-core coprocessors
70 * (like the pxa2xx ones).
72 if (!ri
->fieldoffset
) {
76 if (cpreg_field_is_64bit(ri
)) {
77 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
79 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
83 /* CPUClass::reset() */
84 static void arm_cpu_reset(CPUState
*s
)
86 ARMCPU
*cpu
= ARM_CPU(s
);
87 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
88 CPUARMState
*env
= &cpu
->env
;
92 memset(env
, 0, offsetof(CPUARMState
, features
));
93 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
94 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
95 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
96 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
97 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
99 cpu
->powered_off
= cpu
->start_powered_off
;
100 s
->halted
= cpu
->start_powered_off
;
102 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
103 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
106 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
107 /* 64 bit CPUs always start in 64 bit mode */
109 #if defined(CONFIG_USER_ONLY)
110 env
->pstate
= PSTATE_MODE_EL0t
;
111 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
112 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
113 /* and to the FP/Neon instructions */
114 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
116 /* Reset into the highest available EL */
117 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
118 env
->pstate
= PSTATE_MODE_EL3h
;
119 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
120 env
->pstate
= PSTATE_MODE_EL2h
;
122 env
->pstate
= PSTATE_MODE_EL1h
;
124 env
->pc
= cpu
->rvbar
;
127 #if defined(CONFIG_USER_ONLY)
128 /* Userspace expects access to cp10 and cp11 for FP/Neon */
129 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
133 #if defined(CONFIG_USER_ONLY)
134 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
135 /* For user mode we must enable access to coprocessors */
136 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
137 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
138 env
->cp15
.c15_cpar
= 3;
139 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
140 env
->cp15
.c15_cpar
= 1;
143 /* SVC mode with interrupts disabled. */
144 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
145 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
146 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
147 * clear at reset. Initial SP and PC are loaded from ROM.
150 uint32_t initial_msp
; /* Loaded from 0x0 */
151 uint32_t initial_pc
; /* Loaded from 0x4 */
154 env
->daif
&= ~PSTATE_I
;
157 /* Address zero is covered by ROM which hasn't yet been
158 * copied into physical memory.
160 initial_msp
= ldl_p(rom
);
161 initial_pc
= ldl_p(rom
+ 4);
163 /* Address zero not covered by a ROM blob, or the ROM blob
164 * is in non-modifiable memory and this is a second reset after
165 * it got copied into memory. In the latter case, rom_ptr
166 * will return a NULL pointer and we should use ldl_phys instead.
168 initial_msp
= ldl_phys(s
->as
, 0);
169 initial_pc
= ldl_phys(s
->as
, 4);
172 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
173 env
->regs
[15] = initial_pc
& ~1;
174 env
->thumb
= initial_pc
& 1;
177 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
178 * executing as AArch32 then check if highvecs are enabled and
179 * adjust the PC accordingly.
181 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
182 env
->regs
[15] = 0xFFFF0000;
185 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
187 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
188 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
189 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
190 set_float_detect_tininess(float_tininess_before_rounding
,
191 &env
->vfp
.fp_status
);
192 set_float_detect_tininess(float_tininess_before_rounding
,
193 &env
->vfp
.standard_fp_status
);
196 #ifndef CONFIG_USER_ONLY
198 kvm_arm_reset_vcpu(cpu
);
202 hw_breakpoint_update_all(cpu
);
203 hw_watchpoint_update_all(cpu
);
206 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
208 CPUClass
*cc
= CPU_GET_CLASS(cs
);
209 CPUARMState
*env
= cs
->env_ptr
;
210 uint32_t cur_el
= arm_current_el(env
);
211 bool secure
= arm_is_secure(env
);
216 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
218 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
219 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
220 cs
->exception_index
= excp_idx
;
221 env
->exception
.target_el
= target_el
;
222 cc
->do_interrupt(cs
);
226 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
228 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
229 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
230 cs
->exception_index
= excp_idx
;
231 env
->exception
.target_el
= target_el
;
232 cc
->do_interrupt(cs
);
236 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
237 excp_idx
= EXCP_VIRQ
;
239 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
240 cs
->exception_index
= excp_idx
;
241 env
->exception
.target_el
= target_el
;
242 cc
->do_interrupt(cs
);
246 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
247 excp_idx
= EXCP_VFIQ
;
249 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
250 cs
->exception_index
= excp_idx
;
251 env
->exception
.target_el
= target_el
;
252 cc
->do_interrupt(cs
);
260 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
261 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
263 CPUClass
*cc
= CPU_GET_CLASS(cs
);
264 ARMCPU
*cpu
= ARM_CPU(cs
);
265 CPUARMState
*env
= &cpu
->env
;
269 if (interrupt_request
& CPU_INTERRUPT_FIQ
270 && !(env
->daif
& PSTATE_F
)) {
271 cs
->exception_index
= EXCP_FIQ
;
272 cc
->do_interrupt(cs
);
275 /* ARMv7-M interrupt return works by loading a magic value
276 * into the PC. On real hardware the load causes the
277 * return to occur. The qemu implementation performs the
278 * jump normally, then does the exception return when the
279 * CPU tries to execute code at the magic address.
280 * This will cause the magic PC value to be pushed to
281 * the stack if an interrupt occurred at the wrong time.
282 * We avoid this by disabling interrupts when
283 * pc contains a magic address.
285 if (interrupt_request
& CPU_INTERRUPT_HARD
286 && !(env
->daif
& PSTATE_I
)
287 && (env
->regs
[15] < 0xfffffff0)) {
288 cs
->exception_index
= EXCP_IRQ
;
289 cc
->do_interrupt(cs
);
296 #ifndef CONFIG_USER_ONLY
297 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
299 ARMCPU
*cpu
= opaque
;
300 CPUARMState
*env
= &cpu
->env
;
301 CPUState
*cs
= CPU(cpu
);
302 static const int mask
[] = {
303 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
304 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
305 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
306 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
312 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
313 hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
320 cpu_interrupt(cs
, mask
[irq
]);
322 cpu_reset_interrupt(cs
, mask
[irq
]);
326 hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq
);
330 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
333 ARMCPU
*cpu
= opaque
;
334 CPUState
*cs
= CPU(cpu
);
335 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
339 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
342 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
345 hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq
);
347 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
348 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
352 static bool arm_cpu_is_big_endian(CPUState
*cs
)
354 ARMCPU
*cpu
= ARM_CPU(cs
);
355 CPUARMState
*env
= &cpu
->env
;
358 cpu_synchronize_state(cs
);
360 /* In 32bit guest endianness is determined by looking at CPSR's E bit */
362 return (env
->uncached_cpsr
& CPSR_E
) ? 1 : 0;
365 cur_el
= arm_current_el(env
);
368 return (env
->cp15
.sctlr_el
[1] & SCTLR_E0E
) != 0;
371 return (env
->cp15
.sctlr_el
[cur_el
] & SCTLR_EE
) != 0;
376 static inline void set_feature(CPUARMState
*env
, int feature
)
378 env
->features
|= 1ULL << feature
;
381 static inline void unset_feature(CPUARMState
*env
, int feature
)
383 env
->features
&= ~(1ULL << feature
);
386 #define ARM_CPUS_PER_CLUSTER 8
388 static void arm_cpu_initfn(Object
*obj
)
390 CPUState
*cs
= CPU(obj
);
391 ARMCPU
*cpu
= ARM_CPU(obj
);
395 cs
->env_ptr
= &cpu
->env
;
396 cpu_exec_init(&cpu
->env
);
397 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
400 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
401 * We don't support setting cluster ID ([16..23]) (known as Aff2
402 * in later ARM ARM versions), or any of the higher affinity level fields,
403 * so these bits always RAZ.
405 Aff1
= cs
->cpu_index
/ ARM_CPUS_PER_CLUSTER
;
406 Aff0
= cs
->cpu_index
% ARM_CPUS_PER_CLUSTER
;
407 cpu
->mp_affinity
= (Aff1
<< 8) | Aff0
;
409 #ifndef CONFIG_USER_ONLY
410 /* Our inbound IRQ and FIQ lines */
412 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
413 * the same interface as non-KVM CPUs.
415 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
417 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
420 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
421 arm_gt_ptimer_cb
, cpu
);
422 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
423 arm_gt_vtimer_cb
, cpu
);
424 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
425 ARRAY_SIZE(cpu
->gt_timer_outputs
));
428 /* DTB consumers generally don't in fact care what the 'compatible'
429 * string is, so always provide some string and trust that a hypothetical
430 * picky DTB consumer will also provide a helpful error message.
432 cpu
->dtb_compatible
= "qemu,unknown";
433 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
434 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
437 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
440 arm_translate_init();
445 static Property arm_cpu_reset_cbar_property
=
446 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
448 static Property arm_cpu_reset_hivecs_property
=
449 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
451 static Property arm_cpu_rvbar_property
=
452 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
454 static Property arm_cpu_has_el3_property
=
455 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
457 static Property arm_cpu_has_mpu_property
=
458 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
460 static Property arm_cpu_pmsav7_dregion_property
=
461 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU
, pmsav7_dregion
, 16);
463 static void arm_cpu_post_init(Object
*obj
)
465 ARMCPU
*cpu
= ARM_CPU(obj
);
467 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
468 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
469 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
473 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
474 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
478 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
479 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
483 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
484 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
485 * prevent "has_el3" from existing on CPUs which cannot support EL3.
487 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
491 if (arm_feature(&cpu
->env
, ARM_FEATURE_MPU
)) {
492 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
494 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
495 qdev_property_add_static(DEVICE(obj
),
496 &arm_cpu_pmsav7_dregion_property
,
503 static void arm_cpu_finalizefn(Object
*obj
)
505 ARMCPU
*cpu
= ARM_CPU(obj
);
506 g_hash_table_destroy(cpu
->cp_regs
);
509 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
511 CPUState
*cs
= CPU(dev
);
512 ARMCPU
*cpu
= ARM_CPU(dev
);
513 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
514 CPUARMState
*env
= &cpu
->env
;
516 /* Some features automatically imply others: */
517 if (arm_feature(env
, ARM_FEATURE_V8
)) {
518 set_feature(env
, ARM_FEATURE_V7
);
519 set_feature(env
, ARM_FEATURE_ARM_DIV
);
520 set_feature(env
, ARM_FEATURE_LPAE
);
522 if (arm_feature(env
, ARM_FEATURE_V7
)) {
523 set_feature(env
, ARM_FEATURE_VAPA
);
524 set_feature(env
, ARM_FEATURE_THUMB2
);
525 set_feature(env
, ARM_FEATURE_MPIDR
);
526 if (!arm_feature(env
, ARM_FEATURE_M
)) {
527 set_feature(env
, ARM_FEATURE_V6K
);
529 set_feature(env
, ARM_FEATURE_V6
);
532 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
533 set_feature(env
, ARM_FEATURE_V6
);
534 set_feature(env
, ARM_FEATURE_MVFR
);
536 if (arm_feature(env
, ARM_FEATURE_V6
)) {
537 set_feature(env
, ARM_FEATURE_V5
);
538 if (!arm_feature(env
, ARM_FEATURE_M
)) {
539 set_feature(env
, ARM_FEATURE_AUXCR
);
542 if (arm_feature(env
, ARM_FEATURE_V5
)) {
543 set_feature(env
, ARM_FEATURE_V4T
);
545 if (arm_feature(env
, ARM_FEATURE_M
)) {
546 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
548 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
549 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
551 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
552 set_feature(env
, ARM_FEATURE_VFP3
);
553 set_feature(env
, ARM_FEATURE_VFP_FP16
);
555 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
556 set_feature(env
, ARM_FEATURE_VFP
);
558 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
559 set_feature(env
, ARM_FEATURE_V7MP
);
560 set_feature(env
, ARM_FEATURE_PXN
);
562 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
563 set_feature(env
, ARM_FEATURE_CBAR
);
565 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
566 !arm_feature(env
, ARM_FEATURE_M
)) {
567 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
570 if (cpu
->reset_hivecs
) {
571 cpu
->reset_sctlr
|= (1 << 13);
575 /* If the has_el3 CPU property is disabled then we need to disable the
578 unset_feature(env
, ARM_FEATURE_EL3
);
580 /* Disable the security extension feature bits in the processor feature
581 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
583 cpu
->id_pfr1
&= ~0xf0;
584 cpu
->id_aa64pfr0
&= ~0xf000;
588 unset_feature(env
, ARM_FEATURE_MPU
);
591 if (arm_feature(env
, ARM_FEATURE_MPU
) &&
592 arm_feature(env
, ARM_FEATURE_V7
)) {
593 uint32_t nr
= cpu
->pmsav7_dregion
;
596 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
"\n", nr
);
601 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
602 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
603 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
607 register_cp_regs_for_features(cpu
);
608 arm_cpu_register_gdb_regs_for_features(cpu
);
610 init_cpreg_list(cpu
);
615 acc
->parent_realize(dev
, errp
);
618 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
628 cpuname
= g_strsplit(cpu_model
, ",", 1);
629 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpuname
[0]);
630 oc
= object_class_by_name(typename
);
633 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
634 object_class_is_abstract(oc
)) {
640 /* CPU models. These are not needed for the AArch64 linux-user build. */
641 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
643 static void arm926_initfn(Object
*obj
)
645 ARMCPU
*cpu
= ARM_CPU(obj
);
647 cpu
->dtb_compatible
= "arm,arm926";
648 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
649 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
650 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
651 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
652 cpu
->midr
= 0x41069265;
653 cpu
->reset_fpsid
= 0x41011090;
654 cpu
->ctr
= 0x1dd20d2;
655 cpu
->reset_sctlr
= 0x00090078;
658 static void arm946_initfn(Object
*obj
)
660 ARMCPU
*cpu
= ARM_CPU(obj
);
662 cpu
->dtb_compatible
= "arm,arm946";
663 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
664 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
665 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
666 cpu
->midr
= 0x41059461;
667 cpu
->ctr
= 0x0f004006;
668 cpu
->reset_sctlr
= 0x00000078;
671 static void arm1026_initfn(Object
*obj
)
673 ARMCPU
*cpu
= ARM_CPU(obj
);
675 cpu
->dtb_compatible
= "arm,arm1026";
676 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
677 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
678 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
679 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
680 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
681 cpu
->midr
= 0x4106a262;
682 cpu
->reset_fpsid
= 0x410110a0;
683 cpu
->ctr
= 0x1dd20d2;
684 cpu
->reset_sctlr
= 0x00090078;
685 cpu
->reset_auxcr
= 1;
687 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
688 ARMCPRegInfo ifar
= {
689 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
691 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
694 define_one_arm_cp_reg(cpu
, &ifar
);
698 static void arm1136_r2_initfn(Object
*obj
)
700 ARMCPU
*cpu
= ARM_CPU(obj
);
701 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
702 * older core than plain "arm1136". In particular this does not
703 * have the v6K features.
704 * These ID register values are correct for 1136 but may be wrong
705 * for 1136_r2 (in particular r0p2 does not actually implement most
706 * of the ID registers).
709 cpu
->dtb_compatible
= "arm,arm1136";
710 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
711 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
712 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
713 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
714 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
715 cpu
->midr
= 0x4107b362;
716 cpu
->reset_fpsid
= 0x410120b4;
717 cpu
->mvfr0
= 0x11111111;
718 cpu
->mvfr1
= 0x00000000;
719 cpu
->ctr
= 0x1dd20d2;
720 cpu
->reset_sctlr
= 0x00050078;
721 cpu
->id_pfr0
= 0x111;
725 cpu
->id_mmfr0
= 0x01130003;
726 cpu
->id_mmfr1
= 0x10030302;
727 cpu
->id_mmfr2
= 0x01222110;
728 cpu
->id_isar0
= 0x00140011;
729 cpu
->id_isar1
= 0x12002111;
730 cpu
->id_isar2
= 0x11231111;
731 cpu
->id_isar3
= 0x01102131;
732 cpu
->id_isar4
= 0x141;
733 cpu
->reset_auxcr
= 7;
736 static void arm1136_initfn(Object
*obj
)
738 ARMCPU
*cpu
= ARM_CPU(obj
);
740 cpu
->dtb_compatible
= "arm,arm1136";
741 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
742 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
743 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
744 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
745 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
746 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
747 cpu
->midr
= 0x4117b363;
748 cpu
->reset_fpsid
= 0x410120b4;
749 cpu
->mvfr0
= 0x11111111;
750 cpu
->mvfr1
= 0x00000000;
751 cpu
->ctr
= 0x1dd20d2;
752 cpu
->reset_sctlr
= 0x00050078;
753 cpu
->id_pfr0
= 0x111;
757 cpu
->id_mmfr0
= 0x01130003;
758 cpu
->id_mmfr1
= 0x10030302;
759 cpu
->id_mmfr2
= 0x01222110;
760 cpu
->id_isar0
= 0x00140011;
761 cpu
->id_isar1
= 0x12002111;
762 cpu
->id_isar2
= 0x11231111;
763 cpu
->id_isar3
= 0x01102131;
764 cpu
->id_isar4
= 0x141;
765 cpu
->reset_auxcr
= 7;
768 static void arm1176_initfn(Object
*obj
)
770 ARMCPU
*cpu
= ARM_CPU(obj
);
772 cpu
->dtb_compatible
= "arm,arm1176";
773 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
774 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
775 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
776 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
777 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
778 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
779 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
780 cpu
->midr
= 0x410fb767;
781 cpu
->reset_fpsid
= 0x410120b5;
782 cpu
->mvfr0
= 0x11111111;
783 cpu
->mvfr1
= 0x00000000;
784 cpu
->ctr
= 0x1dd20d2;
785 cpu
->reset_sctlr
= 0x00050078;
786 cpu
->id_pfr0
= 0x111;
790 cpu
->id_mmfr0
= 0x01130003;
791 cpu
->id_mmfr1
= 0x10030302;
792 cpu
->id_mmfr2
= 0x01222100;
793 cpu
->id_isar0
= 0x0140011;
794 cpu
->id_isar1
= 0x12002111;
795 cpu
->id_isar2
= 0x11231121;
796 cpu
->id_isar3
= 0x01102131;
797 cpu
->id_isar4
= 0x01141;
798 cpu
->reset_auxcr
= 7;
801 static void arm11mpcore_initfn(Object
*obj
)
803 ARMCPU
*cpu
= ARM_CPU(obj
);
805 cpu
->dtb_compatible
= "arm,arm11mpcore";
806 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
807 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
808 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
809 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
810 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
811 cpu
->midr
= 0x410fb022;
812 cpu
->reset_fpsid
= 0x410120b4;
813 cpu
->mvfr0
= 0x11111111;
814 cpu
->mvfr1
= 0x00000000;
815 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
816 cpu
->id_pfr0
= 0x111;
820 cpu
->id_mmfr0
= 0x01100103;
821 cpu
->id_mmfr1
= 0x10020302;
822 cpu
->id_mmfr2
= 0x01222000;
823 cpu
->id_isar0
= 0x00100011;
824 cpu
->id_isar1
= 0x12002111;
825 cpu
->id_isar2
= 0x11221011;
826 cpu
->id_isar3
= 0x01102131;
827 cpu
->id_isar4
= 0x141;
828 cpu
->reset_auxcr
= 1;
831 static void cortex_m3_initfn(Object
*obj
)
833 ARMCPU
*cpu
= ARM_CPU(obj
);
834 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
835 set_feature(&cpu
->env
, ARM_FEATURE_M
);
836 cpu
->midr
= 0x410fc231;
839 static void cortex_m4_initfn(Object
*obj
)
841 ARMCPU
*cpu
= ARM_CPU(obj
);
843 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
844 set_feature(&cpu
->env
, ARM_FEATURE_M
);
845 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
846 cpu
->midr
= 0x410fc240; /* r0p0 */
848 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
850 CPUClass
*cc
= CPU_CLASS(oc
);
852 #ifndef CONFIG_USER_ONLY
853 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
856 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
859 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
860 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
861 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
862 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
863 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
867 static void cortex_a8_initfn(Object
*obj
)
869 ARMCPU
*cpu
= ARM_CPU(obj
);
871 cpu
->dtb_compatible
= "arm,cortex-a8";
872 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
873 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
874 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
875 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
876 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
877 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
878 cpu
->midr
= 0x410fc080;
879 cpu
->reset_fpsid
= 0x410330c0;
880 cpu
->mvfr0
= 0x11110222;
881 cpu
->mvfr1
= 0x00011100;
882 cpu
->ctr
= 0x82048004;
883 cpu
->reset_sctlr
= 0x00c50078;
884 cpu
->id_pfr0
= 0x1031;
886 cpu
->id_dfr0
= 0x400;
888 cpu
->id_mmfr0
= 0x31100003;
889 cpu
->id_mmfr1
= 0x20000000;
890 cpu
->id_mmfr2
= 0x01202000;
891 cpu
->id_mmfr3
= 0x11;
892 cpu
->id_isar0
= 0x00101111;
893 cpu
->id_isar1
= 0x12112111;
894 cpu
->id_isar2
= 0x21232031;
895 cpu
->id_isar3
= 0x11112131;
896 cpu
->id_isar4
= 0x00111142;
897 cpu
->dbgdidr
= 0x15141000;
898 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
899 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
900 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
901 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
902 cpu
->reset_auxcr
= 2;
903 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
906 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
907 /* power_control should be set to maximum latency. Again,
908 * default to 0 and set by private hook
910 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
911 .access
= PL1_RW
, .resetvalue
= 0,
912 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
913 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
914 .access
= PL1_RW
, .resetvalue
= 0,
915 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
916 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
917 .access
= PL1_RW
, .resetvalue
= 0,
918 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
919 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
920 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
921 /* TLB lockdown control */
922 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
923 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
924 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
925 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
926 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
927 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
928 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
929 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
930 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
931 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
935 static void cortex_a9_initfn(Object
*obj
)
937 ARMCPU
*cpu
= ARM_CPU(obj
);
939 cpu
->dtb_compatible
= "arm,cortex-a9";
940 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
941 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
942 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
943 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
944 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
945 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
946 /* Note that A9 supports the MP extensions even for
947 * A9UP and single-core A9MP (which are both different
948 * and valid configurations; we don't model A9UP).
950 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
951 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
952 cpu
->midr
= 0x410fc090;
953 cpu
->reset_fpsid
= 0x41033090;
954 cpu
->mvfr0
= 0x11110222;
955 cpu
->mvfr1
= 0x01111111;
956 cpu
->ctr
= 0x80038003;
957 cpu
->reset_sctlr
= 0x00c50078;
958 cpu
->id_pfr0
= 0x1031;
960 cpu
->id_dfr0
= 0x000;
962 cpu
->id_mmfr0
= 0x00100103;
963 cpu
->id_mmfr1
= 0x20000000;
964 cpu
->id_mmfr2
= 0x01230000;
965 cpu
->id_mmfr3
= 0x00002111;
966 cpu
->id_isar0
= 0x00101111;
967 cpu
->id_isar1
= 0x13112111;
968 cpu
->id_isar2
= 0x21232041;
969 cpu
->id_isar3
= 0x11112131;
970 cpu
->id_isar4
= 0x00111142;
971 cpu
->dbgdidr
= 0x35141000;
972 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
973 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
974 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
975 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
978 #ifndef CONFIG_USER_ONLY
979 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
981 /* Linux wants the number of processors from here.
982 * Might as well set the interrupt-controller bit too.
984 return ((smp_cpus
- 1) << 24) | (1 << 23);
988 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
989 #ifndef CONFIG_USER_ONLY
990 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
991 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
992 .writefn
= arm_cp_write_ignore
, },
994 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
995 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
999 static void cortex_a15_initfn(Object
*obj
)
1001 ARMCPU
*cpu
= ARM_CPU(obj
);
1003 cpu
->dtb_compatible
= "arm,cortex-a15";
1004 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1005 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1006 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1007 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1008 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1009 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1010 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1011 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1012 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1013 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1014 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1015 cpu
->midr
= 0x412fc0f1;
1016 cpu
->reset_fpsid
= 0x410430f0;
1017 cpu
->mvfr0
= 0x10110222;
1018 cpu
->mvfr1
= 0x11111111;
1019 cpu
->ctr
= 0x8444c004;
1020 cpu
->reset_sctlr
= 0x00c50078;
1021 cpu
->id_pfr0
= 0x00001131;
1022 cpu
->id_pfr1
= 0x00011011;
1023 cpu
->id_dfr0
= 0x02010555;
1024 cpu
->id_afr0
= 0x00000000;
1025 cpu
->id_mmfr0
= 0x10201105;
1026 cpu
->id_mmfr1
= 0x20000000;
1027 cpu
->id_mmfr2
= 0x01240000;
1028 cpu
->id_mmfr3
= 0x02102211;
1029 cpu
->id_isar0
= 0x02101110;
1030 cpu
->id_isar1
= 0x13112111;
1031 cpu
->id_isar2
= 0x21232041;
1032 cpu
->id_isar3
= 0x11112131;
1033 cpu
->id_isar4
= 0x10011142;
1034 cpu
->dbgdidr
= 0x3515f021;
1035 cpu
->clidr
= 0x0a200023;
1036 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1037 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1038 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1039 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1042 static void ti925t_initfn(Object
*obj
)
1044 ARMCPU
*cpu
= ARM_CPU(obj
);
1045 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1046 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1047 cpu
->midr
= ARM_CPUID_TI925T
;
1048 cpu
->ctr
= 0x5109149;
1049 cpu
->reset_sctlr
= 0x00000070;
1052 static void sa1100_initfn(Object
*obj
)
1054 ARMCPU
*cpu
= ARM_CPU(obj
);
1056 cpu
->dtb_compatible
= "intel,sa1100";
1057 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1058 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1059 cpu
->midr
= 0x4401A11B;
1060 cpu
->reset_sctlr
= 0x00000070;
1063 static void sa1110_initfn(Object
*obj
)
1065 ARMCPU
*cpu
= ARM_CPU(obj
);
1066 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1067 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1068 cpu
->midr
= 0x6901B119;
1069 cpu
->reset_sctlr
= 0x00000070;
1072 static void pxa250_initfn(Object
*obj
)
1074 ARMCPU
*cpu
= ARM_CPU(obj
);
1076 cpu
->dtb_compatible
= "marvell,xscale";
1077 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1078 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1079 cpu
->midr
= 0x69052100;
1080 cpu
->ctr
= 0xd172172;
1081 cpu
->reset_sctlr
= 0x00000078;
1084 static void pxa255_initfn(Object
*obj
)
1086 ARMCPU
*cpu
= ARM_CPU(obj
);
1088 cpu
->dtb_compatible
= "marvell,xscale";
1089 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1090 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1091 cpu
->midr
= 0x69052d00;
1092 cpu
->ctr
= 0xd172172;
1093 cpu
->reset_sctlr
= 0x00000078;
1096 static void pxa260_initfn(Object
*obj
)
1098 ARMCPU
*cpu
= ARM_CPU(obj
);
1100 cpu
->dtb_compatible
= "marvell,xscale";
1101 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1102 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1103 cpu
->midr
= 0x69052903;
1104 cpu
->ctr
= 0xd172172;
1105 cpu
->reset_sctlr
= 0x00000078;
1108 static void pxa261_initfn(Object
*obj
)
1110 ARMCPU
*cpu
= ARM_CPU(obj
);
1112 cpu
->dtb_compatible
= "marvell,xscale";
1113 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1114 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1115 cpu
->midr
= 0x69052d05;
1116 cpu
->ctr
= 0xd172172;
1117 cpu
->reset_sctlr
= 0x00000078;
1120 static void pxa262_initfn(Object
*obj
)
1122 ARMCPU
*cpu
= ARM_CPU(obj
);
1124 cpu
->dtb_compatible
= "marvell,xscale";
1125 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1126 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1127 cpu
->midr
= 0x69052d06;
1128 cpu
->ctr
= 0xd172172;
1129 cpu
->reset_sctlr
= 0x00000078;
1132 static void pxa270a0_initfn(Object
*obj
)
1134 ARMCPU
*cpu
= ARM_CPU(obj
);
1136 cpu
->dtb_compatible
= "marvell,xscale";
1137 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1138 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1139 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1140 cpu
->midr
= 0x69054110;
1141 cpu
->ctr
= 0xd172172;
1142 cpu
->reset_sctlr
= 0x00000078;
1145 static void pxa270a1_initfn(Object
*obj
)
1147 ARMCPU
*cpu
= ARM_CPU(obj
);
1149 cpu
->dtb_compatible
= "marvell,xscale";
1150 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1151 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1152 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1153 cpu
->midr
= 0x69054111;
1154 cpu
->ctr
= 0xd172172;
1155 cpu
->reset_sctlr
= 0x00000078;
1158 static void pxa270b0_initfn(Object
*obj
)
1160 ARMCPU
*cpu
= ARM_CPU(obj
);
1162 cpu
->dtb_compatible
= "marvell,xscale";
1163 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1164 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1165 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1166 cpu
->midr
= 0x69054112;
1167 cpu
->ctr
= 0xd172172;
1168 cpu
->reset_sctlr
= 0x00000078;
1171 static void pxa270b1_initfn(Object
*obj
)
1173 ARMCPU
*cpu
= ARM_CPU(obj
);
1175 cpu
->dtb_compatible
= "marvell,xscale";
1176 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1177 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1178 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1179 cpu
->midr
= 0x69054113;
1180 cpu
->ctr
= 0xd172172;
1181 cpu
->reset_sctlr
= 0x00000078;
1184 static void pxa270c0_initfn(Object
*obj
)
1186 ARMCPU
*cpu
= ARM_CPU(obj
);
1188 cpu
->dtb_compatible
= "marvell,xscale";
1189 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1190 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1191 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1192 cpu
->midr
= 0x69054114;
1193 cpu
->ctr
= 0xd172172;
1194 cpu
->reset_sctlr
= 0x00000078;
1197 static void pxa270c5_initfn(Object
*obj
)
1199 ARMCPU
*cpu
= ARM_CPU(obj
);
1201 cpu
->dtb_compatible
= "marvell,xscale";
1202 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1203 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1204 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1205 cpu
->midr
= 0x69054117;
1206 cpu
->ctr
= 0xd172172;
1207 cpu
->reset_sctlr
= 0x00000078;
1210 #ifdef CONFIG_USER_ONLY
1211 static void arm_any_initfn(Object
*obj
)
1213 ARMCPU
*cpu
= ARM_CPU(obj
);
1214 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1215 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1216 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1217 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1218 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1219 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1220 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1221 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1222 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1223 cpu
->midr
= 0xffffffff;
1227 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1229 typedef struct ARMCPUInfo
{
1231 void (*initfn
)(Object
*obj
);
1232 void (*class_init
)(ObjectClass
*oc
, void *data
);
1235 static const ARMCPUInfo arm_cpus
[] = {
1236 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1237 { .name
= "arm926", .initfn
= arm926_initfn
},
1238 { .name
= "arm946", .initfn
= arm946_initfn
},
1239 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1240 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1241 * older core than plain "arm1136". In particular this does not
1242 * have the v6K features.
1244 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1245 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1246 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1247 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1248 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1249 .class_init
= arm_v7m_class_init
},
1250 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1251 .class_init
= arm_v7m_class_init
},
1252 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1253 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1254 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1255 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1256 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1257 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1258 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1259 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1260 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1261 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1262 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1263 /* "pxa270" is an alias for "pxa270-a0" */
1264 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1265 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1266 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1267 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1268 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1269 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1270 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1271 #ifdef CONFIG_USER_ONLY
1272 { .name
= "any", .initfn
= arm_any_initfn
},
1278 static Property arm_cpu_properties
[] = {
1279 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1280 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1281 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1282 DEFINE_PROP_END_OF_LIST()
1285 #ifdef CONFIG_USER_ONLY
1286 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
1289 ARMCPU
*cpu
= ARM_CPU(cs
);
1290 CPUARMState
*env
= &cpu
->env
;
1292 env
->exception
.vaddress
= address
;
1294 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1296 cs
->exception_index
= EXCP_DATA_ABORT
;
1302 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1304 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1305 CPUClass
*cc
= CPU_CLASS(acc
);
1306 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1308 acc
->parent_realize
= dc
->realize
;
1309 dc
->realize
= arm_cpu_realizefn
;
1310 dc
->props
= arm_cpu_properties
;
1312 acc
->parent_reset
= cc
->reset
;
1313 cc
->reset
= arm_cpu_reset
;
1315 cc
->class_by_name
= arm_cpu_class_by_name
;
1316 cc
->has_work
= arm_cpu_has_work
;
1317 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1318 cc
->dump_state
= arm_cpu_dump_state
;
1319 cc
->set_pc
= arm_cpu_set_pc
;
1320 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1321 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1322 #ifdef CONFIG_USER_ONLY
1323 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1325 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1326 cc
->get_phys_page_debug
= arm_cpu_get_phys_page_debug
;
1327 cc
->vmsd
= &vmstate_arm_cpu
;
1328 cc
->virtio_is_big_endian
= arm_cpu_is_big_endian
;
1330 cc
->gdb_num_core_regs
= 26;
1331 cc
->gdb_core_xml_file
= "arm-core.xml";
1332 cc
->gdb_stop_before_watchpoint
= true;
1333 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1336 static void cpu_register(const ARMCPUInfo
*info
)
1338 TypeInfo type_info
= {
1339 .parent
= TYPE_ARM_CPU
,
1340 .instance_size
= sizeof(ARMCPU
),
1341 .instance_init
= info
->initfn
,
1342 .class_size
= sizeof(ARMCPUClass
),
1343 .class_init
= info
->class_init
,
1346 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1347 type_register(&type_info
);
1348 g_free((void *)type_info
.name
);
1351 static const TypeInfo arm_cpu_type_info
= {
1352 .name
= TYPE_ARM_CPU
,
1354 .instance_size
= sizeof(ARMCPU
),
1355 .instance_init
= arm_cpu_initfn
,
1356 .instance_post_init
= arm_cpu_post_init
,
1357 .instance_finalize
= arm_cpu_finalizefn
,
1359 .class_size
= sizeof(ARMCPUClass
),
1360 .class_init
= arm_cpu_class_init
,
1363 static void arm_cpu_register_types(void)
1365 const ARMCPUInfo
*info
= arm_cpus
;
1367 type_register_static(&arm_cpu_type_info
);
1369 while (info
->name
) {
1375 type_init(arm_cpu_register_types
)