include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 struct TranslationBlock;
  44 typedef struct TranslationBlock TranslationBlock;
  45
  46 /* XXX: make safe guess about sizes */
  47 #define MAX_OP_PER_INSTR 266
  48
  49 #if HOST_LONG_BITS == 32
  50 #define MAX_OPC_PARAM_PER_ARG 2
  51 #else
  52 #define MAX_OPC_PARAM_PER_ARG 1
  53 #endif
  54 #define MAX_OPC_PARAM_IARGS 5
  55 #define MAX_OPC_PARAM_OARGS 1
  56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  57
  58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  59  * and up to 4 + N parameters on 64-bit archs
  60  * (N = number of input arguments + output arguments).  */
  61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  62 #define OPC_BUF_SIZE 640
  63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  64
  65 /* Maximum size a TCG op can expand to.  This is complicated because a
  66    single op may require several host instructions and register reloads.
  67    For now take a wild guess at 192 bytes, which should allow at least
  68    a couple of fixup instructions per argument.  */
  69 #define TCG_MAX_OP_SIZE 192
  70
  71 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  72
  73 #include "qemu/log.h"
  74
  75 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
  76 void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
  77 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
  78                           int pc_pos);
  79
  80 void cpu_gen_init(void);
  81 int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
  82                  int *gen_code_size_ptr);
  83 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
  84 void page_size_init(void);
  85
  86 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
  87 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
  88 TranslationBlock *tb_gen_code(CPUState *cpu,
  89                               target_ulong pc, target_ulong cs_base, int flags,
  90                               int cflags);
  91 void cpu_exec_init(CPUState *cpu, Error **errp);
  92 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
  93
  94 #if !defined(CONFIG_USER_ONLY)
  95 bool qemu_in_vcpu_thread(void);
  96 void cpu_reload_memory_map(CPUState *cpu);
  97 void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
  98 /* cputlb.c */
  99 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 100 void tlb_flush(CPUState *cpu, int flush_global);
 101 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 102                   hwaddr paddr, int prot,
 103                   int mmu_idx, target_ulong size);
 104 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 105                              hwaddr paddr, MemTxAttrs attrs,
 106                              int prot, int mmu_idx, target_ulong size);
 107 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
 108 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
 109                  uintptr_t retaddr);
 110 #else
 111 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 112 {
 113 }
 114
 115 static inline void tlb_flush(CPUState *cpu, int flush_global)
 116 {
 117 }
 118 #endif
 119
 120 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 121
 122 #define CODE_GEN_PHYS_HASH_BITS     15
 123 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 124
 125 /* estimated block size for TB allocation */
 126 /* XXX: use a per code average code fragment size and modulate it
 127    according to the host CPU */
 128 #if defined(CONFIG_SOFTMMU)
 129 #define CODE_GEN_AVG_BLOCK_SIZE 128
 130 #else
 131 #define CODE_GEN_AVG_BLOCK_SIZE 64
 132 #endif
 133
 134 #if defined(__arm__) || defined(_ARCH_PPC) \
 135     || defined(__x86_64__) || defined(__i386__) \
 136     || defined(__sparc__) || defined(__aarch64__) \
 137     || defined(__s390x__) || defined(__mips__) \
 138     || defined(CONFIG_TCG_INTERPRETER)
 139 #define USE_DIRECT_JUMP
 140 #endif
 141
 142 struct TranslationBlock {
 143     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 144     target_ulong cs_base; /* CS base for this block */
 145     uint64_t flags; /* flags defining in which context the code was generated */
 146     uint16_t size;      /* size of target code for this block (1 <=
 147                            size <= TARGET_PAGE_SIZE) */
 148     uint16_t icount;
 149     uint32_t cflags;    /* compile flags */
 150 #define CF_COUNT_MASK  0x7fff
 151 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 152 #define CF_NOCACHE     0x10000 /* To be freed after execution */
 153 #define CF_USE_ICOUNT  0x20000
 154
 155     void *tc_ptr;    /* pointer to the translated code */
 156     /* next matching tb for physical address. */
 157     struct TranslationBlock *phys_hash_next;
 158     /* first and second physical page containing code. The lower bit
 159        of the pointer tells the index in page_next[] */
 160     struct TranslationBlock *page_next[2];
 161     tb_page_addr_t page_addr[2];
 162
 163     /* the following data are used to directly call another TB from
 164        the code of this one. */
 165     uint16_t tb_next_offset[2]; /* offset of original jump target */
 166 #ifdef USE_DIRECT_JUMP
 167     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 168 #else
 169     uintptr_t tb_next[2]; /* address of jump generated code */
 170 #endif
 171     /* list of TBs jumping to this one. This is a circular list using
 172        the two least significant bits of the pointers to tell what is
 173        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 174        jmp_first */
 175     struct TranslationBlock *jmp_next[2];
 176     struct TranslationBlock *jmp_first;
 177 };
 178
 179 #include "exec/spinlock.h"
 180
 181 typedef struct TBContext TBContext;
 182
 183 struct TBContext {
 184
 185     TranslationBlock *tbs;
 186     TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 187     int nb_tbs;
 188     /* any access to the tbs or the page table must use this lock */
 189     spinlock_t tb_lock;
 190
 191     /* statistics */
 192     int tb_flush_count;
 193     int tb_phys_invalidate_count;
 194
 195     int tb_invalidated_flag;
 196 };
 197
 198 void tb_free(TranslationBlock *tb);
 199 void tb_flush(CPUState *cpu);
 200 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 201
 202 #if defined(USE_DIRECT_JUMP)
 203
 204 #if defined(CONFIG_TCG_INTERPRETER)
 205 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 206 {
 207     /* patch the branch destination */
 208     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 209     /* no need to flush icache explicitly */
 210 }
 211 #elif defined(_ARCH_PPC)
 212 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 213 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 214 #elif defined(__i386__) || defined(__x86_64__)
 215 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 216 {
 217     /* patch the branch destination */
 218     stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4));
 219     /* no need to flush icache explicitly */
 220 }
 221 #elif defined(__s390x__)
 222 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 223 {
 224     /* patch the branch destination */
 225     intptr_t disp = addr - (jmp_addr - 2);
 226     stl_be_p((void*)jmp_addr, disp / 2);
 227     /* no need to flush icache explicitly */
 228 }
 229 #elif defined(__aarch64__)
 230 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 231 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
 232 #elif defined(__arm__)
 233 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 234 {
 235 #if !QEMU_GNUC_PREREQ(4, 1)
 236     register unsigned long _beg __asm ("a1");
 237     register unsigned long _end __asm ("a2");
 238     register unsigned long _flg __asm ("a3");
 239 #endif
 240
 241     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 242     *(uint32_t *)jmp_addr =
 243         (*(uint32_t *)jmp_addr & ~0xffffff)
 244         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 245
 246 #if QEMU_GNUC_PREREQ(4, 1)
 247     __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 248 #else
 249     /* flush icache */
 250     _beg = jmp_addr;
 251     _end = jmp_addr + 4;
 252     _flg = 0;
 253     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 254 #endif
 255 }
 256 #elif defined(__sparc__) || defined(__mips__)
 257 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
 258 #else
 259 #error tb_set_jmp_target1 is missing
 260 #endif
 261
 262 static inline void tb_set_jmp_target(TranslationBlock *tb,
 263                                      int n, uintptr_t addr)
 264 {
 265     uint16_t offset = tb->tb_jmp_offset[n];
 266     tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
 267 }
 268
 269 #else
 270
 271 /* set the jump target */
 272 static inline void tb_set_jmp_target(TranslationBlock *tb,
 273                                      int n, uintptr_t addr)
 274 {
 275     tb->tb_next[n] = addr;
 276 }
 277
 278 #endif
 279
 280 static inline void tb_add_jump(TranslationBlock *tb, int n,
 281                                TranslationBlock *tb_next)
 282 {
 283     /* NOTE: this test is only needed for thread safety */
 284     if (!tb->jmp_next[n]) {
 285         /* patch the native jump address */
 286         tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
 287
 288         /* add in TB jmp circular list */
 289         tb->jmp_next[n] = tb_next->jmp_first;
 290         tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
 291     }
 292 }
 293
 294 /* GETRA is the true target of the return instruction that we'll execute,
 295    defined here for simplicity of defining the follow-up macros.  */
 296 #if defined(CONFIG_TCG_INTERPRETER)
 297 extern uintptr_t tci_tb_ptr;
 298 # define GETRA() tci_tb_ptr
 299 #else
 300 # define GETRA() \
 301     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 302 #endif
 303
 304 /* The true return address will often point to a host insn that is part of
 305    the next translated guest insn.  Adjust the address backward to point to
 306    the middle of the call insn.  Subtracting one would do the job except for
 307    several compressed mode architectures (arm, mips) which set the low bit
 308    to indicate the compressed mode; subtracting two works around that.  It
 309    is also the case that there are no host isas that contain a call insn
 310    smaller than 4 bytes, so we don't worry about special-casing this.  */
 311 #if defined(CONFIG_TCG_INTERPRETER)
 312 # define GETPC_ADJ   0
 313 #else
 314 # define GETPC_ADJ   2
 315 #endif
 316
 317 #define GETPC()  (GETRA() - GETPC_ADJ)
 318
 319 #if !defined(CONFIG_USER_ONLY)
 320
 321 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align));
 322
 323 struct MemoryRegion *iotlb_to_region(CPUState *cpu,
 324                                      hwaddr index);
 325
 326 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
 327               uintptr_t retaddr);
 328
 329 #endif
 330
 331 #if defined(CONFIG_USER_ONLY)
 332 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 333 {
 334     return addr;
 335 }
 336 #else
 337 /* cputlb.c */
 338 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
 339 #endif
 340
 341 /* vl.c */
 342 extern int singlestep;
 343
 344 /* cpu-exec.c */
 345 extern volatile sig_atomic_t exit_request;
 346
 347 /**
 348  * cpu_can_do_io:
 349  * @cpu: The CPU for which to check IO.
 350  *
 351  * Deterministic execution requires that IO only be performed on the last
 352  * instruction of a TB so that interrupts take effect immediately.
 353  *
 354  * Returns: %true if memory-mapped IO is safe, %false otherwise.
 355  */
 356 static inline bool cpu_can_do_io(CPUState *cpu)
 357 {
 358     if (!use_icount) {
 359         return true;
 360     }
 361     /* If not executing code then assume we are ok.  */
 362     if (cpu->current_tb == NULL) {
 363         return true;
 364     }
 365     return cpu->can_do_io != 0;
 366 }
 367
 368 #if !defined(CONFIG_USER_ONLY)
 369 void migration_bitmap_extend(ram_addr_t old, ram_addr_t new);
 370 #endif
 371 #endif