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hw/pci: add support for NUMA nodes
[qemu/cris-port.git] / hw / pci / pci.c
blob4989408ece7a851ff08105f7a8faa470d7bb875c
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/pci/pci.h"
26 #include "hw/pci/pci_bridge.h"
27 #include "hw/pci/pci_bus.h"
28 #include "hw/pci/pci_host.h"
29 #include "monitor/monitor.h"
30 #include "net/net.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/loader.h"
33 #include "qemu/range.h"
34 #include "qmp-commands.h"
35 #include "trace.h"
36 #include "hw/pci/msi.h"
37 #include "hw/pci/msix.h"
38 #include "exec/address-spaces.h"
39 #include "hw/hotplug.h"
40
41 //#define DEBUG_PCI
42 #ifdef DEBUG_PCI
43 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
44 #else
45 # define PCI_DPRINTF(format, ...) do { } while (0)
46 #endif
47
48 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
49 static char *pcibus_get_dev_path(DeviceState *dev);
50 static char *pcibus_get_fw_dev_path(DeviceState *dev);
51 static void pcibus_reset(BusState *qbus);
52
53 static Property pci_props[] = {
54 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
55 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
56 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
57 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
58 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
59 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
60 QEMU_PCI_CAP_SERR_BITNR, true),
61 DEFINE_PROP_END_OF_LIST()
62 };
63
64 static const VMStateDescription vmstate_pcibus = {
65 .name = "PCIBUS",
66 .version_id = 1,
67 .minimum_version_id = 1,
68 .fields = (VMStateField[]) {
69 VMSTATE_INT32_EQUAL(nirq, PCIBus),
70 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
71 nirq, 0, vmstate_info_int32,
72 int32_t),
73 VMSTATE_END_OF_LIST()
74 }
75 };
76
77 static void pci_bus_realize(BusState *qbus, Error **errp)
78 {
79 PCIBus *bus = PCI_BUS(qbus);
80
81 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
82 }
83
84 static void pci_bus_unrealize(BusState *qbus, Error **errp)
85 {
86 PCIBus *bus = PCI_BUS(qbus);
87
88 vmstate_unregister(NULL, &vmstate_pcibus, bus);
89 }
90
91 static bool pcibus_is_root(PCIBus *bus)
92 {
93 return !bus->parent_dev;
94 }
95
96 static int pcibus_num(PCIBus *bus)
97 {
98 if (pcibus_is_root(bus)) {
99 return 0; /* pci host bridge */
100 }
101 return bus->parent_dev->config[PCI_SECONDARY_BUS];
102 }
103
104 static uint16_t pcibus_numa_node(PCIBus *bus)
105 {
106 return NUMA_NODE_UNASSIGNED;
107 }
108
109 static void pci_bus_class_init(ObjectClass *klass, void *data)
110 {
111 BusClass *k = BUS_CLASS(klass);
112 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
113
114 k->print_dev = pcibus_dev_print;
115 k->get_dev_path = pcibus_get_dev_path;
116 k->get_fw_dev_path = pcibus_get_fw_dev_path;
117 k->realize = pci_bus_realize;
118 k->unrealize = pci_bus_unrealize;
119 k->reset = pcibus_reset;
120
121 pbc->is_root = pcibus_is_root;
122 pbc->bus_num = pcibus_num;
123 pbc->numa_node = pcibus_numa_node;
124 }
125
126 static const TypeInfo pci_bus_info = {
127 .name = TYPE_PCI_BUS,
128 .parent = TYPE_BUS,
129 .instance_size = sizeof(PCIBus),
130 .class_size = sizeof(PCIBusClass),
131 .class_init = pci_bus_class_init,
132 };
133
134 static const TypeInfo pcie_bus_info = {
135 .name = TYPE_PCIE_BUS,
136 .parent = TYPE_PCI_BUS,
137 };
138
139 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
140 static void pci_update_mappings(PCIDevice *d);
141 static void pci_irq_handler(void *opaque, int irq_num, int level);
142 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
143 static void pci_del_option_rom(PCIDevice *pdev);
144
145 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
146 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
147
148 static QLIST_HEAD(, PCIHostState) pci_host_bridges;
149
150 static int pci_bar(PCIDevice *d, int reg)
151 {
152 uint8_t type;
153
154 if (reg != PCI_ROM_SLOT)
155 return PCI_BASE_ADDRESS_0 + reg * 4;
156
157 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
158 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
159 }
160
161 static inline int pci_irq_state(PCIDevice *d, int irq_num)
162 {
163 return (d->irq_state >> irq_num) & 0x1;
164 }
165
166 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
167 {
168 d->irq_state &= ~(0x1 << irq_num);
169 d->irq_state |= level << irq_num;
170 }
171
172 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
173 {
174 PCIBus *bus;
175 for (;;) {
176 bus = pci_dev->bus;
177 irq_num = bus->map_irq(pci_dev, irq_num);
178 if (bus->set_irq)
179 break;
180 pci_dev = bus->parent_dev;
181 }
182 bus->irq_count[irq_num] += change;
183 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
184 }
185
186 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
187 {
188 assert(irq_num >= 0);
189 assert(irq_num < bus->nirq);
190 return !!bus->irq_count[irq_num];
191 }
192
193 /* Update interrupt status bit in config space on interrupt
194 * state change. */
195 static void pci_update_irq_status(PCIDevice *dev)
196 {
197 if (dev->irq_state) {
198 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
199 } else {
200 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
201 }
202 }
203
204 void pci_device_deassert_intx(PCIDevice *dev)
205 {
206 int i;
207 for (i = 0; i < PCI_NUM_PINS; ++i) {
208 pci_irq_handler(dev, i, 0);
209 }
210 }
211
212 static void pci_do_device_reset(PCIDevice *dev)
213 {
214 int r;
215
216 pci_device_deassert_intx(dev);
217 assert(dev->irq_state == 0);
218
219 /* Clear all writable bits */
220 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
221 pci_get_word(dev->wmask + PCI_COMMAND) |
222 pci_get_word(dev->w1cmask + PCI_COMMAND));
223 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
224 pci_get_word(dev->wmask + PCI_STATUS) |
225 pci_get_word(dev->w1cmask + PCI_STATUS));
226 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
227 dev->config[PCI_INTERRUPT_LINE] = 0x0;
228 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
229 PCIIORegion *region = &dev->io_regions[r];
230 if (!region->size) {
231 continue;
232 }
233
234 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
235 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
236 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
237 } else {
238 pci_set_long(dev->config + pci_bar(dev, r), region->type);
239 }
240 }
241 pci_update_mappings(dev);
242
243 msi_reset(dev);
244 msix_reset(dev);
245 }
246
247 /*
248 * This function is called on #RST and FLR.
249 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
250 */
251 void pci_device_reset(PCIDevice *dev)
252 {
253 qdev_reset_all(&dev->qdev);
254 pci_do_device_reset(dev);
255 }
256
257 /*
258 * Trigger pci bus reset under a given bus.
259 * Called via qbus_reset_all on RST# assert, after the devices
260 * have been reset qdev_reset_all-ed already.
261 */
262 static void pcibus_reset(BusState *qbus)
263 {
264 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
265 int i;
266
267 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
268 if (bus->devices[i]) {
269 pci_do_device_reset(bus->devices[i]);
270 }
271 }
272
273 for (i = 0; i < bus->nirq; i++) {
274 assert(bus->irq_count[i] == 0);
275 }
276 }
277
278 static void pci_host_bus_register(PCIBus *bus, DeviceState *parent)
279 {
280 PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent);
281
282 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
283 }
284
285 PCIBus *pci_find_primary_bus(void)
286 {
287 PCIBus *primary_bus = NULL;
288 PCIHostState *host;
289
290 QLIST_FOREACH(host, &pci_host_bridges, next) {
291 if (primary_bus) {
292 /* We have multiple root buses, refuse to select a primary */
293 return NULL;
294 }
295 primary_bus = host->bus;
296 }
297
298 return primary_bus;
299 }
300
301 PCIBus *pci_device_root_bus(const PCIDevice *d)
302 {
303 PCIBus *bus = d->bus;
304
305 while (!pci_bus_is_root(bus)) {
306 d = bus->parent_dev;
307 assert(d != NULL);
308
309 bus = d->bus;
310 }
311
312 return bus;
313 }
314
315 const char *pci_root_bus_path(PCIDevice *dev)
316 {
317 PCIBus *rootbus = pci_device_root_bus(dev);
318 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
319 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
320
321 assert(host_bridge->bus == rootbus);
322
323 if (hc->root_bus_path) {
324 return (*hc->root_bus_path)(host_bridge, rootbus);
325 }
326
327 return rootbus->qbus.name;
328 }
329
330 static void pci_bus_init(PCIBus *bus, DeviceState *parent,
331 const char *name,
332 MemoryRegion *address_space_mem,
333 MemoryRegion *address_space_io,
334 uint8_t devfn_min)
335 {
336 assert(PCI_FUNC(devfn_min) == 0);
337 bus->devfn_min = devfn_min;
338 bus->address_space_mem = address_space_mem;
339 bus->address_space_io = address_space_io;
340
341 /* host bridge */
342 QLIST_INIT(&bus->child);
343
344 pci_host_bus_register(bus, parent);
345 }
346
347 bool pci_bus_is_express(PCIBus *bus)
348 {
349 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
350 }
351
352 bool pci_bus_is_root(PCIBus *bus)
353 {
354 return PCI_BUS_GET_CLASS(bus)->is_root(bus);
355 }
356
357 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
358 const char *name,
359 MemoryRegion *address_space_mem,
360 MemoryRegion *address_space_io,
361 uint8_t devfn_min, const char *typename)
362 {
363 qbus_create_inplace(bus, bus_size, typename, parent, name);
364 pci_bus_init(bus, parent, name, address_space_mem,
365 address_space_io, devfn_min);
366 }
367
368 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
369 MemoryRegion *address_space_mem,
370 MemoryRegion *address_space_io,
371 uint8_t devfn_min, const char *typename)
372 {
373 PCIBus *bus;
374
375 bus = PCI_BUS(qbus_create(typename, parent, name));
376 pci_bus_init(bus, parent, name, address_space_mem,
377 address_space_io, devfn_min);
378 return bus;
379 }
380
381 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
382 void *irq_opaque, int nirq)
383 {
384 bus->set_irq = set_irq;
385 bus->map_irq = map_irq;
386 bus->irq_opaque = irq_opaque;
387 bus->nirq = nirq;
388 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
389 }
390
391 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
392 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
393 void *irq_opaque,
394 MemoryRegion *address_space_mem,
395 MemoryRegion *address_space_io,
396 uint8_t devfn_min, int nirq, const char *typename)
397 {
398 PCIBus *bus;
399
400 bus = pci_bus_new(parent, name, address_space_mem,
401 address_space_io, devfn_min, typename);
402 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
403 return bus;
404 }
405
406 int pci_bus_num(PCIBus *s)
407 {
408 return PCI_BUS_GET_CLASS(s)->bus_num(s);
409 }
410
411 int pci_bus_numa_node(PCIBus *bus)
412 {
413 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
414 }
415
416 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
417 {
418 PCIDevice *s = container_of(pv, PCIDevice, config);
419 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
420 uint8_t *config;
421 int i;
422
423 assert(size == pci_config_size(s));
424 config = g_malloc(size);
425
426 qemu_get_buffer(f, config, size);
427 for (i = 0; i < size; ++i) {
428 if ((config[i] ^ s->config[i]) &
429 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
430 g_free(config);
431 return -EINVAL;
432 }
433 }
434 memcpy(s->config, config, size);
435
436 pci_update_mappings(s);
437 if (pc->is_bridge) {
438 PCIBridge *b = PCI_BRIDGE(s);
439 pci_bridge_update_mappings(b);
440 }
441
442 memory_region_set_enabled(&s->bus_master_enable_region,
443 pci_get_word(s->config + PCI_COMMAND)
444 & PCI_COMMAND_MASTER);
445
446 g_free(config);
447 return 0;
448 }
449
450 /* just put buffer */
451 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
452 {
453 const uint8_t **v = pv;
454 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
455 qemu_put_buffer(f, *v, size);
456 }
457
458 static VMStateInfo vmstate_info_pci_config = {
459 .name = "pci config",
460 .get = get_pci_config_device,
461 .put = put_pci_config_device,
462 };
463
464 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
465 {
466 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
467 uint32_t irq_state[PCI_NUM_PINS];
468 int i;
469 for (i = 0; i < PCI_NUM_PINS; ++i) {
470 irq_state[i] = qemu_get_be32(f);
471 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
472 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
473 irq_state[i]);
474 return -EINVAL;
475 }
476 }
477
478 for (i = 0; i < PCI_NUM_PINS; ++i) {
479 pci_set_irq_state(s, i, irq_state[i]);
480 }
481
482 return 0;
483 }
484
485 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
486 {
487 int i;
488 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
489
490 for (i = 0; i < PCI_NUM_PINS; ++i) {
491 qemu_put_be32(f, pci_irq_state(s, i));
492 }
493 }
494
495 static VMStateInfo vmstate_info_pci_irq_state = {
496 .name = "pci irq state",
497 .get = get_pci_irq_state,
498 .put = put_pci_irq_state,
499 };
500
501 const VMStateDescription vmstate_pci_device = {
502 .name = "PCIDevice",
503 .version_id = 2,
504 .minimum_version_id = 1,
505 .fields = (VMStateField[]) {
506 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
507 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
508 vmstate_info_pci_config,
509 PCI_CONFIG_SPACE_SIZE),
510 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
511 vmstate_info_pci_irq_state,
512 PCI_NUM_PINS * sizeof(int32_t)),
513 VMSTATE_END_OF_LIST()
514 }
515 };
516
517 const VMStateDescription vmstate_pcie_device = {
518 .name = "PCIEDevice",
519 .version_id = 2,
520 .minimum_version_id = 1,
521 .fields = (VMStateField[]) {
522 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
523 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
524 vmstate_info_pci_config,
525 PCIE_CONFIG_SPACE_SIZE),
526 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
527 vmstate_info_pci_irq_state,
528 PCI_NUM_PINS * sizeof(int32_t)),
529 VMSTATE_END_OF_LIST()
530 }
531 };
532
533 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
534 {
535 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
536 }
537
538 void pci_device_save(PCIDevice *s, QEMUFile *f)
539 {
540 /* Clear interrupt status bit: it is implicit
541 * in irq_state which we are saving.
542 * This makes us compatible with old devices
543 * which never set or clear this bit. */
544 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
545 vmstate_save_state(f, pci_get_vmstate(s), s, NULL);
546 /* Restore the interrupt status bit. */
547 pci_update_irq_status(s);
548 }
549
550 int pci_device_load(PCIDevice *s, QEMUFile *f)
551 {
552 int ret;
553 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
554 /* Restore the interrupt status bit. */
555 pci_update_irq_status(s);
556 return ret;
557 }
558
559 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
560 {
561 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
562 pci_default_sub_vendor_id);
563 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
564 pci_default_sub_device_id);
565 }
566
567 /*
568 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
569 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
570 */
571 static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
572 unsigned int *slotp, unsigned int *funcp)
573 {
574 const char *p;
575 char *e;
576 unsigned long val;
577 unsigned long dom = 0, bus = 0;
578 unsigned int slot = 0;
579 unsigned int func = 0;
580
581 p = addr;
582 val = strtoul(p, &e, 16);
583 if (e == p)
584 return -1;
585 if (*e == ':') {
586 bus = val;
587 p = e + 1;
588 val = strtoul(p, &e, 16);
589 if (e == p)
590 return -1;
591 if (*e == ':') {
592 dom = bus;
593 bus = val;
594 p = e + 1;
595 val = strtoul(p, &e, 16);
596 if (e == p)
597 return -1;
598 }
599 }
600
601 slot = val;
602
603 if (funcp != NULL) {
604 if (*e != '.')
605 return -1;
606
607 p = e + 1;
608 val = strtoul(p, &e, 16);
609 if (e == p)
610 return -1;
611
612 func = val;
613 }
614
615 /* if funcp == NULL func is 0 */
616 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
617 return -1;
618
619 if (*e)
620 return -1;
621
622 *domp = dom;
623 *busp = bus;
624 *slotp = slot;
625 if (funcp != NULL)
626 *funcp = func;
627 return 0;
628 }
629
630 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
631 const char *devaddr)
632 {
633 int dom, bus;
634 unsigned slot;
635
636 if (!root) {
637 fprintf(stderr, "No primary PCI bus\n");
638 return NULL;
639 }
640
641 assert(!root->parent_dev);
642
643 if (!devaddr) {
644 *devfnp = -1;
645 return pci_find_bus_nr(root, 0);
646 }
647
648 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
649 return NULL;
650 }
651
652 if (dom != 0) {
653 fprintf(stderr, "No support for non-zero PCI domains\n");
654 return NULL;
655 }
656
657 *devfnp = PCI_DEVFN(slot, 0);
658 return pci_find_bus_nr(root, bus);
659 }
660
661 static void pci_init_cmask(PCIDevice *dev)
662 {
663 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
664 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
665 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
666 dev->cmask[PCI_REVISION_ID] = 0xff;
667 dev->cmask[PCI_CLASS_PROG] = 0xff;
668 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
669 dev->cmask[PCI_HEADER_TYPE] = 0xff;
670 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
671 }
672
673 static void pci_init_wmask(PCIDevice *dev)
674 {
675 int config_size = pci_config_size(dev);
676
677 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
678 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
679 pci_set_word(dev->wmask + PCI_COMMAND,
680 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
681 PCI_COMMAND_INTX_DISABLE);
682 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
683 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
684 }
685
686 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
687 config_size - PCI_CONFIG_HEADER_SIZE);
688 }
689
690 static void pci_init_w1cmask(PCIDevice *dev)
691 {
692 /*
693 * Note: It's okay to set w1cmask even for readonly bits as
694 * long as their value is hardwired to 0.
695 */
696 pci_set_word(dev->w1cmask + PCI_STATUS,
697 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
698 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
699 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
700 }
701
702 static void pci_init_mask_bridge(PCIDevice *d)
703 {
704 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
705 PCI_SEC_LETENCY_TIMER */
706 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
707
708 /* base and limit */
709 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
710 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
711 pci_set_word(d->wmask + PCI_MEMORY_BASE,
712 PCI_MEMORY_RANGE_MASK & 0xffff);
713 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
714 PCI_MEMORY_RANGE_MASK & 0xffff);
715 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
716 PCI_PREF_RANGE_MASK & 0xffff);
717 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
718 PCI_PREF_RANGE_MASK & 0xffff);
719
720 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
721 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
722
723 /* Supported memory and i/o types */
724 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
725 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
726 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
727 PCI_PREF_RANGE_TYPE_64);
728 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
729 PCI_PREF_RANGE_TYPE_64);
730
731 /*
732 * TODO: Bridges default to 10-bit VGA decoding but we currently only
733 * implement 16-bit decoding (no alias support).
734 */
735 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
736 PCI_BRIDGE_CTL_PARITY |
737 PCI_BRIDGE_CTL_SERR |
738 PCI_BRIDGE_CTL_ISA |
739 PCI_BRIDGE_CTL_VGA |
740 PCI_BRIDGE_CTL_VGA_16BIT |
741 PCI_BRIDGE_CTL_MASTER_ABORT |
742 PCI_BRIDGE_CTL_BUS_RESET |
743 PCI_BRIDGE_CTL_FAST_BACK |
744 PCI_BRIDGE_CTL_DISCARD |
745 PCI_BRIDGE_CTL_SEC_DISCARD |
746 PCI_BRIDGE_CTL_DISCARD_SERR);
747 /* Below does not do anything as we never set this bit, put here for
748 * completeness. */
749 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
750 PCI_BRIDGE_CTL_DISCARD_STATUS);
751 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
752 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
753 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
754 PCI_PREF_RANGE_TYPE_MASK);
755 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
756 PCI_PREF_RANGE_TYPE_MASK);
757 }
758
759 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
760 {
761 uint8_t slot = PCI_SLOT(dev->devfn);
762 uint8_t func;
763
764 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
765 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
766 }
767
768 /*
769 * multifunction bit is interpreted in two ways as follows.
770 * - all functions must set the bit to 1.
771 * Example: Intel X53
772 * - function 0 must set the bit, but the rest function (> 0)
773 * is allowed to leave the bit to 0.
774 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
775 *
776 * So OS (at least Linux) checks the bit of only function 0,
777 * and doesn't see the bit of function > 0.
778 *
779 * The below check allows both interpretation.
780 */
781 if (PCI_FUNC(dev->devfn)) {
782 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
783 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
784 /* function 0 should set multifunction bit */
785 error_setg(errp, "PCI: single function device can't be populated "
786 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
787 return;
788 }
789 return;
790 }
791
792 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
793 return;
794 }
795 /* function 0 indicates single function, so function > 0 must be NULL */
796 for (func = 1; func < PCI_FUNC_MAX; ++func) {
797 if (bus->devices[PCI_DEVFN(slot, func)]) {
798 error_setg(errp, "PCI: %x.0 indicates single function, "
799 "but %x.%x is already populated.",
800 slot, slot, func);
801 return;
802 }
803 }
804 }
805
806 static void pci_config_alloc(PCIDevice *pci_dev)
807 {
808 int config_size = pci_config_size(pci_dev);
809
810 pci_dev->config = g_malloc0(config_size);
811 pci_dev->cmask = g_malloc0(config_size);
812 pci_dev->wmask = g_malloc0(config_size);
813 pci_dev->w1cmask = g_malloc0(config_size);
814 pci_dev->used = g_malloc0(config_size);
815 }
816
817 static void pci_config_free(PCIDevice *pci_dev)
818 {
819 g_free(pci_dev->config);
820 g_free(pci_dev->cmask);
821 g_free(pci_dev->wmask);
822 g_free(pci_dev->w1cmask);
823 g_free(pci_dev->used);
824 }
825
826 static void do_pci_unregister_device(PCIDevice *pci_dev)
827 {
828 pci_dev->bus->devices[pci_dev->devfn] = NULL;
829 pci_config_free(pci_dev);
830
831 address_space_destroy(&pci_dev->bus_master_as);
832 }
833
834 /* -1 for devfn means auto assign */
835 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
836 const char *name, int devfn,
837 Error **errp)
838 {
839 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
840 PCIConfigReadFunc *config_read = pc->config_read;
841 PCIConfigWriteFunc *config_write = pc->config_write;
842 Error *local_err = NULL;
843 AddressSpace *dma_as;
844
845 if (devfn < 0) {
846 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
847 devfn += PCI_FUNC_MAX) {
848 if (!bus->devices[devfn])
849 goto found;
850 }
851 error_setg(errp, "PCI: no slot/function available for %s, all in use",
852 name);
853 return NULL;
854 found: ;
855 } else if (bus->devices[devfn]) {
856 error_setg(errp, "PCI: slot %d function %d not available for %s,"
857 " in use by %s",
858 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
859 bus->devices[devfn]->name);
860 return NULL;
861 }
862
863 pci_dev->bus = bus;
864 pci_dev->devfn = devfn;
865 dma_as = pci_device_iommu_address_space(pci_dev);
866
867 memory_region_init_alias(&pci_dev->bus_master_enable_region,
868 OBJECT(pci_dev), "bus master",
869 dma_as->root, 0, memory_region_size(dma_as->root));
870 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
871 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region,
872 name);
873
874 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
875 pci_dev->irq_state = 0;
876 pci_config_alloc(pci_dev);
877
878 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
879 pci_config_set_device_id(pci_dev->config, pc->device_id);
880 pci_config_set_revision(pci_dev->config, pc->revision);
881 pci_config_set_class(pci_dev->config, pc->class_id);
882
883 if (!pc->is_bridge) {
884 if (pc->subsystem_vendor_id || pc->subsystem_id) {
885 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
886 pc->subsystem_vendor_id);
887 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
888 pc->subsystem_id);
889 } else {
890 pci_set_default_subsystem_id(pci_dev);
891 }
892 } else {
893 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
894 assert(!pc->subsystem_vendor_id);
895 assert(!pc->subsystem_id);
896 }
897 pci_init_cmask(pci_dev);
898 pci_init_wmask(pci_dev);
899 pci_init_w1cmask(pci_dev);
900 if (pc->is_bridge) {
901 pci_init_mask_bridge(pci_dev);
902 }
903 pci_init_multifunction(bus, pci_dev, &local_err);
904 if (local_err) {
905 error_propagate(errp, local_err);
906 do_pci_unregister_device(pci_dev);
907 return NULL;
908 }
909
910 if (!config_read)
911 config_read = pci_default_read_config;
912 if (!config_write)
913 config_write = pci_default_write_config;
914 pci_dev->config_read = config_read;
915 pci_dev->config_write = config_write;
916 bus->devices[devfn] = pci_dev;
917 pci_dev->version_id = 2; /* Current pci device vmstate version */
918 return pci_dev;
919 }
920
921 static void pci_unregister_io_regions(PCIDevice *pci_dev)
922 {
923 PCIIORegion *r;
924 int i;
925
926 for(i = 0; i < PCI_NUM_REGIONS; i++) {
927 r = &pci_dev->io_regions[i];
928 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
929 continue;
930 memory_region_del_subregion(r->address_space, r->memory);
931 }
932
933 pci_unregister_vga(pci_dev);
934 }
935
936 static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
937 {
938 PCIDevice *pci_dev = PCI_DEVICE(dev);
939 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
940
941 pci_unregister_io_regions(pci_dev);
942 pci_del_option_rom(pci_dev);
943
944 if (pc->exit) {
945 pc->exit(pci_dev);
946 }
947
948 do_pci_unregister_device(pci_dev);
949 }
950
951 void pci_register_bar(PCIDevice *pci_dev, int region_num,
952 uint8_t type, MemoryRegion *memory)
953 {
954 PCIIORegion *r;
955 uint32_t addr;
956 uint64_t wmask;
957 pcibus_t size = memory_region_size(memory);
958
959 assert(region_num >= 0);
960 assert(region_num < PCI_NUM_REGIONS);
961 if (size & (size-1)) {
962 fprintf(stderr, "ERROR: PCI region size must be pow2 "
963 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
964 exit(1);
965 }
966
967 r = &pci_dev->io_regions[region_num];
968 r->addr = PCI_BAR_UNMAPPED;
969 r->size = size;
970 r->type = type;
971 r->memory = NULL;
972
973 wmask = ~(size - 1);
974 addr = pci_bar(pci_dev, region_num);
975 if (region_num == PCI_ROM_SLOT) {
976 /* ROM enable bit is writable */
977 wmask |= PCI_ROM_ADDRESS_ENABLE;
978 }
979 pci_set_long(pci_dev->config + addr, type);
980 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
981 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
982 pci_set_quad(pci_dev->wmask + addr, wmask);
983 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
984 } else {
985 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
986 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
987 }
988 pci_dev->io_regions[region_num].memory = memory;
989 pci_dev->io_regions[region_num].address_space
990 = type & PCI_BASE_ADDRESS_SPACE_IO
991 ? pci_dev->bus->address_space_io
992 : pci_dev->bus->address_space_mem;
993 }
994
995 static void pci_update_vga(PCIDevice *pci_dev)
996 {
997 uint16_t cmd;
998
999 if (!pci_dev->has_vga) {
1000 return;
1001 }
1002
1003 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1004
1005 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1006 cmd & PCI_COMMAND_MEMORY);
1007 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1008 cmd & PCI_COMMAND_IO);
1009 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1010 cmd & PCI_COMMAND_IO);
1011 }
1012
1013 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1014 MemoryRegion *io_lo, MemoryRegion *io_hi)
1015 {
1016 assert(!pci_dev->has_vga);
1017
1018 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1019 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1020 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
1021 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1022
1023 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1024 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1025 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1026 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1027
1028 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1029 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1030 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1031 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1032 pci_dev->has_vga = true;
1033
1034 pci_update_vga(pci_dev);
1035 }
1036
1037 void pci_unregister_vga(PCIDevice *pci_dev)
1038 {
1039 if (!pci_dev->has_vga) {
1040 return;
1041 }
1042
1043 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1044 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1045 memory_region_del_subregion(pci_dev->bus->address_space_io,
1046 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1047 memory_region_del_subregion(pci_dev->bus->address_space_io,
1048 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1049 pci_dev->has_vga = false;
1050 }
1051
1052 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1053 {
1054 return pci_dev->io_regions[region_num].addr;
1055 }
1056
1057 static pcibus_t pci_bar_address(PCIDevice *d,
1058 int reg, uint8_t type, pcibus_t size)
1059 {
1060 pcibus_t new_addr, last_addr;
1061 int bar = pci_bar(d, reg);
1062 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1063
1064 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1065 if (!(cmd & PCI_COMMAND_IO)) {
1066 return PCI_BAR_UNMAPPED;
1067 }
1068 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1069 last_addr = new_addr + size - 1;
1070 /* Check if 32 bit BAR wraps around explicitly.
1071 * TODO: make priorities correct and remove this work around.
1072 */
1073 if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) {
1074 return PCI_BAR_UNMAPPED;
1075 }
1076 return new_addr;
1077 }
1078
1079 if (!(cmd & PCI_COMMAND_MEMORY)) {
1080 return PCI_BAR_UNMAPPED;
1081 }
1082 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1083 new_addr = pci_get_quad(d->config + bar);
1084 } else {
1085 new_addr = pci_get_long(d->config + bar);
1086 }
1087 /* the ROM slot has a specific enable bit */
1088 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1089 return PCI_BAR_UNMAPPED;
1090 }
1091 new_addr &= ~(size - 1);
1092 last_addr = new_addr + size - 1;
1093 /* NOTE: we do not support wrapping */
1094 /* XXX: as we cannot support really dynamic
1095 mappings, we handle specific values as invalid
1096 mappings. */
1097 if (last_addr <= new_addr || new_addr == 0 ||
1098 last_addr == PCI_BAR_UNMAPPED) {
1099 return PCI_BAR_UNMAPPED;
1100 }
1101
1102 /* Now pcibus_t is 64bit.
1103 * Check if 32 bit BAR wraps around explicitly.
1104 * Without this, PC ide doesn't work well.
1105 * TODO: remove this work around.
1106 */
1107 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1108 return PCI_BAR_UNMAPPED;
1109 }
1110
1111 /*
1112 * OS is allowed to set BAR beyond its addressable
1113 * bits. For example, 32 bit OS can set 64bit bar
1114 * to >4G. Check it. TODO: we might need to support
1115 * it in the future for e.g. PAE.
1116 */
1117 if (last_addr >= HWADDR_MAX) {
1118 return PCI_BAR_UNMAPPED;
1119 }
1120
1121 return new_addr;
1122 }
1123
1124 static void pci_update_mappings(PCIDevice *d)
1125 {
1126 PCIIORegion *r;
1127 int i;
1128 pcibus_t new_addr;
1129
1130 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1131 r = &d->io_regions[i];
1132
1133 /* this region isn't registered */
1134 if (!r->size)
1135 continue;
1136
1137 new_addr = pci_bar_address(d, i, r->type, r->size);
1138
1139 /* This bar isn't changed */
1140 if (new_addr == r->addr)
1141 continue;
1142
1143 /* now do the real mapping */
1144 if (r->addr != PCI_BAR_UNMAPPED) {
1145 trace_pci_update_mappings_del(d, pci_bus_num(d->bus),
1146 PCI_FUNC(d->devfn),
1147 PCI_SLOT(d->devfn),
1148 i, r->addr, r->size);
1149 memory_region_del_subregion(r->address_space, r->memory);
1150 }
1151 r->addr = new_addr;
1152 if (r->addr != PCI_BAR_UNMAPPED) {
1153 trace_pci_update_mappings_add(d, pci_bus_num(d->bus),
1154 PCI_FUNC(d->devfn),
1155 PCI_SLOT(d->devfn),
1156 i, r->addr, r->size);
1157 memory_region_add_subregion_overlap(r->address_space,
1158 r->addr, r->memory, 1);
1159 }
1160 }
1161
1162 pci_update_vga(d);
1163 }
1164
1165 static inline int pci_irq_disabled(PCIDevice *d)
1166 {
1167 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1168 }
1169
1170 /* Called after interrupt disabled field update in config space,
1171 * assert/deassert interrupts if necessary.
1172 * Gets original interrupt disable bit value (before update). */
1173 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1174 {
1175 int i, disabled = pci_irq_disabled(d);
1176 if (disabled == was_irq_disabled)
1177 return;
1178 for (i = 0; i < PCI_NUM_PINS; ++i) {
1179 int state = pci_irq_state(d, i);
1180 pci_change_irq_level(d, i, disabled ? -state : state);
1181 }
1182 }
1183
1184 uint32_t pci_default_read_config(PCIDevice *d,
1185 uint32_t address, int len)
1186 {
1187 uint32_t val = 0;
1188
1189 memcpy(&val, d->config + address, len);
1190 return le32_to_cpu(val);
1191 }
1192
1193 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1194 {
1195 int i, was_irq_disabled = pci_irq_disabled(d);
1196 uint32_t val = val_in;
1197
1198 for (i = 0; i < l; val >>= 8, ++i) {
1199 uint8_t wmask = d->wmask[addr + i];
1200 uint8_t w1cmask = d->w1cmask[addr + i];
1201 assert(!(wmask & w1cmask));
1202 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1203 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1204 }
1205 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1206 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1207 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1208 range_covers_byte(addr, l, PCI_COMMAND))
1209 pci_update_mappings(d);
1210
1211 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1212 pci_update_irq_disabled(d, was_irq_disabled);
1213 memory_region_set_enabled(&d->bus_master_enable_region,
1214 pci_get_word(d->config + PCI_COMMAND)
1215 & PCI_COMMAND_MASTER);
1216 }
1217
1218 msi_write_config(d, addr, val_in, l);
1219 msix_write_config(d, addr, val_in, l);
1220 }
1221
1222 /***********************************************************/
1223 /* generic PCI irq support */
1224
1225 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1226 static void pci_irq_handler(void *opaque, int irq_num, int level)
1227 {
1228 PCIDevice *pci_dev = opaque;
1229 int change;
1230
1231 change = level - pci_irq_state(pci_dev, irq_num);
1232 if (!change)
1233 return;
1234
1235 pci_set_irq_state(pci_dev, irq_num, level);
1236 pci_update_irq_status(pci_dev);
1237 if (pci_irq_disabled(pci_dev))
1238 return;
1239 pci_change_irq_level(pci_dev, irq_num, change);
1240 }
1241
1242 static inline int pci_intx(PCIDevice *pci_dev)
1243 {
1244 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1245 }
1246
1247 qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1248 {
1249 int intx = pci_intx(pci_dev);
1250
1251 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1252 }
1253
1254 void pci_set_irq(PCIDevice *pci_dev, int level)
1255 {
1256 int intx = pci_intx(pci_dev);
1257 pci_irq_handler(pci_dev, intx, level);
1258 }
1259
1260 /* Special hooks used by device assignment */
1261 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1262 {
1263 assert(pci_bus_is_root(bus));
1264 bus->route_intx_to_irq = route_intx_to_irq;
1265 }
1266
1267 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1268 {
1269 PCIBus *bus;
1270
1271 do {
1272 bus = dev->bus;
1273 pin = bus->map_irq(dev, pin);
1274 dev = bus->parent_dev;
1275 } while (dev);
1276
1277 if (!bus->route_intx_to_irq) {
1278 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1279 object_get_typename(OBJECT(bus->qbus.parent)));
1280 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1281 }
1282
1283 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1284 }
1285
1286 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1287 {
1288 return old->mode != new->mode || old->irq != new->irq;
1289 }
1290
1291 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1292 {
1293 PCIDevice *dev;
1294 PCIBus *sec;
1295 int i;
1296
1297 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1298 dev = bus->devices[i];
1299 if (dev && dev->intx_routing_notifier) {
1300 dev->intx_routing_notifier(dev);
1301 }
1302 }
1303
1304 QLIST_FOREACH(sec, &bus->child, sibling) {
1305 pci_bus_fire_intx_routing_notifier(sec);
1306 }
1307 }
1308
1309 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1310 PCIINTxRoutingNotifier notifier)
1311 {
1312 dev->intx_routing_notifier = notifier;
1313 }
1314
1315 /*
1316 * PCI-to-PCI bridge specification
1317 * 9.1: Interrupt routing. Table 9-1
1318 *
1319 * the PCI Express Base Specification, Revision 2.1
1320 * 2.2.8.1: INTx interrutp signaling - Rules
1321 * the Implementation Note
1322 * Table 2-20
1323 */
1324 /*
1325 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1326 * 0-origin unlike PCI interrupt pin register.
1327 */
1328 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1329 {
1330 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1331 }
1332
1333 /***********************************************************/
1334 /* monitor info on PCI */
1335
1336 typedef struct {
1337 uint16_t class;
1338 const char *desc;
1339 const char *fw_name;
1340 uint16_t fw_ign_bits;
1341 } pci_class_desc;
1342
1343 static const pci_class_desc pci_class_descriptions[] =
1344 {
1345 { 0x0001, "VGA controller", "display"},
1346 { 0x0100, "SCSI controller", "scsi"},
1347 { 0x0101, "IDE controller", "ide"},
1348 { 0x0102, "Floppy controller", "fdc"},
1349 { 0x0103, "IPI controller", "ipi"},
1350 { 0x0104, "RAID controller", "raid"},
1351 { 0x0106, "SATA controller"},
1352 { 0x0107, "SAS controller"},
1353 { 0x0180, "Storage controller"},
1354 { 0x0200, "Ethernet controller", "ethernet"},
1355 { 0x0201, "Token Ring controller", "token-ring"},
1356 { 0x0202, "FDDI controller", "fddi"},
1357 { 0x0203, "ATM controller", "atm"},
1358 { 0x0280, "Network controller"},
1359 { 0x0300, "VGA controller", "display", 0x00ff},
1360 { 0x0301, "XGA controller"},
1361 { 0x0302, "3D controller"},
1362 { 0x0380, "Display controller"},
1363 { 0x0400, "Video controller", "video"},
1364 { 0x0401, "Audio controller", "sound"},
1365 { 0x0402, "Phone"},
1366 { 0x0403, "Audio controller", "sound"},
1367 { 0x0480, "Multimedia controller"},
1368 { 0x0500, "RAM controller", "memory"},
1369 { 0x0501, "Flash controller", "flash"},
1370 { 0x0580, "Memory controller"},
1371 { 0x0600, "Host bridge", "host"},
1372 { 0x0601, "ISA bridge", "isa"},
1373 { 0x0602, "EISA bridge", "eisa"},
1374 { 0x0603, "MC bridge", "mca"},
1375 { 0x0604, "PCI bridge", "pci-bridge"},
1376 { 0x0605, "PCMCIA bridge", "pcmcia"},
1377 { 0x0606, "NUBUS bridge", "nubus"},
1378 { 0x0607, "CARDBUS bridge", "cardbus"},
1379 { 0x0608, "RACEWAY bridge"},
1380 { 0x0680, "Bridge"},
1381 { 0x0700, "Serial port", "serial"},
1382 { 0x0701, "Parallel port", "parallel"},
1383 { 0x0800, "Interrupt controller", "interrupt-controller"},
1384 { 0x0801, "DMA controller", "dma-controller"},
1385 { 0x0802, "Timer", "timer"},
1386 { 0x0803, "RTC", "rtc"},
1387 { 0x0900, "Keyboard", "keyboard"},
1388 { 0x0901, "Pen", "pen"},
1389 { 0x0902, "Mouse", "mouse"},
1390 { 0x0A00, "Dock station", "dock", 0x00ff},
1391 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1392 { 0x0c00, "Fireware contorller", "fireware"},
1393 { 0x0c01, "Access bus controller", "access-bus"},
1394 { 0x0c02, "SSA controller", "ssa"},
1395 { 0x0c03, "USB controller", "usb"},
1396 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1397 { 0x0c05, "SMBus"},
1398 { 0, NULL}
1399 };
1400
1401 static void pci_for_each_device_under_bus(PCIBus *bus,
1402 void (*fn)(PCIBus *b, PCIDevice *d,
1403 void *opaque),
1404 void *opaque)
1405 {
1406 PCIDevice *d;
1407 int devfn;
1408
1409 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1410 d = bus->devices[devfn];
1411 if (d) {
1412 fn(bus, d, opaque);
1413 }
1414 }
1415 }
1416
1417 void pci_for_each_device(PCIBus *bus, int bus_num,
1418 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1419 void *opaque)
1420 {
1421 bus = pci_find_bus_nr(bus, bus_num);
1422
1423 if (bus) {
1424 pci_for_each_device_under_bus(bus, fn, opaque);
1425 }
1426 }
1427
1428 static const pci_class_desc *get_class_desc(int class)
1429 {
1430 const pci_class_desc *desc;
1431
1432 desc = pci_class_descriptions;
1433 while (desc->desc && class != desc->class) {
1434 desc++;
1435 }
1436
1437 return desc;
1438 }
1439
1440 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1441
1442 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1443 {
1444 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1445 int i;
1446
1447 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1448 const PCIIORegion *r = &dev->io_regions[i];
1449 PciMemoryRegionList *region;
1450
1451 if (!r->size) {
1452 continue;
1453 }
1454
1455 region = g_malloc0(sizeof(*region));
1456 region->value = g_malloc0(sizeof(*region->value));
1457
1458 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1459 region->value->type = g_strdup("io");
1460 } else {
1461 region->value->type = g_strdup("memory");
1462 region->value->has_prefetch = true;
1463 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1464 region->value->has_mem_type_64 = true;
1465 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1466 }
1467
1468 region->value->bar = i;
1469 region->value->address = r->addr;
1470 region->value->size = r->size;
1471
1472 /* XXX: waiting for the qapi to support GSList */
1473 if (!cur_item) {
1474 head = cur_item = region;
1475 } else {
1476 cur_item->next = region;
1477 cur_item = region;
1478 }
1479 }
1480
1481 return head;
1482 }
1483
1484 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1485 int bus_num)
1486 {
1487 PciBridgeInfo *info;
1488 PciMemoryRange *range;
1489
1490 info = g_new0(PciBridgeInfo, 1);
1491
1492 info->bus = g_new0(PciBusInfo, 1);
1493 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1494 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1495 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
1496
1497 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1498 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1499 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1500
1501 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1502 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1503 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1504
1505 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1506 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1507 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1508
1509 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1510 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1511 if (child_bus) {
1512 info->has_devices = true;
1513 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1514 }
1515 }
1516
1517 return info;
1518 }
1519
1520 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1521 int bus_num)
1522 {
1523 const pci_class_desc *desc;
1524 PciDeviceInfo *info;
1525 uint8_t type;
1526 int class;
1527
1528 info = g_new0(PciDeviceInfo, 1);
1529 info->bus = bus_num;
1530 info->slot = PCI_SLOT(dev->devfn);
1531 info->function = PCI_FUNC(dev->devfn);
1532
1533 info->class_info = g_new0(PciDeviceClass, 1);
1534 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1535 info->class_info->q_class = class;
1536 desc = get_class_desc(class);
1537 if (desc->desc) {
1538 info->class_info->has_desc = true;
1539 info->class_info->desc = g_strdup(desc->desc);
1540 }
1541
1542 info->id = g_new0(PciDeviceId, 1);
1543 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1544 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
1545 info->regions = qmp_query_pci_regions(dev);
1546 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1547
1548 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1549 info->has_irq = true;
1550 info->irq = dev->config[PCI_INTERRUPT_LINE];
1551 }
1552
1553 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1554 if (type == PCI_HEADER_TYPE_BRIDGE) {
1555 info->has_pci_bridge = true;
1556 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1557 }
1558
1559 return info;
1560 }
1561
1562 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1563 {
1564 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1565 PCIDevice *dev;
1566 int devfn;
1567
1568 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1569 dev = bus->devices[devfn];
1570 if (dev) {
1571 info = g_malloc0(sizeof(*info));
1572 info->value = qmp_query_pci_device(dev, bus, bus_num);
1573
1574 /* XXX: waiting for the qapi to support GSList */
1575 if (!cur_item) {
1576 head = cur_item = info;
1577 } else {
1578 cur_item->next = info;
1579 cur_item = info;
1580 }
1581 }
1582 }
1583
1584 return head;
1585 }
1586
1587 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1588 {
1589 PciInfo *info = NULL;
1590
1591 bus = pci_find_bus_nr(bus, bus_num);
1592 if (bus) {
1593 info = g_malloc0(sizeof(*info));
1594 info->bus = bus_num;
1595 info->devices = qmp_query_pci_devices(bus, bus_num);
1596 }
1597
1598 return info;
1599 }
1600
1601 PciInfoList *qmp_query_pci(Error **errp)
1602 {
1603 PciInfoList *info, *head = NULL, *cur_item = NULL;
1604 PCIHostState *host_bridge;
1605
1606 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1607 info = g_malloc0(sizeof(*info));
1608 info->value = qmp_query_pci_bus(host_bridge->bus,
1609 pci_bus_num(host_bridge->bus));
1610
1611 /* XXX: waiting for the qapi to support GSList */
1612 if (!cur_item) {
1613 head = cur_item = info;
1614 } else {
1615 cur_item->next = info;
1616 cur_item = info;
1617 }
1618 }
1619
1620 return head;
1621 }
1622
1623 static const char * const pci_nic_models[] = {
1624 "ne2k_pci",
1625 "i82551",
1626 "i82557b",
1627 "i82559er",
1628 "rtl8139",
1629 "e1000",
1630 "pcnet",
1631 "virtio",
1632 NULL
1633 };
1634
1635 static const char * const pci_nic_names[] = {
1636 "ne2k_pci",
1637 "i82551",
1638 "i82557b",
1639 "i82559er",
1640 "rtl8139",
1641 "e1000",
1642 "pcnet",
1643 "virtio-net-pci",
1644 NULL
1645 };
1646
1647 /* Initialize a PCI NIC. */
1648 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1649 const char *default_model,
1650 const char *default_devaddr)
1651 {
1652 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1653 Error *err = NULL;
1654 PCIBus *bus;
1655 PCIDevice *pci_dev;
1656 DeviceState *dev;
1657 int devfn;
1658 int i;
1659
1660 if (qemu_show_nic_models(nd->model, pci_nic_models)) {
1661 exit(0);
1662 }
1663
1664 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1665 if (i < 0) {
1666 exit(1);
1667 }
1668
1669 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1670 if (!bus) {
1671 error_report("Invalid PCI device address %s for device %s",
1672 devaddr, pci_nic_names[i]);
1673 exit(1);
1674 }
1675
1676 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1677 dev = &pci_dev->qdev;
1678 qdev_set_nic_properties(dev, nd);
1679
1680 object_property_set_bool(OBJECT(dev), true, "realized", &err);
1681 if (err) {
1682 error_report_err(err);
1683 object_unparent(OBJECT(dev));
1684 exit(1);
1685 }
1686
1687 return pci_dev;
1688 }
1689
1690 PCIDevice *pci_vga_init(PCIBus *bus)
1691 {
1692 switch (vga_interface_type) {
1693 case VGA_CIRRUS:
1694 return pci_create_simple(bus, -1, "cirrus-vga");
1695 case VGA_QXL:
1696 return pci_create_simple(bus, -1, "qxl-vga");
1697 case VGA_STD:
1698 return pci_create_simple(bus, -1, "VGA");
1699 case VGA_VMWARE:
1700 return pci_create_simple(bus, -1, "vmware-svga");
1701 case VGA_NONE:
1702 default: /* Other non-PCI types. Checking for unsupported types is already
1703 done in vl.c. */
1704 return NULL;
1705 }
1706 }
1707
1708 /* Whether a given bus number is in range of the secondary
1709 * bus of the given bridge device. */
1710 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1711 {
1712 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1713 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1714 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
1715 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1716 }
1717
1718 /* Whether a given bus number is in a range of a root bus */
1719 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1720 {
1721 int i;
1722
1723 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1724 PCIDevice *dev = bus->devices[i];
1725
1726 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1727 if (pci_secondary_bus_in_range(dev, bus_num)) {
1728 return true;
1729 }
1730 }
1731 }
1732
1733 return false;
1734 }
1735
1736 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1737 {
1738 PCIBus *sec;
1739
1740 if (!bus) {
1741 return NULL;
1742 }
1743
1744 if (pci_bus_num(bus) == bus_num) {
1745 return bus;
1746 }
1747
1748 /* Consider all bus numbers in range for the host pci bridge. */
1749 if (!pci_bus_is_root(bus) &&
1750 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1751 return NULL;
1752 }
1753
1754 /* try child bus */
1755 for (; bus; bus = sec) {
1756 QLIST_FOREACH(sec, &bus->child, sibling) {
1757 if (pci_bus_num(sec) == bus_num) {
1758 return sec;
1759 }
1760 /* PXB buses assumed to be children of bus 0 */
1761 if (pci_bus_is_root(sec)) {
1762 if (pci_root_bus_in_range(sec, bus_num)) {
1763 break;
1764 }
1765 } else {
1766 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1767 break;
1768 }
1769 }
1770 }
1771 }
1772
1773 return NULL;
1774 }
1775
1776 void pci_for_each_bus_depth_first(PCIBus *bus,
1777 void *(*begin)(PCIBus *bus, void *parent_state),
1778 void (*end)(PCIBus *bus, void *state),
1779 void *parent_state)
1780 {
1781 PCIBus *sec;
1782 void *state;
1783
1784 if (!bus) {
1785 return;
1786 }
1787
1788 if (begin) {
1789 state = begin(bus, parent_state);
1790 } else {
1791 state = parent_state;
1792 }
1793
1794 QLIST_FOREACH(sec, &bus->child, sibling) {
1795 pci_for_each_bus_depth_first(sec, begin, end, state);
1796 }
1797
1798 if (end) {
1799 end(bus, state);
1800 }
1801 }
1802
1803
1804 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1805 {
1806 bus = pci_find_bus_nr(bus, bus_num);
1807
1808 if (!bus)
1809 return NULL;
1810
1811 return bus->devices[devfn];
1812 }
1813
1814 static void pci_qdev_realize(DeviceState *qdev, Error **errp)
1815 {
1816 PCIDevice *pci_dev = (PCIDevice *)qdev;
1817 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1818 Error *local_err = NULL;
1819 PCIBus *bus;
1820 bool is_default_rom;
1821
1822 /* initialize cap_present for pci_is_express() and pci_config_size() */
1823 if (pc->is_express) {
1824 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1825 }
1826
1827 bus = PCI_BUS(qdev_get_parent_bus(qdev));
1828 pci_dev = do_pci_register_device(pci_dev, bus,
1829 object_get_typename(OBJECT(qdev)),
1830 pci_dev->devfn, errp);
1831 if (pci_dev == NULL)
1832 return;
1833
1834 if (pc->realize) {
1835 pc->realize(pci_dev, &local_err);
1836 if (local_err) {
1837 error_propagate(errp, local_err);
1838 do_pci_unregister_device(pci_dev);
1839 return;
1840 }
1841 }
1842
1843 /* rom loading */
1844 is_default_rom = false;
1845 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
1846 pci_dev->romfile = g_strdup(pc->romfile);
1847 is_default_rom = true;
1848 }
1849
1850 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
1851 if (local_err) {
1852 error_propagate(errp, local_err);
1853 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
1854 return;
1855 }
1856 }
1857
1858 static void pci_default_realize(PCIDevice *dev, Error **errp)
1859 {
1860 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1861
1862 if (pc->init) {
1863 if (pc->init(dev) < 0) {
1864 error_setg(errp, "Device initialization failed");
1865 return;
1866 }
1867 }
1868 }
1869
1870 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1871 const char *name)
1872 {
1873 DeviceState *dev;
1874
1875 dev = qdev_create(&bus->qbus, name);
1876 qdev_prop_set_int32(dev, "addr", devfn);
1877 qdev_prop_set_bit(dev, "multifunction", multifunction);
1878 return PCI_DEVICE(dev);
1879 }
1880
1881 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1882 bool multifunction,
1883 const char *name)
1884 {
1885 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1886 qdev_init_nofail(&dev->qdev);
1887 return dev;
1888 }
1889
1890 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1891 {
1892 return pci_create_multifunction(bus, devfn, false, name);
1893 }
1894
1895 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1896 {
1897 return pci_create_simple_multifunction(bus, devfn, false, name);
1898 }
1899
1900 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
1901 {
1902 int offset = PCI_CONFIG_HEADER_SIZE;
1903 int i;
1904 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
1905 if (pdev->used[i])
1906 offset = i + 1;
1907 else if (i - offset + 1 == size)
1908 return offset;
1909 }
1910 return 0;
1911 }
1912
1913 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1914 uint8_t *prev_p)
1915 {
1916 uint8_t next, prev;
1917
1918 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1919 return 0;
1920
1921 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1922 prev = next + PCI_CAP_LIST_NEXT)
1923 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1924 break;
1925
1926 if (prev_p)
1927 *prev_p = prev;
1928 return next;
1929 }
1930
1931 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1932 {
1933 uint8_t next, prev, found = 0;
1934
1935 if (!(pdev->used[offset])) {
1936 return 0;
1937 }
1938
1939 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1940
1941 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1942 prev = next + PCI_CAP_LIST_NEXT) {
1943 if (next <= offset && next > found) {
1944 found = next;
1945 }
1946 }
1947 return found;
1948 }
1949
1950 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1951 This is needed for an option rom which is used for more than one device. */
1952 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1953 {
1954 uint16_t vendor_id;
1955 uint16_t device_id;
1956 uint16_t rom_vendor_id;
1957 uint16_t rom_device_id;
1958 uint16_t rom_magic;
1959 uint16_t pcir_offset;
1960 uint8_t checksum;
1961
1962 /* Words in rom data are little endian (like in PCI configuration),
1963 so they can be read / written with pci_get_word / pci_set_word. */
1964
1965 /* Only a valid rom will be patched. */
1966 rom_magic = pci_get_word(ptr);
1967 if (rom_magic != 0xaa55) {
1968 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1969 return;
1970 }
1971 pcir_offset = pci_get_word(ptr + 0x18);
1972 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1973 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1974 return;
1975 }
1976
1977 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1978 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1979 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1980 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1981
1982 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1983 vendor_id, device_id, rom_vendor_id, rom_device_id);
1984
1985 checksum = ptr[6];
1986
1987 if (vendor_id != rom_vendor_id) {
1988 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1989 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1990 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1991 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1992 ptr[6] = checksum;
1993 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1994 }
1995
1996 if (device_id != rom_device_id) {
1997 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1998 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1999 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2000 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2001 ptr[6] = checksum;
2002 pci_set_word(ptr + pcir_offset + 6, device_id);
2003 }
2004 }
2005
2006 /* Add an option rom for the device */
2007 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2008 Error **errp)
2009 {
2010 int size;
2011 char *path;
2012 void *ptr;
2013 char name[32];
2014 const VMStateDescription *vmsd;
2015
2016 if (!pdev->romfile)
2017 return;
2018 if (strlen(pdev->romfile) == 0)
2019 return;
2020
2021 if (!pdev->rom_bar) {
2022 /*
2023 * Load rom via fw_cfg instead of creating a rom bar,
2024 * for 0.11 compatibility.
2025 */
2026 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
2027
2028 /*
2029 * Hot-plugged devices can't use the option ROM
2030 * if the rom bar is disabled.
2031 */
2032 if (DEVICE(pdev)->hotplugged) {
2033 error_setg(errp, "Hot-plugged device without ROM bar"
2034 " can't have an option ROM");
2035 return;
2036 }
2037
2038 if (class == 0x0300) {
2039 rom_add_vga(pdev->romfile);
2040 } else {
2041 rom_add_option(pdev->romfile, -1);
2042 }
2043 return;
2044 }
2045
2046 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
2047 if (path == NULL) {
2048 path = g_strdup(pdev->romfile);
2049 }
2050
2051 size = get_image_size(path);
2052 if (size < 0) {
2053 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
2054 g_free(path);
2055 return;
2056 } else if (size == 0) {
2057 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
2058 g_free(path);
2059 return;
2060 }
2061 if (size & (size - 1)) {
2062 size = 1 << qemu_fls(size);
2063 }
2064
2065 vmsd = qdev_get_vmsd(DEVICE(pdev));
2066
2067 if (vmsd) {
2068 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2069 } else {
2070 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
2071 }
2072 pdev->has_rom = true;
2073 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size, &error_abort);
2074 vmstate_register_ram(&pdev->rom, &pdev->qdev);
2075 ptr = memory_region_get_ram_ptr(&pdev->rom);
2076 load_image(path, ptr);
2077 g_free(path);
2078
2079 if (is_default_rom) {
2080 /* Only the default rom images will be patched (if needed). */
2081 pci_patch_ids(pdev, ptr, size);
2082 }
2083
2084 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
2085 }
2086
2087 static void pci_del_option_rom(PCIDevice *pdev)
2088 {
2089 if (!pdev->has_rom)
2090 return;
2091
2092 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
2093 pdev->has_rom = false;
2094 }
2095
2096 /*
2097 * if !offset
2098 * Reserve space and add capability to the linked list in pci config space
2099 *
2100 * if offset = 0,
2101 * Find and reserve space and add capability to the linked list
2102 * in pci config space */
2103 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2104 uint8_t offset, uint8_t size)
2105 {
2106 int ret;
2107 Error *local_err = NULL;
2108
2109 ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
2110 if (local_err) {
2111 assert(ret < 0);
2112 error_report_err(local_err);
2113 } else {
2114 /* success implies a positive offset in config space */
2115 assert(ret > 0);
2116 }
2117 return ret;
2118 }
2119
2120 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
2121 uint8_t offset, uint8_t size,
2122 Error **errp)
2123 {
2124 uint8_t *config;
2125 int i, overlapping_cap;
2126
2127 if (!offset) {
2128 offset = pci_find_space(pdev, size);
2129 if (!offset) {
2130 error_setg(errp, "out of PCI config space");
2131 return -ENOSPC;
2132 }
2133 } else {
2134 /* Verify that capabilities don't overlap. Note: device assignment
2135 * depends on this check to verify that the device is not broken.
2136 * Should never trigger for emulated devices, but it's helpful
2137 * for debugging these. */
2138 for (i = offset; i < offset + size; i++) {
2139 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2140 if (overlapping_cap) {
2141 error_setg(errp, "%s:%02x:%02x.%x "
2142 "Attempt to add PCI capability %x at offset "
2143 "%x overlaps existing capability %x at offset %x",
2144 pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2145 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2146 cap_id, offset, overlapping_cap, i);
2147 return -EINVAL;
2148 }
2149 }
2150 }
2151
2152 config = pdev->config + offset;
2153 config[PCI_CAP_LIST_ID] = cap_id;
2154 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2155 pdev->config[PCI_CAPABILITY_LIST] = offset;
2156 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2157 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2158 /* Make capability read-only by default */
2159 memset(pdev->wmask + offset, 0, size);
2160 /* Check capability by default */
2161 memset(pdev->cmask + offset, 0xFF, size);
2162 return offset;
2163 }
2164
2165 /* Unlink capability from the pci config space. */
2166 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2167 {
2168 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2169 if (!offset)
2170 return;
2171 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2172 /* Make capability writable again */
2173 memset(pdev->wmask + offset, 0xff, size);
2174 memset(pdev->w1cmask + offset, 0, size);
2175 /* Clear cmask as device-specific registers can't be checked */
2176 memset(pdev->cmask + offset, 0, size);
2177 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2178
2179 if (!pdev->config[PCI_CAPABILITY_LIST])
2180 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2181 }
2182
2183 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2184 {
2185 return pci_find_capability_list(pdev, cap_id, NULL);
2186 }
2187
2188 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2189 {
2190 PCIDevice *d = (PCIDevice *)dev;
2191 const pci_class_desc *desc;
2192 char ctxt[64];
2193 PCIIORegion *r;
2194 int i, class;
2195
2196 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2197 desc = pci_class_descriptions;
2198 while (desc->desc && class != desc->class)
2199 desc++;
2200 if (desc->desc) {
2201 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2202 } else {
2203 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2204 }
2205
2206 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2207 "pci id %04x:%04x (sub %04x:%04x)\n",
2208 indent, "", ctxt, pci_bus_num(d->bus),
2209 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2210 pci_get_word(d->config + PCI_VENDOR_ID),
2211 pci_get_word(d->config + PCI_DEVICE_ID),
2212 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2213 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2214 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2215 r = &d->io_regions[i];
2216 if (!r->size)
2217 continue;
2218 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2219 " [0x%"FMT_PCIBUS"]\n",
2220 indent, "",
2221 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2222 r->addr, r->addr + r->size - 1);
2223 }
2224 }
2225
2226 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2227 {
2228 PCIDevice *d = (PCIDevice *)dev;
2229 const char *name = NULL;
2230 const pci_class_desc *desc = pci_class_descriptions;
2231 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2232
2233 while (desc->desc &&
2234 (class & ~desc->fw_ign_bits) !=
2235 (desc->class & ~desc->fw_ign_bits)) {
2236 desc++;
2237 }
2238
2239 if (desc->desc) {
2240 name = desc->fw_name;
2241 }
2242
2243 if (name) {
2244 pstrcpy(buf, len, name);
2245 } else {
2246 snprintf(buf, len, "pci%04x,%04x",
2247 pci_get_word(d->config + PCI_VENDOR_ID),
2248 pci_get_word(d->config + PCI_DEVICE_ID));
2249 }
2250
2251 return buf;
2252 }
2253
2254 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2255 {
2256 PCIDevice *d = (PCIDevice *)dev;
2257 char path[50], name[33];
2258 int off;
2259
2260 off = snprintf(path, sizeof(path), "%s@%x",
2261 pci_dev_fw_name(dev, name, sizeof name),
2262 PCI_SLOT(d->devfn));
2263 if (PCI_FUNC(d->devfn))
2264 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2265 return g_strdup(path);
2266 }
2267
2268 static char *pcibus_get_dev_path(DeviceState *dev)
2269 {
2270 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2271 PCIDevice *t;
2272 int slot_depth;
2273 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2274 * 00 is added here to make this format compatible with
2275 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2276 * Slot.Function list specifies the slot and function numbers for all
2277 * devices on the path from root to the specific device. */
2278 const char *root_bus_path;
2279 int root_bus_len;
2280 char slot[] = ":SS.F";
2281 int slot_len = sizeof slot - 1 /* For '\0' */;
2282 int path_len;
2283 char *path, *p;
2284 int s;
2285
2286 root_bus_path = pci_root_bus_path(d);
2287 root_bus_len = strlen(root_bus_path);
2288
2289 /* Calculate # of slots on path between device and root. */;
2290 slot_depth = 0;
2291 for (t = d; t; t = t->bus->parent_dev) {
2292 ++slot_depth;
2293 }
2294
2295 path_len = root_bus_len + slot_len * slot_depth;
2296
2297 /* Allocate memory, fill in the terminating null byte. */
2298 path = g_malloc(path_len + 1 /* For '\0' */);
2299 path[path_len] = '\0';
2300
2301 memcpy(path, root_bus_path, root_bus_len);
2302
2303 /* Fill in slot numbers. We walk up from device to root, so need to print
2304 * them in the reverse order, last to first. */
2305 p = path + path_len;
2306 for (t = d; t; t = t->bus->parent_dev) {
2307 p -= slot_len;
2308 s = snprintf(slot, sizeof slot, ":%02x.%x",
2309 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2310 assert(s == slot_len);
2311 memcpy(p, slot, slot_len);
2312 }
2313
2314 return path;
2315 }
2316
2317 static int pci_qdev_find_recursive(PCIBus *bus,
2318 const char *id, PCIDevice **pdev)
2319 {
2320 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2321 if (!qdev) {
2322 return -ENODEV;
2323 }
2324
2325 /* roughly check if given qdev is pci device */
2326 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2327 *pdev = PCI_DEVICE(qdev);
2328 return 0;
2329 }
2330 return -EINVAL;
2331 }
2332
2333 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2334 {
2335 PCIHostState *host_bridge;
2336 int rc = -ENODEV;
2337
2338 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2339 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2340 if (!tmp) {
2341 rc = 0;
2342 break;
2343 }
2344 if (tmp != -ENODEV) {
2345 rc = tmp;
2346 }
2347 }
2348
2349 return rc;
2350 }
2351
2352 MemoryRegion *pci_address_space(PCIDevice *dev)
2353 {
2354 return dev->bus->address_space_mem;
2355 }
2356
2357 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2358 {
2359 return dev->bus->address_space_io;
2360 }
2361
2362 static void pci_device_class_init(ObjectClass *klass, void *data)
2363 {
2364 DeviceClass *k = DEVICE_CLASS(klass);
2365 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
2366
2367 k->realize = pci_qdev_realize;
2368 k->unrealize = pci_qdev_unrealize;
2369 k->bus_type = TYPE_PCI_BUS;
2370 k->props = pci_props;
2371 pc->realize = pci_default_realize;
2372 }
2373
2374 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2375 {
2376 PCIBus *bus = PCI_BUS(dev->bus);
2377
2378 if (bus->iommu_fn) {
2379 return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn);
2380 }
2381
2382 if (bus->parent_dev) {
2383 /** We are ignoring the bus master DMA bit of the bridge
2384 * as it would complicate things such as VFIO for no good reason */
2385 return pci_device_iommu_address_space(bus->parent_dev);
2386 }
2387
2388 return &address_space_memory;
2389 }
2390
2391 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2392 {
2393 bus->iommu_fn = fn;
2394 bus->iommu_opaque = opaque;
2395 }
2396
2397 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2398 {
2399 Range *range = opaque;
2400 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2401 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2402 int i;
2403
2404 if (!(cmd & PCI_COMMAND_MEMORY)) {
2405 return;
2406 }
2407
2408 if (pc->is_bridge) {
2409 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2410 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2411
2412 base = MAX(base, 0x1ULL << 32);
2413
2414 if (limit >= base) {
2415 Range pref_range;
2416 pref_range.begin = base;
2417 pref_range.end = limit + 1;
2418 range_extend(range, &pref_range);
2419 }
2420 }
2421 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2422 PCIIORegion *r = &dev->io_regions[i];
2423 Range region_range;
2424
2425 if (!r->size ||
2426 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2427 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2428 continue;
2429 }
2430 region_range.begin = pci_bar_address(dev, i, r->type, r->size);
2431 region_range.end = region_range.begin + r->size;
2432
2433 if (region_range.begin == PCI_BAR_UNMAPPED) {
2434 continue;
2435 }
2436
2437 region_range.begin = MAX(region_range.begin, 0x1ULL << 32);
2438
2439 if (region_range.end - 1 >= region_range.begin) {
2440 range_extend(range, &region_range);
2441 }
2442 }
2443 }
2444
2445 void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2446 {
2447 range->begin = range->end = 0;
2448 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2449 }
2450
2451 static const TypeInfo pci_device_type_info = {
2452 .name = TYPE_PCI_DEVICE,
2453 .parent = TYPE_DEVICE,
2454 .instance_size = sizeof(PCIDevice),
2455 .abstract = true,
2456 .class_size = sizeof(PCIDeviceClass),
2457 .class_init = pci_device_class_init,
2458 };
2459
2460 static void pci_register_types(void)
2461 {
2462 type_register_static(&pci_bus_info);
2463 type_register_static(&pcie_bus_info);
2464 type_register_static(&pci_device_type_info);
2465 }
2466
2467 type_init(pci_register_types)
CRIS target port of Qemu