target-xtensa/op_helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "exec/helper-proto.h"
  30 #include "qemu/host-utils.h"
  31 #include "exec/cpu_ldst.h"
  32 #include "exec/address-spaces.h"
  33 #include "qemu/timer.h"
  34
  35 void xtensa_cpu_do_unaligned_access(CPUState *cs,
  36         vaddr addr, int is_write, int is_user, uintptr_t retaddr)
  37 {
  38     XtensaCPU *cpu = XTENSA_CPU(cs);
  39     CPUXtensaState *env = &cpu->env;
  40
  41     if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
  42             !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
  43         cpu_restore_state(CPU(cpu), retaddr);
  44         HELPER(exception_cause_vaddr)(env,
  45                 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
  46     }
  47 }
  48
  49 void tlb_fill(CPUState *cs,
  50               target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
  51 {
  52     XtensaCPU *cpu = XTENSA_CPU(cs);
  53     CPUXtensaState *env = &cpu->env;
  54     uint32_t paddr;
  55     uint32_t page_size;
  56     unsigned access;
  57     int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx,
  58             &paddr, &page_size, &access);
  59
  60     qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__,
  61             vaddr, is_write, mmu_idx, paddr, ret);
  62
  63     if (ret == 0) {
  64         tlb_set_page(cs,
  65                      vaddr & TARGET_PAGE_MASK,
  66                      paddr & TARGET_PAGE_MASK,
  67                      access, mmu_idx, page_size);
  68     } else {
  69         cpu_restore_state(cs, retaddr);
  70         HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
  71     }
  72 }
  73
  74 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
  75 {
  76     uint32_t paddr;
  77     uint32_t page_size;
  78     unsigned access;
  79     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
  80             &paddr, &page_size, &access);
  81     if (ret == 0) {
  82         tb_invalidate_phys_addr(&address_space_memory, paddr);
  83     }
  84 }
  85
  86 void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
  87 {
  88     CPUState *cs = CPU(xtensa_env_get_cpu(env));
  89
  90     cs->exception_index = excp;
  91     if (excp == EXCP_DEBUG) {
  92         env->exception_taken = 0;
  93     }
  94     cpu_loop_exit(cs);
  95 }
  96
  97 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
  98 {
  99     uint32_t vector;
 100
 101     env->pc = pc;
 102     if (env->sregs[PS] & PS_EXCM) {
 103         if (env->config->ndepc) {
 104             env->sregs[DEPC] = pc;
 105         } else {
 106             env->sregs[EPC1] = pc;
 107         }
 108         vector = EXC_DOUBLE;
 109     } else {
 110         env->sregs[EPC1] = pc;
 111         vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 112     }
 113
 114     env->sregs[EXCCAUSE] = cause;
 115     env->sregs[PS] |= PS_EXCM;
 116
 117     HELPER(exception)(env, vector);
 118 }
 119
 120 void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
 121         uint32_t pc, uint32_t cause, uint32_t vaddr)
 122 {
 123     env->sregs[EXCVADDR] = vaddr;
 124     HELPER(exception_cause)(env, pc, cause);
 125 }
 126
 127 void debug_exception_env(CPUXtensaState *env, uint32_t cause)
 128 {
 129     if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 130         HELPER(debug_exception)(env, env->pc, cause);
 131     }
 132 }
 133
 134 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 135 {
 136     unsigned level = env->config->debug_level;
 137
 138     env->pc = pc;
 139     env->sregs[DEBUGCAUSE] = cause;
 140     env->sregs[EPC1 + level - 1] = pc;
 141     env->sregs[EPS2 + level - 2] = env->sregs[PS];
 142     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
 143         (level << PS_INTLEVEL_SHIFT);
 144     HELPER(exception)(env, EXC_DEBUG);
 145 }
 146
 147 uint32_t HELPER(nsa)(uint32_t v)
 148 {
 149     if (v & 0x80000000) {
 150         v = ~v;
 151     }
 152     return v ? clz32(v) - 1 : 31;
 153 }
 154
 155 uint32_t HELPER(nsau)(uint32_t v)
 156 {
 157     return v ? clz32(v) : 32;
 158 }
 159
 160 static void copy_window_from_phys(CPUXtensaState *env,
 161         uint32_t window, uint32_t phys, uint32_t n)
 162 {
 163     assert(phys < env->config->nareg);
 164     if (phys + n <= env->config->nareg) {
 165         memcpy(env->regs + window, env->phys_regs + phys,
 166                 n * sizeof(uint32_t));
 167     } else {
 168         uint32_t n1 = env->config->nareg - phys;
 169         memcpy(env->regs + window, env->phys_regs + phys,
 170                 n1 * sizeof(uint32_t));
 171         memcpy(env->regs + window + n1, env->phys_regs,
 172                 (n - n1) * sizeof(uint32_t));
 173     }
 174 }
 175
 176 static void copy_phys_from_window(CPUXtensaState *env,
 177         uint32_t phys, uint32_t window, uint32_t n)
 178 {
 179     assert(phys < env->config->nareg);
 180     if (phys + n <= env->config->nareg) {
 181         memcpy(env->phys_regs + phys, env->regs + window,
 182                 n * sizeof(uint32_t));
 183     } else {
 184         uint32_t n1 = env->config->nareg - phys;
 185         memcpy(env->phys_regs + phys, env->regs + window,
 186                 n1 * sizeof(uint32_t));
 187         memcpy(env->phys_regs, env->regs + window + n1,
 188                 (n - n1) * sizeof(uint32_t));
 189     }
 190 }
 191
 192
 193 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
 194 {
 195     return a & (env->config->nareg / 4 - 1);
 196 }
 197
 198 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
 199 {
 200     return 1 << windowbase_bound(a, env);
 201 }
 202
 203 void xtensa_sync_window_from_phys(CPUXtensaState *env)
 204 {
 205     copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
 206 }
 207
 208 void xtensa_sync_phys_from_window(CPUXtensaState *env)
 209 {
 210     copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
 211 }
 212
 213 static void rotate_window_abs(CPUXtensaState *env, uint32_t position)
 214 {
 215     xtensa_sync_phys_from_window(env);
 216     env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
 217     xtensa_sync_window_from_phys(env);
 218 }
 219
 220 static void rotate_window(CPUXtensaState *env, uint32_t delta)
 221 {
 222     rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
 223 }
 224
 225 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
 226 {
 227     rotate_window_abs(env, v);
 228 }
 229
 230 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
 231 {
 232     int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
 233     if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 234         qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
 235                 pc, env->sregs[PS]);
 236         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 237     } else {
 238         uint32_t windowstart = xtensa_replicate_windowstart(env) >>
 239             (env->sregs[WINDOW_BASE] + 1);
 240
 241         if (windowstart & ((1 << callinc) - 1)) {
 242             HELPER(window_check)(env, pc, callinc);
 243         }
 244         env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
 245         rotate_window(env, callinc);
 246         env->sregs[WINDOW_START] |=
 247             windowstart_bit(env->sregs[WINDOW_BASE], env);
 248     }
 249 }
 250
 251 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
 252 {
 253     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 254     uint32_t windowstart = xtensa_replicate_windowstart(env) >>
 255         (env->sregs[WINDOW_BASE] + 1);
 256     uint32_t n = ctz32(windowstart) + 1;
 257
 258     assert(n <= w);
 259
 260     rotate_window(env, n);
 261     env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 262         (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 263     env->sregs[EPC1] = env->pc = pc;
 264
 265     switch (ctz32(windowstart >> n)) {
 266     case 0:
 267         HELPER(exception)(env, EXC_WINDOW_OVERFLOW4);
 268         break;
 269     case 1:
 270         HELPER(exception)(env, EXC_WINDOW_OVERFLOW8);
 271         break;
 272     default:
 273         HELPER(exception)(env, EXC_WINDOW_OVERFLOW12);
 274         break;
 275     }
 276 }
 277
 278 uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
 279 {
 280     int n = (env->regs[0] >> 30) & 0x3;
 281     int m = 0;
 282     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 283     uint32_t windowstart = env->sregs[WINDOW_START];
 284     uint32_t ret_pc = 0;
 285
 286     if (windowstart & windowstart_bit(windowbase - 1, env)) {
 287         m = 1;
 288     } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
 289         m = 2;
 290     } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
 291         m = 3;
 292     }
 293
 294     if (n == 0 || (m != 0 && m != n) ||
 295             ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 296         qemu_log("Illegal retw instruction(pc = %08x), "
 297                 "PS = %08x, m = %d, n = %d\n",
 298                 pc, env->sregs[PS], m, n);
 299         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 300     } else {
 301         int owb = windowbase;
 302
 303         ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
 304
 305         rotate_window(env, -n);
 306         if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
 307             env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
 308         } else {
 309             /* window underflow */
 310             env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 311                 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 312             env->sregs[EPC1] = env->pc = pc;
 313
 314             if (n == 1) {
 315                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
 316             } else if (n == 2) {
 317                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
 318             } else if (n == 3) {
 319                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
 320             }
 321         }
 322     }
 323     return ret_pc;
 324 }
 325
 326 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
 327 {
 328     rotate_window(env, imm4);
 329 }
 330
 331 void HELPER(restore_owb)(CPUXtensaState *env)
 332 {
 333     rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
 334 }
 335
 336 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc)
 337 {
 338     if ((env->sregs[WINDOW_START] &
 339             (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
 340              windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
 341              windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
 342         HELPER(exception_cause)(env, pc, ALLOCA_CAUSE);
 343     }
 344 }
 345
 346 void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v)
 347 {
 348     if (env->sregs[LBEG] != v) {
 349         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 350         env->sregs[LBEG] = v;
 351     }
 352 }
 353
 354 void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v)
 355 {
 356     if (env->sregs[LEND] != v) {
 357         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 358         env->sregs[LEND] = v;
 359         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 360     }
 361 }
 362
 363 void HELPER(dump_state)(CPUXtensaState *env)
 364 {
 365     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 366
 367     cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
 368 }
 369
 370 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
 371 {
 372     CPUState *cpu;
 373
 374     env->pc = pc;
 375     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
 376         (intlevel << PS_INTLEVEL_SHIFT);
 377     check_interrupts(env);
 378     if (env->pending_irq_level) {
 379         cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
 380         return;
 381     }
 382
 383     cpu = CPU(xtensa_env_get_cpu(env));
 384     env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 385     cpu->halted = 1;
 386     if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
 387         xtensa_rearm_ccompare_timer(env);
 388     }
 389     HELPER(exception)(env, EXCP_HLT);
 390 }
 391
 392 void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active)
 393 {
 394     xtensa_timer_irq(env, id, active);
 395 }
 396
 397 void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d)
 398 {
 399     xtensa_advance_ccount(env, d);
 400 }
 401
 402 void HELPER(check_interrupts)(CPUXtensaState *env)
 403 {
 404     check_interrupts(env);
 405 }
 406
 407 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
 408 {
 409     get_page_addr_code(env, vaddr);
 410 }
 411
 412 /*!
 413  * Check vaddr accessibility/cache attributes and raise an exception if
 414  * specified by the ATOMCTL SR.
 415  *
 416  * Note: local memory exclusion is not implemented
 417  */
 418 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
 419 {
 420     uint32_t paddr, page_size, access;
 421     uint32_t atomctl = env->sregs[ATOMCTL];
 422     int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
 423             xtensa_get_cring(env), &paddr, &page_size, &access);
 424
 425     /*
 426      * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
 427      * see opcode description in the ISA
 428      */
 429     if (rc == 0 &&
 430             (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
 431         rc = STORE_PROHIBITED_CAUSE;
 432     }
 433
 434     if (rc) {
 435         HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
 436     }
 437
 438     /*
 439      * When data cache is not configured use ATOMCTL bypass field.
 440      * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
 441      * under the Conditional Store Option.
 442      */
 443     if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
 444         access = PAGE_CACHE_BYPASS;
 445     }
 446
 447     switch (access & PAGE_CACHE_MASK) {
 448     case PAGE_CACHE_WB:
 449         atomctl >>= 2;
 450         /* fall through */
 451     case PAGE_CACHE_WT:
 452         atomctl >>= 2;
 453         /* fall through */
 454     case PAGE_CACHE_BYPASS:
 455         if ((atomctl & 0x3) == 0) {
 456             HELPER(exception_cause_vaddr)(env, pc,
 457                     LOAD_STORE_ERROR_CAUSE, vaddr);
 458         }
 459         break;
 460
 461     case PAGE_CACHE_ISOLATE:
 462         HELPER(exception_cause_vaddr)(env, pc,
 463                 LOAD_STORE_ERROR_CAUSE, vaddr);
 464         break;
 465
 466     default:
 467         break;
 468     }
 469 }
 470
 471 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
 472 {
 473     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 474
 475     v = (v & 0xffffff00) | 0x1;
 476     if (v != env->sregs[RASID]) {
 477         env->sregs[RASID] = v;
 478         tlb_flush(CPU(cpu), 1);
 479     }
 480 }
 481
 482 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
 483 {
 484     uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
 485
 486     switch (way) {
 487     case 4:
 488         return (tlbcfg >> 16) & 0x3;
 489
 490     case 5:
 491         return (tlbcfg >> 20) & 0x1;
 492
 493     case 6:
 494         return (tlbcfg >> 24) & 0x1;
 495
 496     default:
 497         return 0;
 498     }
 499 }
 500
 501 /*!
 502  * Get bit mask for the virtual address bits translated by the TLB way
 503  */
 504 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 505 {
 506     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 507         bool varway56 = dtlb ?
 508             env->config->dtlb.varway56 :
 509             env->config->itlb.varway56;
 510
 511         switch (way) {
 512         case 4:
 513             return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
 514
 515         case 5:
 516             if (varway56) {
 517                 return 0xf8000000 << get_page_size(env, dtlb, way);
 518             } else {
 519                 return 0xf8000000;
 520             }
 521
 522         case 6:
 523             if (varway56) {
 524                 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
 525             } else {
 526                 return 0xf0000000;
 527             }
 528
 529         default:
 530             return 0xfffff000;
 531         }
 532     } else {
 533         return REGION_PAGE_MASK;
 534     }
 535 }
 536
 537 /*!
 538  * Get bit mask for the 'VPN without index' field.
 539  * See ISA, 4.6.5.6, data format for RxTLB0
 540  */
 541 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 542 {
 543     if (way < 4) {
 544         bool is32 = (dtlb ?
 545                 env->config->dtlb.nrefillentries :
 546                 env->config->itlb.nrefillentries) == 32;
 547         return is32 ? 0xffff8000 : 0xffffc000;
 548     } else if (way == 4) {
 549         return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
 550     } else if (way <= 6) {
 551         uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
 552         bool varway56 = dtlb ?
 553             env->config->dtlb.varway56 :
 554             env->config->itlb.varway56;
 555
 556         if (varway56) {
 557             return mask << (way == 5 ? 2 : 3);
 558         } else {
 559             return mask << 1;
 560         }
 561     } else {
 562         return 0xfffff000;
 563     }
 564 }
 565
 566 /*!
 567  * Split virtual address into VPN (with index) and entry index
 568  * for the given TLB way
 569  */
 570 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 571         uint32_t *vpn, uint32_t wi, uint32_t *ei)
 572 {
 573     bool varway56 = dtlb ?
 574         env->config->dtlb.varway56 :
 575         env->config->itlb.varway56;
 576
 577     if (!dtlb) {
 578         wi &= 7;
 579     }
 580
 581     if (wi < 4) {
 582         bool is32 = (dtlb ?
 583                 env->config->dtlb.nrefillentries :
 584                 env->config->itlb.nrefillentries) == 32;
 585         *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
 586     } else {
 587         switch (wi) {
 588         case 4:
 589             {
 590                 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
 591                 *ei = (v >> eibase) & 0x3;
 592             }
 593             break;
 594
 595         case 5:
 596             if (varway56) {
 597                 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
 598                 *ei = (v >> eibase) & 0x3;
 599             } else {
 600                 *ei = (v >> 27) & 0x1;
 601             }
 602             break;
 603
 604         case 6:
 605             if (varway56) {
 606                 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
 607                 *ei = (v >> eibase) & 0x7;
 608             } else {
 609                 *ei = (v >> 28) & 0x1;
 610             }
 611             break;
 612
 613         default:
 614             *ei = 0;
 615             break;
 616         }
 617     }
 618     *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 619 }
 620
 621 /*!
 622  * Split TLB address into TLB way, entry index and VPN (with index).
 623  * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
 624  */
 625 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
 626         uint32_t *vpn, uint32_t *wi, uint32_t *ei)
 627 {
 628     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 629         *wi = v & (dtlb ? 0xf : 0x7);
 630         split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
 631     } else {
 632         *vpn = v & REGION_PAGE_MASK;
 633         *wi = 0;
 634         *ei = (v >> 29) & 0x7;
 635     }
 636 }
 637
 638 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
 639         uint32_t v, bool dtlb, uint32_t *pwi)
 640 {
 641     uint32_t vpn;
 642     uint32_t wi;
 643     uint32_t ei;
 644
 645     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 646     if (pwi) {
 647         *pwi = wi;
 648     }
 649     return xtensa_tlb_get_entry(env, dtlb, wi, ei);
 650 }
 651
 652 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 653 {
 654     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 655         uint32_t wi;
 656         const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 657         return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
 658     } else {
 659         return v & REGION_PAGE_MASK;
 660     }
 661 }
 662
 663 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 664 {
 665     const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
 666     return entry->paddr | entry->attr;
 667 }
 668
 669 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 670 {
 671     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 672         uint32_t wi;
 673         xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 674         if (entry->variable && entry->asid) {
 675             tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
 676             entry->asid = 0;
 677         }
 678     }
 679 }
 680
 681 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 682 {
 683     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 684         uint32_t wi;
 685         uint32_t ei;
 686         uint8_t ring;
 687         int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
 688
 689         switch (res) {
 690         case 0:
 691             if (ring >= xtensa_get_ring(env)) {
 692                 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
 693             }
 694             break;
 695
 696         case INST_TLB_MULTI_HIT_CAUSE:
 697         case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
 698             HELPER(exception_cause_vaddr)(env, env->pc, res, v);
 699             break;
 700         }
 701         return 0;
 702     } else {
 703         return (v & REGION_PAGE_MASK) | 0x1;
 704     }
 705 }
 706
 707 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 708         xtensa_tlb_entry *entry, bool dtlb,
 709         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 710 {
 711     entry->vaddr = vpn;
 712     entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 713     entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
 714     entry->attr = pte & 0xf;
 715 }
 716
 717 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 718         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 719 {
 720     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 721     CPUState *cs = CPU(cpu);
 722     xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 723
 724     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 725         if (entry->variable) {
 726             if (entry->asid) {
 727                 tlb_flush_page(cs, entry->vaddr);
 728             }
 729             xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
 730             tlb_flush_page(cs, entry->vaddr);
 731         } else {
 732             qemu_log("%s %d, %d, %d trying to set immutable entry\n",
 733                     __func__, dtlb, wi, ei);
 734         }
 735     } else {
 736         tlb_flush_page(cs, entry->vaddr);
 737         if (xtensa_option_enabled(env->config,
 738                     XTENSA_OPTION_REGION_TRANSLATION)) {
 739             entry->paddr = pte & REGION_PAGE_MASK;
 740         }
 741         entry->attr = pte & 0xf;
 742     }
 743 }
 744
 745 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
 746 {
 747     uint32_t vpn;
 748     uint32_t wi;
 749     uint32_t ei;
 750     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 751     xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
 752 }
 753
 754
 755 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
 756 {
 757     uint32_t change = v ^ env->sregs[IBREAKENABLE];
 758     unsigned i;
 759
 760     for (i = 0; i < env->config->nibreak; ++i) {
 761         if (change & (1 << i)) {
 762             tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 763         }
 764     }
 765     env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
 766 }
 767
 768 void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 769 {
 770     if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
 771         tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 772         tb_invalidate_virtual_addr(env, v);
 773     }
 774     env->sregs[IBREAKA + i] = v;
 775 }
 776
 777 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
 778         uint32_t dbreakc)
 779 {
 780     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 781     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
 782     uint32_t mask = dbreakc | ~DBREAKC_MASK;
 783
 784     if (env->cpu_watchpoint[i]) {
 785         cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
 786     }
 787     if (dbreakc & DBREAKC_SB) {
 788         flags |= BP_MEM_WRITE;
 789     }
 790     if (dbreakc & DBREAKC_LB) {
 791         flags |= BP_MEM_READ;
 792     }
 793     /* contiguous mask after inversion is one less than some power of 2 */
 794     if ((~mask + 1) & ~mask) {
 795         qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
 796         /* cut mask after the first zero bit */
 797         mask = 0xffffffff << (32 - clo32(mask));
 798     }
 799     if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
 800             flags, &env->cpu_watchpoint[i])) {
 801         env->cpu_watchpoint[i] = NULL;
 802         qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
 803                 dbreaka & mask, ~mask + 1);
 804     }
 805 }
 806
 807 void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 808 {
 809     uint32_t dbreakc = env->sregs[DBREAKC + i];
 810
 811     if ((dbreakc & DBREAKC_SB_LB) &&
 812             env->sregs[DBREAKA + i] != v) {
 813         set_dbreak(env, i, v, dbreakc);
 814     }
 815     env->sregs[DBREAKA + i] = v;
 816 }
 817
 818 void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
 819 {
 820     if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
 821         if (v & DBREAKC_SB_LB) {
 822             set_dbreak(env, i, env->sregs[DBREAKA + i], v);
 823         } else {
 824             if (env->cpu_watchpoint[i]) {
 825                 CPUState *cs = CPU(xtensa_env_get_cpu(env));
 826
 827                 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
 828                 env->cpu_watchpoint[i] = NULL;
 829             }
 830         }
 831     }
 832     env->sregs[DBREAKC + i] = v;
 833 }
 834
 835 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
 836 {
 837     static const int rounding_mode[] = {
 838         float_round_nearest_even,
 839         float_round_to_zero,
 840         float_round_up,
 841         float_round_down,
 842     };
 843
 844     env->uregs[FCR] = v & 0xfffff07f;
 845     set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
 846 }
 847
 848 float32 HELPER(abs_s)(float32 v)
 849 {
 850     return float32_abs(v);
 851 }
 852
 853 float32 HELPER(neg_s)(float32 v)
 854 {
 855     return float32_chs(v);
 856 }
 857
 858 float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
 859 {
 860     return float32_add(a, b, &env->fp_status);
 861 }
 862
 863 float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
 864 {
 865     return float32_sub(a, b, &env->fp_status);
 866 }
 867
 868 float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
 869 {
 870     return float32_mul(a, b, &env->fp_status);
 871 }
 872
 873 float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 874 {
 875     return float32_muladd(b, c, a, 0,
 876             &env->fp_status);
 877 }
 878
 879 float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 880 {
 881     return float32_muladd(b, c, a, float_muladd_negate_product,
 882             &env->fp_status);
 883 }
 884
 885 uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
 886 {
 887     float_status fp_status = {0};
 888
 889     set_float_rounding_mode(rounding_mode, &fp_status);
 890     return float32_to_int32(
 891             float32_scalbn(v, scale, &fp_status), &fp_status);
 892 }
 893
 894 uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
 895 {
 896     float_status fp_status = {0};
 897     float32 res;
 898
 899     set_float_rounding_mode(rounding_mode, &fp_status);
 900
 901     res = float32_scalbn(v, scale, &fp_status);
 902
 903     if (float32_is_neg(v) && !float32_is_any_nan(v)) {
 904         return float32_to_int32(res, &fp_status);
 905     } else {
 906         return float32_to_uint32(res, &fp_status);
 907     }
 908 }
 909
 910 float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 911 {
 912     return float32_scalbn(int32_to_float32(v, &env->fp_status),
 913             (int32_t)scale, &env->fp_status);
 914 }
 915
 916 float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 917 {
 918     return float32_scalbn(uint32_to_float32(v, &env->fp_status),
 919             (int32_t)scale, &env->fp_status);
 920 }
 921
 922 static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
 923 {
 924     if (v) {
 925         env->sregs[BR] |= br;
 926     } else {
 927         env->sregs[BR] &= ~br;
 928     }
 929 }
 930
 931 void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 932 {
 933     set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
 934 }
 935
 936 void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 937 {
 938     set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
 939 }
 940
 941 void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 942 {
 943     int v = float32_compare_quiet(a, b, &env->fp_status);
 944     set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
 945 }
 946
 947 void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 948 {
 949     set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
 950 }
 951
 952 void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 953 {
 954     int v = float32_compare_quiet(a, b, &env->fp_status);
 955     set_br(env, v == float_relation_less || v == float_relation_unordered, br);
 956 }
 957
 958 void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 959 {
 960     set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
 961 }
 962
 963 void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 964 {
 965     int v = float32_compare_quiet(a, b, &env->fp_status);
 966     set_br(env, v != float_relation_greater, br);
 967 }