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block: Close backing file early in bdrv_img_create
[qemu/cris-port.git] / hw / net / rtl8139.c
blob5329f44a9dfd73a5d93201accdab70b8097a2572
1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
49 */
50
51 /* For crc32 */
52 #include <zlib.h>
53
54 #include "hw/hw.h"
55 #include "hw/pci/pci.h"
56 #include "sysemu/dma.h"
57 #include "qemu/timer.h"
58 #include "net/net.h"
59 #include "hw/loader.h"
60 #include "sysemu/sysemu.h"
61 #include "qemu/iov.h"
62
63 /* debug RTL8139 card */
64 //#define DEBUG_RTL8139 1
65
66 #define PCI_FREQUENCY 33000000L
67
68 #define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70
71 /* arg % size for size which is a power of 2 */
72 #define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
74
75 #define ETHER_ADDR_LEN 6
76 #define ETHER_TYPE_LEN 2
77 #define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
78 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
79 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
80 #define ETH_MTU 1500
81
82 #define VLAN_TCI_LEN 2
83 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
84
85 #if defined (DEBUG_RTL8139)
86 # define DPRINTF(fmt, ...) \
87 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
88 #else
89 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
90 {
91 return 0;
92 }
93 #endif
94
95 #define TYPE_RTL8139 "rtl8139"
96
97 #define RTL8139(obj) \
98 OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139)
99
100 /* Symbolic offsets to registers. */
101 enum RTL8139_registers {
102 MAC0 = 0, /* Ethernet hardware address. */
103 MAR0 = 8, /* Multicast filter. */
104 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
105 /* Dump Tally Conter control register(64bit). C+ mode only */
106 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
107 RxBuf = 0x30,
108 ChipCmd = 0x37,
109 RxBufPtr = 0x38,
110 RxBufAddr = 0x3A,
111 IntrMask = 0x3C,
112 IntrStatus = 0x3E,
113 TxConfig = 0x40,
114 RxConfig = 0x44,
115 Timer = 0x48, /* A general-purpose counter. */
116 RxMissed = 0x4C, /* 24 bits valid, write clears. */
117 Cfg9346 = 0x50,
118 Config0 = 0x51,
119 Config1 = 0x52,
120 FlashReg = 0x54,
121 MediaStatus = 0x58,
122 Config3 = 0x59,
123 Config4 = 0x5A, /* absent on RTL-8139A */
124 HltClk = 0x5B,
125 MultiIntr = 0x5C,
126 PCIRevisionID = 0x5E,
127 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
128 BasicModeCtrl = 0x62,
129 BasicModeStatus = 0x64,
130 NWayAdvert = 0x66,
131 NWayLPAR = 0x68,
132 NWayExpansion = 0x6A,
133 /* Undocumented registers, but required for proper operation. */
134 FIFOTMS = 0x70, /* FIFO Control and test. */
135 CSCR = 0x74, /* Chip Status and Configuration Register. */
136 PARA78 = 0x78,
137 PARA7c = 0x7c, /* Magic transceiver parameter register. */
138 Config5 = 0xD8, /* absent on RTL-8139A */
139 /* C+ mode */
140 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
141 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
142 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
143 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
144 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
145 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
146 TxThresh = 0xEC, /* Early Tx threshold */
147 };
148
149 enum ClearBitMasks {
150 MultiIntrClear = 0xF000,
151 ChipCmdClear = 0xE2,
152 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
153 };
154
155 enum ChipCmdBits {
156 CmdReset = 0x10,
157 CmdRxEnb = 0x08,
158 CmdTxEnb = 0x04,
159 RxBufEmpty = 0x01,
160 };
161
162 /* C+ mode */
163 enum CplusCmdBits {
164 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
165 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
166 CPlusRxEnb = 0x0002,
167 CPlusTxEnb = 0x0001,
168 };
169
170 /* Interrupt register bits, using my own meaningful names. */
171 enum IntrStatusBits {
172 PCIErr = 0x8000,
173 PCSTimeout = 0x4000,
174 RxFIFOOver = 0x40,
175 RxUnderrun = 0x20, /* Packet Underrun / Link Change */
176 RxOverflow = 0x10,
177 TxErr = 0x08,
178 TxOK = 0x04,
179 RxErr = 0x02,
180 RxOK = 0x01,
181
182 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
183 };
184
185 enum TxStatusBits {
186 TxHostOwns = 0x2000,
187 TxUnderrun = 0x4000,
188 TxStatOK = 0x8000,
189 TxOutOfWindow = 0x20000000,
190 TxAborted = 0x40000000,
191 TxCarrierLost = 0x80000000,
192 };
193 enum RxStatusBits {
194 RxMulticast = 0x8000,
195 RxPhysical = 0x4000,
196 RxBroadcast = 0x2000,
197 RxBadSymbol = 0x0020,
198 RxRunt = 0x0010,
199 RxTooLong = 0x0008,
200 RxCRCErr = 0x0004,
201 RxBadAlign = 0x0002,
202 RxStatusOK = 0x0001,
203 };
204
205 /* Bits in RxConfig. */
206 enum rx_mode_bits {
207 AcceptErr = 0x20,
208 AcceptRunt = 0x10,
209 AcceptBroadcast = 0x08,
210 AcceptMulticast = 0x04,
211 AcceptMyPhys = 0x02,
212 AcceptAllPhys = 0x01,
213 };
214
215 /* Bits in TxConfig. */
216 enum tx_config_bits {
217
218 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
219 TxIFGShift = 24,
220 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
221 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
222 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
223 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
224
225 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
226 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
227 TxClearAbt = (1 << 0), /* Clear abort (WO) */
228 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
229 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
230
231 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
232 };
233
234
235 /* Transmit Status of All Descriptors (TSAD) Register */
236 enum TSAD_bits {
237 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
238 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
239 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
240 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
241 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
242 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
243 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
244 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
245 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
246 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
247 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
248 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
249 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
250 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
251 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
252 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
253 };
254
255
256 /* Bits in Config1 */
257 enum Config1Bits {
258 Cfg1_PM_Enable = 0x01,
259 Cfg1_VPD_Enable = 0x02,
260 Cfg1_PIO = 0x04,
261 Cfg1_MMIO = 0x08,
262 LWAKE = 0x10, /* not on 8139, 8139A */
263 Cfg1_Driver_Load = 0x20,
264 Cfg1_LED0 = 0x40,
265 Cfg1_LED1 = 0x80,
266 SLEEP = (1 << 1), /* only on 8139, 8139A */
267 PWRDN = (1 << 0), /* only on 8139, 8139A */
268 };
269
270 /* Bits in Config3 */
271 enum Config3Bits {
272 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
273 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
274 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
275 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
276 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
277 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
278 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
279 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
280 };
281
282 /* Bits in Config4 */
283 enum Config4Bits {
284 LWPTN = (1 << 2), /* not on 8139, 8139A */
285 };
286
287 /* Bits in Config5 */
288 enum Config5Bits {
289 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
290 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
291 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
292 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
293 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
294 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
295 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
296 };
297
298 enum RxConfigBits {
299 /* rx fifo threshold */
300 RxCfgFIFOShift = 13,
301 RxCfgFIFONone = (7 << RxCfgFIFOShift),
302
303 /* Max DMA burst */
304 RxCfgDMAShift = 8,
305 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
306
307 /* rx ring buffer length */
308 RxCfgRcv8K = 0,
309 RxCfgRcv16K = (1 << 11),
310 RxCfgRcv32K = (1 << 12),
311 RxCfgRcv64K = (1 << 11) | (1 << 12),
312
313 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
314 RxNoWrap = (1 << 7),
315 };
316
317 /* Twister tuning parameters from RealTek.
318 Completely undocumented, but required to tune bad links on some boards. */
319 /*
320 enum CSCRBits {
321 CSCR_LinkOKBit = 0x0400,
322 CSCR_LinkChangeBit = 0x0800,
323 CSCR_LinkStatusBits = 0x0f000,
324 CSCR_LinkDownOffCmd = 0x003c0,
325 CSCR_LinkDownCmd = 0x0f3c0,
326 */
327 enum CSCRBits {
328 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
329 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
330 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
331 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
332 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
333 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
334 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
335 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
336 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
337 };
338
339 enum Cfg9346Bits {
340 Cfg9346_Normal = 0x00,
341 Cfg9346_Autoload = 0x40,
342 Cfg9346_Programming = 0x80,
343 Cfg9346_ConfigWrite = 0xC0,
344 };
345
346 typedef enum {
347 CH_8139 = 0,
348 CH_8139_K,
349 CH_8139A,
350 CH_8139A_G,
351 CH_8139B,
352 CH_8130,
353 CH_8139C,
354 CH_8100,
355 CH_8100B_8139D,
356 CH_8101,
357 } chip_t;
358
359 enum chip_flags {
360 HasHltClk = (1 << 0),
361 HasLWake = (1 << 1),
362 };
363
364 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
365 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
366 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
367
368 #define RTL8139_PCI_REVID_8139 0x10
369 #define RTL8139_PCI_REVID_8139CPLUS 0x20
370
371 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
372
373 /* Size is 64 * 16bit words */
374 #define EEPROM_9346_ADDR_BITS 6
375 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
376 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
377
378 enum Chip9346Operation
379 {
380 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
381 Chip9346_op_read = 0x80, /* 10 AAAAAA */
382 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
383 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
384 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
385 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
386 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
387 };
388
389 enum Chip9346Mode
390 {
391 Chip9346_none = 0,
392 Chip9346_enter_command_mode,
393 Chip9346_read_command,
394 Chip9346_data_read, /* from output register */
395 Chip9346_data_write, /* to input register, then to contents at specified address */
396 Chip9346_data_write_all, /* to input register, then filling contents */
397 };
398
399 typedef struct EEprom9346
400 {
401 uint16_t contents[EEPROM_9346_SIZE];
402 int mode;
403 uint32_t tick;
404 uint8_t address;
405 uint16_t input;
406 uint16_t output;
407
408 uint8_t eecs;
409 uint8_t eesk;
410 uint8_t eedi;
411 uint8_t eedo;
412 } EEprom9346;
413
414 typedef struct RTL8139TallyCounters
415 {
416 /* Tally counters */
417 uint64_t TxOk;
418 uint64_t RxOk;
419 uint64_t TxERR;
420 uint32_t RxERR;
421 uint16_t MissPkt;
422 uint16_t FAE;
423 uint32_t Tx1Col;
424 uint32_t TxMCol;
425 uint64_t RxOkPhy;
426 uint64_t RxOkBrd;
427 uint32_t RxOkMul;
428 uint16_t TxAbt;
429 uint16_t TxUndrn;
430 } RTL8139TallyCounters;
431
432 /* Clears all tally counters */
433 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
434
435 typedef struct RTL8139State {
436 /*< private >*/
437 PCIDevice parent_obj;
438 /*< public >*/
439
440 uint8_t phys[8]; /* mac address */
441 uint8_t mult[8]; /* multicast mask array */
442
443 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
444 uint32_t TxAddr[4]; /* TxAddr0 */
445 uint32_t RxBuf; /* Receive buffer */
446 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
447 uint32_t RxBufPtr;
448 uint32_t RxBufAddr;
449
450 uint16_t IntrStatus;
451 uint16_t IntrMask;
452
453 uint32_t TxConfig;
454 uint32_t RxConfig;
455 uint32_t RxMissed;
456
457 uint16_t CSCR;
458
459 uint8_t Cfg9346;
460 uint8_t Config0;
461 uint8_t Config1;
462 uint8_t Config3;
463 uint8_t Config4;
464 uint8_t Config5;
465
466 uint8_t clock_enabled;
467 uint8_t bChipCmdState;
468
469 uint16_t MultiIntr;
470
471 uint16_t BasicModeCtrl;
472 uint16_t BasicModeStatus;
473 uint16_t NWayAdvert;
474 uint16_t NWayLPAR;
475 uint16_t NWayExpansion;
476
477 uint16_t CpCmd;
478 uint8_t TxThresh;
479
480 NICState *nic;
481 NICConf conf;
482
483 /* C ring mode */
484 uint32_t currTxDesc;
485
486 /* C+ mode */
487 uint32_t cplus_enabled;
488
489 uint32_t currCPlusRxDesc;
490 uint32_t currCPlusTxDesc;
491
492 uint32_t RxRingAddrLO;
493 uint32_t RxRingAddrHI;
494
495 EEprom9346 eeprom;
496
497 uint32_t TCTR;
498 uint32_t TimerInt;
499 int64_t TCTR_base;
500
501 /* Tally counters */
502 RTL8139TallyCounters tally_counters;
503
504 /* Non-persistent data */
505 uint8_t *cplus_txbuffer;
506 int cplus_txbuffer_len;
507 int cplus_txbuffer_offset;
508
509 /* PCI interrupt timer */
510 QEMUTimer *timer;
511 int64_t TimerExpire;
512
513 MemoryRegion bar_io;
514 MemoryRegion bar_mem;
515
516 /* Support migration to/from old versions */
517 int rtl8139_mmio_io_addr_dummy;
518 } RTL8139State;
519
520 /* Writes tally counters to memory via DMA */
521 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
522
523 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
524
525 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
526 {
527 DPRINTF("eeprom command 0x%02x\n", command);
528
529 switch (command & Chip9346_op_mask)
530 {
531 case Chip9346_op_read:
532 {
533 eeprom->address = command & EEPROM_9346_ADDR_MASK;
534 eeprom->output = eeprom->contents[eeprom->address];
535 eeprom->eedo = 0;
536 eeprom->tick = 0;
537 eeprom->mode = Chip9346_data_read;
538 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
539 eeprom->address, eeprom->output);
540 }
541 break;
542
543 case Chip9346_op_write:
544 {
545 eeprom->address = command & EEPROM_9346_ADDR_MASK;
546 eeprom->input = 0;
547 eeprom->tick = 0;
548 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
549 DPRINTF("eeprom begin write to address 0x%02x\n",
550 eeprom->address);
551 }
552 break;
553 default:
554 eeprom->mode = Chip9346_none;
555 switch (command & Chip9346_op_ext_mask)
556 {
557 case Chip9346_op_write_enable:
558 DPRINTF("eeprom write enabled\n");
559 break;
560 case Chip9346_op_write_all:
561 DPRINTF("eeprom begin write all\n");
562 break;
563 case Chip9346_op_write_disable:
564 DPRINTF("eeprom write disabled\n");
565 break;
566 }
567 break;
568 }
569 }
570
571 static void prom9346_shift_clock(EEprom9346 *eeprom)
572 {
573 int bit = eeprom->eedi?1:0;
574
575 ++ eeprom->tick;
576
577 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
578 eeprom->eedo);
579
580 switch (eeprom->mode)
581 {
582 case Chip9346_enter_command_mode:
583 if (bit)
584 {
585 eeprom->mode = Chip9346_read_command;
586 eeprom->tick = 0;
587 eeprom->input = 0;
588 DPRINTF("eeprom: +++ synchronized, begin command read\n");
589 }
590 break;
591
592 case Chip9346_read_command:
593 eeprom->input = (eeprom->input << 1) | (bit & 1);
594 if (eeprom->tick == 8)
595 {
596 prom9346_decode_command(eeprom, eeprom->input & 0xff);
597 }
598 break;
599
600 case Chip9346_data_read:
601 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
602 eeprom->output <<= 1;
603 if (eeprom->tick == 16)
604 {
605 #if 1
606 // the FreeBSD drivers (rl and re) don't explicitly toggle
607 // CS between reads (or does setting Cfg9346 to 0 count too?),
608 // so we need to enter wait-for-command state here
609 eeprom->mode = Chip9346_enter_command_mode;
610 eeprom->input = 0;
611 eeprom->tick = 0;
612
613 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
614 #else
615 // original behaviour
616 ++eeprom->address;
617 eeprom->address &= EEPROM_9346_ADDR_MASK;
618 eeprom->output = eeprom->contents[eeprom->address];
619 eeprom->tick = 0;
620
621 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
622 eeprom->address, eeprom->output);
623 #endif
624 }
625 break;
626
627 case Chip9346_data_write:
628 eeprom->input = (eeprom->input << 1) | (bit & 1);
629 if (eeprom->tick == 16)
630 {
631 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
632 eeprom->address, eeprom->input);
633
634 eeprom->contents[eeprom->address] = eeprom->input;
635 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
636 eeprom->tick = 0;
637 eeprom->input = 0;
638 }
639 break;
640
641 case Chip9346_data_write_all:
642 eeprom->input = (eeprom->input << 1) | (bit & 1);
643 if (eeprom->tick == 16)
644 {
645 int i;
646 for (i = 0; i < EEPROM_9346_SIZE; i++)
647 {
648 eeprom->contents[i] = eeprom->input;
649 }
650 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
651
652 eeprom->mode = Chip9346_enter_command_mode;
653 eeprom->tick = 0;
654 eeprom->input = 0;
655 }
656 break;
657
658 default:
659 break;
660 }
661 }
662
663 static int prom9346_get_wire(RTL8139State *s)
664 {
665 EEprom9346 *eeprom = &s->eeprom;
666 if (!eeprom->eecs)
667 return 0;
668
669 return eeprom->eedo;
670 }
671
672 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
673 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
674 {
675 EEprom9346 *eeprom = &s->eeprom;
676 uint8_t old_eecs = eeprom->eecs;
677 uint8_t old_eesk = eeprom->eesk;
678
679 eeprom->eecs = eecs;
680 eeprom->eesk = eesk;
681 eeprom->eedi = eedi;
682
683 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
684 eeprom->eesk, eeprom->eedi, eeprom->eedo);
685
686 if (!old_eecs && eecs)
687 {
688 /* Synchronize start */
689 eeprom->tick = 0;
690 eeprom->input = 0;
691 eeprom->output = 0;
692 eeprom->mode = Chip9346_enter_command_mode;
693
694 DPRINTF("=== eeprom: begin access, enter command mode\n");
695 }
696
697 if (!eecs)
698 {
699 DPRINTF("=== eeprom: end access\n");
700 return;
701 }
702
703 if (!old_eesk && eesk)
704 {
705 /* SK front rules */
706 prom9346_shift_clock(eeprom);
707 }
708 }
709
710 static void rtl8139_update_irq(RTL8139State *s)
711 {
712 PCIDevice *d = PCI_DEVICE(s);
713 int isr;
714 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
715
716 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
717 s->IntrMask);
718
719 pci_set_irq(d, (isr != 0));
720 }
721
722 static int rtl8139_RxWrap(RTL8139State *s)
723 {
724 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
725 return (s->RxConfig & (1 << 7));
726 }
727
728 static int rtl8139_receiver_enabled(RTL8139State *s)
729 {
730 return s->bChipCmdState & CmdRxEnb;
731 }
732
733 static int rtl8139_transmitter_enabled(RTL8139State *s)
734 {
735 return s->bChipCmdState & CmdTxEnb;
736 }
737
738 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
739 {
740 return s->CpCmd & CPlusRxEnb;
741 }
742
743 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
744 {
745 return s->CpCmd & CPlusTxEnb;
746 }
747
748 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
749 {
750 PCIDevice *d = PCI_DEVICE(s);
751
752 if (s->RxBufAddr + size > s->RxBufferSize)
753 {
754 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
755
756 /* write packet data */
757 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
758 {
759 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
760
761 if (size > wrapped)
762 {
763 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
764 buf, size-wrapped);
765 }
766
767 /* reset buffer pointer */
768 s->RxBufAddr = 0;
769
770 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
771 buf + (size-wrapped), wrapped);
772
773 s->RxBufAddr = wrapped;
774
775 return;
776 }
777 }
778
779 /* non-wrapping path or overwrapping enabled */
780 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size);
781
782 s->RxBufAddr += size;
783 }
784
785 #define MIN_BUF_SIZE 60
786 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
787 {
788 return low | ((uint64_t)high << 32);
789 }
790
791 /* Workaround for buggy guest driver such as linux who allocates rx
792 * rings after the receiver were enabled. */
793 static bool rtl8139_cp_rx_valid(RTL8139State *s)
794 {
795 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
796 }
797
798 static int rtl8139_can_receive(NetClientState *nc)
799 {
800 RTL8139State *s = qemu_get_nic_opaque(nc);
801 int avail;
802
803 /* Receive (drop) packets if card is disabled. */
804 if (!s->clock_enabled)
805 return 1;
806 if (!rtl8139_receiver_enabled(s))
807 return 1;
808
809 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
810 /* ??? Flow control not implemented in c+ mode.
811 This is a hack to work around slirp deficiencies anyway. */
812 return 1;
813 } else {
814 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
815 s->RxBufferSize);
816 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow));
817 }
818 }
819
820 static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
821 {
822 RTL8139State *s = qemu_get_nic_opaque(nc);
823 PCIDevice *d = PCI_DEVICE(s);
824 /* size is the length of the buffer passed to the driver */
825 int size = size_;
826 const uint8_t *dot1q_buf = NULL;
827
828 uint32_t packet_header = 0;
829
830 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
831 static const uint8_t broadcast_macaddr[6] =
832 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
833
834 DPRINTF(">>> received len=%d\n", size);
835
836 /* test if board clock is stopped */
837 if (!s->clock_enabled)
838 {
839 DPRINTF("stopped ==========================\n");
840 return -1;
841 }
842
843 /* first check if receiver is enabled */
844
845 if (!rtl8139_receiver_enabled(s))
846 {
847 DPRINTF("receiver disabled ================\n");
848 return -1;
849 }
850
851 /* XXX: check this */
852 if (s->RxConfig & AcceptAllPhys) {
853 /* promiscuous: receive all */
854 DPRINTF(">>> packet received in promiscuous mode\n");
855
856 } else {
857 if (!memcmp(buf, broadcast_macaddr, 6)) {
858 /* broadcast address */
859 if (!(s->RxConfig & AcceptBroadcast))
860 {
861 DPRINTF(">>> broadcast packet rejected\n");
862
863 /* update tally counter */
864 ++s->tally_counters.RxERR;
865
866 return size;
867 }
868
869 packet_header |= RxBroadcast;
870
871 DPRINTF(">>> broadcast packet received\n");
872
873 /* update tally counter */
874 ++s->tally_counters.RxOkBrd;
875
876 } else if (buf[0] & 0x01) {
877 /* multicast */
878 if (!(s->RxConfig & AcceptMulticast))
879 {
880 DPRINTF(">>> multicast packet rejected\n");
881
882 /* update tally counter */
883 ++s->tally_counters.RxERR;
884
885 return size;
886 }
887
888 int mcast_idx = compute_mcast_idx(buf);
889
890 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
891 {
892 DPRINTF(">>> multicast address mismatch\n");
893
894 /* update tally counter */
895 ++s->tally_counters.RxERR;
896
897 return size;
898 }
899
900 packet_header |= RxMulticast;
901
902 DPRINTF(">>> multicast packet received\n");
903
904 /* update tally counter */
905 ++s->tally_counters.RxOkMul;
906
907 } else if (s->phys[0] == buf[0] &&
908 s->phys[1] == buf[1] &&
909 s->phys[2] == buf[2] &&
910 s->phys[3] == buf[3] &&
911 s->phys[4] == buf[4] &&
912 s->phys[5] == buf[5]) {
913 /* match */
914 if (!(s->RxConfig & AcceptMyPhys))
915 {
916 DPRINTF(">>> rejecting physical address matching packet\n");
917
918 /* update tally counter */
919 ++s->tally_counters.RxERR;
920
921 return size;
922 }
923
924 packet_header |= RxPhysical;
925
926 DPRINTF(">>> physical address matching packet received\n");
927
928 /* update tally counter */
929 ++s->tally_counters.RxOkPhy;
930
931 } else {
932
933 DPRINTF(">>> unknown packet\n");
934
935 /* update tally counter */
936 ++s->tally_counters.RxERR;
937
938 return size;
939 }
940 }
941
942 /* if too small buffer, then expand it
943 * Include some tailroom in case a vlan tag is later removed. */
944 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
945 memcpy(buf1, buf, size);
946 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
947 buf = buf1;
948 if (size < MIN_BUF_SIZE) {
949 size = MIN_BUF_SIZE;
950 }
951 }
952
953 if (rtl8139_cp_receiver_enabled(s))
954 {
955 if (!rtl8139_cp_rx_valid(s)) {
956 return size;
957 }
958
959 DPRINTF("in C+ Rx mode ================\n");
960
961 /* begin C+ receiver mode */
962
963 /* w0 ownership flag */
964 #define CP_RX_OWN (1<<31)
965 /* w0 end of ring flag */
966 #define CP_RX_EOR (1<<30)
967 /* w0 bits 0...12 : buffer size */
968 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
969 /* w1 tag available flag */
970 #define CP_RX_TAVA (1<<16)
971 /* w1 bits 0...15 : VLAN tag */
972 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
973 /* w2 low 32bit of Rx buffer ptr */
974 /* w3 high 32bit of Rx buffer ptr */
975
976 int descriptor = s->currCPlusRxDesc;
977 dma_addr_t cplus_rx_ring_desc;
978
979 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
980 cplus_rx_ring_desc += 16 * descriptor;
981
982 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
983 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
984 s->RxRingAddrLO, cplus_rx_ring_desc);
985
986 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
987
988 pci_dma_read(d, cplus_rx_ring_desc, &val, 4);
989 rxdw0 = le32_to_cpu(val);
990 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4);
991 rxdw1 = le32_to_cpu(val);
992 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4);
993 rxbufLO = le32_to_cpu(val);
994 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4);
995 rxbufHI = le32_to_cpu(val);
996
997 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
998 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
999
1000 if (!(rxdw0 & CP_RX_OWN))
1001 {
1002 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1003 descriptor);
1004
1005 s->IntrStatus |= RxOverflow;
1006 ++s->RxMissed;
1007
1008 /* update tally counter */
1009 ++s->tally_counters.RxERR;
1010 ++s->tally_counters.MissPkt;
1011
1012 rtl8139_update_irq(s);
1013 return size_;
1014 }
1015
1016 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1017
1018 /* write VLAN info to descriptor variables. */
1019 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1020 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1021 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1022 size -= VLAN_HLEN;
1023 /* if too small buffer, use the tailroom added duing expansion */
1024 if (size < MIN_BUF_SIZE) {
1025 size = MIN_BUF_SIZE;
1026 }
1027
1028 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1029 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1030 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1031 &dot1q_buf[ETHER_TYPE_LEN]);
1032
1033 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1034 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
1035 } else {
1036 /* reset VLAN tag flag */
1037 rxdw1 &= ~CP_RX_TAVA;
1038 }
1039
1040 /* TODO: scatter the packet over available receive ring descriptors space */
1041
1042 if (size+4 > rx_space)
1043 {
1044 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1045 descriptor, rx_space, size);
1046
1047 s->IntrStatus |= RxOverflow;
1048 ++s->RxMissed;
1049
1050 /* update tally counter */
1051 ++s->tally_counters.RxERR;
1052 ++s->tally_counters.MissPkt;
1053
1054 rtl8139_update_irq(s);
1055 return size_;
1056 }
1057
1058 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1059
1060 /* receive/copy to target memory */
1061 if (dot1q_buf) {
1062 pci_dma_write(d, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1063 pci_dma_write(d, rx_addr + 2 * ETHER_ADDR_LEN,
1064 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1065 size - 2 * ETHER_ADDR_LEN);
1066 } else {
1067 pci_dma_write(d, rx_addr, buf, size);
1068 }
1069
1070 if (s->CpCmd & CPlusRxChkSum)
1071 {
1072 /* do some packet checksumming */
1073 }
1074
1075 /* write checksum */
1076 val = cpu_to_le32(crc32(0, buf, size_));
1077 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4);
1078
1079 /* first segment of received packet flag */
1080 #define CP_RX_STATUS_FS (1<<29)
1081 /* last segment of received packet flag */
1082 #define CP_RX_STATUS_LS (1<<28)
1083 /* multicast packet flag */
1084 #define CP_RX_STATUS_MAR (1<<26)
1085 /* physical-matching packet flag */
1086 #define CP_RX_STATUS_PAM (1<<25)
1087 /* broadcast packet flag */
1088 #define CP_RX_STATUS_BAR (1<<24)
1089 /* runt packet flag */
1090 #define CP_RX_STATUS_RUNT (1<<19)
1091 /* crc error flag */
1092 #define CP_RX_STATUS_CRC (1<<18)
1093 /* IP checksum error flag */
1094 #define CP_RX_STATUS_IPF (1<<15)
1095 /* UDP checksum error flag */
1096 #define CP_RX_STATUS_UDPF (1<<14)
1097 /* TCP checksum error flag */
1098 #define CP_RX_STATUS_TCPF (1<<13)
1099
1100 /* transfer ownership to target */
1101 rxdw0 &= ~CP_RX_OWN;
1102
1103 /* set first segment bit */
1104 rxdw0 |= CP_RX_STATUS_FS;
1105
1106 /* set last segment bit */
1107 rxdw0 |= CP_RX_STATUS_LS;
1108
1109 /* set received packet type flags */
1110 if (packet_header & RxBroadcast)
1111 rxdw0 |= CP_RX_STATUS_BAR;
1112 if (packet_header & RxMulticast)
1113 rxdw0 |= CP_RX_STATUS_MAR;
1114 if (packet_header & RxPhysical)
1115 rxdw0 |= CP_RX_STATUS_PAM;
1116
1117 /* set received size */
1118 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1119 rxdw0 |= (size+4);
1120
1121 /* update ring data */
1122 val = cpu_to_le32(rxdw0);
1123 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4);
1124 val = cpu_to_le32(rxdw1);
1125 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1126
1127 /* update tally counter */
1128 ++s->tally_counters.RxOk;
1129
1130 /* seek to next Rx descriptor */
1131 if (rxdw0 & CP_RX_EOR)
1132 {
1133 s->currCPlusRxDesc = 0;
1134 }
1135 else
1136 {
1137 ++s->currCPlusRxDesc;
1138 }
1139
1140 DPRINTF("done C+ Rx mode ----------------\n");
1141
1142 }
1143 else
1144 {
1145 DPRINTF("in ring Rx mode ================\n");
1146
1147 /* begin ring receiver mode */
1148 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1149
1150 /* if receiver buffer is empty then avail == 0 */
1151
1152 if (avail != 0 && size + 8 >= avail)
1153 {
1154 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1155 "read 0x%04x === available 0x%04x need 0x%04x\n",
1156 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
1157
1158 s->IntrStatus |= RxOverflow;
1159 ++s->RxMissed;
1160 rtl8139_update_irq(s);
1161 return size_;
1162 }
1163
1164 packet_header |= RxStatusOK;
1165
1166 packet_header |= (((size+4) << 16) & 0xffff0000);
1167
1168 /* write header */
1169 uint32_t val = cpu_to_le32(packet_header);
1170
1171 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1172
1173 rtl8139_write_buffer(s, buf, size);
1174
1175 /* write checksum */
1176 val = cpu_to_le32(crc32(0, buf, size));
1177 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1178
1179 /* correct buffer write pointer */
1180 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1181
1182 /* now we can signal we have received something */
1183
1184 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1185 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
1186 }
1187
1188 s->IntrStatus |= RxOK;
1189
1190 if (do_interrupt)
1191 {
1192 rtl8139_update_irq(s);
1193 }
1194
1195 return size_;
1196 }
1197
1198 static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1199 {
1200 return rtl8139_do_receive(nc, buf, size, 1);
1201 }
1202
1203 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1204 {
1205 s->RxBufferSize = bufferSize;
1206 s->RxBufPtr = 0;
1207 s->RxBufAddr = 0;
1208 }
1209
1210 static void rtl8139_reset(DeviceState *d)
1211 {
1212 RTL8139State *s = RTL8139(d);
1213 int i;
1214
1215 /* restore MAC address */
1216 memcpy(s->phys, s->conf.macaddr.a, 6);
1217 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
1218
1219 /* reset interrupt mask */
1220 s->IntrStatus = 0;
1221 s->IntrMask = 0;
1222
1223 rtl8139_update_irq(s);
1224
1225 /* mark all status registers as owned by host */
1226 for (i = 0; i < 4; ++i)
1227 {
1228 s->TxStatus[i] = TxHostOwns;
1229 }
1230
1231 s->currTxDesc = 0;
1232 s->currCPlusRxDesc = 0;
1233 s->currCPlusTxDesc = 0;
1234
1235 s->RxRingAddrLO = 0;
1236 s->RxRingAddrHI = 0;
1237
1238 s->RxBuf = 0;
1239
1240 rtl8139_reset_rxring(s, 8192);
1241
1242 /* ACK the reset */
1243 s->TxConfig = 0;
1244
1245 #if 0
1246 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1247 s->clock_enabled = 0;
1248 #else
1249 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1250 s->clock_enabled = 1;
1251 #endif
1252
1253 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1254
1255 /* set initial state data */
1256 s->Config0 = 0x0; /* No boot ROM */
1257 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1258 s->Config3 = 0x1; /* fast back-to-back compatible */
1259 s->Config5 = 0x0;
1260
1261 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1262
1263 s->CpCmd = 0x0; /* reset C+ mode */
1264 s->cplus_enabled = 0;
1265
1266
1267 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1268 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1269 s->BasicModeCtrl = 0x1000; // autonegotiation
1270
1271 s->BasicModeStatus = 0x7809;
1272 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1273 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1274 /* preserve link state */
1275 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04;
1276
1277 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1278 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1279 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1280
1281 /* also reset timer and disable timer interrupt */
1282 s->TCTR = 0;
1283 s->TimerInt = 0;
1284 s->TCTR_base = 0;
1285
1286 /* reset tally counters */
1287 RTL8139TallyCounters_clear(&s->tally_counters);
1288 }
1289
1290 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1291 {
1292 counters->TxOk = 0;
1293 counters->RxOk = 0;
1294 counters->TxERR = 0;
1295 counters->RxERR = 0;
1296 counters->MissPkt = 0;
1297 counters->FAE = 0;
1298 counters->Tx1Col = 0;
1299 counters->TxMCol = 0;
1300 counters->RxOkPhy = 0;
1301 counters->RxOkBrd = 0;
1302 counters->RxOkMul = 0;
1303 counters->TxAbt = 0;
1304 counters->TxUndrn = 0;
1305 }
1306
1307 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
1308 {
1309 PCIDevice *d = PCI_DEVICE(s);
1310 RTL8139TallyCounters *tally_counters = &s->tally_counters;
1311 uint16_t val16;
1312 uint32_t val32;
1313 uint64_t val64;
1314
1315 val64 = cpu_to_le64(tally_counters->TxOk);
1316 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8);
1317
1318 val64 = cpu_to_le64(tally_counters->RxOk);
1319 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8);
1320
1321 val64 = cpu_to_le64(tally_counters->TxERR);
1322 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8);
1323
1324 val32 = cpu_to_le32(tally_counters->RxERR);
1325 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4);
1326
1327 val16 = cpu_to_le16(tally_counters->MissPkt);
1328 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2);
1329
1330 val16 = cpu_to_le16(tally_counters->FAE);
1331 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2);
1332
1333 val32 = cpu_to_le32(tally_counters->Tx1Col);
1334 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4);
1335
1336 val32 = cpu_to_le32(tally_counters->TxMCol);
1337 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4);
1338
1339 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1340 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8);
1341
1342 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1343 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8);
1344
1345 val32 = cpu_to_le32(tally_counters->RxOkMul);
1346 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4);
1347
1348 val16 = cpu_to_le16(tally_counters->TxAbt);
1349 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2);
1350
1351 val16 = cpu_to_le16(tally_counters->TxUndrn);
1352 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2);
1353 }
1354
1355 /* Loads values of tally counters from VM state file */
1356
1357 static const VMStateDescription vmstate_tally_counters = {
1358 .name = "tally_counters",
1359 .version_id = 1,
1360 .minimum_version_id = 1,
1361 .minimum_version_id_old = 1,
1362 .fields = (VMStateField []) {
1363 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1364 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1365 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1366 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1367 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1368 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1369 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1370 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1371 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1372 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1373 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1374 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1375 VMSTATE_END_OF_LIST()
1376 }
1377 };
1378
1379 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1380 {
1381 DeviceState *d = DEVICE(s);
1382
1383 val &= 0xff;
1384
1385 DPRINTF("ChipCmd write val=0x%08x\n", val);
1386
1387 if (val & CmdReset)
1388 {
1389 DPRINTF("ChipCmd reset\n");
1390 rtl8139_reset(d);
1391 }
1392 if (val & CmdRxEnb)
1393 {
1394 DPRINTF("ChipCmd enable receiver\n");
1395
1396 s->currCPlusRxDesc = 0;
1397 }
1398 if (val & CmdTxEnb)
1399 {
1400 DPRINTF("ChipCmd enable transmitter\n");
1401
1402 s->currCPlusTxDesc = 0;
1403 }
1404
1405 /* mask unwritable bits */
1406 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1407
1408 /* Deassert reset pin before next read */
1409 val &= ~CmdReset;
1410
1411 s->bChipCmdState = val;
1412 }
1413
1414 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1415 {
1416 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1417
1418 if (unread != 0)
1419 {
1420 DPRINTF("receiver buffer data available 0x%04x\n", unread);
1421 return 0;
1422 }
1423
1424 DPRINTF("receiver buffer is empty\n");
1425
1426 return 1;
1427 }
1428
1429 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1430 {
1431 uint32_t ret = s->bChipCmdState;
1432
1433 if (rtl8139_RxBufferEmpty(s))
1434 ret |= RxBufEmpty;
1435
1436 DPRINTF("ChipCmd read val=0x%04x\n", ret);
1437
1438 return ret;
1439 }
1440
1441 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1442 {
1443 val &= 0xffff;
1444
1445 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
1446
1447 s->cplus_enabled = 1;
1448
1449 /* mask unwritable bits */
1450 val = SET_MASKED(val, 0xff84, s->CpCmd);
1451
1452 s->CpCmd = val;
1453 }
1454
1455 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1456 {
1457 uint32_t ret = s->CpCmd;
1458
1459 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
1460
1461 return ret;
1462 }
1463
1464 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1465 {
1466 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
1467 }
1468
1469 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1470 {
1471 uint32_t ret = 0;
1472
1473 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
1474
1475 return ret;
1476 }
1477
1478 static int rtl8139_config_writable(RTL8139State *s)
1479 {
1480 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
1481 {
1482 return 1;
1483 }
1484
1485 DPRINTF("Configuration registers are write-protected\n");
1486
1487 return 0;
1488 }
1489
1490 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1491 {
1492 val &= 0xffff;
1493
1494 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
1495
1496 /* mask unwritable bits */
1497 uint32_t mask = 0x4cff;
1498
1499 if (1 || !rtl8139_config_writable(s))
1500 {
1501 /* Speed setting and autonegotiation enable bits are read-only */
1502 mask |= 0x3000;
1503 /* Duplex mode setting is read-only */
1504 mask |= 0x0100;
1505 }
1506
1507 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1508
1509 s->BasicModeCtrl = val;
1510 }
1511
1512 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1513 {
1514 uint32_t ret = s->BasicModeCtrl;
1515
1516 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
1517
1518 return ret;
1519 }
1520
1521 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1522 {
1523 val &= 0xffff;
1524
1525 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
1526
1527 /* mask unwritable bits */
1528 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1529
1530 s->BasicModeStatus = val;
1531 }
1532
1533 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1534 {
1535 uint32_t ret = s->BasicModeStatus;
1536
1537 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
1538
1539 return ret;
1540 }
1541
1542 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1543 {
1544 DeviceState *d = DEVICE(s);
1545
1546 val &= 0xff;
1547
1548 DPRINTF("Cfg9346 write val=0x%02x\n", val);
1549
1550 /* mask unwritable bits */
1551 val = SET_MASKED(val, 0x31, s->Cfg9346);
1552
1553 uint32_t opmode = val & 0xc0;
1554 uint32_t eeprom_val = val & 0xf;
1555
1556 if (opmode == 0x80) {
1557 /* eeprom access */
1558 int eecs = (eeprom_val & 0x08)?1:0;
1559 int eesk = (eeprom_val & 0x04)?1:0;
1560 int eedi = (eeprom_val & 0x02)?1:0;
1561 prom9346_set_wire(s, eecs, eesk, eedi);
1562 } else if (opmode == 0x40) {
1563 /* Reset. */
1564 val = 0;
1565 rtl8139_reset(d);
1566 }
1567
1568 s->Cfg9346 = val;
1569 }
1570
1571 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1572 {
1573 uint32_t ret = s->Cfg9346;
1574
1575 uint32_t opmode = ret & 0xc0;
1576
1577 if (opmode == 0x80)
1578 {
1579 /* eeprom access */
1580 int eedo = prom9346_get_wire(s);
1581 if (eedo)
1582 {
1583 ret |= 0x01;
1584 }
1585 else
1586 {
1587 ret &= ~0x01;
1588 }
1589 }
1590
1591 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
1592
1593 return ret;
1594 }
1595
1596 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1597 {
1598 val &= 0xff;
1599
1600 DPRINTF("Config0 write val=0x%02x\n", val);
1601
1602 if (!rtl8139_config_writable(s)) {
1603 return;
1604 }
1605
1606 /* mask unwritable bits */
1607 val = SET_MASKED(val, 0xf8, s->Config0);
1608
1609 s->Config0 = val;
1610 }
1611
1612 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1613 {
1614 uint32_t ret = s->Config0;
1615
1616 DPRINTF("Config0 read val=0x%02x\n", ret);
1617
1618 return ret;
1619 }
1620
1621 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1622 {
1623 val &= 0xff;
1624
1625 DPRINTF("Config1 write val=0x%02x\n", val);
1626
1627 if (!rtl8139_config_writable(s)) {
1628 return;
1629 }
1630
1631 /* mask unwritable bits */
1632 val = SET_MASKED(val, 0xC, s->Config1);
1633
1634 s->Config1 = val;
1635 }
1636
1637 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1638 {
1639 uint32_t ret = s->Config1;
1640
1641 DPRINTF("Config1 read val=0x%02x\n", ret);
1642
1643 return ret;
1644 }
1645
1646 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1647 {
1648 val &= 0xff;
1649
1650 DPRINTF("Config3 write val=0x%02x\n", val);
1651
1652 if (!rtl8139_config_writable(s)) {
1653 return;
1654 }
1655
1656 /* mask unwritable bits */
1657 val = SET_MASKED(val, 0x8F, s->Config3);
1658
1659 s->Config3 = val;
1660 }
1661
1662 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1663 {
1664 uint32_t ret = s->Config3;
1665
1666 DPRINTF("Config3 read val=0x%02x\n", ret);
1667
1668 return ret;
1669 }
1670
1671 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1672 {
1673 val &= 0xff;
1674
1675 DPRINTF("Config4 write val=0x%02x\n", val);
1676
1677 if (!rtl8139_config_writable(s)) {
1678 return;
1679 }
1680
1681 /* mask unwritable bits */
1682 val = SET_MASKED(val, 0x0a, s->Config4);
1683
1684 s->Config4 = val;
1685 }
1686
1687 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1688 {
1689 uint32_t ret = s->Config4;
1690
1691 DPRINTF("Config4 read val=0x%02x\n", ret);
1692
1693 return ret;
1694 }
1695
1696 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1697 {
1698 val &= 0xff;
1699
1700 DPRINTF("Config5 write val=0x%02x\n", val);
1701
1702 /* mask unwritable bits */
1703 val = SET_MASKED(val, 0x80, s->Config5);
1704
1705 s->Config5 = val;
1706 }
1707
1708 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1709 {
1710 uint32_t ret = s->Config5;
1711
1712 DPRINTF("Config5 read val=0x%02x\n", ret);
1713
1714 return ret;
1715 }
1716
1717 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1718 {
1719 if (!rtl8139_transmitter_enabled(s))
1720 {
1721 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
1722 return;
1723 }
1724
1725 DPRINTF("TxConfig write val=0x%08x\n", val);
1726
1727 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1728
1729 s->TxConfig = val;
1730 }
1731
1732 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1733 {
1734 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
1735
1736 uint32_t tc = s->TxConfig;
1737 tc &= 0xFFFFFF00;
1738 tc |= (val & 0x000000FF);
1739 rtl8139_TxConfig_write(s, tc);
1740 }
1741
1742 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1743 {
1744 uint32_t ret = s->TxConfig;
1745
1746 DPRINTF("TxConfig read val=0x%04x\n", ret);
1747
1748 return ret;
1749 }
1750
1751 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1752 {
1753 DPRINTF("RxConfig write val=0x%08x\n", val);
1754
1755 /* mask unwritable bits */
1756 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1757
1758 s->RxConfig = val;
1759
1760 /* reset buffer size and read/write pointers */
1761 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1762
1763 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
1764 }
1765
1766 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1767 {
1768 uint32_t ret = s->RxConfig;
1769
1770 DPRINTF("RxConfig read val=0x%08x\n", ret);
1771
1772 return ret;
1773 }
1774
1775 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1776 int do_interrupt, const uint8_t *dot1q_buf)
1777 {
1778 struct iovec *iov = NULL;
1779
1780 if (!size)
1781 {
1782 DPRINTF("+++ empty ethernet frame\n");
1783 return;
1784 }
1785
1786 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1787 iov = (struct iovec[3]) {
1788 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1789 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1790 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1791 .iov_len = size - ETHER_ADDR_LEN * 2 },
1792 };
1793 }
1794
1795 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1796 {
1797 size_t buf2_size;
1798 uint8_t *buf2;
1799
1800 if (iov) {
1801 buf2_size = iov_size(iov, 3);
1802 buf2 = g_malloc(buf2_size);
1803 iov_to_buf(iov, 3, 0, buf2, buf2_size);
1804 buf = buf2;
1805 }
1806
1807 DPRINTF("+++ transmit loopback mode\n");
1808 rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt);
1809
1810 if (iov) {
1811 g_free(buf2);
1812 }
1813 }
1814 else
1815 {
1816 if (iov) {
1817 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3);
1818 } else {
1819 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
1820 }
1821 }
1822 }
1823
1824 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1825 {
1826 if (!rtl8139_transmitter_enabled(s))
1827 {
1828 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1829 "disabled\n", descriptor);
1830 return 0;
1831 }
1832
1833 if (s->TxStatus[descriptor] & TxHostOwns)
1834 {
1835 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1836 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
1837 return 0;
1838 }
1839
1840 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
1841
1842 PCIDevice *d = PCI_DEVICE(s);
1843 int txsize = s->TxStatus[descriptor] & 0x1fff;
1844 uint8_t txbuffer[0x2000];
1845
1846 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1847 txsize, s->TxAddr[descriptor]);
1848
1849 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize);
1850
1851 /* Mark descriptor as transferred */
1852 s->TxStatus[descriptor] |= TxHostOwns;
1853 s->TxStatus[descriptor] |= TxStatOK;
1854
1855 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
1856
1857 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1858 descriptor);
1859
1860 /* update interrupt */
1861 s->IntrStatus |= TxOK;
1862 rtl8139_update_irq(s);
1863
1864 return 1;
1865 }
1866
1867 /* structures and macros for task offloading */
1868 typedef struct ip_header
1869 {
1870 uint8_t ip_ver_len; /* version and header length */
1871 uint8_t ip_tos; /* type of service */
1872 uint16_t ip_len; /* total length */
1873 uint16_t ip_id; /* identification */
1874 uint16_t ip_off; /* fragment offset field */
1875 uint8_t ip_ttl; /* time to live */
1876 uint8_t ip_p; /* protocol */
1877 uint16_t ip_sum; /* checksum */
1878 uint32_t ip_src,ip_dst; /* source and dest address */
1879 } ip_header;
1880
1881 #define IP_HEADER_VERSION_4 4
1882 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1883 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1884
1885 typedef struct tcp_header
1886 {
1887 uint16_t th_sport; /* source port */
1888 uint16_t th_dport; /* destination port */
1889 uint32_t th_seq; /* sequence number */
1890 uint32_t th_ack; /* acknowledgement number */
1891 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1892 uint16_t th_win; /* window */
1893 uint16_t th_sum; /* checksum */
1894 uint16_t th_urp; /* urgent pointer */
1895 } tcp_header;
1896
1897 typedef struct udp_header
1898 {
1899 uint16_t uh_sport; /* source port */
1900 uint16_t uh_dport; /* destination port */
1901 uint16_t uh_ulen; /* udp length */
1902 uint16_t uh_sum; /* udp checksum */
1903 } udp_header;
1904
1905 typedef struct ip_pseudo_header
1906 {
1907 uint32_t ip_src;
1908 uint32_t ip_dst;
1909 uint8_t zeros;
1910 uint8_t ip_proto;
1911 uint16_t ip_payload;
1912 } ip_pseudo_header;
1913
1914 #define IP_PROTO_TCP 6
1915 #define IP_PROTO_UDP 17
1916
1917 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1918 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1919 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1920
1921 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1922
1923 #define TCP_FLAG_FIN 0x01
1924 #define TCP_FLAG_PUSH 0x08
1925
1926 /* produces ones' complement sum of data */
1927 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1928 {
1929 uint32_t result = 0;
1930
1931 for (; len > 1; data+=2, len-=2)
1932 {
1933 result += *(uint16_t*)data;
1934 }
1935
1936 /* add the remainder byte */
1937 if (len)
1938 {
1939 uint8_t odd[2] = {*data, 0};
1940 result += *(uint16_t*)odd;
1941 }
1942
1943 while (result>>16)
1944 result = (result & 0xffff) + (result >> 16);
1945
1946 return result;
1947 }
1948
1949 static uint16_t ip_checksum(void *data, size_t len)
1950 {
1951 return ~ones_complement_sum((uint8_t*)data, len);
1952 }
1953
1954 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1955 {
1956 if (!rtl8139_transmitter_enabled(s))
1957 {
1958 DPRINTF("+++ C+ mode: transmitter disabled\n");
1959 return 0;
1960 }
1961
1962 if (!rtl8139_cp_transmitter_enabled(s))
1963 {
1964 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
1965 return 0 ;
1966 }
1967
1968 PCIDevice *d = PCI_DEVICE(s);
1969 int descriptor = s->currCPlusTxDesc;
1970
1971 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1972
1973 /* Normal priority ring */
1974 cplus_tx_ring_desc += 16 * descriptor;
1975
1976 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1977 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
1978 s->TxAddr[0], cplus_tx_ring_desc);
1979
1980 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1981
1982 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
1983 txdw0 = le32_to_cpu(val);
1984 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1985 txdw1 = le32_to_cpu(val);
1986 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1987 txbufLO = le32_to_cpu(val);
1988 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1989 txbufHI = le32_to_cpu(val);
1990
1991 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1992 txdw0, txdw1, txbufLO, txbufHI);
1993
1994 /* w0 ownership flag */
1995 #define CP_TX_OWN (1<<31)
1996 /* w0 end of ring flag */
1997 #define CP_TX_EOR (1<<30)
1998 /* first segment of received packet flag */
1999 #define CP_TX_FS (1<<29)
2000 /* last segment of received packet flag */
2001 #define CP_TX_LS (1<<28)
2002 /* large send packet flag */
2003 #define CP_TX_LGSEN (1<<27)
2004 /* large send MSS mask, bits 16...25 */
2005 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
2006
2007 /* IP checksum offload flag */
2008 #define CP_TX_IPCS (1<<18)
2009 /* UDP checksum offload flag */
2010 #define CP_TX_UDPCS (1<<17)
2011 /* TCP checksum offload flag */
2012 #define CP_TX_TCPCS (1<<16)
2013
2014 /* w0 bits 0...15 : buffer size */
2015 #define CP_TX_BUFFER_SIZE (1<<16)
2016 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
2017 /* w1 add tag flag */
2018 #define CP_TX_TAGC (1<<17)
2019 /* w1 bits 0...15 : VLAN tag (big endian) */
2020 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2021 /* w2 low 32bit of Rx buffer ptr */
2022 /* w3 high 32bit of Rx buffer ptr */
2023
2024 /* set after transmission */
2025 /* FIFO underrun flag */
2026 #define CP_TX_STATUS_UNF (1<<25)
2027 /* transmit error summary flag, valid if set any of three below */
2028 #define CP_TX_STATUS_TES (1<<23)
2029 /* out-of-window collision flag */
2030 #define CP_TX_STATUS_OWC (1<<22)
2031 /* link failure flag */
2032 #define CP_TX_STATUS_LNKF (1<<21)
2033 /* excessive collisions flag */
2034 #define CP_TX_STATUS_EXC (1<<20)
2035
2036 if (!(txdw0 & CP_TX_OWN))
2037 {
2038 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
2039 return 0 ;
2040 }
2041
2042 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
2043
2044 if (txdw0 & CP_TX_FS)
2045 {
2046 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2047 "descriptor\n", descriptor);
2048
2049 /* reset internal buffer offset */
2050 s->cplus_txbuffer_offset = 0;
2051 }
2052
2053 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
2054 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
2055
2056 /* make sure we have enough space to assemble the packet */
2057 if (!s->cplus_txbuffer)
2058 {
2059 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2060 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
2061 s->cplus_txbuffer_offset = 0;
2062
2063 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2064 s->cplus_txbuffer_len);
2065 }
2066
2067 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2068 {
2069 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2070 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2071 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2072 "length to %d\n", txsize);
2073 }
2074
2075 if (!s->cplus_txbuffer)
2076 {
2077 /* out of memory */
2078
2079 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2080 s->cplus_txbuffer_len);
2081
2082 /* update tally counter */
2083 ++s->tally_counters.TxERR;
2084 ++s->tally_counters.TxAbt;
2085
2086 return 0;
2087 }
2088
2089 /* append more data to the packet */
2090
2091 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
2092 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2093 s->cplus_txbuffer_offset);
2094
2095 pci_dma_read(d, tx_addr,
2096 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2097 s->cplus_txbuffer_offset += txsize;
2098
2099 /* seek to next Rx descriptor */
2100 if (txdw0 & CP_TX_EOR)
2101 {
2102 s->currCPlusTxDesc = 0;
2103 }
2104 else
2105 {
2106 ++s->currCPlusTxDesc;
2107 if (s->currCPlusTxDesc >= 64)
2108 s->currCPlusTxDesc = 0;
2109 }
2110
2111 /* transfer ownership to target */
2112 txdw0 &= ~CP_RX_OWN;
2113
2114 /* reset error indicator bits */
2115 txdw0 &= ~CP_TX_STATUS_UNF;
2116 txdw0 &= ~CP_TX_STATUS_TES;
2117 txdw0 &= ~CP_TX_STATUS_OWC;
2118 txdw0 &= ~CP_TX_STATUS_LNKF;
2119 txdw0 &= ~CP_TX_STATUS_EXC;
2120
2121 /* update ring data */
2122 val = cpu_to_le32(txdw0);
2123 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
2124
2125 /* Now decide if descriptor being processed is holding the last segment of packet */
2126 if (txdw0 & CP_TX_LS)
2127 {
2128 uint8_t dot1q_buffer_space[VLAN_HLEN];
2129 uint16_t *dot1q_buffer;
2130
2131 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2132 descriptor);
2133
2134 /* can transfer fully assembled packet */
2135
2136 uint8_t *saved_buffer = s->cplus_txbuffer;
2137 int saved_size = s->cplus_txbuffer_offset;
2138 int saved_buffer_len = s->cplus_txbuffer_len;
2139
2140 /* create vlan tag */
2141 if (txdw1 & CP_TX_TAGC) {
2142 /* the vlan tag is in BE byte order in the descriptor
2143 * BE + le_to_cpu() + ~swap()~ = cpu */
2144 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2145 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
2146
2147 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2148 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2149 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2150 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2151 } else {
2152 dot1q_buffer = NULL;
2153 }
2154
2155 /* reset the card space to protect from recursive call */
2156 s->cplus_txbuffer = NULL;
2157 s->cplus_txbuffer_offset = 0;
2158 s->cplus_txbuffer_len = 0;
2159
2160 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2161 {
2162 DPRINTF("+++ C+ mode offloaded task checksum\n");
2163
2164 /* ip packet header */
2165 ip_header *ip = NULL;
2166 int hlen = 0;
2167 uint8_t ip_protocol = 0;
2168 uint16_t ip_data_len = 0;
2169
2170 uint8_t *eth_payload_data = NULL;
2171 size_t eth_payload_len = 0;
2172
2173 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2174 if (proto == ETH_P_IP)
2175 {
2176 DPRINTF("+++ C+ mode has IP packet\n");
2177
2178 /* not aligned */
2179 eth_payload_data = saved_buffer + ETH_HLEN;
2180 eth_payload_len = saved_size - ETH_HLEN;
2181
2182 ip = (ip_header*)eth_payload_data;
2183
2184 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2185 DPRINTF("+++ C+ mode packet has bad IP version %d "
2186 "expected %d\n", IP_HEADER_VERSION(ip),
2187 IP_HEADER_VERSION_4);
2188 ip = NULL;
2189 } else {
2190 hlen = IP_HEADER_LENGTH(ip);
2191 ip_protocol = ip->ip_p;
2192 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2193 }
2194 }
2195
2196 if (ip)
2197 {
2198 if (txdw0 & CP_TX_IPCS)
2199 {
2200 DPRINTF("+++ C+ mode need IP checksum\n");
2201
2202 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2203 /* bad packet header len */
2204 /* or packet too short */
2205 }
2206 else
2207 {
2208 ip->ip_sum = 0;
2209 ip->ip_sum = ip_checksum(ip, hlen);
2210 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2211 hlen, ip->ip_sum);
2212 }
2213 }
2214
2215 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2216 {
2217 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2218
2219 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2220 "frame data %d specified MSS=%d\n", ETH_MTU,
2221 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
2222
2223 int tcp_send_offset = 0;
2224 int send_count = 0;
2225
2226 /* maximum IP header length is 60 bytes */
2227 uint8_t saved_ip_header[60];
2228
2229 /* save IP header template; data area is used in tcp checksum calculation */
2230 memcpy(saved_ip_header, eth_payload_data, hlen);
2231
2232 /* a placeholder for checksum calculation routine in tcp case */
2233 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2234 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2235
2236 /* pointer to TCP header */
2237 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2238
2239 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2240
2241 /* ETH_MTU = ip header len + tcp header len + payload */
2242 int tcp_data_len = ip_data_len - tcp_hlen;
2243 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2244
2245 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2246 "data len %d TCP chunk size %d\n", ip_data_len,
2247 tcp_hlen, tcp_data_len, tcp_chunk_size);
2248
2249 /* note the cycle below overwrites IP header data,
2250 but restores it from saved_ip_header before sending packet */
2251
2252 int is_last_frame = 0;
2253
2254 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2255 {
2256 uint16_t chunk_size = tcp_chunk_size;
2257
2258 /* check if this is the last frame */
2259 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2260 {
2261 is_last_frame = 1;
2262 chunk_size = tcp_data_len - tcp_send_offset;
2263 }
2264
2265 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2266 be32_to_cpu(p_tcp_hdr->th_seq));
2267
2268 /* add 4 TCP pseudoheader fields */
2269 /* copy IP source and destination fields */
2270 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2271
2272 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2273 "packet with %d bytes data\n", tcp_hlen +
2274 chunk_size);
2275
2276 if (tcp_send_offset)
2277 {
2278 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2279 }
2280
2281 /* keep PUSH and FIN flags only for the last frame */
2282 if (!is_last_frame)
2283 {
2284 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2285 }
2286
2287 /* recalculate TCP checksum */
2288 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2289 p_tcpip_hdr->zeros = 0;
2290 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2291 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2292
2293 p_tcp_hdr->th_sum = 0;
2294
2295 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2296 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2297 tcp_checksum);
2298
2299 p_tcp_hdr->th_sum = tcp_checksum;
2300
2301 /* restore IP header */
2302 memcpy(eth_payload_data, saved_ip_header, hlen);
2303
2304 /* set IP data length and recalculate IP checksum */
2305 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2306
2307 /* increment IP id for subsequent frames */
2308 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2309
2310 ip->ip_sum = 0;
2311 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2312 DPRINTF("+++ C+ mode TSO IP header len=%d "
2313 "checksum=%04x\n", hlen, ip->ip_sum);
2314
2315 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2316 DPRINTF("+++ C+ mode TSO transferring packet size "
2317 "%d\n", tso_send_size);
2318 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2319 0, (uint8_t *) dot1q_buffer);
2320
2321 /* add transferred count to TCP sequence number */
2322 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2323 ++send_count;
2324 }
2325
2326 /* Stop sending this frame */
2327 saved_size = 0;
2328 }
2329 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2330 {
2331 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2332
2333 /* maximum IP header length is 60 bytes */
2334 uint8_t saved_ip_header[60];
2335 memcpy(saved_ip_header, eth_payload_data, hlen);
2336
2337 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2338 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2339
2340 /* add 4 TCP pseudoheader fields */
2341 /* copy IP source and destination fields */
2342 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2343
2344 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2345 {
2346 DPRINTF("+++ C+ mode calculating TCP checksum for "
2347 "packet with %d bytes data\n", ip_data_len);
2348
2349 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2350 p_tcpip_hdr->zeros = 0;
2351 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2352 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2353
2354 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2355
2356 p_tcp_hdr->th_sum = 0;
2357
2358 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2359 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2360 tcp_checksum);
2361
2362 p_tcp_hdr->th_sum = tcp_checksum;
2363 }
2364 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2365 {
2366 DPRINTF("+++ C+ mode calculating UDP checksum for "
2367 "packet with %d bytes data\n", ip_data_len);
2368
2369 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2370 p_udpip_hdr->zeros = 0;
2371 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2372 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2373
2374 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2375
2376 p_udp_hdr->uh_sum = 0;
2377
2378 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2379 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2380 udp_checksum);
2381
2382 p_udp_hdr->uh_sum = udp_checksum;
2383 }
2384
2385 /* restore IP header */
2386 memcpy(eth_payload_data, saved_ip_header, hlen);
2387 }
2388 }
2389 }
2390
2391 /* update tally counter */
2392 ++s->tally_counters.TxOk;
2393
2394 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
2395
2396 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2397 (uint8_t *) dot1q_buffer);
2398
2399 /* restore card space if there was no recursion and reset offset */
2400 if (!s->cplus_txbuffer)
2401 {
2402 s->cplus_txbuffer = saved_buffer;
2403 s->cplus_txbuffer_len = saved_buffer_len;
2404 s->cplus_txbuffer_offset = 0;
2405 }
2406 else
2407 {
2408 g_free(saved_buffer);
2409 }
2410 }
2411 else
2412 {
2413 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
2414 }
2415
2416 return 1;
2417 }
2418
2419 static void rtl8139_cplus_transmit(RTL8139State *s)
2420 {
2421 int txcount = 0;
2422
2423 while (rtl8139_cplus_transmit_one(s))
2424 {
2425 ++txcount;
2426 }
2427
2428 /* Mark transfer completed */
2429 if (!txcount)
2430 {
2431 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2432 s->currCPlusTxDesc);
2433 }
2434 else
2435 {
2436 /* update interrupt status */
2437 s->IntrStatus |= TxOK;
2438 rtl8139_update_irq(s);
2439 }
2440 }
2441
2442 static void rtl8139_transmit(RTL8139State *s)
2443 {
2444 int descriptor = s->currTxDesc, txcount = 0;
2445
2446 /*while*/
2447 if (rtl8139_transmit_one(s, descriptor))
2448 {
2449 ++s->currTxDesc;
2450 s->currTxDesc %= 4;
2451 ++txcount;
2452 }
2453
2454 /* Mark transfer completed */
2455 if (!txcount)
2456 {
2457 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2458 s->currTxDesc);
2459 }
2460 }
2461
2462 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2463 {
2464
2465 int descriptor = txRegOffset/4;
2466
2467 /* handle C+ transmit mode register configuration */
2468
2469 if (s->cplus_enabled)
2470 {
2471 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2472 "descriptor=%d\n", txRegOffset, val, descriptor);
2473
2474 /* handle Dump Tally Counters command */
2475 s->TxStatus[descriptor] = val;
2476
2477 if (descriptor == 0 && (val & 0x8))
2478 {
2479 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2480
2481 /* dump tally counters to specified memory location */
2482 RTL8139TallyCounters_dma_write(s, tc_addr);
2483
2484 /* mark dump completed */
2485 s->TxStatus[0] &= ~0x8;
2486 }
2487
2488 return;
2489 }
2490
2491 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2492 txRegOffset, val, descriptor);
2493
2494 /* mask only reserved bits */
2495 val &= ~0xff00c000; /* these bits are reset on write */
2496 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2497
2498 s->TxStatus[descriptor] = val;
2499
2500 /* attempt to start transmission */
2501 rtl8139_transmit(s);
2502 }
2503
2504 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2505 uint32_t base, uint8_t addr,
2506 int size)
2507 {
2508 uint32_t reg = (addr - base) / 4;
2509 uint32_t offset = addr & 0x3;
2510 uint32_t ret = 0;
2511
2512 if (addr & (size - 1)) {
2513 DPRINTF("not implemented read for TxStatus/TxAddr "
2514 "addr=0x%x size=0x%x\n", addr, size);
2515 return ret;
2516 }
2517
2518 switch (size) {
2519 case 1: /* fall through */
2520 case 2: /* fall through */
2521 case 4:
2522 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
2523 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2524 reg, addr, size, ret);
2525 break;
2526 default:
2527 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
2528 break;
2529 }
2530
2531 return ret;
2532 }
2533
2534 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2535 {
2536 uint16_t ret = 0;
2537
2538 /* Simulate TSAD, it is read only anyway */
2539
2540 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2541 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2542 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2543 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2544
2545 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2546 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2547 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2548 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2549
2550 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2551 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2552 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2553 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2554
2555 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2556 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2557 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2558 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2559
2560
2561 DPRINTF("TSAD read val=0x%04x\n", ret);
2562
2563 return ret;
2564 }
2565
2566 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2567 {
2568 uint16_t ret = s->CSCR;
2569
2570 DPRINTF("CSCR read val=0x%04x\n", ret);
2571
2572 return ret;
2573 }
2574
2575 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2576 {
2577 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
2578
2579 s->TxAddr[txAddrOffset/4] = val;
2580 }
2581
2582 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2583 {
2584 uint32_t ret = s->TxAddr[txAddrOffset/4];
2585
2586 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
2587
2588 return ret;
2589 }
2590
2591 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2592 {
2593 DPRINTF("RxBufPtr write val=0x%04x\n", val);
2594
2595 /* this value is off by 16 */
2596 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2597
2598 /* more buffer space may be available so try to receive */
2599 qemu_flush_queued_packets(qemu_get_queue(s->nic));
2600
2601 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2602 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
2603 }
2604
2605 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2606 {
2607 /* this value is off by 16 */
2608 uint32_t ret = s->RxBufPtr - 0x10;
2609
2610 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
2611
2612 return ret;
2613 }
2614
2615 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2616 {
2617 /* this value is NOT off by 16 */
2618 uint32_t ret = s->RxBufAddr;
2619
2620 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
2621
2622 return ret;
2623 }
2624
2625 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2626 {
2627 DPRINTF("RxBuf write val=0x%08x\n", val);
2628
2629 s->RxBuf = val;
2630
2631 /* may need to reset rxring here */
2632 }
2633
2634 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2635 {
2636 uint32_t ret = s->RxBuf;
2637
2638 DPRINTF("RxBuf read val=0x%08x\n", ret);
2639
2640 return ret;
2641 }
2642
2643 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2644 {
2645 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
2646
2647 /* mask unwritable bits */
2648 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2649
2650 s->IntrMask = val;
2651
2652 rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
2653 rtl8139_update_irq(s);
2654
2655 }
2656
2657 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2658 {
2659 uint32_t ret = s->IntrMask;
2660
2661 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
2662
2663 return ret;
2664 }
2665
2666 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2667 {
2668 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
2669
2670 #if 0
2671
2672 /* writing to ISR has no effect */
2673
2674 return;
2675
2676 #else
2677 uint16_t newStatus = s->IntrStatus & ~val;
2678
2679 /* mask unwritable bits */
2680 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2681
2682 /* writing 1 to interrupt status register bit clears it */
2683 s->IntrStatus = 0;
2684 rtl8139_update_irq(s);
2685
2686 s->IntrStatus = newStatus;
2687 /*
2688 * Computing if we miss an interrupt here is not that correct but
2689 * considered that we should have had already an interrupt
2690 * and probably emulated is slower is better to assume this resetting was
2691 * done before testing on previous rtl8139_update_irq lead to IRQ losing
2692 */
2693 rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
2694 rtl8139_update_irq(s);
2695
2696 #endif
2697 }
2698
2699 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2700 {
2701 rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
2702
2703 uint32_t ret = s->IntrStatus;
2704
2705 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
2706
2707 #if 0
2708
2709 /* reading ISR clears all interrupts */
2710 s->IntrStatus = 0;
2711
2712 rtl8139_update_irq(s);
2713
2714 #endif
2715
2716 return ret;
2717 }
2718
2719 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2720 {
2721 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
2722
2723 /* mask unwritable bits */
2724 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2725
2726 s->MultiIntr = val;
2727 }
2728
2729 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2730 {
2731 uint32_t ret = s->MultiIntr;
2732
2733 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
2734
2735 return ret;
2736 }
2737
2738 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2739 {
2740 RTL8139State *s = opaque;
2741
2742 switch (addr)
2743 {
2744 case MAC0 ... MAC0+4:
2745 s->phys[addr - MAC0] = val;
2746 break;
2747 case MAC0+5:
2748 s->phys[addr - MAC0] = val;
2749 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
2750 break;
2751 case MAC0+6 ... MAC0+7:
2752 /* reserved */
2753 break;
2754 case MAR0 ... MAR0+7:
2755 s->mult[addr - MAR0] = val;
2756 break;
2757 case ChipCmd:
2758 rtl8139_ChipCmd_write(s, val);
2759 break;
2760 case Cfg9346:
2761 rtl8139_Cfg9346_write(s, val);
2762 break;
2763 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2764 rtl8139_TxConfig_writeb(s, val);
2765 break;
2766 case Config0:
2767 rtl8139_Config0_write(s, val);
2768 break;
2769 case Config1:
2770 rtl8139_Config1_write(s, val);
2771 break;
2772 case Config3:
2773 rtl8139_Config3_write(s, val);
2774 break;
2775 case Config4:
2776 rtl8139_Config4_write(s, val);
2777 break;
2778 case Config5:
2779 rtl8139_Config5_write(s, val);
2780 break;
2781 case MediaStatus:
2782 /* ignore */
2783 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2784 val);
2785 break;
2786
2787 case HltClk:
2788 DPRINTF("HltClk write val=0x%08x\n", val);
2789 if (val == 'R')
2790 {
2791 s->clock_enabled = 1;
2792 }
2793 else if (val == 'H')
2794 {
2795 s->clock_enabled = 0;
2796 }
2797 break;
2798
2799 case TxThresh:
2800 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
2801 s->TxThresh = val;
2802 break;
2803
2804 case TxPoll:
2805 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
2806 if (val & (1 << 7))
2807 {
2808 DPRINTF("C+ TxPoll high priority transmission (not "
2809 "implemented)\n");
2810 //rtl8139_cplus_transmit(s);
2811 }
2812 if (val & (1 << 6))
2813 {
2814 DPRINTF("C+ TxPoll normal priority transmission\n");
2815 rtl8139_cplus_transmit(s);
2816 }
2817
2818 break;
2819
2820 default:
2821 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2822 val);
2823 break;
2824 }
2825 }
2826
2827 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2828 {
2829 RTL8139State *s = opaque;
2830
2831 switch (addr)
2832 {
2833 case IntrMask:
2834 rtl8139_IntrMask_write(s, val);
2835 break;
2836
2837 case IntrStatus:
2838 rtl8139_IntrStatus_write(s, val);
2839 break;
2840
2841 case MultiIntr:
2842 rtl8139_MultiIntr_write(s, val);
2843 break;
2844
2845 case RxBufPtr:
2846 rtl8139_RxBufPtr_write(s, val);
2847 break;
2848
2849 case BasicModeCtrl:
2850 rtl8139_BasicModeCtrl_write(s, val);
2851 break;
2852 case BasicModeStatus:
2853 rtl8139_BasicModeStatus_write(s, val);
2854 break;
2855 case NWayAdvert:
2856 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
2857 s->NWayAdvert = val;
2858 break;
2859 case NWayLPAR:
2860 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
2861 break;
2862 case NWayExpansion:
2863 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
2864 s->NWayExpansion = val;
2865 break;
2866
2867 case CpCmd:
2868 rtl8139_CpCmd_write(s, val);
2869 break;
2870
2871 case IntrMitigate:
2872 rtl8139_IntrMitigate_write(s, val);
2873 break;
2874
2875 default:
2876 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2877 addr, val);
2878
2879 rtl8139_io_writeb(opaque, addr, val & 0xff);
2880 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2881 break;
2882 }
2883 }
2884
2885 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2886 {
2887 int64_t pci_time, next_time;
2888 uint32_t low_pci;
2889
2890 DPRINTF("entered rtl8139_set_next_tctr_time\n");
2891
2892 if (s->TimerExpire && current_time >= s->TimerExpire) {
2893 s->IntrStatus |= PCSTimeout;
2894 rtl8139_update_irq(s);
2895 }
2896
2897 /* Set QEMU timer only if needed that is
2898 * - TimerInt <> 0 (we have a timer)
2899 * - mask = 1 (we want an interrupt timer)
2900 * - irq = 0 (irq is not already active)
2901 * If any of above change we need to compute timer again
2902 * Also we must check if timer is passed without QEMU timer
2903 */
2904 s->TimerExpire = 0;
2905 if (!s->TimerInt) {
2906 return;
2907 }
2908
2909 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2910 get_ticks_per_sec());
2911 low_pci = pci_time & 0xffffffff;
2912 pci_time = pci_time - low_pci + s->TimerInt;
2913 if (low_pci >= s->TimerInt) {
2914 pci_time += 0x100000000LL;
2915 }
2916 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2917 PCI_FREQUENCY);
2918 s->TimerExpire = next_time;
2919
2920 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2921 timer_mod(s->timer, next_time);
2922 }
2923 }
2924
2925 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2926 {
2927 RTL8139State *s = opaque;
2928
2929 switch (addr)
2930 {
2931 case RxMissed:
2932 DPRINTF("RxMissed clearing on write\n");
2933 s->RxMissed = 0;
2934 break;
2935
2936 case TxConfig:
2937 rtl8139_TxConfig_write(s, val);
2938 break;
2939
2940 case RxConfig:
2941 rtl8139_RxConfig_write(s, val);
2942 break;
2943
2944 case TxStatus0 ... TxStatus0+4*4-1:
2945 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2946 break;
2947
2948 case TxAddr0 ... TxAddr0+4*4-1:
2949 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2950 break;
2951
2952 case RxBuf:
2953 rtl8139_RxBuf_write(s, val);
2954 break;
2955
2956 case RxRingAddrLO:
2957 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
2958 s->RxRingAddrLO = val;
2959 break;
2960
2961 case RxRingAddrHI:
2962 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
2963 s->RxRingAddrHI = val;
2964 break;
2965
2966 case Timer:
2967 DPRINTF("TCTR Timer reset on write\n");
2968 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2969 rtl8139_set_next_tctr_time(s, s->TCTR_base);
2970 break;
2971
2972 case FlashReg:
2973 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
2974 if (s->TimerInt != val) {
2975 s->TimerInt = val;
2976 rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
2977 }
2978 break;
2979
2980 default:
2981 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2982 addr, val);
2983 rtl8139_io_writeb(opaque, addr, val & 0xff);
2984 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2985 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2986 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2987 break;
2988 }
2989 }
2990
2991 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2992 {
2993 RTL8139State *s = opaque;
2994 int ret;
2995
2996 switch (addr)
2997 {
2998 case MAC0 ... MAC0+5:
2999 ret = s->phys[addr - MAC0];
3000 break;
3001 case MAC0+6 ... MAC0+7:
3002 ret = 0;
3003 break;
3004 case MAR0 ... MAR0+7:
3005 ret = s->mult[addr - MAR0];
3006 break;
3007 case TxStatus0 ... TxStatus0+4*4-1:
3008 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3009 addr, 1);
3010 break;
3011 case ChipCmd:
3012 ret = rtl8139_ChipCmd_read(s);
3013 break;
3014 case Cfg9346:
3015 ret = rtl8139_Cfg9346_read(s);
3016 break;
3017 case Config0:
3018 ret = rtl8139_Config0_read(s);
3019 break;
3020 case Config1:
3021 ret = rtl8139_Config1_read(s);
3022 break;
3023 case Config3:
3024 ret = rtl8139_Config3_read(s);
3025 break;
3026 case Config4:
3027 ret = rtl8139_Config4_read(s);
3028 break;
3029 case Config5:
3030 ret = rtl8139_Config5_read(s);
3031 break;
3032
3033 case MediaStatus:
3034 /* The LinkDown bit of MediaStatus is inverse with link status */
3035 ret = 0xd0 | (~s->BasicModeStatus & 0x04);
3036 DPRINTF("MediaStatus read 0x%x\n", ret);
3037 break;
3038
3039 case HltClk:
3040 ret = s->clock_enabled;
3041 DPRINTF("HltClk read 0x%x\n", ret);
3042 break;
3043
3044 case PCIRevisionID:
3045 ret = RTL8139_PCI_REVID;
3046 DPRINTF("PCI Revision ID read 0x%x\n", ret);
3047 break;
3048
3049 case TxThresh:
3050 ret = s->TxThresh;
3051 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
3052 break;
3053
3054 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3055 ret = s->TxConfig >> 24;
3056 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
3057 break;
3058
3059 default:
3060 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
3061 ret = 0;
3062 break;
3063 }
3064
3065 return ret;
3066 }
3067
3068 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3069 {
3070 RTL8139State *s = opaque;
3071 uint32_t ret;
3072
3073 switch (addr)
3074 {
3075 case TxAddr0 ... TxAddr0+4*4-1:
3076 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
3077 break;
3078 case IntrMask:
3079 ret = rtl8139_IntrMask_read(s);
3080 break;
3081
3082 case IntrStatus:
3083 ret = rtl8139_IntrStatus_read(s);
3084 break;
3085
3086 case MultiIntr:
3087 ret = rtl8139_MultiIntr_read(s);
3088 break;
3089
3090 case RxBufPtr:
3091 ret = rtl8139_RxBufPtr_read(s);
3092 break;
3093
3094 case RxBufAddr:
3095 ret = rtl8139_RxBufAddr_read(s);
3096 break;
3097
3098 case BasicModeCtrl:
3099 ret = rtl8139_BasicModeCtrl_read(s);
3100 break;
3101 case BasicModeStatus:
3102 ret = rtl8139_BasicModeStatus_read(s);
3103 break;
3104 case NWayAdvert:
3105 ret = s->NWayAdvert;
3106 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
3107 break;
3108 case NWayLPAR:
3109 ret = s->NWayLPAR;
3110 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
3111 break;
3112 case NWayExpansion:
3113 ret = s->NWayExpansion;
3114 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
3115 break;
3116
3117 case CpCmd:
3118 ret = rtl8139_CpCmd_read(s);
3119 break;
3120
3121 case IntrMitigate:
3122 ret = rtl8139_IntrMitigate_read(s);
3123 break;
3124
3125 case TxSummary:
3126 ret = rtl8139_TSAD_read(s);
3127 break;
3128
3129 case CSCR:
3130 ret = rtl8139_CSCR_read(s);
3131 break;
3132
3133 default:
3134 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
3135
3136 ret = rtl8139_io_readb(opaque, addr);
3137 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3138
3139 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
3140 break;
3141 }
3142
3143 return ret;
3144 }
3145
3146 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3147 {
3148 RTL8139State *s = opaque;
3149 uint32_t ret;
3150
3151 switch (addr)
3152 {
3153 case RxMissed:
3154 ret = s->RxMissed;
3155
3156 DPRINTF("RxMissed read val=0x%08x\n", ret);
3157 break;
3158
3159 case TxConfig:
3160 ret = rtl8139_TxConfig_read(s);
3161 break;
3162
3163 case RxConfig:
3164 ret = rtl8139_RxConfig_read(s);
3165 break;
3166
3167 case TxStatus0 ... TxStatus0+4*4-1:
3168 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3169 addr, 4);
3170 break;
3171
3172 case TxAddr0 ... TxAddr0+4*4-1:
3173 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3174 break;
3175
3176 case RxBuf:
3177 ret = rtl8139_RxBuf_read(s);
3178 break;
3179
3180 case RxRingAddrLO:
3181 ret = s->RxRingAddrLO;
3182 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
3183 break;
3184
3185 case RxRingAddrHI:
3186 ret = s->RxRingAddrHI;
3187 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
3188 break;
3189
3190 case Timer:
3191 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base,
3192 PCI_FREQUENCY, get_ticks_per_sec());
3193 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
3194 break;
3195
3196 case FlashReg:
3197 ret = s->TimerInt;
3198 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
3199 break;
3200
3201 default:
3202 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
3203
3204 ret = rtl8139_io_readb(opaque, addr);
3205 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3206 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3207 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3208
3209 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
3210 break;
3211 }
3212
3213 return ret;
3214 }
3215
3216 /* */
3217
3218 static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
3219 {
3220 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3221 }
3222
3223 static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
3224 {
3225 rtl8139_io_writew(opaque, addr & 0xFF, val);
3226 }
3227
3228 static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
3229 {
3230 rtl8139_io_writel(opaque, addr & 0xFF, val);
3231 }
3232
3233 static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr)
3234 {
3235 return rtl8139_io_readb(opaque, addr & 0xFF);
3236 }
3237
3238 static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr)
3239 {
3240 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3241 return val;
3242 }
3243
3244 static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr)
3245 {
3246 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3247 return val;
3248 }
3249
3250 static int rtl8139_post_load(void *opaque, int version_id)
3251 {
3252 RTL8139State* s = opaque;
3253 rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3254 if (version_id < 4) {
3255 s->cplus_enabled = s->CpCmd != 0;
3256 }
3257
3258 /* nc.link_down can't be migrated, so infer link_down according
3259 * to link status bit in BasicModeStatus */
3260 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0;
3261
3262 return 0;
3263 }
3264
3265 static bool rtl8139_hotplug_ready_needed(void *opaque)
3266 {
3267 return qdev_machine_modified();
3268 }
3269
3270 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3271 .name = "rtl8139/hotplug_ready",
3272 .version_id = 1,
3273 .minimum_version_id = 1,
3274 .minimum_version_id_old = 1,
3275 .fields = (VMStateField []) {
3276 VMSTATE_END_OF_LIST()
3277 }
3278 };
3279
3280 static void rtl8139_pre_save(void *opaque)
3281 {
3282 RTL8139State* s = opaque;
3283 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
3284
3285 /* set IntrStatus correctly */
3286 rtl8139_set_next_tctr_time(s, current_time);
3287 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3288 get_ticks_per_sec());
3289 s->rtl8139_mmio_io_addr_dummy = 0;
3290 }
3291
3292 static const VMStateDescription vmstate_rtl8139 = {
3293 .name = "rtl8139",
3294 .version_id = 4,
3295 .minimum_version_id = 3,
3296 .minimum_version_id_old = 3,
3297 .post_load = rtl8139_post_load,
3298 .pre_save = rtl8139_pre_save,
3299 .fields = (VMStateField []) {
3300 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State),
3301 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3302 VMSTATE_BUFFER(mult, RTL8139State),
3303 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3304 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3305
3306 VMSTATE_UINT32(RxBuf, RTL8139State),
3307 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3308 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3309 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3310
3311 VMSTATE_UINT16(IntrStatus, RTL8139State),
3312 VMSTATE_UINT16(IntrMask, RTL8139State),
3313
3314 VMSTATE_UINT32(TxConfig, RTL8139State),
3315 VMSTATE_UINT32(RxConfig, RTL8139State),
3316 VMSTATE_UINT32(RxMissed, RTL8139State),
3317 VMSTATE_UINT16(CSCR, RTL8139State),
3318
3319 VMSTATE_UINT8(Cfg9346, RTL8139State),
3320 VMSTATE_UINT8(Config0, RTL8139State),
3321 VMSTATE_UINT8(Config1, RTL8139State),
3322 VMSTATE_UINT8(Config3, RTL8139State),
3323 VMSTATE_UINT8(Config4, RTL8139State),
3324 VMSTATE_UINT8(Config5, RTL8139State),
3325
3326 VMSTATE_UINT8(clock_enabled, RTL8139State),
3327 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3328
3329 VMSTATE_UINT16(MultiIntr, RTL8139State),
3330
3331 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3332 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3333 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3334 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3335 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3336
3337 VMSTATE_UINT16(CpCmd, RTL8139State),
3338 VMSTATE_UINT8(TxThresh, RTL8139State),
3339
3340 VMSTATE_UNUSED(4),
3341 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3342 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3343
3344 VMSTATE_UINT32(currTxDesc, RTL8139State),
3345 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3346 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3347 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3348 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3349
3350 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3351 VMSTATE_INT32(eeprom.mode, RTL8139State),
3352 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3353 VMSTATE_UINT8(eeprom.address, RTL8139State),
3354 VMSTATE_UINT16(eeprom.input, RTL8139State),
3355 VMSTATE_UINT16(eeprom.output, RTL8139State),
3356
3357 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3358 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3359 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3360 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3361
3362 VMSTATE_UINT32(TCTR, RTL8139State),
3363 VMSTATE_UINT32(TimerInt, RTL8139State),
3364 VMSTATE_INT64(TCTR_base, RTL8139State),
3365
3366 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3367 vmstate_tally_counters, RTL8139TallyCounters),
3368
3369 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3370 VMSTATE_END_OF_LIST()
3371 },
3372 .subsections = (VMStateSubsection []) {
3373 {
3374 .vmsd = &vmstate_rtl8139_hotplug_ready,
3375 .needed = rtl8139_hotplug_ready_needed,
3376 }, {
3377 /* empty */
3378 }
3379 }
3380 };
3381
3382 /***********************************************************/
3383 /* PCI RTL8139 definitions */
3384
3385 static void rtl8139_ioport_write(void *opaque, hwaddr addr,
3386 uint64_t val, unsigned size)
3387 {
3388 switch (size) {
3389 case 1:
3390 rtl8139_io_writeb(opaque, addr, val);
3391 break;
3392 case 2:
3393 rtl8139_io_writew(opaque, addr, val);
3394 break;
3395 case 4:
3396 rtl8139_io_writel(opaque, addr, val);
3397 break;
3398 }
3399 }
3400
3401 static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr,
3402 unsigned size)
3403 {
3404 switch (size) {
3405 case 1:
3406 return rtl8139_io_readb(opaque, addr);
3407 case 2:
3408 return rtl8139_io_readw(opaque, addr);
3409 case 4:
3410 return rtl8139_io_readl(opaque, addr);
3411 }
3412
3413 return -1;
3414 }
3415
3416 static const MemoryRegionOps rtl8139_io_ops = {
3417 .read = rtl8139_ioport_read,
3418 .write = rtl8139_ioport_write,
3419 .impl = {
3420 .min_access_size = 1,
3421 .max_access_size = 4,
3422 },
3423 .endianness = DEVICE_LITTLE_ENDIAN,
3424 };
3425
3426 static const MemoryRegionOps rtl8139_mmio_ops = {
3427 .old_mmio = {
3428 .read = {
3429 rtl8139_mmio_readb,
3430 rtl8139_mmio_readw,
3431 rtl8139_mmio_readl,
3432 },
3433 .write = {
3434 rtl8139_mmio_writeb,
3435 rtl8139_mmio_writew,
3436 rtl8139_mmio_writel,
3437 },
3438 },
3439 .endianness = DEVICE_LITTLE_ENDIAN,
3440 };
3441
3442 static void rtl8139_timer(void *opaque)
3443 {
3444 RTL8139State *s = opaque;
3445
3446 if (!s->clock_enabled)
3447 {
3448 DPRINTF(">>> timer: clock is not running\n");
3449 return;
3450 }
3451
3452 s->IntrStatus |= PCSTimeout;
3453 rtl8139_update_irq(s);
3454 rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3455 }
3456
3457 static void rtl8139_cleanup(NetClientState *nc)
3458 {
3459 RTL8139State *s = qemu_get_nic_opaque(nc);
3460
3461 s->nic = NULL;
3462 }
3463
3464 static void pci_rtl8139_uninit(PCIDevice *dev)
3465 {
3466 RTL8139State *s = RTL8139(dev);
3467
3468 memory_region_destroy(&s->bar_io);
3469 memory_region_destroy(&s->bar_mem);
3470 if (s->cplus_txbuffer) {
3471 g_free(s->cplus_txbuffer);
3472 s->cplus_txbuffer = NULL;
3473 }
3474 timer_del(s->timer);
3475 timer_free(s->timer);
3476 qemu_del_nic(s->nic);
3477 }
3478
3479 static void rtl8139_set_link_status(NetClientState *nc)
3480 {
3481 RTL8139State *s = qemu_get_nic_opaque(nc);
3482
3483 if (nc->link_down) {
3484 s->BasicModeStatus &= ~0x04;
3485 } else {
3486 s->BasicModeStatus |= 0x04;
3487 }
3488
3489 s->IntrStatus |= RxUnderrun;
3490 rtl8139_update_irq(s);
3491 }
3492
3493 static NetClientInfo net_rtl8139_info = {
3494 .type = NET_CLIENT_OPTIONS_KIND_NIC,
3495 .size = sizeof(NICState),
3496 .can_receive = rtl8139_can_receive,
3497 .receive = rtl8139_receive,
3498 .cleanup = rtl8139_cleanup,
3499 .link_status_changed = rtl8139_set_link_status,
3500 };
3501
3502 static int pci_rtl8139_init(PCIDevice *dev)
3503 {
3504 RTL8139State *s = RTL8139(dev);
3505 DeviceState *d = DEVICE(dev);
3506 uint8_t *pci_conf;
3507
3508 pci_conf = dev->config;
3509 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
3510 /* TODO: start of capability list, but no capability
3511 * list bit in status register, and offset 0xdc seems unused. */
3512 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3513
3514 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s,
3515 "rtl8139", 0x100);
3516 memory_region_init_io(&s->bar_mem, OBJECT(s), &rtl8139_mmio_ops, s,
3517 "rtl8139", 0x100);
3518 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3519 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
3520
3521 qemu_macaddr_default_if_unset(&s->conf.macaddr);
3522
3523 /* prepare eeprom */
3524 s->eeprom.contents[0] = 0x8129;
3525 #if 1
3526 /* PCI vendor and device ID should be mirrored here */
3527 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3528 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3529 #endif
3530 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3531 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3532 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3533
3534 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3535 object_get_typename(OBJECT(dev)), d->id, s);
3536 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
3537
3538 s->cplus_txbuffer = NULL;
3539 s->cplus_txbuffer_len = 0;
3540 s->cplus_txbuffer_offset = 0;
3541
3542 s->TimerExpire = 0;
3543 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s);
3544 rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3545
3546 add_boot_device_path(s->conf.bootindex, d, "/ethernet-phy@0");
3547
3548 return 0;
3549 }
3550
3551 static Property rtl8139_properties[] = {
3552 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3553 DEFINE_PROP_END_OF_LIST(),
3554 };
3555
3556 static void rtl8139_class_init(ObjectClass *klass, void *data)
3557 {
3558 DeviceClass *dc = DEVICE_CLASS(klass);
3559 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3560
3561 k->init = pci_rtl8139_init;
3562 k->exit = pci_rtl8139_uninit;
3563 k->romfile = "efi-rtl8139.rom";
3564 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3565 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3566 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3567 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
3568 dc->reset = rtl8139_reset;
3569 dc->vmsd = &vmstate_rtl8139;
3570 dc->props = rtl8139_properties;
3571 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
3572 }
3573
3574 static const TypeInfo rtl8139_info = {
3575 .name = TYPE_RTL8139,
3576 .parent = TYPE_PCI_DEVICE,
3577 .instance_size = sizeof(RTL8139State),
3578 .class_init = rtl8139_class_init,
3579 };
3580
3581 static void rtl8139_register_types(void)
3582 {
3583 type_register_static(&rtl8139_info);
3584 }
3585
3586 type_init(rtl8139_register_types)
CRIS target port of Qemu