2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "hw/sysbus.h"
32 #include "hw/arm/arm.h"
33 #include "hw/arm/primecell.h"
34 #include "hw/arm/virt.h"
35 #include "hw/devices.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/device_tree.h"
39 #include "sysemu/sysemu.h"
40 #include "sysemu/kvm.h"
41 #include "hw/boards.h"
42 #include "hw/loader.h"
43 #include "exec/address-spaces.h"
44 #include "qemu/bitops.h"
45 #include "qemu/error-report.h"
46 #include "hw/pci-host/gpex.h"
47 #include "hw/arm/virt-acpi-build.h"
48 #include "hw/arm/sysbus-fdt.h"
49 #include "hw/platform-bus.h"
50 #include "hw/arm/fdt.h"
51 #include "hw/intc/arm_gic_common.h"
53 #include "hw/smbios/smbios.h"
55 /* Number of external interrupt lines to configure the GIC with */
58 #define PLATFORM_BUS_NUM_IRQS 64
60 static ARMPlatformBusSystemParams platform_bus_params
;
62 typedef struct VirtBoardInfo
{
63 struct arm_boot_info bootinfo
;
64 const char *cpu_model
;
65 const MemMapEntry
*memmap
;
70 uint32_t clock_phandle
;
77 VirtBoardInfo
*daughterboard
;
86 #define VIRT_MACHINE_NAME "virt"
87 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME(VIRT_MACHINE_NAME)
88 #define VIRT_MACHINE(obj) \
89 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
90 #define VIRT_MACHINE_GET_CLASS(obj) \
91 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
92 #define VIRT_MACHINE_CLASS(klass) \
93 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
95 /* Addresses and sizes of our components.
96 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
97 * 128MB..256MB is used for miscellaneous device I/O.
98 * 256MB..1GB is reserved for possible future PCI support (ie where the
99 * PCI memory window will go if we add a PCI host controller).
100 * 1GB and up is RAM (which may happily spill over into the
101 * high memory region beyond 4GB).
102 * This represents a compromise between how much RAM can be given to
103 * a 32 bit VM and leaving space for expansion and in particular for PCI.
104 * Note that devices should generally be placed at multiples of 0x10000,
105 * to accommodate guests using 64K pages.
107 static const MemMapEntry a15memmap
[] = {
108 /* Space up to 0x8000000 is reserved for a boot ROM */
109 [VIRT_FLASH
] = { 0, 0x08000000 },
110 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
111 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
112 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
113 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
114 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
115 [VIRT_UART
] = { 0x09000000, 0x00001000 },
116 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
117 [VIRT_FW_CFG
] = { 0x09020000, 0x0000000a },
118 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
119 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
120 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
121 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
122 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
123 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
124 [VIRT_MEM
] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
125 /* Second PCIe window, 512GB wide at the 512GB boundary */
126 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
129 static const int a15irqmap
[] = {
132 [VIRT_PCIE
] = 3, /* ... to 6 */
133 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
134 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
135 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
138 static VirtBoardInfo machines
[] = {
140 .cpu_model
= "cortex-a15",
145 .cpu_model
= "cortex-a53",
150 .cpu_model
= "cortex-a57",
161 static VirtBoardInfo
*find_machine_info(const char *cpu
)
165 for (i
= 0; i
< ARRAY_SIZE(machines
); i
++) {
166 if (strcmp(cpu
, machines
[i
].cpu_model
) == 0) {
173 static void create_fdt(VirtBoardInfo
*vbi
)
175 void *fdt
= create_device_tree(&vbi
->fdt_size
);
178 error_report("create_device_tree() failed");
185 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
186 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
187 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
190 * /chosen and /memory nodes must exist for load_dtb
191 * to fill in necessary properties later
193 qemu_fdt_add_subnode(fdt
, "/chosen");
194 qemu_fdt_add_subnode(fdt
, "/memory");
195 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
197 /* Clock node, for the benefit of the UART. The kernel device tree
198 * binding documentation claims the PL011 node clock properties are
199 * optional but in practice if you omit them the kernel refuses to
200 * probe for the device.
202 vbi
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
203 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
204 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
205 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
206 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
207 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
209 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vbi
->clock_phandle
);
213 static void fdt_add_psci_node(const VirtBoardInfo
*vbi
)
215 uint32_t cpu_suspend_fn
;
219 void *fdt
= vbi
->fdt
;
220 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
222 qemu_fdt_add_subnode(fdt
, "/psci");
223 if (armcpu
->psci_version
== 2) {
224 const char comp
[] = "arm,psci-0.2\0arm,psci";
225 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
227 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
228 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
229 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
230 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
231 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
233 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
234 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
235 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
238 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
240 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
241 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
242 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
243 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
246 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
247 * to the instruction that should be used to invoke PSCI functions.
248 * However, the device tree binding uses 'method' instead, so that is
249 * what we should use here.
251 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
253 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
254 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
255 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
256 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
259 static void fdt_add_timer_nodes(const VirtBoardInfo
*vbi
)
261 /* Note that on A15 h/w these interrupts are level-triggered,
262 * but for the GIC implementation provided by both QEMU and KVM
263 * they are edge-triggered.
266 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
268 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
269 GIC_FDT_IRQ_PPI_CPU_WIDTH
, (1 << vbi
->smp_cpus
) - 1);
271 qemu_fdt_add_subnode(vbi
->fdt
, "/timer");
273 armcpu
= ARM_CPU(qemu_get_cpu(0));
274 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
275 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
276 qemu_fdt_setprop(vbi
->fdt
, "/timer", "compatible",
277 compat
, sizeof(compat
));
279 qemu_fdt_setprop_string(vbi
->fdt
, "/timer", "compatible",
282 qemu_fdt_setprop_cells(vbi
->fdt
, "/timer", "interrupts",
283 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
284 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
285 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
286 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
289 static void fdt_add_cpu_nodes(const VirtBoardInfo
*vbi
)
295 * From Documentation/devicetree/bindings/arm/cpus.txt
296 * On ARM v8 64-bit systems value should be set to 2,
297 * that corresponds to the MPIDR_EL1 register size.
298 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
299 * in the system, #address-cells can be set to 1, since
300 * MPIDR_EL1[63:32] bits are not used for CPUs
303 * Here we actually don't know whether our system is 32- or 64-bit one.
304 * The simplest way to go is to examine affinity IDs of all our CPUs. If
305 * at least one of them has Aff3 populated, we set #address-cells to 2.
307 for (cpu
= 0; cpu
< vbi
->smp_cpus
; cpu
++) {
308 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
310 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
316 qemu_fdt_add_subnode(vbi
->fdt
, "/cpus");
317 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#address-cells", addr_cells
);
318 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#size-cells", 0x0);
320 for (cpu
= vbi
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
321 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
322 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
324 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
325 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "cpu");
326 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible",
327 armcpu
->dtb_compatible
);
329 if (vbi
->smp_cpus
> 1) {
330 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
331 "enable-method", "psci");
334 if (addr_cells
== 2) {
335 qemu_fdt_setprop_u64(vbi
->fdt
, nodename
, "reg",
336 armcpu
->mp_affinity
);
338 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "reg",
339 armcpu
->mp_affinity
);
346 static void fdt_add_v2m_gic_node(VirtBoardInfo
*vbi
)
348 vbi
->v2m_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
349 qemu_fdt_add_subnode(vbi
->fdt
, "/intc/v2m");
350 qemu_fdt_setprop_string(vbi
->fdt
, "/intc/v2m", "compatible",
351 "arm,gic-v2m-frame");
352 qemu_fdt_setprop(vbi
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
353 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc/v2m", "reg",
354 2, vbi
->memmap
[VIRT_GIC_V2M
].base
,
355 2, vbi
->memmap
[VIRT_GIC_V2M
].size
);
356 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc/v2m", "phandle", vbi
->v2m_phandle
);
359 static void fdt_add_gic_node(VirtBoardInfo
*vbi
)
361 vbi
->gic_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
362 qemu_fdt_setprop_cell(vbi
->fdt
, "/", "interrupt-parent", vbi
->gic_phandle
);
364 qemu_fdt_add_subnode(vbi
->fdt
, "/intc");
365 /* 'cortex-a15-gic' means 'GIC v2' */
366 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
367 "arm,cortex-a15-gic");
368 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#interrupt-cells", 3);
369 qemu_fdt_setprop(vbi
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
370 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
371 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
372 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
373 2, vbi
->memmap
[VIRT_GIC_CPU
].base
,
374 2, vbi
->memmap
[VIRT_GIC_CPU
].size
);
375 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#address-cells", 0x2);
376 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#size-cells", 0x2);
377 qemu_fdt_setprop(vbi
->fdt
, "/intc", "ranges", NULL
, 0);
378 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "phandle", vbi
->gic_phandle
);
381 static void create_v2m(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
384 int irq
= vbi
->irqmap
[VIRT_GIC_V2M
];
387 dev
= qdev_create(NULL
, "arm-gicv2m");
388 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vbi
->memmap
[VIRT_GIC_V2M
].base
);
389 qdev_prop_set_uint32(dev
, "base-spi", irq
);
390 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
391 qdev_init_nofail(dev
);
393 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
394 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
397 fdt_add_v2m_gic_node(vbi
);
400 static void create_gic(VirtBoardInfo
*vbi
, qemu_irq
*pic
, bool secure
)
402 /* We create a standalone GIC v2 */
404 SysBusDevice
*gicbusdev
;
408 gictype
= gic_class_name();
410 gicdev
= qdev_create(NULL
, gictype
);
411 qdev_prop_set_uint32(gicdev
, "revision", 2);
412 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
413 /* Note that the num-irq property counts both internal and external
414 * interrupts; there are always 32 of the former (mandated by GIC spec).
416 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
417 if (!kvm_irqchip_in_kernel()) {
418 qdev_prop_set_bit(gicdev
, "has-security-extensions", secure
);
420 qdev_init_nofail(gicdev
);
421 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
422 sysbus_mmio_map(gicbusdev
, 0, vbi
->memmap
[VIRT_GIC_DIST
].base
);
423 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_CPU
].base
);
425 /* Wire the outputs from each CPU's generic timer to the
426 * appropriate GIC PPI inputs, and the GIC's IRQ output to
427 * the CPU's IRQ input.
429 for (i
= 0; i
< smp_cpus
; i
++) {
430 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
431 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
433 /* Mapping from the output timer irq lines from the CPU to the
434 * GIC PPI inputs we use for the virt board.
436 const int timer_irq
[] = {
437 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
438 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
439 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
440 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
443 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
444 qdev_connect_gpio_out(cpudev
, irq
,
445 qdev_get_gpio_in(gicdev
,
446 ppibase
+ timer_irq
[irq
]));
449 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
450 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
451 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
454 for (i
= 0; i
< NUM_IRQS
; i
++) {
455 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
458 fdt_add_gic_node(vbi
);
460 create_v2m(vbi
, pic
);
463 static void create_uart(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
466 hwaddr base
= vbi
->memmap
[VIRT_UART
].base
;
467 hwaddr size
= vbi
->memmap
[VIRT_UART
].size
;
468 int irq
= vbi
->irqmap
[VIRT_UART
];
469 const char compat
[] = "arm,pl011\0arm,primecell";
470 const char clocknames
[] = "uartclk\0apb_pclk";
472 sysbus_create_simple("pl011", base
, pic
[irq
]);
474 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
475 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
476 /* Note that we can't use setprop_string because of the embedded NUL */
477 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible",
478 compat
, sizeof(compat
));
479 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
481 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
482 GIC_FDT_IRQ_TYPE_SPI
, irq
,
483 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
484 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "clocks",
485 vbi
->clock_phandle
, vbi
->clock_phandle
);
486 qemu_fdt_setprop(vbi
->fdt
, nodename
, "clock-names",
487 clocknames
, sizeof(clocknames
));
489 qemu_fdt_setprop_string(vbi
->fdt
, "/chosen", "stdout-path", nodename
);
493 static void create_rtc(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
496 hwaddr base
= vbi
->memmap
[VIRT_RTC
].base
;
497 hwaddr size
= vbi
->memmap
[VIRT_RTC
].size
;
498 int irq
= vbi
->irqmap
[VIRT_RTC
];
499 const char compat
[] = "arm,pl031\0arm,primecell";
501 sysbus_create_simple("pl031", base
, pic
[irq
]);
503 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
504 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
505 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
506 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
508 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
509 GIC_FDT_IRQ_TYPE_SPI
, irq
,
510 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
511 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
512 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
516 static void create_virtio_devices(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
519 hwaddr size
= vbi
->memmap
[VIRT_MMIO
].size
;
521 /* We create the transports in forwards order. Since qbus_realize()
522 * prepends (not appends) new child buses, the incrementing loop below will
523 * create a list of virtio-mmio buses with decreasing base addresses.
525 * When a -device option is processed from the command line,
526 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
527 * order. The upshot is that -device options in increasing command line
528 * order are mapped to virtio-mmio buses with decreasing base addresses.
530 * When this code was originally written, that arrangement ensured that the
531 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
532 * the first -device on the command line. (The end-to-end order is a
533 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
534 * guest kernel's name-to-address assignment strategy.)
536 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
537 * the message, if not necessarily the code, of commit 70161ff336.
538 * Therefore the loop now establishes the inverse of the original intent.
540 * Unfortunately, we can't counteract the kernel change by reversing the
541 * loop; it would break existing command lines.
543 * In any case, the kernel makes no guarantee about the stability of
544 * enumeration order of virtio devices (as demonstrated by it changing
545 * between kernel versions). For reliable and stable identification
546 * of disks users must use UUIDs or similar mechanisms.
548 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
549 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
550 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
552 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
555 /* We add dtb nodes in reverse order so that they appear in the finished
556 * device tree lowest address first.
558 * Note that this mapping is independent of the loop above. The previous
559 * loop influences virtio device to virtio transport assignment, whereas
560 * this loop controls how virtio transports are laid out in the dtb.
562 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
564 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
565 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
567 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
568 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
569 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
570 "compatible", "virtio,mmio");
571 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
573 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
574 GIC_FDT_IRQ_TYPE_SPI
, irq
,
575 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
580 static void create_one_flash(const char *name
, hwaddr flashbase
,
583 /* Create and map a single flash device. We use the same
584 * parameters as the flash devices on the Versatile Express board.
586 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
587 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
588 const uint64_t sectorlength
= 256 * 1024;
591 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
595 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
596 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
597 qdev_prop_set_uint8(dev
, "width", 4);
598 qdev_prop_set_uint8(dev
, "device-width", 2);
599 qdev_prop_set_bit(dev
, "big-endian", false);
600 qdev_prop_set_uint16(dev
, "id0", 0x89);
601 qdev_prop_set_uint16(dev
, "id1", 0x18);
602 qdev_prop_set_uint16(dev
, "id2", 0x00);
603 qdev_prop_set_uint16(dev
, "id3", 0x00);
604 qdev_prop_set_string(dev
, "name", name
);
605 qdev_init_nofail(dev
);
607 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, flashbase
);
610 static void create_flash(const VirtBoardInfo
*vbi
)
612 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
613 * Any file passed via -bios goes in the first of these.
615 hwaddr flashsize
= vbi
->memmap
[VIRT_FLASH
].size
/ 2;
616 hwaddr flashbase
= vbi
->memmap
[VIRT_FLASH
].base
;
623 if (drive_get(IF_PFLASH
, 0, 0)) {
624 error_report("The contents of the first flash device may be "
625 "specified with -bios or with -drive if=pflash... "
626 "but you cannot use both options at once");
629 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
631 error_report("Could not find ROM image '%s'", bios_name
);
634 image_size
= load_image_targphys(fn
, flashbase
, flashsize
);
636 if (image_size
< 0) {
637 error_report("Could not load ROM image '%s'", bios_name
);
642 create_one_flash("virt.flash0", flashbase
, flashsize
);
643 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
);
645 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
646 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
647 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
648 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
649 2, flashbase
, 2, flashsize
,
650 2, flashbase
+ flashsize
, 2, flashsize
);
651 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
655 static void create_fw_cfg(const VirtBoardInfo
*vbi
)
657 hwaddr base
= vbi
->memmap
[VIRT_FW_CFG
].base
;
658 hwaddr size
= vbi
->memmap
[VIRT_FW_CFG
].size
;
661 fw_cfg_init_mem_wide(base
+ 8, base
, 8);
663 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
664 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
665 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
666 "compatible", "qemu,fw-cfg-mmio");
667 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
672 static void create_pcie_irq_map(const VirtBoardInfo
*vbi
, uint32_t gic_phandle
,
673 int first_irq
, const char *nodename
)
676 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
677 uint32_t *irq_map
= full_irq_map
;
679 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
680 for (pin
= 0; pin
< 4; pin
++) {
681 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
682 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
683 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
687 devfn
<< 8, 0, 0, /* devfn */
688 pin
+ 1, /* PCI pin */
689 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
691 /* Convert map to big endian */
692 for (i
= 0; i
< 10; i
++) {
693 irq_map
[i
] = cpu_to_be32(map
[i
]);
699 qemu_fdt_setprop(vbi
->fdt
, nodename
, "interrupt-map",
700 full_irq_map
, sizeof(full_irq_map
));
702 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupt-map-mask",
703 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
707 static void create_pcie(const VirtBoardInfo
*vbi
, qemu_irq
*pic
,
710 hwaddr base_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].base
;
711 hwaddr size_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].size
;
712 hwaddr base_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
713 hwaddr size_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
714 hwaddr base_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].base
;
715 hwaddr size_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].size
;
716 hwaddr base_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].base
;
717 hwaddr size_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].size
;
718 hwaddr base
= base_mmio
;
719 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
720 int irq
= vbi
->irqmap
[VIRT_PCIE
];
721 MemoryRegion
*mmio_alias
;
722 MemoryRegion
*mmio_reg
;
723 MemoryRegion
*ecam_alias
;
724 MemoryRegion
*ecam_reg
;
729 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
730 qdev_init_nofail(dev
);
732 /* Map only the first size_ecam bytes of ECAM space */
733 ecam_alias
= g_new0(MemoryRegion
, 1);
734 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
735 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
736 ecam_reg
, 0, size_ecam
);
737 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
739 /* Map the MMIO window into system address space so as to expose
740 * the section of PCI MMIO space which starts at the same base address
741 * (ie 1:1 mapping for that part of PCI MMIO space visible through
744 mmio_alias
= g_new0(MemoryRegion
, 1);
745 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
746 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
747 mmio_reg
, base_mmio
, size_mmio
);
748 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
751 /* Map high MMIO space */
752 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
754 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
755 mmio_reg
, base_mmio_high
, size_mmio_high
);
756 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
760 /* Map IO port space */
761 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
763 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
764 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
767 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
768 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
769 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
770 "compatible", "pci-host-ecam-generic");
771 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "pci");
772 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#address-cells", 3);
773 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#size-cells", 2);
774 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "bus-range", 0,
777 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "msi-parent", vbi
->v2m_phandle
);
779 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
780 2, base_ecam
, 2, size_ecam
);
783 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
784 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
785 2, base_pio
, 2, size_pio
,
786 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
787 2, base_mmio
, 2, size_mmio
,
788 1, FDT_PCI_RANGE_MMIO_64BIT
,
790 2, base_mmio_high
, 2, size_mmio_high
);
792 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
793 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
794 2, base_pio
, 2, size_pio
,
795 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
796 2, base_mmio
, 2, size_mmio
);
799 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#interrupt-cells", 1);
800 create_pcie_irq_map(vbi
, vbi
->gic_phandle
, irq
, nodename
);
805 static void create_platform_bus(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
810 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
811 MemoryRegion
*sysmem
= get_system_memory();
813 platform_bus_params
.platform_bus_base
= vbi
->memmap
[VIRT_PLATFORM_BUS
].base
;
814 platform_bus_params
.platform_bus_size
= vbi
->memmap
[VIRT_PLATFORM_BUS
].size
;
815 platform_bus_params
.platform_bus_first_irq
= vbi
->irqmap
[VIRT_PLATFORM_BUS
];
816 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
818 fdt_params
->system_params
= &platform_bus_params
;
819 fdt_params
->binfo
= &vbi
->bootinfo
;
820 fdt_params
->intc
= "/intc";
822 * register a machine init done notifier that creates the device tree
823 * nodes of the platform bus and its children dynamic sysbus devices
825 arm_register_platform_bus_fdt_creator(fdt_params
);
827 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
828 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
829 qdev_prop_set_uint32(dev
, "num_irqs",
830 platform_bus_params
.platform_bus_num_irqs
);
831 qdev_prop_set_uint32(dev
, "mmio_size",
832 platform_bus_params
.platform_bus_size
);
833 qdev_init_nofail(dev
);
834 s
= SYS_BUS_DEVICE(dev
);
836 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
837 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
838 sysbus_connect_irq(s
, i
, pic
[irqn
]);
841 memory_region_add_subregion(sysmem
,
842 platform_bus_params
.platform_bus_base
,
843 sysbus_mmio_get_region(s
, 0));
846 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
848 const VirtBoardInfo
*board
= (const VirtBoardInfo
*)binfo
;
850 *fdt_size
= board
->fdt_size
;
854 static void virt_build_smbios(VirtGuestInfo
*guest_info
)
856 FWCfgState
*fw_cfg
= guest_info
->fw_cfg
;
857 uint8_t *smbios_tables
, *smbios_anchor
;
858 size_t smbios_tables_len
, smbios_anchor_len
;
864 smbios_set_defaults("QEMU", "QEMU Virtual Machine",
865 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
867 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
868 &smbios_anchor
, &smbios_anchor_len
);
871 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-tables",
872 smbios_tables
, smbios_tables_len
);
873 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-anchor",
874 smbios_anchor
, smbios_anchor_len
);
879 void virt_guest_info_machine_done(Notifier
*notifier
, void *data
)
881 VirtGuestInfoState
*guest_info_state
= container_of(notifier
,
882 VirtGuestInfoState
, machine_done
);
883 virt_acpi_setup(&guest_info_state
->info
);
884 virt_build_smbios(&guest_info_state
->info
);
887 static void machvirt_init(MachineState
*machine
)
889 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
890 qemu_irq pic
[NUM_IRQS
];
891 MemoryRegion
*sysmem
= get_system_memory();
893 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
894 const char *cpu_model
= machine
->cpu_model
;
896 VirtGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
897 VirtGuestInfo
*guest_info
= &guest_info_state
->info
;
901 cpu_model
= "cortex-a15";
904 /* Separate the actual CPU model name from any appended features */
905 cpustr
= g_strsplit(cpu_model
, ",", 2);
907 vbi
= find_machine_info(cpustr
[0]);
910 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
914 vbi
->smp_cpus
= smp_cpus
;
916 if (machine
->ram_size
> vbi
->memmap
[VIRT_MEM
].size
) {
917 error_report("mach-virt: cannot model more than 30GB RAM");
923 for (n
= 0; n
< smp_cpus
; n
++) {
924 ObjectClass
*oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
925 CPUClass
*cc
= CPU_CLASS(oc
);
928 char *cpuopts
= g_strdup(cpustr
[1]);
931 fprintf(stderr
, "Unable to find CPU definition\n");
934 cpuobj
= object_new(object_class_get_name(oc
));
936 /* Handle any CPU options specified by the user */
937 cc
->parse_features(CPU(cpuobj
), cpuopts
, &err
);
940 error_report_err(err
);
945 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
948 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
, "psci-conduit",
951 /* Secondary CPUs start in PSCI powered-down state */
953 object_property_set_bool(cpuobj
, true, "start-powered-off", NULL
);
956 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
957 object_property_set_int(cpuobj
, vbi
->memmap
[VIRT_CPUPERIPHS
].base
,
958 "reset-cbar", &error_abort
);
961 object_property_set_bool(cpuobj
, true, "realized", NULL
);
964 fdt_add_timer_nodes(vbi
);
965 fdt_add_cpu_nodes(vbi
);
966 fdt_add_psci_node(vbi
);
968 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
970 memory_region_add_subregion(sysmem
, vbi
->memmap
[VIRT_MEM
].base
, ram
);
974 create_gic(vbi
, pic
, vms
->secure
);
976 create_uart(vbi
, pic
);
978 create_rtc(vbi
, pic
);
980 create_pcie(vbi
, pic
, vms
->highmem
);
982 /* Create mmio transports, so the user can create virtio backends
983 * (which will be automatically plugged in to the transports). If
984 * no backend is created the transport will just sit harmlessly idle.
986 create_virtio_devices(vbi
, pic
);
989 rom_set_fw(fw_cfg_find());
991 guest_info
->smp_cpus
= smp_cpus
;
992 guest_info
->fw_cfg
= fw_cfg_find();
993 guest_info
->memmap
= vbi
->memmap
;
994 guest_info
->irqmap
= vbi
->irqmap
;
995 guest_info
->use_highmem
= vms
->highmem
;
996 guest_info_state
->machine_done
.notify
= virt_guest_info_machine_done
;
997 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
999 vbi
->bootinfo
.ram_size
= machine
->ram_size
;
1000 vbi
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1001 vbi
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1002 vbi
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1003 vbi
->bootinfo
.nb_cpus
= smp_cpus
;
1004 vbi
->bootinfo
.board_id
= -1;
1005 vbi
->bootinfo
.loader_start
= vbi
->memmap
[VIRT_MEM
].base
;
1006 vbi
->bootinfo
.get_dtb
= machvirt_dtb
;
1007 vbi
->bootinfo
.firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1008 arm_load_kernel(ARM_CPU(first_cpu
), &vbi
->bootinfo
);
1011 * arm_load_kernel machine init done notifier registration must
1012 * happen before the platform_bus_create call. In this latter,
1013 * another notifier is registered which adds platform bus nodes.
1014 * Notifiers are executed in registration reverse order.
1016 create_platform_bus(vbi
, pic
);
1019 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1021 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1026 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1028 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1030 vms
->secure
= value
;
1033 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1035 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1037 return vms
->highmem
;
1040 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1042 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1044 vms
->highmem
= value
;
1047 static void virt_instance_init(Object
*obj
)
1049 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1051 /* EL3 is disabled by default on virt: this makes us consistent
1052 * between KVM and TCG for this board, and it also allows us to
1053 * boot UEFI blobs which assume no TrustZone support.
1055 vms
->secure
= false;
1056 object_property_add_bool(obj
, "secure", virt_get_secure
,
1057 virt_set_secure
, NULL
);
1058 object_property_set_description(obj
, "secure",
1059 "Set on/off to enable/disable the ARM "
1060 "Security Extensions (TrustZone)",
1063 /* High memory is enabled by default */
1064 vms
->highmem
= true;
1065 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1066 virt_set_highmem
, NULL
);
1067 object_property_set_description(obj
, "highmem",
1068 "Set on/off to enable/disable using "
1069 "physical address space above 32 bits",
1073 static void virt_class_init(ObjectClass
*oc
, void *data
)
1075 MachineClass
*mc
= MACHINE_CLASS(oc
);
1077 mc
->name
= VIRT_MACHINE_NAME
;
1078 mc
->desc
= "ARM Virtual Machine",
1079 mc
->init
= machvirt_init
;
1081 mc
->has_dynamic_sysbus
= true;
1082 mc
->block_default_type
= IF_VIRTIO
;
1086 static const TypeInfo machvirt_info
= {
1087 .name
= TYPE_VIRT_MACHINE
,
1088 .parent
= TYPE_MACHINE
,
1089 .instance_size
= sizeof(VirtMachineState
),
1090 .instance_init
= virt_instance_init
,
1091 .class_size
= sizeof(VirtMachineClass
),
1092 .class_init
= virt_class_init
,
1095 static void machvirt_machine_init(void)
1097 type_register_static(&machvirt_info
);
1100 machine_init(machvirt_machine_init
);