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hw/pl181.c: Add save/load support
[qemu/cris-port.git] / hw / e1000.c
bloba29c944df412344f83540d4ac1a4b328d331ea3f
1 /*
2 * QEMU e1000 emulation
3 *
4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 */
26
27
28 #include "hw.h"
29 #include "pci.h"
30 #include "net.h"
31 #include "net/checksum.h"
32 #include "loader.h"
33 #include "sysemu.h"
34 #include "dma.h"
35
36 #include "e1000_hw.h"
37
38 #define E1000_DEBUG
39
40 #ifdef E1000_DEBUG
41 enum {
42 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
43 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
44 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
45 DEBUG_RXFILTER, DEBUG_NOTYET,
46 };
47 #define DBGBIT(x) (1<<DEBUG_##x)
48 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
49
50 #define DBGOUT(what, fmt, ...) do { \
51 if (debugflags & DBGBIT(what)) \
52 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
53 } while (0)
54 #else
55 #define DBGOUT(what, fmt, ...) do {} while (0)
56 #endif
57
58 #define IOPORT_SIZE 0x40
59 #define PNPMMIO_SIZE 0x20000
60 #define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
61
62 /*
63 * HW models:
64 * E1000_DEV_ID_82540EM works with Windows and Linux
65 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
66 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
67 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
68 * Others never tested
69 */
70 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
71
72 /*
73 * May need to specify additional MAC-to-PHY entries --
74 * Intel's Windows driver refuses to initialize unless they match
75 */
76 enum {
77 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
78 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
79 /* default to E1000_DEV_ID_82540EM */ 0xc20
80 };
81
82 typedef struct E1000State_st {
83 PCIDevice dev;
84 NICState *nic;
85 NICConf conf;
86 MemoryRegion mmio;
87 MemoryRegion io;
88
89 uint32_t mac_reg[0x8000];
90 uint16_t phy_reg[0x20];
91 uint16_t eeprom_data[64];
92
93 uint32_t rxbuf_size;
94 uint32_t rxbuf_min_shift;
95 int check_rxov;
96 struct e1000_tx {
97 unsigned char header[256];
98 unsigned char vlan_header[4];
99 /* Fields vlan and data must not be reordered or separated. */
100 unsigned char vlan[4];
101 unsigned char data[0x10000];
102 uint16_t size;
103 unsigned char sum_needed;
104 unsigned char vlan_needed;
105 uint8_t ipcss;
106 uint8_t ipcso;
107 uint16_t ipcse;
108 uint8_t tucss;
109 uint8_t tucso;
110 uint16_t tucse;
111 uint8_t hdr_len;
112 uint16_t mss;
113 uint32_t paylen;
114 uint16_t tso_frames;
115 char tse;
116 int8_t ip;
117 int8_t tcp;
118 char cptse; // current packet tse bit
119 } tx;
120
121 struct {
122 uint32_t val_in; // shifted in from guest driver
123 uint16_t bitnum_in;
124 uint16_t bitnum_out;
125 uint16_t reading;
126 uint32_t old_eecd;
127 } eecd_state;
128 } E1000State;
129
130 #define defreg(x) x = (E1000_##x>>2)
131 enum {
132 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
133 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
134 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
135 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
136 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
137 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
138 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
139 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
140 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
141 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
142 defreg(VET),
143 };
144
145 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
146 static const char phy_regcap[0x20] = {
147 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
148 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
149 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
150 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
151 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
152 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
153 };
154
155 static void
156 set_interrupt_cause(E1000State *s, int index, uint32_t val)
157 {
158 if (val)
159 val |= E1000_ICR_INT_ASSERTED;
160 s->mac_reg[ICR] = val;
161 s->mac_reg[ICS] = val;
162 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
163 }
164
165 static void
166 set_ics(E1000State *s, int index, uint32_t val)
167 {
168 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
169 s->mac_reg[IMS]);
170 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
171 }
172
173 static int
174 rxbufsize(uint32_t v)
175 {
176 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
177 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
178 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
179 switch (v) {
180 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
181 return 16384;
182 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
183 return 8192;
184 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
185 return 4096;
186 case E1000_RCTL_SZ_1024:
187 return 1024;
188 case E1000_RCTL_SZ_512:
189 return 512;
190 case E1000_RCTL_SZ_256:
191 return 256;
192 }
193 return 2048;
194 }
195
196 static void
197 set_ctrl(E1000State *s, int index, uint32_t val)
198 {
199 /* RST is self clearing */
200 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
201 }
202
203 static void
204 set_rx_control(E1000State *s, int index, uint32_t val)
205 {
206 s->mac_reg[RCTL] = val;
207 s->rxbuf_size = rxbufsize(val);
208 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
209 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
210 s->mac_reg[RCTL]);
211 }
212
213 static void
214 set_mdic(E1000State *s, int index, uint32_t val)
215 {
216 uint32_t data = val & E1000_MDIC_DATA_MASK;
217 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
218
219 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
220 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
221 else if (val & E1000_MDIC_OP_READ) {
222 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
223 if (!(phy_regcap[addr] & PHY_R)) {
224 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
225 val |= E1000_MDIC_ERROR;
226 } else
227 val = (val ^ data) | s->phy_reg[addr];
228 } else if (val & E1000_MDIC_OP_WRITE) {
229 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
230 if (!(phy_regcap[addr] & PHY_W)) {
231 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
232 val |= E1000_MDIC_ERROR;
233 } else
234 s->phy_reg[addr] = data;
235 }
236 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
237 set_ics(s, 0, E1000_ICR_MDAC);
238 }
239
240 static uint32_t
241 get_eecd(E1000State *s, int index)
242 {
243 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
244
245 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
246 s->eecd_state.bitnum_out, s->eecd_state.reading);
247 if (!s->eecd_state.reading ||
248 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
249 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
250 ret |= E1000_EECD_DO;
251 return ret;
252 }
253
254 static void
255 set_eecd(E1000State *s, int index, uint32_t val)
256 {
257 uint32_t oldval = s->eecd_state.old_eecd;
258
259 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
260 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
261 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
262 return;
263 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
264 s->eecd_state.val_in = 0;
265 s->eecd_state.bitnum_in = 0;
266 s->eecd_state.bitnum_out = 0;
267 s->eecd_state.reading = 0;
268 }
269 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
270 return;
271 if (!(E1000_EECD_SK & val)) { // falling edge
272 s->eecd_state.bitnum_out++;
273 return;
274 }
275 s->eecd_state.val_in <<= 1;
276 if (val & E1000_EECD_DI)
277 s->eecd_state.val_in |= 1;
278 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
279 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
280 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
281 EEPROM_READ_OPCODE_MICROWIRE);
282 }
283 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
284 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
285 s->eecd_state.reading);
286 }
287
288 static uint32_t
289 flash_eerd_read(E1000State *s, int x)
290 {
291 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
292
293 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
294 return (s->mac_reg[EERD]);
295
296 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
297 return (E1000_EEPROM_RW_REG_DONE | r);
298
299 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
300 E1000_EEPROM_RW_REG_DONE | r);
301 }
302
303 static void
304 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
305 {
306 uint32_t sum;
307
308 if (cse && cse < n)
309 n = cse + 1;
310 if (sloc < n-1) {
311 sum = net_checksum_add(n-css, data+css);
312 cpu_to_be16wu((uint16_t *)(data + sloc),
313 net_checksum_finish(sum));
314 }
315 }
316
317 static inline int
318 vlan_enabled(E1000State *s)
319 {
320 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
321 }
322
323 static inline int
324 vlan_rx_filter_enabled(E1000State *s)
325 {
326 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
327 }
328
329 static inline int
330 is_vlan_packet(E1000State *s, const uint8_t *buf)
331 {
332 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
333 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
334 }
335
336 static inline int
337 is_vlan_txd(uint32_t txd_lower)
338 {
339 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
340 }
341
342 /* FCS aka Ethernet CRC-32. We don't get it from backends and can't
343 * fill it in, just pad descriptor length by 4 bytes unless guest
344 * told us to strip it off the packet. */
345 static inline int
346 fcs_len(E1000State *s)
347 {
348 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
349 }
350
351 static void
352 xmit_seg(E1000State *s)
353 {
354 uint16_t len, *sp;
355 unsigned int frames = s->tx.tso_frames, css, sofar, n;
356 struct e1000_tx *tp = &s->tx;
357
358 if (tp->tse && tp->cptse) {
359 css = tp->ipcss;
360 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
361 frames, tp->size, css);
362 if (tp->ip) { // IPv4
363 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
364 tp->size - css);
365 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
366 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
367 } else // IPv6
368 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
369 tp->size - css);
370 css = tp->tucss;
371 len = tp->size - css;
372 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
373 if (tp->tcp) {
374 sofar = frames * tp->mss;
375 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
376 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
377 if (tp->paylen - sofar > tp->mss)
378 tp->data[css + 13] &= ~9; // PSH, FIN
379 } else // UDP
380 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
381 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
382 unsigned int phsum;
383 // add pseudo-header length before checksum calculation
384 sp = (uint16_t *)(tp->data + tp->tucso);
385 phsum = be16_to_cpup(sp) + len;
386 phsum = (phsum >> 16) + (phsum & 0xffff);
387 cpu_to_be16wu(sp, phsum);
388 }
389 tp->tso_frames++;
390 }
391
392 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
393 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
394 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
395 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
396 if (tp->vlan_needed) {
397 memmove(tp->vlan, tp->data, 4);
398 memmove(tp->data, tp->data + 4, 8);
399 memcpy(tp->data + 8, tp->vlan_header, 4);
400 qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
401 } else
402 qemu_send_packet(&s->nic->nc, tp->data, tp->size);
403 s->mac_reg[TPT]++;
404 s->mac_reg[GPTC]++;
405 n = s->mac_reg[TOTL];
406 if ((s->mac_reg[TOTL] += s->tx.size) < n)
407 s->mac_reg[TOTH]++;
408 }
409
410 static void
411 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
412 {
413 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
414 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
415 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
416 unsigned int msh = 0xfffff, hdr = 0;
417 uint64_t addr;
418 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
419 struct e1000_tx *tp = &s->tx;
420
421 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
422 op = le32_to_cpu(xp->cmd_and_length);
423 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
424 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
425 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
426 tp->tucss = xp->upper_setup.tcp_fields.tucss;
427 tp->tucso = xp->upper_setup.tcp_fields.tucso;
428 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
429 tp->paylen = op & 0xfffff;
430 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
431 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
432 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
433 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
434 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
435 tp->tso_frames = 0;
436 if (tp->tucso == 0) { // this is probably wrong
437 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
438 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
439 }
440 return;
441 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
442 // data descriptor
443 if (tp->size == 0) {
444 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
445 }
446 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
447 } else {
448 // legacy descriptor
449 tp->cptse = 0;
450 }
451
452 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
453 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
454 tp->vlan_needed = 1;
455 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
456 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
457 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
458 le16_to_cpu(dp->upper.fields.special));
459 }
460
461 addr = le64_to_cpu(dp->buffer_addr);
462 if (tp->tse && tp->cptse) {
463 hdr = tp->hdr_len;
464 msh = hdr + tp->mss;
465 do {
466 bytes = split_size;
467 if (tp->size + bytes > msh)
468 bytes = msh - tp->size;
469 pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes);
470 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
471 memmove(tp->header, tp->data, hdr);
472 tp->size = sz;
473 addr += bytes;
474 if (sz == msh) {
475 xmit_seg(s);
476 memmove(tp->data, tp->header, hdr);
477 tp->size = hdr;
478 }
479 } while (split_size -= bytes);
480 } else if (!tp->tse && tp->cptse) {
481 // context descriptor TSE is not set, while data descriptor TSE is set
482 DBGOUT(TXERR, "TCP segmentaion Error\n");
483 } else {
484 pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size);
485 tp->size += split_size;
486 }
487
488 if (!(txd_lower & E1000_TXD_CMD_EOP))
489 return;
490 if (!(tp->tse && tp->cptse && tp->size < hdr))
491 xmit_seg(s);
492 tp->tso_frames = 0;
493 tp->sum_needed = 0;
494 tp->vlan_needed = 0;
495 tp->size = 0;
496 tp->cptse = 0;
497 }
498
499 static uint32_t
500 txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
501 {
502 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
503
504 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
505 return 0;
506 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
507 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
508 dp->upper.data = cpu_to_le32(txd_upper);
509 pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp),
510 &dp->upper, sizeof(dp->upper));
511 return E1000_ICR_TXDW;
512 }
513
514 static uint64_t tx_desc_base(E1000State *s)
515 {
516 uint64_t bah = s->mac_reg[TDBAH];
517 uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
518
519 return (bah << 32) + bal;
520 }
521
522 static void
523 start_xmit(E1000State *s)
524 {
525 dma_addr_t base;
526 struct e1000_tx_desc desc;
527 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
528
529 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
530 DBGOUT(TX, "tx disabled\n");
531 return;
532 }
533
534 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
535 base = tx_desc_base(s) +
536 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
537 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
538
539 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
540 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
541 desc.upper.data);
542
543 process_tx_desc(s, &desc);
544 cause |= txdesc_writeback(s, base, &desc);
545
546 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
547 s->mac_reg[TDH] = 0;
548 /*
549 * the following could happen only if guest sw assigns
550 * bogus values to TDT/TDLEN.
551 * there's nothing too intelligent we could do about this.
552 */
553 if (s->mac_reg[TDH] == tdh_start) {
554 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
555 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
556 break;
557 }
558 }
559 set_ics(s, 0, cause);
560 }
561
562 static int
563 receive_filter(E1000State *s, const uint8_t *buf, int size)
564 {
565 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
566 static const int mta_shift[] = {4, 3, 2, 0};
567 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
568
569 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
570 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
571 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
572 ((vid >> 5) & 0x7f));
573 if ((vfta & (1 << (vid & 0x1f))) == 0)
574 return 0;
575 }
576
577 if (rctl & E1000_RCTL_UPE) // promiscuous
578 return 1;
579
580 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
581 return 1;
582
583 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
584 return 1;
585
586 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
587 if (!(rp[1] & E1000_RAH_AV))
588 continue;
589 ra[0] = cpu_to_le32(rp[0]);
590 ra[1] = cpu_to_le32(rp[1]);
591 if (!memcmp(buf, (uint8_t *)ra, 6)) {
592 DBGOUT(RXFILTER,
593 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
594 (int)(rp - s->mac_reg - RA)/2,
595 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
596 return 1;
597 }
598 }
599 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
600 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
601
602 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
603 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
604 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
605 return 1;
606 DBGOUT(RXFILTER,
607 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
608 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
609 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
610 s->mac_reg[MTA + (f >> 5)]);
611
612 return 0;
613 }
614
615 static void
616 e1000_set_link_status(VLANClientState *nc)
617 {
618 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
619 uint32_t old_status = s->mac_reg[STATUS];
620
621 if (nc->link_down) {
622 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
623 s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
624 } else {
625 s->mac_reg[STATUS] |= E1000_STATUS_LU;
626 s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
627 }
628
629 if (s->mac_reg[STATUS] != old_status)
630 set_ics(s, 0, E1000_ICR_LSC);
631 }
632
633 static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
634 {
635 int bufs;
636 /* Fast-path short packets */
637 if (total_size <= s->rxbuf_size) {
638 return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
639 }
640 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
641 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
642 } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) {
643 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
644 s->mac_reg[RDT] - s->mac_reg[RDH];
645 } else {
646 return false;
647 }
648 return total_size <= bufs * s->rxbuf_size;
649 }
650
651 static int
652 e1000_can_receive(VLANClientState *nc)
653 {
654 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
655
656 return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
657 }
658
659 static uint64_t rx_desc_base(E1000State *s)
660 {
661 uint64_t bah = s->mac_reg[RDBAH];
662 uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
663
664 return (bah << 32) + bal;
665 }
666
667 static ssize_t
668 e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
669 {
670 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
671 struct e1000_rx_desc desc;
672 dma_addr_t base;
673 unsigned int n, rdt;
674 uint32_t rdh_start;
675 uint16_t vlan_special = 0;
676 uint8_t vlan_status = 0, vlan_offset = 0;
677 uint8_t min_buf[MIN_BUF_SIZE];
678 size_t desc_offset;
679 size_t desc_size;
680 size_t total_size;
681
682 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
683 return -1;
684
685 /* Pad to minimum Ethernet frame length */
686 if (size < sizeof(min_buf)) {
687 memcpy(min_buf, buf, size);
688 memset(&min_buf[size], 0, sizeof(min_buf) - size);
689 buf = min_buf;
690 size = sizeof(min_buf);
691 }
692
693 if (!receive_filter(s, buf, size))
694 return size;
695
696 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
697 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
698 memmove((uint8_t *)buf + 4, buf, 12);
699 vlan_status = E1000_RXD_STAT_VP;
700 vlan_offset = 4;
701 size -= 4;
702 }
703
704 rdh_start = s->mac_reg[RDH];
705 desc_offset = 0;
706 total_size = size + fcs_len(s);
707 if (!e1000_has_rxbufs(s, total_size)) {
708 set_ics(s, 0, E1000_ICS_RXO);
709 return -1;
710 }
711 do {
712 desc_size = total_size - desc_offset;
713 if (desc_size > s->rxbuf_size) {
714 desc_size = s->rxbuf_size;
715 }
716 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
717 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
718 desc.special = vlan_special;
719 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
720 if (desc.buffer_addr) {
721 if (desc_offset < size) {
722 size_t copy_size = size - desc_offset;
723 if (copy_size > s->rxbuf_size) {
724 copy_size = s->rxbuf_size;
725 }
726 pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),
727 buf + desc_offset + vlan_offset, copy_size);
728 }
729 desc_offset += desc_size;
730 desc.length = cpu_to_le16(desc_size);
731 if (desc_offset >= total_size) {
732 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
733 } else {
734 /* Guest zeroing out status is not a hardware requirement.
735 Clear EOP in case guest didn't do it. */
736 desc.status &= ~E1000_RXD_STAT_EOP;
737 }
738 } else { // as per intel docs; skip descriptors with null buf addr
739 DBGOUT(RX, "Null RX descriptor!!\n");
740 }
741 pci_dma_write(&s->dev, base, &desc, sizeof(desc));
742
743 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
744 s->mac_reg[RDH] = 0;
745 s->check_rxov = 1;
746 /* see comment in start_xmit; same here */
747 if (s->mac_reg[RDH] == rdh_start) {
748 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
749 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
750 set_ics(s, 0, E1000_ICS_RXO);
751 return -1;
752 }
753 } while (desc_offset < total_size);
754
755 s->mac_reg[GPRC]++;
756 s->mac_reg[TPR]++;
757 /* TOR - Total Octets Received:
758 * This register includes bytes received in a packet from the <Destination
759 * Address> field through the <CRC> field, inclusively.
760 */
761 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
762 if (n < s->mac_reg[TORL])
763 s->mac_reg[TORH]++;
764 s->mac_reg[TORL] = n;
765
766 n = E1000_ICS_RXT0;
767 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
768 rdt += s->mac_reg[RDLEN] / sizeof(desc);
769 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
770 s->rxbuf_min_shift)
771 n |= E1000_ICS_RXDMT0;
772
773 set_ics(s, 0, n);
774
775 return size;
776 }
777
778 static uint32_t
779 mac_readreg(E1000State *s, int index)
780 {
781 return s->mac_reg[index];
782 }
783
784 static uint32_t
785 mac_icr_read(E1000State *s, int index)
786 {
787 uint32_t ret = s->mac_reg[ICR];
788
789 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
790 set_interrupt_cause(s, 0, 0);
791 return ret;
792 }
793
794 static uint32_t
795 mac_read_clr4(E1000State *s, int index)
796 {
797 uint32_t ret = s->mac_reg[index];
798
799 s->mac_reg[index] = 0;
800 return ret;
801 }
802
803 static uint32_t
804 mac_read_clr8(E1000State *s, int index)
805 {
806 uint32_t ret = s->mac_reg[index];
807
808 s->mac_reg[index] = 0;
809 s->mac_reg[index-1] = 0;
810 return ret;
811 }
812
813 static void
814 mac_writereg(E1000State *s, int index, uint32_t val)
815 {
816 s->mac_reg[index] = val;
817 }
818
819 static void
820 set_rdt(E1000State *s, int index, uint32_t val)
821 {
822 s->check_rxov = 0;
823 s->mac_reg[index] = val & 0xffff;
824 }
825
826 static void
827 set_16bit(E1000State *s, int index, uint32_t val)
828 {
829 s->mac_reg[index] = val & 0xffff;
830 }
831
832 static void
833 set_dlen(E1000State *s, int index, uint32_t val)
834 {
835 s->mac_reg[index] = val & 0xfff80;
836 }
837
838 static void
839 set_tctl(E1000State *s, int index, uint32_t val)
840 {
841 s->mac_reg[index] = val;
842 s->mac_reg[TDT] &= 0xffff;
843 start_xmit(s);
844 }
845
846 static void
847 set_icr(E1000State *s, int index, uint32_t val)
848 {
849 DBGOUT(INTERRUPT, "set_icr %x\n", val);
850 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
851 }
852
853 static void
854 set_imc(E1000State *s, int index, uint32_t val)
855 {
856 s->mac_reg[IMS] &= ~val;
857 set_ics(s, 0, 0);
858 }
859
860 static void
861 set_ims(E1000State *s, int index, uint32_t val)
862 {
863 s->mac_reg[IMS] |= val;
864 set_ics(s, 0, 0);
865 }
866
867 #define getreg(x) [x] = mac_readreg
868 static uint32_t (*macreg_readops[])(E1000State *, int) = {
869 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
870 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
871 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
872 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
873 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
874 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
875 getreg(TDLEN), getreg(RDLEN),
876
877 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
878 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
879 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
880 [CRCERRS ... MPC] = &mac_readreg,
881 [RA ... RA+31] = &mac_readreg,
882 [MTA ... MTA+127] = &mac_readreg,
883 [VFTA ... VFTA+127] = &mac_readreg,
884 };
885 enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
886
887 #define putreg(x) [x] = mac_writereg
888 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
889 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
890 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
891 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
892 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
893 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
894 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
895 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
896 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
897 [RA ... RA+31] = &mac_writereg,
898 [MTA ... MTA+127] = &mac_writereg,
899 [VFTA ... VFTA+127] = &mac_writereg,
900 };
901 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
902
903 static void
904 e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
905 unsigned size)
906 {
907 E1000State *s = opaque;
908 unsigned int index = (addr & 0x1ffff) >> 2;
909
910 if (index < NWRITEOPS && macreg_writeops[index]) {
911 macreg_writeops[index](s, index, val);
912 } else if (index < NREADOPS && macreg_readops[index]) {
913 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
914 } else {
915 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
916 index<<2, val);
917 }
918 }
919
920 static uint64_t
921 e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
922 {
923 E1000State *s = opaque;
924 unsigned int index = (addr & 0x1ffff) >> 2;
925
926 if (index < NREADOPS && macreg_readops[index])
927 {
928 return macreg_readops[index](s, index);
929 }
930 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
931 return 0;
932 }
933
934 static const MemoryRegionOps e1000_mmio_ops = {
935 .read = e1000_mmio_read,
936 .write = e1000_mmio_write,
937 .endianness = DEVICE_LITTLE_ENDIAN,
938 .impl = {
939 .min_access_size = 4,
940 .max_access_size = 4,
941 },
942 };
943
944 static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
945 unsigned size)
946 {
947 E1000State *s = opaque;
948
949 (void)s;
950 return 0;
951 }
952
953 static void e1000_io_write(void *opaque, target_phys_addr_t addr,
954 uint64_t val, unsigned size)
955 {
956 E1000State *s = opaque;
957
958 (void)s;
959 }
960
961 static const MemoryRegionOps e1000_io_ops = {
962 .read = e1000_io_read,
963 .write = e1000_io_write,
964 .endianness = DEVICE_LITTLE_ENDIAN,
965 };
966
967 static bool is_version_1(void *opaque, int version_id)
968 {
969 return version_id == 1;
970 }
971
972 static const VMStateDescription vmstate_e1000 = {
973 .name = "e1000",
974 .version_id = 2,
975 .minimum_version_id = 1,
976 .minimum_version_id_old = 1,
977 .fields = (VMStateField []) {
978 VMSTATE_PCI_DEVICE(dev, E1000State),
979 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
980 VMSTATE_UNUSED(4), /* Was mmio_base. */
981 VMSTATE_UINT32(rxbuf_size, E1000State),
982 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
983 VMSTATE_UINT32(eecd_state.val_in, E1000State),
984 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
985 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
986 VMSTATE_UINT16(eecd_state.reading, E1000State),
987 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
988 VMSTATE_UINT8(tx.ipcss, E1000State),
989 VMSTATE_UINT8(tx.ipcso, E1000State),
990 VMSTATE_UINT16(tx.ipcse, E1000State),
991 VMSTATE_UINT8(tx.tucss, E1000State),
992 VMSTATE_UINT8(tx.tucso, E1000State),
993 VMSTATE_UINT16(tx.tucse, E1000State),
994 VMSTATE_UINT32(tx.paylen, E1000State),
995 VMSTATE_UINT8(tx.hdr_len, E1000State),
996 VMSTATE_UINT16(tx.mss, E1000State),
997 VMSTATE_UINT16(tx.size, E1000State),
998 VMSTATE_UINT16(tx.tso_frames, E1000State),
999 VMSTATE_UINT8(tx.sum_needed, E1000State),
1000 VMSTATE_INT8(tx.ip, E1000State),
1001 VMSTATE_INT8(tx.tcp, E1000State),
1002 VMSTATE_BUFFER(tx.header, E1000State),
1003 VMSTATE_BUFFER(tx.data, E1000State),
1004 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
1005 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1006 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1007 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1008 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1009 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1010 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1011 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1012 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1013 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1014 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1015 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1016 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1017 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1018 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1019 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1020 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1021 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1022 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1023 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1024 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1025 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1026 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1027 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1028 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1029 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1030 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1031 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1032 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1033 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1034 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1035 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1036 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1037 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1038 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1039 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1040 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1041 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1042 VMSTATE_UINT32(mac_reg[VET], E1000State),
1043 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1044 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1045 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1046 VMSTATE_END_OF_LIST()
1047 }
1048 };
1049
1050 static const uint16_t e1000_eeprom_template[64] = {
1051 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1052 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1053 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1054 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1055 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1056 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1057 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1058 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1059 };
1060
1061 static const uint16_t phy_reg_init[] = {
1062 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
1063 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
1064 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
1065 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
1066 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
1067 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
1068 };
1069
1070 static const uint32_t mac_reg_init[] = {
1071 [PBA] = 0x00100030,
1072 [LEDCTL] = 0x602,
1073 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
1074 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
1075 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
1076 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
1077 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
1078 E1000_STATUS_LU,
1079 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1080 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1081 E1000_MANC_RMCP_EN,
1082 };
1083
1084 /* PCI interface */
1085
1086 static void
1087 e1000_mmio_setup(E1000State *d)
1088 {
1089 int i;
1090 const uint32_t excluded_regs[] = {
1091 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1092 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1093 };
1094
1095 memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
1096 PNPMMIO_SIZE);
1097 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
1098 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1099 memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
1100 excluded_regs[i+1] - excluded_regs[i] - 4);
1101 memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
1102 }
1103
1104 static void
1105 e1000_cleanup(VLANClientState *nc)
1106 {
1107 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1108
1109 s->nic = NULL;
1110 }
1111
1112 static int
1113 pci_e1000_uninit(PCIDevice *dev)
1114 {
1115 E1000State *d = DO_UPCAST(E1000State, dev, dev);
1116
1117 memory_region_destroy(&d->mmio);
1118 memory_region_destroy(&d->io);
1119 qemu_del_vlan_client(&d->nic->nc);
1120 return 0;
1121 }
1122
1123 static void e1000_reset(void *opaque)
1124 {
1125 E1000State *d = opaque;
1126
1127 memset(d->phy_reg, 0, sizeof d->phy_reg);
1128 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1129 memset(d->mac_reg, 0, sizeof d->mac_reg);
1130 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1131 d->rxbuf_min_shift = 1;
1132 memset(&d->tx, 0, sizeof d->tx);
1133 }
1134
1135 static NetClientInfo net_e1000_info = {
1136 .type = NET_CLIENT_TYPE_NIC,
1137 .size = sizeof(NICState),
1138 .can_receive = e1000_can_receive,
1139 .receive = e1000_receive,
1140 .cleanup = e1000_cleanup,
1141 .link_status_changed = e1000_set_link_status,
1142 };
1143
1144 static int pci_e1000_init(PCIDevice *pci_dev)
1145 {
1146 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1147 uint8_t *pci_conf;
1148 uint16_t checksum = 0;
1149 int i;
1150 uint8_t *macaddr;
1151
1152 pci_conf = d->dev.config;
1153
1154 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1155 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
1156
1157 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
1158
1159 e1000_mmio_setup(d);
1160
1161 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
1162
1163 pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
1164
1165 memmove(d->eeprom_data, e1000_eeprom_template,
1166 sizeof e1000_eeprom_template);
1167 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1168 macaddr = d->conf.macaddr.a;
1169 for (i = 0; i < 3; i++)
1170 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
1171 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1172 checksum += d->eeprom_data[i];
1173 checksum = (uint16_t) EEPROM_SUM - checksum;
1174 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1175
1176 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1177 d->dev.qdev.info->name, d->dev.qdev.id, d);
1178
1179 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1180
1181 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1182
1183 return 0;
1184 }
1185
1186 static void qdev_e1000_reset(DeviceState *dev)
1187 {
1188 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1189 e1000_reset(d);
1190 }
1191
1192 static PCIDeviceInfo e1000_info = {
1193 .qdev.name = "e1000",
1194 .qdev.desc = "Intel Gigabit Ethernet",
1195 .qdev.size = sizeof(E1000State),
1196 .qdev.reset = qdev_e1000_reset,
1197 .qdev.vmsd = &vmstate_e1000,
1198 .init = pci_e1000_init,
1199 .exit = pci_e1000_uninit,
1200 .romfile = "pxe-e1000.rom",
1201 .vendor_id = PCI_VENDOR_ID_INTEL,
1202 .device_id = E1000_DEVID,
1203 .revision = 0x03,
1204 .class_id = PCI_CLASS_NETWORK_ETHERNET,
1205 .qdev.props = (Property[]) {
1206 DEFINE_NIC_PROPERTIES(E1000State, conf),
1207 DEFINE_PROP_END_OF_LIST(),
1208 }
1209 };
1210
1211 static void e1000_register_devices(void)
1212 {
1213 pci_qdev_register(&e1000_info);
1214 }
1215
1216 device_init(e1000_register_devices)
CRIS target port of Qemu