hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "qemu/osdep.h"
  31 #include "hw/hw.h"
  32 #include "hw/loader.h"
  33 #include "sysemu/arch_init.h"
  34 #include "hw/i2c/smbus.h"
  35 #include "hw/boards.h"
  36 #include "hw/timer/mc146818rtc.h"
  37 #include "hw/xen/xen.h"
  38 #include "sysemu/kvm.h"
  39 #include "hw/kvm/clock.h"
  40 #include "hw/pci-host/q35.h"
  41 #include "exec/address-spaces.h"
  42 #include "hw/i386/ich9.h"
  43 #include "hw/smbios/smbios.h"
  44 #include "hw/ide/pci.h"
  45 #include "hw/ide/ahci.h"
  46 #include "hw/usb.h"
  47 #include "qemu/error-report.h"
  48 #include "migration/migration.h"
  49
  50 /* ICH9 AHCI has 6 ports */
  51 #define MAX_SATA_PORTS     6
  52
  53 /* PC hardware initialisation */
  54 static void pc_q35_init(MachineState *machine)
  55 {
  56     PCMachineState *pcms = PC_MACHINE(machine);
  57     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
  58     Q35PCIHost *q35_host;
  59     PCIHostState *phb;
  60     PCIBus *host_bus;
  61     PCIDevice *lpc;
  62     BusState *idebus[MAX_SATA_PORTS];
  63     ISADevice *rtc_state;
  64     MemoryRegion *system_io = get_system_io();
  65     MemoryRegion *pci_memory;
  66     MemoryRegion *rom_memory;
  67     MemoryRegion *ram_memory;
  68     GSIState *gsi_state;
  69     ISABus *isa_bus;
  70     qemu_irq *gsi;
  71     qemu_irq *i8259;
  72     int i;
  73     ICH9LPCState *ich9_lpc;
  74     PCIDevice *ahci;
  75     ram_addr_t lowmem;
  76     DriveInfo *hd[MAX_SATA_PORTS];
  77     MachineClass *mc = MACHINE_GET_CLASS(machine);
  78
  79     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
  80      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
  81      * also known as MMCFG).
  82      * If it doesn't, we need to split it in chunks below and above 4G.
  83      * In any case, try to make sure that guest addresses aligned at
  84      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
  85      */
  86     if (machine->ram_size >= 0xb0000000) {
  87         lowmem = 0x80000000;
  88     } else {
  89         lowmem = 0xb0000000;
  90     }
  91
  92     /* Handle the machine opt max-ram-below-4g.  It is basically doing
  93      * min(qemu limit, user limit).
  94      */
  95     if (lowmem > pcms->max_ram_below_4g) {
  96         lowmem = pcms->max_ram_below_4g;
  97         if (machine->ram_size - lowmem > lowmem &&
  98             lowmem & ((1ULL << 30) - 1)) {
  99             error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
 100                          ") not a multiple of 1G; possible bad performance.",
 101                          pcms->max_ram_below_4g);
 102         }
 103     }
 104
 105     if (machine->ram_size >= lowmem) {
 106         pcms->above_4g_mem_size = machine->ram_size - lowmem;
 107         pcms->below_4g_mem_size = lowmem;
 108     } else {
 109         pcms->above_4g_mem_size = 0;
 110         pcms->below_4g_mem_size = machine->ram_size;
 111     }
 112
 113     if (xen_enabled()) {
 114         xen_hvm_init(pcms, &ram_memory);
 115     }
 116
 117     pc_cpus_init(pcms);
 118
 119     kvmclock_create();
 120
 121     /* pci enabled */
 122     if (pcmc->pci_enabled) {
 123         pci_memory = g_new(MemoryRegion, 1);
 124         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 125         rom_memory = pci_memory;
 126     } else {
 127         pci_memory = NULL;
 128         rom_memory = get_system_memory();
 129     }
 130
 131     pc_guest_info_init(pcms);
 132
 133     if (pcmc->smbios_defaults) {
 134         /* These values are guest ABI, do not change */
 135         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 136                             mc->name, pcmc->smbios_legacy_mode,
 137                             pcmc->smbios_uuid_encoded,
 138                             SMBIOS_ENTRY_POINT_21);
 139     }
 140
 141     /* allocate ram and load rom/bios */
 142     if (!xen_enabled()) {
 143         pc_memory_init(pcms, get_system_memory(),
 144                        rom_memory, &ram_memory);
 145     }
 146
 147     /* irq lines */
 148     gsi_state = g_malloc0(sizeof(*gsi_state));
 149     if (kvm_irqchip_in_kernel()) {
 150         kvm_pc_setup_irq_routing(pcmc->pci_enabled);
 151         gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 152                                  GSI_NUM_PINS);
 153     } else {
 154         gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 155     }
 156
 157     /* create pci host bus */
 158     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 159
 160     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 161     q35_host->mch.ram_memory = ram_memory;
 162     q35_host->mch.pci_address_space = pci_memory;
 163     q35_host->mch.system_memory = get_system_memory();
 164     q35_host->mch.address_space_io = system_io;
 165     q35_host->mch.below_4g_mem_size = pcms->below_4g_mem_size;
 166     q35_host->mch.above_4g_mem_size = pcms->above_4g_mem_size;
 167     /* pci */
 168     qdev_init_nofail(DEVICE(q35_host));
 169     phb = PCI_HOST_BRIDGE(q35_host);
 170     host_bus = phb->bus;
 171     pcms->bus = phb->bus;
 172     /* create ISA bus */
 173     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 174                                           ICH9_LPC_FUNC), true,
 175                                           TYPE_ICH9_LPC_DEVICE);
 176
 177     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 178                              TYPE_HOTPLUG_HANDLER,
 179                              (Object **)&pcms->acpi_dev,
 180                              object_property_allow_set_link,
 181                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 182     object_property_set_link(OBJECT(machine), OBJECT(lpc),
 183                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 184
 185     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 186     ich9_lpc->pic = gsi;
 187     ich9_lpc->ioapic = gsi_state->ioapic_irq;
 188     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 189                  ICH9_LPC_NB_PIRQS);
 190     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 191     isa_bus = ich9_lpc->isa_bus;
 192
 193     /*end early*/
 194     isa_bus_irqs(isa_bus, gsi);
 195
 196     if (kvm_irqchip_in_kernel()) {
 197         i8259 = kvm_i8259_init(isa_bus);
 198     } else if (xen_enabled()) {
 199         i8259 = xen_interrupt_controller_init();
 200     } else {
 201         i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
 202     }
 203
 204     for (i = 0; i < ISA_NUM_IRQS; i++) {
 205         gsi_state->i8259_irq[i] = i8259[i];
 206     }
 207     if (pcmc->pci_enabled) {
 208         ioapic_init_gsi(gsi_state, "q35");
 209     }
 210
 211     pc_register_ferr_irq(gsi[13]);
 212
 213     assert(pcms->vmport != ON_OFF_AUTO__MAX);
 214     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 215         pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 216     }
 217
 218     /* init basic PC hardware */
 219     pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy,
 220                          (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104);
 221
 222     /* connect pm stuff to lpc */
 223     ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms));
 224
 225     /* ahci and SATA device, for q35 1 ahci controller is built-in */
 226     ahci = pci_create_simple_multifunction(host_bus,
 227                                            PCI_DEVFN(ICH9_SATA1_DEV,
 228                                                      ICH9_SATA1_FUNC),
 229                                            true, "ich9-ahci");
 230     idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 231     idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 232     g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
 233     ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
 234     ahci_ide_create_devs(ahci, hd);
 235
 236     if (usb_enabled()) {
 237         /* Should we create 6 UHCI according to ich9 spec? */
 238         ehci_create_ich9_with_companions(host_bus, 0x1d);
 239     }
 240
 241     /* TODO: Populate SPD eeprom data.  */
 242     smbus_eeprom_init(ich9_smb_init(host_bus,
 243                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 244                                     0xb100),
 245                       8, NULL, 0);
 246
 247     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 248
 249     /* the rest devices to which pci devfn is automatically assigned */
 250     pc_vga_init(isa_bus, host_bus);
 251     pc_nic_init(isa_bus, host_bus);
 252     if (pcmc->pci_enabled) {
 253         pc_pci_device_init(host_bus);
 254     }
 255
 256     if (pcms->acpi_nvdimm_state.is_enabled) {
 257         nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io,
 258                                pcms->fw_cfg, OBJECT(pcms));
 259     }
 260 }
 261
 262 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 263     static void pc_init_##suffix(MachineState *machine) \
 264     { \
 265         void (*compat)(MachineState *m) = (compatfn); \
 266         if (compat) { \
 267             compat(machine); \
 268         } \
 269         pc_q35_init(machine); \
 270     } \
 271     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 272
 273
 274 static void pc_q35_machine_options(MachineClass *m)
 275 {
 276     m->family = "pc_q35";
 277     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 278     m->hot_add_cpu = pc_hot_add_cpu;
 279     m->units_per_default_bus = 1;
 280     m->default_machine_opts = "firmware=bios-256k.bin";
 281     m->default_display = "std";
 282     m->no_floppy = 1;
 283 }
 284
 285 static void pc_q35_2_6_machine_options(MachineClass *m)
 286 {
 287     pc_q35_machine_options(m);
 288     m->alias = "q35";
 289 }
 290
 291 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 292                    pc_q35_2_6_machine_options);
 293
 294 static void pc_q35_2_5_machine_options(MachineClass *m)
 295 {
 296     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 297     pc_q35_2_6_machine_options(m);
 298     m->alias = NULL;
 299     pcmc->save_tsc_khz = false;
 300     SET_MACHINE_COMPAT(m, PC_COMPAT_2_5);
 301 }
 302
 303 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 304                    pc_q35_2_5_machine_options);
 305
 306 static void pc_q35_2_4_machine_options(MachineClass *m)
 307 {
 308     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 309     pc_q35_2_5_machine_options(m);
 310     m->hw_version = "2.4.0";
 311     pcmc->broken_reserved_end = true;
 312     SET_MACHINE_COMPAT(m, PC_COMPAT_2_4);
 313 }
 314
 315 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 316                    pc_q35_2_4_machine_options);