hw/acpi/nvdimm.c

   1 /*
   2  * NVDIMM ACPI Implementation
   3  *
   4  * Copyright(C) 2015 Intel Corporation.
   5  *
   6  * Author:
   7  *  Xiao Guangrong <guangrong.xiao@linux.intel.com>
   8  *
   9  * NFIT is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
  10  * and the DSM specification can be found at:
  11  *       http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
  12  *
  13  * Currently, it only supports PMEM Virtualization.
  14  *
  15  * This library is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU Lesser General Public
  17  * License as published by the Free Software Foundation; either
  18  * version 2 of the License, or (at your option) any later version.
  19  *
  20  * This library is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  23  * Lesser General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU Lesser General Public
  26  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  27  */
  28
  29 #include "qemu/osdep.h"
  30 #include "hw/acpi/acpi.h"
  31 #include "hw/acpi/aml-build.h"
  32 #include "hw/nvram/fw_cfg.h"
  33 #include "hw/mem/nvdimm.h"
  34
  35 static int nvdimm_plugged_device_list(Object *obj, void *opaque)
  36 {
  37     GSList **list = opaque;
  38
  39     if (object_dynamic_cast(obj, TYPE_NVDIMM)) {
  40         DeviceState *dev = DEVICE(obj);
  41
  42         if (dev->realized) { /* only realized NVDIMMs matter */
  43             *list = g_slist_append(*list, DEVICE(obj));
  44         }
  45     }
  46
  47     object_child_foreach(obj, nvdimm_plugged_device_list, opaque);
  48     return 0;
  49 }
  50
  51 /*
  52  * inquire plugged NVDIMM devices and link them into the list which is
  53  * returned to the caller.
  54  *
  55  * Note: it is the caller's responsibility to free the list to avoid
  56  * memory leak.
  57  */
  58 static GSList *nvdimm_get_plugged_device_list(void)
  59 {
  60     GSList *list = NULL;
  61
  62     object_child_foreach(qdev_get_machine(), nvdimm_plugged_device_list,
  63                          &list);
  64     return list;
  65 }
  66
  67 #define NVDIMM_UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7)             \
  68    { (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
  69      (b) & 0xff, ((b) >> 8) & 0xff, (c) & 0xff, ((c) >> 8) & 0xff,          \
  70      (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }
  71
  72 /*
  73  * define Byte Addressable Persistent Memory (PM) Region according to
  74  * ACPI 6.0: 5.2.25.1 System Physical Address Range Structure.
  75  */
  76 static const uint8_t nvdimm_nfit_spa_uuid[] =
  77       NVDIMM_UUID_LE(0x66f0d379, 0xb4f3, 0x4074, 0xac, 0x43, 0x0d, 0x33,
  78                      0x18, 0xb7, 0x8c, 0xdb);
  79
  80 /*
  81  * NVDIMM Firmware Interface Table
  82  * @signature: "NFIT"
  83  *
  84  * It provides information that allows OSPM to enumerate NVDIMM present in
  85  * the platform and associate system physical address ranges created by the
  86  * NVDIMMs.
  87  *
  88  * It is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
  89  */
  90 struct NvdimmNfitHeader {
  91     ACPI_TABLE_HEADER_DEF
  92     uint32_t reserved;
  93 } QEMU_PACKED;
  94 typedef struct NvdimmNfitHeader NvdimmNfitHeader;
  95
  96 /*
  97  * define NFIT structures according to ACPI 6.0: 5.2.25 NVDIMM Firmware
  98  * Interface Table (NFIT).
  99  */
 100
 101 /*
 102  * System Physical Address Range Structure
 103  *
 104  * It describes the system physical address ranges occupied by NVDIMMs and
 105  * the types of the regions.
 106  */
 107 struct NvdimmNfitSpa {
 108     uint16_t type;
 109     uint16_t length;
 110     uint16_t spa_index;
 111     uint16_t flags;
 112     uint32_t reserved;
 113     uint32_t proximity_domain;
 114     uint8_t type_guid[16];
 115     uint64_t spa_base;
 116     uint64_t spa_length;
 117     uint64_t mem_attr;
 118 } QEMU_PACKED;
 119 typedef struct NvdimmNfitSpa NvdimmNfitSpa;
 120
 121 /*
 122  * Memory Device to System Physical Address Range Mapping Structure
 123  *
 124  * It enables identifying each NVDIMM region and the corresponding SPA
 125  * describing the memory interleave
 126  */
 127 struct NvdimmNfitMemDev {
 128     uint16_t type;
 129     uint16_t length;
 130     uint32_t nfit_handle;
 131     uint16_t phys_id;
 132     uint16_t region_id;
 133     uint16_t spa_index;
 134     uint16_t dcr_index;
 135     uint64_t region_len;
 136     uint64_t region_offset;
 137     uint64_t region_dpa;
 138     uint16_t interleave_index;
 139     uint16_t interleave_ways;
 140     uint16_t flags;
 141     uint16_t reserved;
 142 } QEMU_PACKED;
 143 typedef struct NvdimmNfitMemDev NvdimmNfitMemDev;
 144
 145 /*
 146  * NVDIMM Control Region Structure
 147  *
 148  * It describes the NVDIMM and if applicable, Block Control Window.
 149  */
 150 struct NvdimmNfitControlRegion {
 151     uint16_t type;
 152     uint16_t length;
 153     uint16_t dcr_index;
 154     uint16_t vendor_id;
 155     uint16_t device_id;
 156     uint16_t revision_id;
 157     uint16_t sub_vendor_id;
 158     uint16_t sub_device_id;
 159     uint16_t sub_revision_id;
 160     uint8_t reserved[6];
 161     uint32_t serial_number;
 162     uint16_t fic;
 163     uint16_t num_bcw;
 164     uint64_t bcw_size;
 165     uint64_t cmd_offset;
 166     uint64_t cmd_size;
 167     uint64_t status_offset;
 168     uint64_t status_size;
 169     uint16_t flags;
 170     uint8_t reserved2[6];
 171 } QEMU_PACKED;
 172 typedef struct NvdimmNfitControlRegion NvdimmNfitControlRegion;
 173
 174 /*
 175  * Module serial number is a unique number for each device. We use the
 176  * slot id of NVDIMM device to generate this number so that each device
 177  * associates with a different number.
 178  *
 179  * 0x123456 is a magic number we arbitrarily chose.
 180  */
 181 static uint32_t nvdimm_slot_to_sn(int slot)
 182 {
 183     return 0x123456 + slot;
 184 }
 185
 186 /*
 187  * handle is used to uniquely associate nfit_memdev structure with NVDIMM
 188  * ACPI device - nfit_memdev.nfit_handle matches with the value returned
 189  * by ACPI device _ADR method.
 190  *
 191  * We generate the handle with the slot id of NVDIMM device and reserve
 192  * 0 for NVDIMM root device.
 193  */
 194 static uint32_t nvdimm_slot_to_handle(int slot)
 195 {
 196     return slot + 1;
 197 }
 198
 199 /*
 200  * index uniquely identifies the structure, 0 is reserved which indicates
 201  * that the structure is not valid or the associated structure is not
 202  * present.
 203  *
 204  * Each NVDIMM device needs two indexes, one for nfit_spa and another for
 205  * nfit_dc which are generated by the slot id of NVDIMM device.
 206  */
 207 static uint16_t nvdimm_slot_to_spa_index(int slot)
 208 {
 209     return (slot + 1) << 1;
 210 }
 211
 212 /* See the comments of nvdimm_slot_to_spa_index(). */
 213 static uint32_t nvdimm_slot_to_dcr_index(int slot)
 214 {
 215     return nvdimm_slot_to_spa_index(slot) + 1;
 216 }
 217
 218 /* ACPI 6.0: 5.2.25.1 System Physical Address Range Structure */
 219 static void
 220 nvdimm_build_structure_spa(GArray *structures, DeviceState *dev)
 221 {
 222     NvdimmNfitSpa *nfit_spa;
 223     uint64_t addr = object_property_get_int(OBJECT(dev), PC_DIMM_ADDR_PROP,
 224                                             NULL);
 225     uint64_t size = object_property_get_int(OBJECT(dev), PC_DIMM_SIZE_PROP,
 226                                             NULL);
 227     uint32_t node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP,
 228                                             NULL);
 229     int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
 230                                             NULL);
 231
 232     nfit_spa = acpi_data_push(structures, sizeof(*nfit_spa));
 233
 234     nfit_spa->type = cpu_to_le16(0 /* System Physical Address Range
 235                                       Structure */);
 236     nfit_spa->length = cpu_to_le16(sizeof(*nfit_spa));
 237     nfit_spa->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
 238
 239     /*
 240      * Control region is strict as all the device info, such as SN, index,
 241      * is associated with slot id.
 242      */
 243     nfit_spa->flags = cpu_to_le16(1 /* Control region is strictly for
 244                                        management during hot add/online
 245                                        operation */ |
 246                                   2 /* Data in Proximity Domain field is
 247                                        valid*/);
 248
 249     /* NUMA node. */
 250     nfit_spa->proximity_domain = cpu_to_le32(node);
 251     /* the region reported as PMEM. */
 252     memcpy(nfit_spa->type_guid, nvdimm_nfit_spa_uuid,
 253            sizeof(nvdimm_nfit_spa_uuid));
 254
 255     nfit_spa->spa_base = cpu_to_le64(addr);
 256     nfit_spa->spa_length = cpu_to_le64(size);
 257
 258     /* It is the PMEM and can be cached as writeback. */
 259     nfit_spa->mem_attr = cpu_to_le64(0x8ULL /* EFI_MEMORY_WB */ |
 260                                      0x8000ULL /* EFI_MEMORY_NV */);
 261 }
 262
 263 /*
 264  * ACPI 6.0: 5.2.25.2 Memory Device to System Physical Address Range Mapping
 265  * Structure
 266  */
 267 static void
 268 nvdimm_build_structure_memdev(GArray *structures, DeviceState *dev)
 269 {
 270     NvdimmNfitMemDev *nfit_memdev;
 271     uint64_t addr = object_property_get_int(OBJECT(dev), PC_DIMM_ADDR_PROP,
 272                                             NULL);
 273     uint64_t size = object_property_get_int(OBJECT(dev), PC_DIMM_SIZE_PROP,
 274                                             NULL);
 275     int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
 276                                             NULL);
 277     uint32_t handle = nvdimm_slot_to_handle(slot);
 278
 279     nfit_memdev = acpi_data_push(structures, sizeof(*nfit_memdev));
 280
 281     nfit_memdev->type = cpu_to_le16(1 /* Memory Device to System Address
 282                                          Range Map Structure*/);
 283     nfit_memdev->length = cpu_to_le16(sizeof(*nfit_memdev));
 284     nfit_memdev->nfit_handle = cpu_to_le32(handle);
 285
 286     /*
 287      * associate memory device with System Physical Address Range
 288      * Structure.
 289      */
 290     nfit_memdev->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
 291     /* associate memory device with Control Region Structure. */
 292     nfit_memdev->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
 293
 294     /* The memory region on the device. */
 295     nfit_memdev->region_len = cpu_to_le64(size);
 296     nfit_memdev->region_dpa = cpu_to_le64(addr);
 297
 298     /* Only one interleave for PMEM. */
 299     nfit_memdev->interleave_ways = cpu_to_le16(1);
 300 }
 301
 302 /*
 303  * ACPI 6.0: 5.2.25.5 NVDIMM Control Region Structure.
 304  */
 305 static void nvdimm_build_structure_dcr(GArray *structures, DeviceState *dev)
 306 {
 307     NvdimmNfitControlRegion *nfit_dcr;
 308     int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
 309                                        NULL);
 310     uint32_t sn = nvdimm_slot_to_sn(slot);
 311
 312     nfit_dcr = acpi_data_push(structures, sizeof(*nfit_dcr));
 313
 314     nfit_dcr->type = cpu_to_le16(4 /* NVDIMM Control Region Structure */);
 315     nfit_dcr->length = cpu_to_le16(sizeof(*nfit_dcr));
 316     nfit_dcr->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
 317
 318     /* vendor: Intel. */
 319     nfit_dcr->vendor_id = cpu_to_le16(0x8086);
 320     nfit_dcr->device_id = cpu_to_le16(1);
 321
 322     /* The _DSM method is following Intel's DSM specification. */
 323     nfit_dcr->revision_id = cpu_to_le16(1 /* Current Revision supported
 324                                              in ACPI 6.0 is 1. */);
 325     nfit_dcr->serial_number = cpu_to_le32(sn);
 326     nfit_dcr->fic = cpu_to_le16(0x201 /* Format Interface Code. See Chapter
 327                                          2: NVDIMM Device Specific Method
 328                                          (DSM) in DSM Spec Rev1.*/);
 329 }
 330
 331 static GArray *nvdimm_build_device_structure(GSList *device_list)
 332 {
 333     GArray *structures = g_array_new(false, true /* clear */, 1);
 334
 335     for (; device_list; device_list = device_list->next) {
 336         DeviceState *dev = device_list->data;
 337
 338         /* build System Physical Address Range Structure. */
 339         nvdimm_build_structure_spa(structures, dev);
 340
 341         /*
 342          * build Memory Device to System Physical Address Range Mapping
 343          * Structure.
 344          */
 345         nvdimm_build_structure_memdev(structures, dev);
 346
 347         /* build NVDIMM Control Region Structure. */
 348         nvdimm_build_structure_dcr(structures, dev);
 349     }
 350
 351     return structures;
 352 }
 353
 354 static void nvdimm_build_nfit(GSList *device_list, GArray *table_offsets,
 355                               GArray *table_data, GArray *linker)
 356 {
 357     GArray *structures = nvdimm_build_device_structure(device_list);
 358     unsigned int header;
 359
 360     acpi_add_table(table_offsets, table_data);
 361
 362     /* NFIT header. */
 363     header = table_data->len;
 364     acpi_data_push(table_data, sizeof(NvdimmNfitHeader));
 365     /* NVDIMM device structures. */
 366     g_array_append_vals(table_data, structures->data, structures->len);
 367
 368     build_header(linker, table_data,
 369                  (void *)(table_data->data + header), "NFIT",
 370                  sizeof(NvdimmNfitHeader) + structures->len, 1, NULL, NULL);
 371     g_array_free(structures, true);
 372 }
 373
 374 static uint64_t
 375 nvdimm_dsm_read(void *opaque, hwaddr addr, unsigned size)
 376 {
 377     return 0;
 378 }
 379
 380 static void
 381 nvdimm_dsm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
 382 {
 383 }
 384
 385 static const MemoryRegionOps nvdimm_dsm_ops = {
 386     .read = nvdimm_dsm_read,
 387     .write = nvdimm_dsm_write,
 388     .endianness = DEVICE_LITTLE_ENDIAN,
 389     .valid = {
 390         .min_access_size = 4,
 391         .max_access_size = 4,
 392     },
 393 };
 394
 395 void nvdimm_init_acpi_state(AcpiNVDIMMState *state, MemoryRegion *io,
 396                             FWCfgState *fw_cfg, Object *owner)
 397 {
 398     memory_region_init_io(&state->io_mr, owner, &nvdimm_dsm_ops, state,
 399                           "nvdimm-acpi-io", NVDIMM_ACPI_IO_LEN);
 400     memory_region_add_subregion(io, NVDIMM_ACPI_IO_BASE, &state->io_mr);
 401
 402     state->dsm_mem = g_array_new(false, true /* clear */, 1);
 403     acpi_data_push(state->dsm_mem, TARGET_PAGE_SIZE);
 404     fw_cfg_add_file(fw_cfg, NVDIMM_DSM_MEM_FILE, state->dsm_mem->data,
 405                     state->dsm_mem->len);
 406 }
 407
 408 #define NVDIMM_COMMON_DSM      "NCAL"
 409
 410 static void nvdimm_build_common_dsm(Aml *dev)
 411 {
 412     Aml *method, *ifctx, *function;
 413     uint8_t byte_list[1];
 414
 415     method = aml_method(NVDIMM_COMMON_DSM, 4, AML_NOTSERIALIZED);
 416     function = aml_arg(2);
 417
 418     /*
 419      * function 0 is called to inquire what functions are supported by
 420      * OSPM
 421      */
 422     ifctx = aml_if(aml_equal(function, aml_int(0)));
 423     byte_list[0] = 0 /* No function Supported */;
 424     aml_append(ifctx, aml_return(aml_buffer(1, byte_list)));
 425     aml_append(method, ifctx);
 426
 427     /* No function is supported yet. */
 428     byte_list[0] = 1 /* Not Supported */;
 429     aml_append(method, aml_return(aml_buffer(1, byte_list)));
 430
 431     aml_append(dev, method);
 432 }
 433
 434 static void nvdimm_build_device_dsm(Aml *dev)
 435 {
 436     Aml *method;
 437
 438     method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
 439     aml_append(method, aml_return(aml_call4(NVDIMM_COMMON_DSM, aml_arg(0),
 440                                   aml_arg(1), aml_arg(2), aml_arg(3))));
 441     aml_append(dev, method);
 442 }
 443
 444 static void nvdimm_build_nvdimm_devices(GSList *device_list, Aml *root_dev)
 445 {
 446     for (; device_list; device_list = device_list->next) {
 447         DeviceState *dev = device_list->data;
 448         int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
 449                                            NULL);
 450         uint32_t handle = nvdimm_slot_to_handle(slot);
 451         Aml *nvdimm_dev;
 452
 453         nvdimm_dev = aml_device("NV%02X", slot);
 454
 455         /*
 456          * ACPI 6.0: 9.20 NVDIMM Devices:
 457          *
 458          * _ADR object that is used to supply OSPM with unique address
 459          * of the NVDIMM device. This is done by returning the NFIT Device
 460          * handle that is used to identify the associated entries in ACPI
 461          * table NFIT or _FIT.
 462          */
 463         aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle)));
 464
 465         nvdimm_build_device_dsm(nvdimm_dev);
 466         aml_append(root_dev, nvdimm_dev);
 467     }
 468 }
 469
 470 static void nvdimm_build_ssdt(GSList *device_list, GArray *table_offsets,
 471                               GArray *table_data, GArray *linker)
 472 {
 473     Aml *ssdt, *sb_scope, *dev;
 474
 475     acpi_add_table(table_offsets, table_data);
 476
 477     ssdt = init_aml_allocator();
 478     acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
 479
 480     sb_scope = aml_scope("\\_SB");
 481
 482     dev = aml_device("NVDR");
 483
 484     /*
 485      * ACPI 6.0: 9.20 NVDIMM Devices:
 486      *
 487      * The ACPI Name Space device uses _HID of ACPI0012 to identify the root
 488      * NVDIMM interface device. Platform firmware is required to contain one
 489      * such device in _SB scope if NVDIMMs support is exposed by platform to
 490      * OSPM.
 491      * For each NVDIMM present or intended to be supported by platform,
 492      * platform firmware also exposes an ACPI Namespace Device under the
 493      * root device.
 494      */
 495     aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012")));
 496
 497     nvdimm_build_common_dsm(dev);
 498     nvdimm_build_device_dsm(dev);
 499
 500     nvdimm_build_nvdimm_devices(device_list, dev);
 501
 502     aml_append(sb_scope, dev);
 503
 504     aml_append(ssdt, sb_scope);
 505     /* copy AML table into ACPI tables blob and patch header there */
 506     g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
 507     build_header(linker, table_data,
 508         (void *)(table_data->data + table_data->len - ssdt->buf->len),
 509         "SSDT", ssdt->buf->len, 1, NULL, "NVDIMM");
 510     free_aml_allocator();
 511 }
 512
 513 void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
 514                        GArray *linker)
 515 {
 516     GSList *device_list;
 517
 518     /* no NVDIMM device is plugged. */
 519     device_list = nvdimm_get_plugged_device_list();
 520     if (!device_list) {
 521         return;
 522     }
 523     nvdimm_build_nfit(device_list, table_offsets, table_data, linker);
 524     nvdimm_build_ssdt(device_list, table_offsets, table_data, linker);
 525     g_slist_free(device_list);
 526 }