We want the argument pass to set_irq to be opaque
[qemu/cris-port.git] / hw / isa.h
blobd98acd5bc47f39b3adc64b0cf62443c5c4543be7
1 #ifndef HW_ISA_H
2 #define HW_ISA_H
4 /* ISA bus */
6 #include "ioport.h"
7 #include "qdev.h"
9 typedef struct ISABus ISABus;
10 typedef struct ISADevice ISADevice;
11 typedef struct ISADeviceInfo ISADeviceInfo;
13 struct ISADevice {
14 DeviceState qdev;
15 uint32_t iobase[2];
16 uint32_t isairq[2];
17 qemu_irq *irqs[2];
18 int nirqs;
21 typedef int (*isa_qdev_initfn)(ISADevice *dev);
22 struct ISADeviceInfo {
23 DeviceInfo qdev;
24 isa_qdev_initfn init;
27 ISABus *isa_bus_new(DeviceState *dev);
28 void isa_bus_irqs(qemu_irq *irqs);
29 void isa_connect_irq(ISADevice *dev, int devirq, int isairq);
30 qemu_irq isa_reserve_irq(int isairq);
31 void isa_init_irq(ISADevice *dev, qemu_irq *p);
32 void isa_qdev_register(ISADeviceInfo *info);
33 ISADevice *isa_create_simple(const char *name, uint32_t iobase, uint32_t iobase2,
34 uint32_t irq, uint32_t irq2);
36 extern target_phys_addr_t isa_mem_base;
38 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
40 /* dma.c */
41 int DMA_get_channel_mode (int nchan);
42 int DMA_read_memory (int nchan, void *buf, int pos, int size);
43 int DMA_write_memory (int nchan, void *buf, int pos, int size);
44 void DMA_hold_DREQ (int nchan);
45 void DMA_release_DREQ (int nchan);
46 void DMA_schedule(int nchan);
47 void DMA_init (int high_page_enable);
48 void DMA_register_channel (int nchan,
49 DMA_transfer_handler transfer_handler,
50 void *opaque);
51 #endif