2 * QEMU VMWARE VMXNET3 paravirtual NIC
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
18 #include "qemu/osdep.h"
20 #include "hw/pci/pci.h"
23 #include "net/checksum.h"
24 #include "sysemu/sysemu.h"
25 #include "qemu-common.h"
26 #include "qemu/bswap.h"
27 #include "hw/pci/msix.h"
28 #include "hw/pci/msi.h"
31 #include "vmxnet_debug.h"
32 #include "vmware_utils.h"
33 #include "vmxnet_tx_pkt.h"
34 #include "vmxnet_rx_pkt.h"
36 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
37 #define VMXNET3_MSIX_BAR_SIZE 0x2000
38 #define MIN_BUF_SIZE 60
40 /* Compatability flags for migration */
41 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
42 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
43 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
44 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
45 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
46 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
48 #define VMXNET3_EXP_EP_OFFSET (0x48)
49 #define VMXNET3_MSI_OFFSET(s) \
50 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
51 #define VMXNET3_MSIX_OFFSET(s) \
52 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
53 #define VMXNET3_DSN_OFFSET (0x100)
55 #define VMXNET3_BAR0_IDX (0)
56 #define VMXNET3_BAR1_IDX (1)
57 #define VMXNET3_MSIX_BAR_IDX (2)
59 #define VMXNET3_OFF_MSIX_TABLE (0x000)
60 #define VMXNET3_OFF_MSIX_PBA(s) \
61 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
63 /* Link speed in Mbps should be shifted by 16 */
64 #define VMXNET3_LINK_SPEED (1000 << 16)
66 /* Link status: 1 - up, 0 - down. */
67 #define VMXNET3_LINK_STATUS_UP 0x1
69 /* Least significant bit should be set for revision and version */
70 #define VMXNET3_UPT_REVISION 0x1
71 #define VMXNET3_DEVICE_REVISION 0x1
73 /* Number of interrupt vectors for non-MSIx modes */
74 #define VMXNET3_MAX_NMSIX_INTRS (1)
76 /* Macros for rings descriptors access */
77 #define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \
78 (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
80 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \
81 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
83 #define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \
84 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
86 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \
87 (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
89 #define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \
90 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
92 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \
93 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
95 #define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \
96 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
98 #define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \
99 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
101 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \
102 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
104 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \
105 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
107 /* Macros for guest driver shared area access */
108 #define VMXNET3_READ_DRV_SHARED64(shpa, field) \
109 (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
111 #define VMXNET3_READ_DRV_SHARED32(shpa, field) \
112 (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
114 #define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \
115 (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
117 #define VMXNET3_READ_DRV_SHARED16(shpa, field) \
118 (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
120 #define VMXNET3_READ_DRV_SHARED8(shpa, field) \
121 (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
123 #define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \
124 (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
126 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
128 typedef struct VMXNET3Class
{
129 PCIDeviceClass parent_class
;
130 DeviceRealize parent_dc_realize
;
133 #define TYPE_VMXNET3 "vmxnet3"
134 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
136 #define VMXNET3_DEVICE_CLASS(klass) \
137 OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3)
138 #define VMXNET3_DEVICE_GET_CLASS(obj) \
139 OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3)
141 /* Cyclic ring abstraction */
150 static inline void vmxnet3_ring_init(Vmxnet3Ring
*ring
,
158 ring
->cell_size
= cell_size
;
159 ring
->gen
= VMXNET3_INIT_GEN
;
163 vmw_shmem_set(pa
, 0, size
* cell_size
);
167 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
168 macro("%s#%d: base %" PRIx64 " size %zu cell_size %zu gen %d next %zu", \
169 (ring_name), (ridx), \
170 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
172 static inline void vmxnet3_ring_inc(Vmxnet3Ring
*ring
)
174 if (++ring
->next
>= ring
->size
) {
180 static inline void vmxnet3_ring_dec(Vmxnet3Ring
*ring
)
182 if (ring
->next
-- == 0) {
183 ring
->next
= ring
->size
- 1;
188 static inline hwaddr
vmxnet3_ring_curr_cell_pa(Vmxnet3Ring
*ring
)
190 return ring
->pa
+ ring
->next
* ring
->cell_size
;
193 static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring
*ring
, void *buff
)
195 vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
198 static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring
*ring
, void *buff
)
200 vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
203 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring
*ring
)
208 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring
*ring
)
213 /* Debug trace-related functions */
215 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc
*descr
)
217 VMW_PKPRN("TX DESCR: "
218 "addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
219 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
220 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
221 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
, descr
->rsvd
,
222 descr
->dtype
, descr
->ext1
, descr
->msscof
, descr
->hlen
, descr
->om
,
223 descr
->eop
, descr
->cq
, descr
->ext2
, descr
->ti
, descr
->tci
);
227 vmxnet3_dump_virt_hdr(struct virtio_net_hdr
*vhdr
)
229 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
230 "csum_start: %d, csum_offset: %d",
231 vhdr
->flags
, vhdr
->gso_type
, vhdr
->hdr_len
, vhdr
->gso_size
,
232 vhdr
->csum_start
, vhdr
->csum_offset
);
236 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc
*descr
)
238 VMW_PKPRN("RX DESCR: addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
239 "dtype: %d, ext1: %d, btype: %d",
240 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
,
241 descr
->rsvd
, descr
->dtype
, descr
->ext1
, descr
->btype
);
244 /* Device state and helper functions */
245 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
249 Vmxnet3Ring comp_ring
;
253 struct UPT1_TxStats txq_stats
;
257 Vmxnet3Ring rx_ring
[VMXNET3_RX_RINGS_PER_QUEUE
];
258 Vmxnet3Ring comp_ring
;
261 struct UPT1_RxStats rxq_stats
;
271 PCIDevice parent_obj
;
276 MemoryRegion msix_bar
;
278 Vmxnet3RxqDescr rxq_descr
[VMXNET3_DEVICE_MAX_RX_QUEUES
];
279 Vmxnet3TxqDescr txq_descr
[VMXNET3_DEVICE_MAX_TX_QUEUES
];
281 /* Whether MSI-X support was installed successfully */
283 /* Whether MSI support was installed successfully */
286 hwaddr temp_shared_guest_driver_memory
;
290 /* This boolean tells whether RX packet being indicated has to */
291 /* be split into head and body chunks from different RX rings */
292 bool rx_packets_compound
;
294 bool rx_vlan_stripping
;
302 /* Maximum number of fragments for indicated TX packets */
303 uint32_t max_tx_frags
;
305 /* Maximum number of fragments for indicated RX packets */
306 uint16_t max_rx_frags
;
308 /* Index for events interrupt */
309 uint8_t event_int_idx
;
311 /* Whether automatic interrupts masking enabled */
312 bool auto_int_masking
;
316 /* TX packets to QEMU interface */
317 struct VmxnetTxPkt
*tx_pkt
;
318 uint32_t offload_mode
;
319 uint32_t cso_or_gso_size
;
323 struct VmxnetRxPkt
*rx_pkt
;
326 bool skip_current_tx_pkt
;
328 uint32_t device_active
;
329 uint32_t last_command
;
331 uint32_t link_status_and_speed
;
333 Vmxnet3IntState interrupt_states
[VMXNET3_MAX_INTRS
];
335 uint32_t temp_mac
; /* To store the low part first */
338 uint32_t vlan_table
[VMXNET3_VFT_SIZE
];
341 uint32_t mcast_list_len
;
342 uint32_t mcast_list_buff_size
; /* needed for live migration. */
344 /* Compatability flags for migration */
345 uint32_t compat_flags
;
348 /* Interrupt management */
351 *This function returns sign whether interrupt line is in asserted state
352 * This depends on the type of interrupt used. For INTX interrupt line will
353 * be asserted until explicit deassertion, for MSI(X) interrupt line will
354 * be deasserted automatically due to notification semantics of the MSI(X)
357 static bool _vmxnet3_assert_interrupt_line(VMXNET3State
*s
, uint32_t int_idx
)
359 PCIDevice
*d
= PCI_DEVICE(s
);
361 if (s
->msix_used
&& msix_enabled(d
)) {
362 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx
);
363 msix_notify(d
, int_idx
);
366 if (s
->msi_used
&& msi_enabled(d
)) {
367 VMW_IRPRN("Sending MSI notification for vector %u", int_idx
);
368 msi_notify(d
, int_idx
);
372 VMW_IRPRN("Asserting line for interrupt %u", int_idx
);
377 static void _vmxnet3_deassert_interrupt_line(VMXNET3State
*s
, int lidx
)
379 PCIDevice
*d
= PCI_DEVICE(s
);
382 * This function should never be called for MSI(X) interrupts
383 * because deassertion never required for message interrupts
385 assert(!s
->msix_used
|| !msix_enabled(d
));
387 * This function should never be called for MSI(X) interrupts
388 * because deassertion never required for message interrupts
390 assert(!s
->msi_used
|| !msi_enabled(d
));
392 VMW_IRPRN("Deasserting line for interrupt %u", lidx
);
396 static void vmxnet3_update_interrupt_line_state(VMXNET3State
*s
, int lidx
)
398 if (!s
->interrupt_states
[lidx
].is_pending
&&
399 s
->interrupt_states
[lidx
].is_asserted
) {
400 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx
);
401 _vmxnet3_deassert_interrupt_line(s
, lidx
);
402 s
->interrupt_states
[lidx
].is_asserted
= false;
406 if (s
->interrupt_states
[lidx
].is_pending
&&
407 !s
->interrupt_states
[lidx
].is_masked
&&
408 !s
->interrupt_states
[lidx
].is_asserted
) {
409 VMW_IRPRN("New interrupt line state for index %d is UP", lidx
);
410 s
->interrupt_states
[lidx
].is_asserted
=
411 _vmxnet3_assert_interrupt_line(s
, lidx
);
412 s
->interrupt_states
[lidx
].is_pending
= false;
417 static void vmxnet3_trigger_interrupt(VMXNET3State
*s
, int lidx
)
419 PCIDevice
*d
= PCI_DEVICE(s
);
420 s
->interrupt_states
[lidx
].is_pending
= true;
421 vmxnet3_update_interrupt_line_state(s
, lidx
);
423 if (s
->msix_used
&& msix_enabled(d
) && s
->auto_int_masking
) {
427 if (s
->msi_used
&& msi_enabled(d
) && s
->auto_int_masking
) {
434 s
->interrupt_states
[lidx
].is_masked
= true;
435 vmxnet3_update_interrupt_line_state(s
, lidx
);
438 static bool vmxnet3_interrupt_asserted(VMXNET3State
*s
, int lidx
)
440 return s
->interrupt_states
[lidx
].is_asserted
;
443 static void vmxnet3_clear_interrupt(VMXNET3State
*s
, int int_idx
)
445 s
->interrupt_states
[int_idx
].is_pending
= false;
446 if (s
->auto_int_masking
) {
447 s
->interrupt_states
[int_idx
].is_masked
= true;
449 vmxnet3_update_interrupt_line_state(s
, int_idx
);
453 vmxnet3_on_interrupt_mask_changed(VMXNET3State
*s
, int lidx
, bool is_masked
)
455 s
->interrupt_states
[lidx
].is_masked
= is_masked
;
456 vmxnet3_update_interrupt_line_state(s
, lidx
);
459 static bool vmxnet3_verify_driver_magic(hwaddr dshmem
)
461 return (VMXNET3_READ_DRV_SHARED32(dshmem
, magic
) == VMXNET3_REV1_MAGIC
);
464 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
465 #define VMXNET3_MAKE_BYTE(byte_num, val) \
466 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
468 static void vmxnet3_set_variable_mac(VMXNET3State
*s
, uint32_t h
, uint32_t l
)
470 s
->conf
.macaddr
.a
[0] = VMXNET3_GET_BYTE(l
, 0);
471 s
->conf
.macaddr
.a
[1] = VMXNET3_GET_BYTE(l
, 1);
472 s
->conf
.macaddr
.a
[2] = VMXNET3_GET_BYTE(l
, 2);
473 s
->conf
.macaddr
.a
[3] = VMXNET3_GET_BYTE(l
, 3);
474 s
->conf
.macaddr
.a
[4] = VMXNET3_GET_BYTE(h
, 0);
475 s
->conf
.macaddr
.a
[5] = VMXNET3_GET_BYTE(h
, 1);
477 VMW_CFPRN("Variable MAC: " VMXNET_MF
, VMXNET_MA(s
->conf
.macaddr
.a
));
479 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
482 static uint64_t vmxnet3_get_mac_low(MACAddr
*addr
)
484 return VMXNET3_MAKE_BYTE(0, addr
->a
[0]) |
485 VMXNET3_MAKE_BYTE(1, addr
->a
[1]) |
486 VMXNET3_MAKE_BYTE(2, addr
->a
[2]) |
487 VMXNET3_MAKE_BYTE(3, addr
->a
[3]);
490 static uint64_t vmxnet3_get_mac_high(MACAddr
*addr
)
492 return VMXNET3_MAKE_BYTE(0, addr
->a
[4]) |
493 VMXNET3_MAKE_BYTE(1, addr
->a
[5]);
497 vmxnet3_inc_tx_consumption_counter(VMXNET3State
*s
, int qidx
)
499 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].tx_ring
);
503 vmxnet3_inc_rx_consumption_counter(VMXNET3State
*s
, int qidx
, int ridx
)
505 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].rx_ring
[ridx
]);
509 vmxnet3_inc_tx_completion_counter(VMXNET3State
*s
, int qidx
)
511 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].comp_ring
);
515 vmxnet3_inc_rx_completion_counter(VMXNET3State
*s
, int qidx
)
517 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].comp_ring
);
521 vmxnet3_dec_rx_completion_counter(VMXNET3State
*s
, int qidx
)
523 vmxnet3_ring_dec(&s
->rxq_descr
[qidx
].comp_ring
);
526 static void vmxnet3_complete_packet(VMXNET3State
*s
, int qidx
, uint32_t tx_ridx
)
528 struct Vmxnet3_TxCompDesc txcq_descr
;
530 VMXNET3_RING_DUMP(VMW_RIPRN
, "TXC", qidx
, &s
->txq_descr
[qidx
].comp_ring
);
532 txcq_descr
.txdIdx
= tx_ridx
;
533 txcq_descr
.gen
= vmxnet3_ring_curr_gen(&s
->txq_descr
[qidx
].comp_ring
);
535 vmxnet3_ring_write_curr_cell(&s
->txq_descr
[qidx
].comp_ring
, &txcq_descr
);
537 /* Flush changes in TX descriptor before changing the counter value */
540 vmxnet3_inc_tx_completion_counter(s
, qidx
);
541 vmxnet3_trigger_interrupt(s
, s
->txq_descr
[qidx
].intr_idx
);
545 vmxnet3_setup_tx_offloads(VMXNET3State
*s
)
547 switch (s
->offload_mode
) {
548 case VMXNET3_OM_NONE
:
549 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, false, false, 0);
552 case VMXNET3_OM_CSUM
:
553 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, false, true, 0);
554 VMW_PKPRN("L4 CSO requested\n");
558 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, true, true,
560 vmxnet_tx_pkt_update_ip_checksums(s
->tx_pkt
);
561 VMW_PKPRN("GSO offload requested.");
565 g_assert_not_reached();
573 vmxnet3_tx_retrieve_metadata(VMXNET3State
*s
,
574 const struct Vmxnet3_TxDesc
*txd
)
576 s
->offload_mode
= txd
->om
;
577 s
->cso_or_gso_size
= txd
->msscof
;
579 s
->needs_vlan
= txd
->ti
;
583 VMXNET3_PKT_STATUS_OK
,
584 VMXNET3_PKT_STATUS_ERROR
,
585 VMXNET3_PKT_STATUS_DISCARD
,/* only for tx */
586 VMXNET3_PKT_STATUS_OUT_OF_BUF
/* only for rx */
590 vmxnet3_on_tx_done_update_stats(VMXNET3State
*s
, int qidx
,
591 Vmxnet3PktStatus status
)
593 size_t tot_len
= vmxnet_tx_pkt_get_total_len(s
->tx_pkt
);
594 struct UPT1_TxStats
*stats
= &s
->txq_descr
[qidx
].txq_stats
;
597 case VMXNET3_PKT_STATUS_OK
:
598 switch (vmxnet_tx_pkt_get_packet_type(s
->tx_pkt
)) {
600 stats
->bcastPktsTxOK
++;
601 stats
->bcastBytesTxOK
+= tot_len
;
604 stats
->mcastPktsTxOK
++;
605 stats
->mcastBytesTxOK
+= tot_len
;
608 stats
->ucastPktsTxOK
++;
609 stats
->ucastBytesTxOK
+= tot_len
;
612 g_assert_not_reached();
615 if (s
->offload_mode
== VMXNET3_OM_TSO
) {
617 * According to VMWARE headers this statistic is a number
618 * of packets after segmentation but since we don't have
619 * this information in QEMU model, the best we can do is to
620 * provide number of non-segmented packets
622 stats
->TSOPktsTxOK
++;
623 stats
->TSOBytesTxOK
+= tot_len
;
627 case VMXNET3_PKT_STATUS_DISCARD
:
628 stats
->pktsTxDiscard
++;
631 case VMXNET3_PKT_STATUS_ERROR
:
632 stats
->pktsTxError
++;
636 g_assert_not_reached();
641 vmxnet3_on_rx_done_update_stats(VMXNET3State
*s
,
643 Vmxnet3PktStatus status
)
645 struct UPT1_RxStats
*stats
= &s
->rxq_descr
[qidx
].rxq_stats
;
646 size_t tot_len
= vmxnet_rx_pkt_get_total_len(s
->rx_pkt
);
649 case VMXNET3_PKT_STATUS_OUT_OF_BUF
:
650 stats
->pktsRxOutOfBuf
++;
653 case VMXNET3_PKT_STATUS_ERROR
:
654 stats
->pktsRxError
++;
656 case VMXNET3_PKT_STATUS_OK
:
657 switch (vmxnet_rx_pkt_get_packet_type(s
->rx_pkt
)) {
659 stats
->bcastPktsRxOK
++;
660 stats
->bcastBytesRxOK
+= tot_len
;
663 stats
->mcastPktsRxOK
++;
664 stats
->mcastBytesRxOK
+= tot_len
;
667 stats
->ucastPktsRxOK
++;
668 stats
->ucastBytesRxOK
+= tot_len
;
671 g_assert_not_reached();
674 if (tot_len
> s
->mtu
) {
675 stats
->LROPktsRxOK
++;
676 stats
->LROBytesRxOK
+= tot_len
;
680 g_assert_not_reached();
685 vmxnet3_pop_next_tx_descr(VMXNET3State
*s
,
687 struct Vmxnet3_TxDesc
*txd
,
690 Vmxnet3Ring
*ring
= &s
->txq_descr
[qidx
].tx_ring
;
692 vmxnet3_ring_read_curr_cell(ring
, txd
);
693 if (txd
->gen
== vmxnet3_ring_curr_gen(ring
)) {
694 /* Only read after generation field verification */
696 /* Re-read to be sure we got the latest version */
697 vmxnet3_ring_read_curr_cell(ring
, txd
);
698 VMXNET3_RING_DUMP(VMW_RIPRN
, "TX", qidx
, ring
);
699 *descr_idx
= vmxnet3_ring_curr_cell_idx(ring
);
700 vmxnet3_inc_tx_consumption_counter(s
, qidx
);
708 vmxnet3_send_packet(VMXNET3State
*s
, uint32_t qidx
)
710 Vmxnet3PktStatus status
= VMXNET3_PKT_STATUS_OK
;
712 if (!vmxnet3_setup_tx_offloads(s
)) {
713 status
= VMXNET3_PKT_STATUS_ERROR
;
718 vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s
->tx_pkt
));
719 vmxnet_tx_pkt_dump(s
->tx_pkt
);
721 if (!vmxnet_tx_pkt_send(s
->tx_pkt
, qemu_get_queue(s
->nic
))) {
722 status
= VMXNET3_PKT_STATUS_DISCARD
;
727 vmxnet3_on_tx_done_update_stats(s
, qidx
, status
);
728 return (status
== VMXNET3_PKT_STATUS_OK
);
731 static void vmxnet3_process_tx_queue(VMXNET3State
*s
, int qidx
)
733 struct Vmxnet3_TxDesc txd
;
739 if (!vmxnet3_pop_next_tx_descr(s
, qidx
, &txd
, &txd_idx
)) {
743 vmxnet3_dump_tx_descr(&txd
);
745 if (!s
->skip_current_tx_pkt
) {
746 data_len
= (txd
.len
> 0) ? txd
.len
: VMXNET3_MAX_TX_BUF_SIZE
;
747 data_pa
= le64_to_cpu(txd
.addr
);
749 if (!vmxnet_tx_pkt_add_raw_fragment(s
->tx_pkt
,
752 s
->skip_current_tx_pkt
= true;
757 vmxnet3_tx_retrieve_metadata(s
, &txd
);
762 if (!s
->skip_current_tx_pkt
&& vmxnet_tx_pkt_parse(s
->tx_pkt
)) {
764 vmxnet_tx_pkt_setup_vlan_header(s
->tx_pkt
, s
->tci
);
767 vmxnet3_send_packet(s
, qidx
);
769 vmxnet3_on_tx_done_update_stats(s
, qidx
,
770 VMXNET3_PKT_STATUS_ERROR
);
773 vmxnet3_complete_packet(s
, qidx
, txd_idx
);
775 s
->skip_current_tx_pkt
= false;
776 vmxnet_tx_pkt_reset(s
->tx_pkt
);
782 vmxnet3_read_next_rx_descr(VMXNET3State
*s
, int qidx
, int ridx
,
783 struct Vmxnet3_RxDesc
*dbuf
, uint32_t *didx
)
785 Vmxnet3Ring
*ring
= &s
->rxq_descr
[qidx
].rx_ring
[ridx
];
786 *didx
= vmxnet3_ring_curr_cell_idx(ring
);
787 vmxnet3_ring_read_curr_cell(ring
, dbuf
);
790 static inline uint8_t
791 vmxnet3_get_rx_ring_gen(VMXNET3State
*s
, int qidx
, int ridx
)
793 return s
->rxq_descr
[qidx
].rx_ring
[ridx
].gen
;
797 vmxnet3_pop_rxc_descr(VMXNET3State
*s
, int qidx
, uint32_t *descr_gen
)
800 struct Vmxnet3_RxCompDesc rxcd
;
803 vmxnet3_ring_curr_cell_pa(&s
->rxq_descr
[qidx
].comp_ring
);
805 cpu_physical_memory_read(daddr
, &rxcd
, sizeof(struct Vmxnet3_RxCompDesc
));
806 ring_gen
= vmxnet3_ring_curr_gen(&s
->rxq_descr
[qidx
].comp_ring
);
808 if (rxcd
.gen
!= ring_gen
) {
809 *descr_gen
= ring_gen
;
810 vmxnet3_inc_rx_completion_counter(s
, qidx
);
818 vmxnet3_revert_rxc_descr(VMXNET3State
*s
, int qidx
)
820 vmxnet3_dec_rx_completion_counter(s
, qidx
);
824 #define RX_HEAD_BODY_RING (0)
825 #define RX_BODY_ONLY_RING (1)
828 vmxnet3_get_next_head_rx_descr(VMXNET3State
*s
,
829 struct Vmxnet3_RxDesc
*descr_buf
,
835 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
836 descr_buf
, descr_idx
);
838 /* If no more free descriptors - return */
839 ring_gen
= vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
840 if (descr_buf
->gen
!= ring_gen
) {
844 /* Only read after generation field verification */
846 /* Re-read to be sure we got the latest version */
847 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
848 descr_buf
, descr_idx
);
850 /* Mark current descriptor as used/skipped */
851 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
853 /* If this is what we are looking for - return */
854 if (descr_buf
->btype
== VMXNET3_RXD_BTYPE_HEAD
) {
855 *ridx
= RX_HEAD_BODY_RING
;
862 vmxnet3_get_next_body_rx_descr(VMXNET3State
*s
,
863 struct Vmxnet3_RxDesc
*d
,
867 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
869 /* Try to find corresponding descriptor in head/body ring */
870 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
)) {
871 /* Only read after generation field verification */
873 /* Re-read to be sure we got the latest version */
874 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
875 if (d
->btype
== VMXNET3_RXD_BTYPE_BODY
) {
876 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
877 *ridx
= RX_HEAD_BODY_RING
;
883 * If there is no free descriptors on head/body ring or next free
884 * descriptor is a head descriptor switch to body only ring
886 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
888 /* If no more free descriptors - return */
889 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_BODY_ONLY_RING
)) {
890 /* Only read after generation field verification */
892 /* Re-read to be sure we got the latest version */
893 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
894 assert(d
->btype
== VMXNET3_RXD_BTYPE_BODY
);
895 *ridx
= RX_BODY_ONLY_RING
;
896 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_BODY_ONLY_RING
);
904 vmxnet3_get_next_rx_descr(VMXNET3State
*s
, bool is_head
,
905 struct Vmxnet3_RxDesc
*descr_buf
,
909 if (is_head
|| !s
->rx_packets_compound
) {
910 return vmxnet3_get_next_head_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
912 return vmxnet3_get_next_body_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
916 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
917 * the implementation always passes an RxCompDesc with a "Checksum
918 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
919 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
921 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
922 * and place a fully computed checksum into the tcp/udp header.
923 * Otherwise, the OS driver will receive a checksum-correct indication
924 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
925 * having just the pseudo header csum value.
927 * While this is not a problem if packet is destined for local delivery,
928 * in the case the host OS performs forwarding, it will forward an
929 * incorrectly checksummed packet.
931 static void vmxnet3_rx_need_csum_calculate(struct VmxnetRxPkt
*pkt
,
932 const void *pkt_data
,
935 struct virtio_net_hdr
*vhdr
;
936 bool isip4
, isip6
, istcp
, isudp
;
940 if (!vmxnet_rx_pkt_has_virt_hdr(pkt
)) {
944 vhdr
= vmxnet_rx_pkt_get_vhdr(pkt
);
945 if (!VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
)) {
949 vmxnet_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
950 if (!(isip4
|| isip6
) || !(istcp
|| isudp
)) {
954 vmxnet3_dump_virt_hdr(vhdr
);
956 /* Validate packet len: csum_start + scum_offset + length of csum field */
957 if (pkt_len
< (vhdr
->csum_start
+ vhdr
->csum_offset
+ 2)) {
958 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
959 "cannot calculate checksum",
960 pkt_len
, vhdr
->csum_start
, vhdr
->csum_offset
);
964 data
= (uint8_t *)pkt_data
+ vhdr
->csum_start
;
965 len
= pkt_len
- vhdr
->csum_start
;
966 /* Put the checksum obtained into the packet */
967 stw_be_p(data
+ vhdr
->csum_offset
, net_raw_checksum(data
, len
));
969 vhdr
->flags
&= ~VIRTIO_NET_HDR_F_NEEDS_CSUM
;
970 vhdr
->flags
|= VIRTIO_NET_HDR_F_DATA_VALID
;
973 static void vmxnet3_rx_update_descr(struct VmxnetRxPkt
*pkt
,
974 struct Vmxnet3_RxCompDesc
*rxcd
)
977 bool isip4
, isip6
, istcp
, isudp
;
978 struct virtio_net_hdr
*vhdr
;
979 uint8_t offload_type
;
981 if (vmxnet_rx_pkt_is_vlan_stripped(pkt
)) {
983 rxcd
->tci
= vmxnet_rx_pkt_get_vlan_tag(pkt
);
986 if (!vmxnet_rx_pkt_has_virt_hdr(pkt
)) {
990 vhdr
= vmxnet_rx_pkt_get_vhdr(pkt
);
992 * Checksum is valid when lower level tell so or when lower level
993 * requires checksum offload telling that packet produced/bridged
994 * locally and did travel over network after last checksum calculation
997 csum_ok
= VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_DATA_VALID
) ||
998 VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
);
1000 offload_type
= vhdr
->gso_type
& ~VIRTIO_NET_HDR_GSO_ECN
;
1001 is_gso
= (offload_type
!= VIRTIO_NET_HDR_GSO_NONE
) ? 1 : 0;
1003 if (!csum_ok
&& !is_gso
) {
1007 vmxnet_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
1008 if ((!istcp
&& !isudp
) || (!isip4
&& !isip6
)) {
1013 rxcd
->v4
= isip4
? 1 : 0;
1014 rxcd
->v6
= isip6
? 1 : 0;
1015 rxcd
->tcp
= istcp
? 1 : 0;
1016 rxcd
->udp
= isudp
? 1 : 0;
1017 rxcd
->fcs
= rxcd
->tuc
= rxcd
->ipc
= 1;
1026 vmxnet3_physical_memory_writev(const struct iovec
*iov
,
1027 size_t start_iov_off
,
1029 size_t bytes_to_copy
)
1031 size_t curr_off
= 0;
1034 while (bytes_to_copy
) {
1035 if (start_iov_off
< (curr_off
+ iov
->iov_len
)) {
1037 MIN((curr_off
+ iov
->iov_len
) - start_iov_off
, bytes_to_copy
);
1039 cpu_physical_memory_write(target_addr
+ copied
,
1040 iov
->iov_base
+ start_iov_off
- curr_off
,
1043 copied
+= chunk_len
;
1044 start_iov_off
+= chunk_len
;
1045 curr_off
= start_iov_off
;
1046 bytes_to_copy
-= chunk_len
;
1048 curr_off
+= iov
->iov_len
;
1055 vmxnet3_indicate_packet(VMXNET3State
*s
)
1057 struct Vmxnet3_RxDesc rxd
;
1058 bool is_head
= true;
1060 uint32_t rx_ridx
= 0;
1062 struct Vmxnet3_RxCompDesc rxcd
;
1063 uint32_t new_rxcd_gen
= VMXNET3_INIT_GEN
;
1064 hwaddr new_rxcd_pa
= 0;
1065 hwaddr ready_rxcd_pa
= 0;
1066 struct iovec
*data
= vmxnet_rx_pkt_get_iovec(s
->rx_pkt
);
1067 size_t bytes_copied
= 0;
1068 size_t bytes_left
= vmxnet_rx_pkt_get_total_len(s
->rx_pkt
);
1069 uint16_t num_frags
= 0;
1072 vmxnet_rx_pkt_dump(s
->rx_pkt
);
1074 while (bytes_left
> 0) {
1076 /* cannot add more frags to packet */
1077 if (num_frags
== s
->max_rx_frags
) {
1081 new_rxcd_pa
= vmxnet3_pop_rxc_descr(s
, RXQ_IDX
, &new_rxcd_gen
);
1086 if (!vmxnet3_get_next_rx_descr(s
, is_head
, &rxd
, &rxd_idx
, &rx_ridx
)) {
1090 chunk_size
= MIN(bytes_left
, rxd
.len
);
1091 vmxnet3_physical_memory_writev(data
, bytes_copied
,
1092 le64_to_cpu(rxd
.addr
), chunk_size
);
1093 bytes_copied
+= chunk_size
;
1094 bytes_left
-= chunk_size
;
1096 vmxnet3_dump_rx_descr(&rxd
);
1098 if (ready_rxcd_pa
!= 0) {
1099 cpu_physical_memory_write(ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1102 memset(&rxcd
, 0, sizeof(struct Vmxnet3_RxCompDesc
));
1103 rxcd
.rxdIdx
= rxd_idx
;
1104 rxcd
.len
= chunk_size
;
1106 rxcd
.gen
= new_rxcd_gen
;
1107 rxcd
.rqID
= RXQ_IDX
+ rx_ridx
* s
->rxq_num
;
1109 if (bytes_left
== 0) {
1110 vmxnet3_rx_update_descr(s
->rx_pkt
, &rxcd
);
1113 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1114 "sop %d csum_correct %lu",
1115 (unsigned long) rx_ridx
,
1116 (unsigned long) rxcd
.rxdIdx
,
1117 (unsigned long) rxcd
.len
,
1119 (unsigned long) rxcd
.tuc
);
1122 ready_rxcd_pa
= new_rxcd_pa
;
1127 if (ready_rxcd_pa
!= 0) {
1129 rxcd
.err
= (bytes_left
!= 0);
1130 cpu_physical_memory_write(ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1132 /* Flush RX descriptor changes */
1136 if (new_rxcd_pa
!= 0) {
1137 vmxnet3_revert_rxc_descr(s
, RXQ_IDX
);
1140 vmxnet3_trigger_interrupt(s
, s
->rxq_descr
[RXQ_IDX
].intr_idx
);
1142 if (bytes_left
== 0) {
1143 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_OK
);
1145 } else if (num_frags
== s
->max_rx_frags
) {
1146 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_ERROR
);
1149 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
,
1150 VMXNET3_PKT_STATUS_OUT_OF_BUF
);
1156 vmxnet3_io_bar0_write(void *opaque
, hwaddr addr
,
1157 uint64_t val
, unsigned size
)
1159 VMXNET3State
*s
= opaque
;
1161 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_TXPROD
,
1162 VMXNET3_DEVICE_MAX_TX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1164 VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_TXPROD
,
1166 assert(tx_queue_idx
<= s
->txq_num
);
1167 vmxnet3_process_tx_queue(s
, tx_queue_idx
);
1171 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1172 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1173 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1176 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64
, l
, val
);
1178 vmxnet3_on_interrupt_mask_changed(s
, l
, val
);
1182 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD
,
1183 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
) ||
1184 VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD2
,
1185 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1189 VMW_WRPRN("BAR0 unknown write [%" PRIx64
"] = %" PRIx64
", size %d",
1190 (uint64_t) addr
, val
, size
);
1194 vmxnet3_io_bar0_read(void *opaque
, hwaddr addr
, unsigned size
)
1196 VMXNET3State
*s
= opaque
;
1198 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1199 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1200 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1202 return s
->interrupt_states
[l
].is_masked
;
1205 VMW_CBPRN("BAR0 unknown read [%" PRIx64
"], size %d", addr
, size
);
1209 static void vmxnet3_reset_interrupt_states(VMXNET3State
*s
)
1212 for (i
= 0; i
< ARRAY_SIZE(s
->interrupt_states
); i
++) {
1213 s
->interrupt_states
[i
].is_asserted
= false;
1214 s
->interrupt_states
[i
].is_pending
= false;
1215 s
->interrupt_states
[i
].is_masked
= true;
1219 static void vmxnet3_reset_mac(VMXNET3State
*s
)
1221 memcpy(&s
->conf
.macaddr
.a
, &s
->perm_mac
.a
, sizeof(s
->perm_mac
.a
));
1222 VMW_CFPRN("MAC address set to: " VMXNET_MF
, VMXNET_MA(s
->conf
.macaddr
.a
));
1225 static void vmxnet3_deactivate_device(VMXNET3State
*s
)
1227 if (s
->device_active
) {
1228 VMW_CBPRN("Deactivating vmxnet3...");
1229 vmxnet_tx_pkt_reset(s
->tx_pkt
);
1230 vmxnet_tx_pkt_uninit(s
->tx_pkt
);
1231 vmxnet_rx_pkt_uninit(s
->rx_pkt
);
1232 s
->device_active
= false;
1236 static void vmxnet3_reset(VMXNET3State
*s
)
1238 VMW_CBPRN("Resetting vmxnet3...");
1240 vmxnet3_deactivate_device(s
);
1241 vmxnet3_reset_interrupt_states(s
);
1244 s
->skip_current_tx_pkt
= false;
1247 static void vmxnet3_update_rx_mode(VMXNET3State
*s
)
1249 s
->rx_mode
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
,
1250 devRead
.rxFilterConf
.rxMode
);
1251 VMW_CFPRN("RX mode: 0x%08X", s
->rx_mode
);
1254 static void vmxnet3_update_vlan_filters(VMXNET3State
*s
)
1258 /* Copy configuration from shared memory */
1259 VMXNET3_READ_DRV_SHARED(s
->drv_shmem
,
1260 devRead
.rxFilterConf
.vfTable
,
1262 sizeof(s
->vlan_table
));
1264 /* Invert byte order when needed */
1265 for (i
= 0; i
< ARRAY_SIZE(s
->vlan_table
); i
++) {
1266 s
->vlan_table
[i
] = le32_to_cpu(s
->vlan_table
[i
]);
1269 /* Dump configuration for debugging purposes */
1270 VMW_CFPRN("Configured VLANs:");
1271 for (i
= 0; i
< sizeof(s
->vlan_table
) * 8; i
++) {
1272 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, i
)) {
1273 VMW_CFPRN("\tVLAN %d is present", i
);
1278 static void vmxnet3_update_mcast_filters(VMXNET3State
*s
)
1280 uint16_t list_bytes
=
1281 VMXNET3_READ_DRV_SHARED16(s
->drv_shmem
,
1282 devRead
.rxFilterConf
.mfTableLen
);
1284 s
->mcast_list_len
= list_bytes
/ sizeof(s
->mcast_list
[0]);
1286 s
->mcast_list
= g_realloc(s
->mcast_list
, list_bytes
);
1287 if (!s
->mcast_list
) {
1288 if (s
->mcast_list_len
== 0) {
1289 VMW_CFPRN("Current multicast list is empty");
1291 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1294 s
->mcast_list_len
= 0;
1297 hwaddr mcast_list_pa
=
1298 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
,
1299 devRead
.rxFilterConf
.mfTablePA
);
1301 cpu_physical_memory_read(mcast_list_pa
, s
->mcast_list
, list_bytes
);
1302 VMW_CFPRN("Current multicast list len is %d:", s
->mcast_list_len
);
1303 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1304 VMW_CFPRN("\t" VMXNET_MF
, VMXNET_MA(s
->mcast_list
[i
].a
));
1309 static void vmxnet3_setup_rx_filtering(VMXNET3State
*s
)
1311 vmxnet3_update_rx_mode(s
);
1312 vmxnet3_update_vlan_filters(s
);
1313 vmxnet3_update_mcast_filters(s
);
1316 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State
*s
)
1318 uint32_t interrupt_mode
= VMXNET3_IT_AUTO
| (VMXNET3_IMM_AUTO
<< 2);
1319 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode
);
1320 return interrupt_mode
;
1323 static void vmxnet3_fill_stats(VMXNET3State
*s
)
1327 if (!s
->device_active
)
1330 for (i
= 0; i
< s
->txq_num
; i
++) {
1331 cpu_physical_memory_write(s
->txq_descr
[i
].tx_stats_pa
,
1332 &s
->txq_descr
[i
].txq_stats
,
1333 sizeof(s
->txq_descr
[i
].txq_stats
));
1336 for (i
= 0; i
< s
->rxq_num
; i
++) {
1337 cpu_physical_memory_write(s
->rxq_descr
[i
].rx_stats_pa
,
1338 &s
->rxq_descr
[i
].rxq_stats
,
1339 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1343 static void vmxnet3_adjust_by_guest_type(VMXNET3State
*s
)
1345 struct Vmxnet3_GOSInfo gos
;
1347 VMXNET3_READ_DRV_SHARED(s
->drv_shmem
, devRead
.misc
.driverInfo
.gos
,
1349 s
->rx_packets_compound
=
1350 (gos
.gosType
== VMXNET3_GOS_TYPE_WIN
) ? false : true;
1352 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s
->rx_packets_compound
);
1356 vmxnet3_dump_conf_descr(const char *name
,
1357 struct Vmxnet3_VariableLenConfDesc
*pm_descr
)
1359 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1360 name
, pm_descr
->confVer
, pm_descr
->confLen
);
1364 static void vmxnet3_update_pm_state(VMXNET3State
*s
)
1366 struct Vmxnet3_VariableLenConfDesc pm_descr
;
1369 VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.pmConfDesc
.confLen
);
1371 VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.pmConfDesc
.confVer
);
1373 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
, devRead
.pmConfDesc
.confPA
);
1375 vmxnet3_dump_conf_descr("PM State", &pm_descr
);
1378 static void vmxnet3_update_features(VMXNET3State
*s
)
1380 uint32_t guest_features
;
1381 int rxcso_supported
;
1383 guest_features
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
,
1384 devRead
.misc
.uptFeatures
);
1386 rxcso_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXCSUM
);
1387 s
->rx_vlan_stripping
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXVLAN
);
1388 s
->lro_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_LRO
);
1390 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1391 s
->lro_supported
, rxcso_supported
,
1392 s
->rx_vlan_stripping
);
1393 if (s
->peer_has_vhdr
) {
1394 qemu_set_offload(qemu_get_queue(s
->nic
)->peer
,
1403 static bool vmxnet3_verify_intx(VMXNET3State
*s
, int intx
)
1405 return s
->msix_used
|| s
->msi_used
|| (intx
==
1406 (pci_get_byte(s
->parent_obj
.config
+ PCI_INTERRUPT_PIN
) - 1));
1409 static void vmxnet3_validate_interrupt_idx(bool is_msix
, int idx
)
1411 int max_ints
= is_msix
? VMXNET3_MAX_INTRS
: VMXNET3_MAX_NMSIX_INTRS
;
1412 if (idx
>= max_ints
) {
1413 hw_error("Bad interrupt index: %d\n", idx
);
1417 static void vmxnet3_validate_interrupts(VMXNET3State
*s
)
1421 VMW_CFPRN("Verifying event interrupt index (%d)", s
->event_int_idx
);
1422 vmxnet3_validate_interrupt_idx(s
->msix_used
, s
->event_int_idx
);
1424 for (i
= 0; i
< s
->txq_num
; i
++) {
1425 int idx
= s
->txq_descr
[i
].intr_idx
;
1426 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i
, idx
);
1427 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1430 for (i
= 0; i
< s
->rxq_num
; i
++) {
1431 int idx
= s
->rxq_descr
[i
].intr_idx
;
1432 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i
, idx
);
1433 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1437 static void vmxnet3_validate_queues(VMXNET3State
*s
)
1440 * txq_num and rxq_num are total number of queues
1441 * configured by guest. These numbers must not
1442 * exceed corresponding maximal values.
1445 if (s
->txq_num
> VMXNET3_DEVICE_MAX_TX_QUEUES
) {
1446 hw_error("Bad TX queues number: %d\n", s
->txq_num
);
1449 if (s
->rxq_num
> VMXNET3_DEVICE_MAX_RX_QUEUES
) {
1450 hw_error("Bad RX queues number: %d\n", s
->rxq_num
);
1454 static void vmxnet3_activate_device(VMXNET3State
*s
)
1457 static const uint32_t VMXNET3_DEF_TX_THRESHOLD
= 1;
1458 hwaddr qdescr_table_pa
;
1462 /* Verify configuration consistency */
1463 if (!vmxnet3_verify_driver_magic(s
->drv_shmem
)) {
1464 VMW_ERPRN("Device configuration received from driver is invalid");
1468 /* Verify if device is active */
1469 if (s
->device_active
) {
1470 VMW_CFPRN("Vmxnet3 device is active");
1474 vmxnet3_adjust_by_guest_type(s
);
1475 vmxnet3_update_features(s
);
1476 vmxnet3_update_pm_state(s
);
1477 vmxnet3_setup_rx_filtering(s
);
1478 /* Cache fields from shared memory */
1479 s
->mtu
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.misc
.mtu
);
1480 VMW_CFPRN("MTU is %u", s
->mtu
);
1483 VMXNET3_READ_DRV_SHARED16(s
->drv_shmem
, devRead
.misc
.maxNumRxSG
);
1485 if (s
->max_rx_frags
== 0) {
1486 s
->max_rx_frags
= 1;
1489 VMW_CFPRN("Max RX fragments is %u", s
->max_rx_frags
);
1492 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.intrConf
.eventIntrIdx
);
1493 assert(vmxnet3_verify_intx(s
, s
->event_int_idx
));
1494 VMW_CFPRN("Events interrupt line is %u", s
->event_int_idx
);
1496 s
->auto_int_masking
=
1497 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.intrConf
.autoMask
);
1498 VMW_CFPRN("Automatic interrupt masking is %d", (int)s
->auto_int_masking
);
1501 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.misc
.numTxQueues
);
1503 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.misc
.numRxQueues
);
1505 VMW_CFPRN("Number of TX/RX queues %u/%u", s
->txq_num
, s
->rxq_num
);
1506 vmxnet3_validate_queues(s
);
1509 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
, devRead
.misc
.queueDescPA
);
1510 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64
, qdescr_table_pa
);
1513 * Worst-case scenario is a packet that holds all TX rings space so
1514 * we calculate total size of all TX rings for max TX fragments number
1516 s
->max_tx_frags
= 0;
1519 for (i
= 0; i
< s
->txq_num
; i
++) {
1521 qdescr_table_pa
+ i
* sizeof(struct Vmxnet3_TxQueueDesc
);
1523 /* Read interrupt number for this TX queue */
1524 s
->txq_descr
[i
].intr_idx
=
1525 VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa
, conf
.intrIdx
);
1526 assert(vmxnet3_verify_intx(s
, s
->txq_descr
[i
].intr_idx
));
1528 VMW_CFPRN("TX Queue %d interrupt: %d", i
, s
->txq_descr
[i
].intr_idx
);
1530 /* Read rings memory locations for TX queues */
1531 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa
, conf
.txRingBasePA
);
1532 size
= VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa
, conf
.txRingSize
);
1534 vmxnet3_ring_init(&s
->txq_descr
[i
].tx_ring
, pa
, size
,
1535 sizeof(struct Vmxnet3_TxDesc
), false);
1536 VMXNET3_RING_DUMP(VMW_CFPRN
, "TX", i
, &s
->txq_descr
[i
].tx_ring
);
1538 s
->max_tx_frags
+= size
;
1541 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa
, conf
.compRingBasePA
);
1542 size
= VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa
, conf
.compRingSize
);
1543 vmxnet3_ring_init(&s
->txq_descr
[i
].comp_ring
, pa
, size
,
1544 sizeof(struct Vmxnet3_TxCompDesc
), true);
1545 VMXNET3_RING_DUMP(VMW_CFPRN
, "TXC", i
, &s
->txq_descr
[i
].comp_ring
);
1547 s
->txq_descr
[i
].tx_stats_pa
=
1548 qdescr_pa
+ offsetof(struct Vmxnet3_TxQueueDesc
, stats
);
1550 memset(&s
->txq_descr
[i
].txq_stats
, 0,
1551 sizeof(s
->txq_descr
[i
].txq_stats
));
1553 /* Fill device-managed parameters for queues */
1554 VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa
,
1556 VMXNET3_DEF_TX_THRESHOLD
);
1559 /* Preallocate TX packet wrapper */
1560 VMW_CFPRN("Max TX fragments is %u", s
->max_tx_frags
);
1561 vmxnet_tx_pkt_init(&s
->tx_pkt
, s
->max_tx_frags
, s
->peer_has_vhdr
);
1562 vmxnet_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
1564 /* Read rings memory locations for RX queues */
1565 for (i
= 0; i
< s
->rxq_num
; i
++) {
1568 qdescr_table_pa
+ s
->txq_num
* sizeof(struct Vmxnet3_TxQueueDesc
) +
1569 i
* sizeof(struct Vmxnet3_RxQueueDesc
);
1571 /* Read interrupt number for this RX queue */
1572 s
->rxq_descr
[i
].intr_idx
=
1573 VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa
, conf
.intrIdx
);
1574 assert(vmxnet3_verify_intx(s
, s
->rxq_descr
[i
].intr_idx
));
1576 VMW_CFPRN("RX Queue %d interrupt: %d", i
, s
->rxq_descr
[i
].intr_idx
);
1578 /* Read rings memory locations */
1579 for (j
= 0; j
< VMXNET3_RX_RINGS_PER_QUEUE
; j
++) {
1581 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa
, conf
.rxRingBasePA
[j
]);
1582 size
= VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa
, conf
.rxRingSize
[j
]);
1583 vmxnet3_ring_init(&s
->rxq_descr
[i
].rx_ring
[j
], pa
, size
,
1584 sizeof(struct Vmxnet3_RxDesc
), false);
1585 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64
", Size: %d",
1590 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa
, conf
.compRingBasePA
);
1591 size
= VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa
, conf
.compRingSize
);
1592 vmxnet3_ring_init(&s
->rxq_descr
[i
].comp_ring
, pa
, size
,
1593 sizeof(struct Vmxnet3_RxCompDesc
), true);
1594 VMW_CFPRN("RXC queue %d: Base: %" PRIx64
", Size: %d", i
, pa
, size
);
1596 s
->rxq_descr
[i
].rx_stats_pa
=
1597 qd_pa
+ offsetof(struct Vmxnet3_RxQueueDesc
, stats
);
1598 memset(&s
->rxq_descr
[i
].rxq_stats
, 0,
1599 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1602 vmxnet3_validate_interrupts(s
);
1604 /* Make sure everything is in place before device activation */
1607 vmxnet3_reset_mac(s
);
1609 s
->device_active
= true;
1612 static void vmxnet3_handle_command(VMXNET3State
*s
, uint64_t cmd
)
1614 s
->last_command
= cmd
;
1617 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1618 VMW_CBPRN("Set: Get upper part of permanent MAC");
1621 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1622 VMW_CBPRN("Set: Get lower part of permanent MAC");
1625 case VMXNET3_CMD_GET_STATS
:
1626 VMW_CBPRN("Set: Get device statistics");
1627 vmxnet3_fill_stats(s
);
1630 case VMXNET3_CMD_ACTIVATE_DEV
:
1631 VMW_CBPRN("Set: Activating vmxnet3 device");
1632 vmxnet3_activate_device(s
);
1635 case VMXNET3_CMD_UPDATE_RX_MODE
:
1636 VMW_CBPRN("Set: Update rx mode");
1637 vmxnet3_update_rx_mode(s
);
1640 case VMXNET3_CMD_UPDATE_VLAN_FILTERS
:
1641 VMW_CBPRN("Set: Update VLAN filters");
1642 vmxnet3_update_vlan_filters(s
);
1645 case VMXNET3_CMD_UPDATE_MAC_FILTERS
:
1646 VMW_CBPRN("Set: Update MAC filters");
1647 vmxnet3_update_mcast_filters(s
);
1650 case VMXNET3_CMD_UPDATE_FEATURE
:
1651 VMW_CBPRN("Set: Update features");
1652 vmxnet3_update_features(s
);
1655 case VMXNET3_CMD_UPDATE_PMCFG
:
1656 VMW_CBPRN("Set: Update power management config");
1657 vmxnet3_update_pm_state(s
);
1660 case VMXNET3_CMD_GET_LINK
:
1661 VMW_CBPRN("Set: Get link");
1664 case VMXNET3_CMD_RESET_DEV
:
1665 VMW_CBPRN("Set: Reset device");
1669 case VMXNET3_CMD_QUIESCE_DEV
:
1670 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
1671 vmxnet3_deactivate_device(s
);
1674 case VMXNET3_CMD_GET_CONF_INTR
:
1675 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1678 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1679 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1680 "adaptive ring info flags");
1683 case VMXNET3_CMD_GET_DID_LO
:
1684 VMW_CBPRN("Set: Get lower part of device ID");
1687 case VMXNET3_CMD_GET_DID_HI
:
1688 VMW_CBPRN("Set: Get upper part of device ID");
1691 case VMXNET3_CMD_GET_DEV_EXTRA_INFO
:
1692 VMW_CBPRN("Set: Get device extra info");
1696 VMW_CBPRN("Received unknown command: %" PRIx64
, cmd
);
1701 static uint64_t vmxnet3_get_command_status(VMXNET3State
*s
)
1705 switch (s
->last_command
) {
1706 case VMXNET3_CMD_ACTIVATE_DEV
:
1707 ret
= (s
->device_active
) ? 0 : 1;
1708 VMW_CFPRN("Device active: %" PRIx64
, ret
);
1711 case VMXNET3_CMD_RESET_DEV
:
1712 case VMXNET3_CMD_QUIESCE_DEV
:
1713 case VMXNET3_CMD_GET_QUEUE_STATUS
:
1714 case VMXNET3_CMD_GET_DEV_EXTRA_INFO
:
1718 case VMXNET3_CMD_GET_LINK
:
1719 ret
= s
->link_status_and_speed
;
1720 VMW_CFPRN("Link and speed: %" PRIx64
, ret
);
1723 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1724 ret
= vmxnet3_get_mac_low(&s
->perm_mac
);
1727 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1728 ret
= vmxnet3_get_mac_high(&s
->perm_mac
);
1731 case VMXNET3_CMD_GET_CONF_INTR
:
1732 ret
= vmxnet3_get_interrupt_config(s
);
1735 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1736 ret
= VMXNET3_DISABLE_ADAPTIVE_RING
;
1739 case VMXNET3_CMD_GET_DID_LO
:
1740 ret
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
1743 case VMXNET3_CMD_GET_DID_HI
:
1744 ret
= VMXNET3_DEVICE_REVISION
;
1748 VMW_WRPRN("Received request for unknown command: %x", s
->last_command
);
1756 static void vmxnet3_set_events(VMXNET3State
*s
, uint32_t val
)
1760 VMW_CBPRN("Setting events: 0x%x", val
);
1761 events
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, ecr
) | val
;
1762 VMXNET3_WRITE_DRV_SHARED32(s
->drv_shmem
, ecr
, events
);
1765 static void vmxnet3_ack_events(VMXNET3State
*s
, uint32_t val
)
1769 VMW_CBPRN("Clearing events: 0x%x", val
);
1770 events
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, ecr
) & ~val
;
1771 VMXNET3_WRITE_DRV_SHARED32(s
->drv_shmem
, ecr
, events
);
1775 vmxnet3_io_bar1_write(void *opaque
,
1780 VMXNET3State
*s
= opaque
;
1783 /* Vmxnet3 Revision Report Selection */
1784 case VMXNET3_REG_VRRS
:
1785 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64
", size %d",
1789 /* UPT Version Report Selection */
1790 case VMXNET3_REG_UVRS
:
1791 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64
", size %d",
1795 /* Driver Shared Address Low */
1796 case VMXNET3_REG_DSAL
:
1797 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64
", size %d",
1800 * Guest driver will first write the low part of the shared
1801 * memory address. We save it to temp variable and set the
1802 * shared address only after we get the high part
1805 vmxnet3_deactivate_device(s
);
1807 s
->temp_shared_guest_driver_memory
= val
;
1811 /* Driver Shared Address High */
1812 case VMXNET3_REG_DSAH
:
1813 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64
", size %d",
1816 * Set the shared memory between guest driver and device.
1817 * We already should have low address part.
1819 s
->drv_shmem
= s
->temp_shared_guest_driver_memory
| (val
<< 32);
1823 case VMXNET3_REG_CMD
:
1824 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64
", size %d",
1826 vmxnet3_handle_command(s
, val
);
1829 /* MAC Address Low */
1830 case VMXNET3_REG_MACL
:
1831 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64
", size %d",
1836 /* MAC Address High */
1837 case VMXNET3_REG_MACH
:
1838 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64
", size %d",
1840 vmxnet3_set_variable_mac(s
, val
, s
->temp_mac
);
1843 /* Interrupt Cause Register */
1844 case VMXNET3_REG_ICR
:
1845 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64
", size %d",
1847 g_assert_not_reached();
1850 /* Event Cause Register */
1851 case VMXNET3_REG_ECR
:
1852 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64
", size %d",
1854 vmxnet3_ack_events(s
, val
);
1858 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64
"] = %" PRIx64
", size %d",
1865 vmxnet3_io_bar1_read(void *opaque
, hwaddr addr
, unsigned size
)
1867 VMXNET3State
*s
= opaque
;
1871 /* Vmxnet3 Revision Report Selection */
1872 case VMXNET3_REG_VRRS
:
1873 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size
);
1874 ret
= VMXNET3_DEVICE_REVISION
;
1877 /* UPT Version Report Selection */
1878 case VMXNET3_REG_UVRS
:
1879 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size
);
1880 ret
= VMXNET3_UPT_REVISION
;
1884 case VMXNET3_REG_CMD
:
1885 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size
);
1886 ret
= vmxnet3_get_command_status(s
);
1889 /* MAC Address Low */
1890 case VMXNET3_REG_MACL
:
1891 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size
);
1892 ret
= vmxnet3_get_mac_low(&s
->conf
.macaddr
);
1895 /* MAC Address High */
1896 case VMXNET3_REG_MACH
:
1897 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size
);
1898 ret
= vmxnet3_get_mac_high(&s
->conf
.macaddr
);
1902 * Interrupt Cause Register
1903 * Used for legacy interrupts only so interrupt index always 0
1905 case VMXNET3_REG_ICR
:
1906 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size
);
1907 if (vmxnet3_interrupt_asserted(s
, 0)) {
1908 vmxnet3_clear_interrupt(s
, 0);
1916 VMW_CBPRN("Unknow read BAR1[%" PRIx64
"], %d bytes", addr
, size
);
1924 vmxnet3_can_receive(NetClientState
*nc
)
1926 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1927 return s
->device_active
&&
1928 VMXNET_FLAG_IS_SET(s
->link_status_and_speed
, VMXNET3_LINK_STATUS_UP
);
1932 vmxnet3_is_registered_vlan(VMXNET3State
*s
, const void *data
)
1934 uint16_t vlan_tag
= eth_get_pkt_tci(data
) & VLAN_VID_MASK
;
1935 if (IS_SPECIAL_VLAN_ID(vlan_tag
)) {
1939 return VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, vlan_tag
);
1943 vmxnet3_is_allowed_mcast_group(VMXNET3State
*s
, const uint8_t *group_mac
)
1946 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1947 if (!memcmp(group_mac
, s
->mcast_list
[i
].a
, sizeof(s
->mcast_list
[i
]))) {
1955 vmxnet3_rx_filter_may_indicate(VMXNET3State
*s
, const void *data
,
1958 struct eth_header
*ehdr
= PKT_GET_ETH_HDR(data
);
1960 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_PROMISC
)) {
1964 if (!vmxnet3_is_registered_vlan(s
, data
)) {
1968 switch (vmxnet_rx_pkt_get_packet_type(s
->rx_pkt
)) {
1970 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_UCAST
)) {
1973 if (memcmp(s
->conf
.macaddr
.a
, ehdr
->h_dest
, ETH_ALEN
)) {
1979 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_BCAST
)) {
1985 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_ALL_MULTI
)) {
1988 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_MCAST
)) {
1991 if (!vmxnet3_is_allowed_mcast_group(s
, ehdr
->h_dest
)) {
1997 g_assert_not_reached();
2004 vmxnet3_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
2006 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
2007 size_t bytes_indicated
;
2008 uint8_t min_buf
[MIN_BUF_SIZE
];
2010 if (!vmxnet3_can_receive(nc
)) {
2011 VMW_PKPRN("Cannot receive now");
2015 if (s
->peer_has_vhdr
) {
2016 vmxnet_rx_pkt_set_vhdr(s
->rx_pkt
, (struct virtio_net_hdr
*)buf
);
2017 buf
+= sizeof(struct virtio_net_hdr
);
2018 size
-= sizeof(struct virtio_net_hdr
);
2021 /* Pad to minimum Ethernet frame length */
2022 if (size
< sizeof(min_buf
)) {
2023 memcpy(min_buf
, buf
, size
);
2024 memset(&min_buf
[size
], 0, sizeof(min_buf
) - size
);
2026 size
= sizeof(min_buf
);
2029 vmxnet_rx_pkt_set_packet_type(s
->rx_pkt
,
2030 get_eth_packet_type(PKT_GET_ETH_HDR(buf
)));
2032 if (vmxnet3_rx_filter_may_indicate(s
, buf
, size
)) {
2033 vmxnet_rx_pkt_set_protocols(s
->rx_pkt
, buf
, size
);
2034 vmxnet3_rx_need_csum_calculate(s
->rx_pkt
, buf
, size
);
2035 vmxnet_rx_pkt_attach_data(s
->rx_pkt
, buf
, size
, s
->rx_vlan_stripping
);
2036 bytes_indicated
= vmxnet3_indicate_packet(s
) ? size
: -1;
2037 if (bytes_indicated
< size
) {
2038 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated
, size
);
2041 VMW_PKPRN("Packet dropped by RX filter");
2042 bytes_indicated
= size
;
2046 assert(bytes_indicated
!= 0);
2047 return bytes_indicated
;
2050 static void vmxnet3_set_link_status(NetClientState
*nc
)
2052 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
2054 if (nc
->link_down
) {
2055 s
->link_status_and_speed
&= ~VMXNET3_LINK_STATUS_UP
;
2057 s
->link_status_and_speed
|= VMXNET3_LINK_STATUS_UP
;
2060 vmxnet3_set_events(s
, VMXNET3_ECR_LINK
);
2061 vmxnet3_trigger_interrupt(s
, s
->event_int_idx
);
2064 static NetClientInfo net_vmxnet3_info
= {
2065 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
2066 .size
= sizeof(NICState
),
2067 .receive
= vmxnet3_receive
,
2068 .link_status_changed
= vmxnet3_set_link_status
,
2071 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State
*s
)
2073 NetClientState
*nc
= qemu_get_queue(s
->nic
);
2075 if (qemu_has_vnet_hdr(nc
->peer
)) {
2082 static void vmxnet3_net_uninit(VMXNET3State
*s
)
2084 g_free(s
->mcast_list
);
2085 vmxnet3_deactivate_device(s
);
2086 qemu_del_nic(s
->nic
);
2089 static void vmxnet3_net_init(VMXNET3State
*s
)
2091 DeviceState
*d
= DEVICE(s
);
2093 VMW_CBPRN("vmxnet3_net_init called...");
2095 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
2097 /* Windows guest will query the address that was set on init */
2098 memcpy(&s
->perm_mac
.a
, &s
->conf
.macaddr
.a
, sizeof(s
->perm_mac
.a
));
2100 s
->mcast_list
= NULL
;
2101 s
->mcast_list_len
= 0;
2103 s
->link_status_and_speed
= VMXNET3_LINK_SPEED
| VMXNET3_LINK_STATUS_UP
;
2105 VMW_CFPRN("Permanent MAC: " VMXNET_MF
, VMXNET_MA(s
->perm_mac
.a
));
2107 s
->nic
= qemu_new_nic(&net_vmxnet3_info
, &s
->conf
,
2108 object_get_typename(OBJECT(s
)),
2111 s
->peer_has_vhdr
= vmxnet3_peer_has_vnet_hdr(s
);
2113 s
->skip_current_tx_pkt
= false;
2116 s
->rx_vlan_stripping
= false;
2117 s
->lro_supported
= false;
2119 if (s
->peer_has_vhdr
) {
2120 qemu_set_vnet_hdr_len(qemu_get_queue(s
->nic
)->peer
,
2121 sizeof(struct virtio_net_hdr
));
2123 qemu_using_vnet_hdr(qemu_get_queue(s
->nic
)->peer
, 1);
2126 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
2130 vmxnet3_unuse_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2132 PCIDevice
*d
= PCI_DEVICE(s
);
2134 for (i
= 0; i
< num_vectors
; i
++) {
2135 msix_vector_unuse(d
, i
);
2140 vmxnet3_use_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2142 PCIDevice
*d
= PCI_DEVICE(s
);
2144 for (i
= 0; i
< num_vectors
; i
++) {
2145 int res
= msix_vector_use(d
, i
);
2147 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i
, res
);
2148 vmxnet3_unuse_msix_vectors(s
, i
);
2156 vmxnet3_init_msix(VMXNET3State
*s
)
2158 PCIDevice
*d
= PCI_DEVICE(s
);
2159 int res
= msix_init(d
, VMXNET3_MAX_INTRS
,
2161 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_TABLE
,
2163 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_PBA(s
),
2164 VMXNET3_MSIX_OFFSET(s
));
2167 VMW_WRPRN("Failed to initialize MSI-X, error %d", res
);
2168 s
->msix_used
= false;
2170 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2171 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res
);
2172 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2173 s
->msix_used
= false;
2175 s
->msix_used
= true;
2178 return s
->msix_used
;
2182 vmxnet3_cleanup_msix(VMXNET3State
*s
)
2184 PCIDevice
*d
= PCI_DEVICE(s
);
2187 vmxnet3_unuse_msix_vectors(s
, VMXNET3_MAX_INTRS
);
2188 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2192 #define VMXNET3_USE_64BIT (true)
2193 #define VMXNET3_PER_VECTOR_MASK (false)
2196 vmxnet3_init_msi(VMXNET3State
*s
)
2198 PCIDevice
*d
= PCI_DEVICE(s
);
2201 res
= msi_init(d
, VMXNET3_MSI_OFFSET(s
), VMXNET3_MAX_NMSIX_INTRS
,
2202 VMXNET3_USE_64BIT
, VMXNET3_PER_VECTOR_MASK
);
2204 VMW_WRPRN("Failed to initialize MSI, error %d", res
);
2205 s
->msi_used
= false;
2214 vmxnet3_cleanup_msi(VMXNET3State
*s
)
2216 PCIDevice
*d
= PCI_DEVICE(s
);
2224 vmxnet3_msix_save(QEMUFile
*f
, void *opaque
)
2226 PCIDevice
*d
= PCI_DEVICE(opaque
);
2231 vmxnet3_msix_load(QEMUFile
*f
, void *opaque
, int version_id
)
2233 PCIDevice
*d
= PCI_DEVICE(opaque
);
2238 static const MemoryRegionOps b0_ops
= {
2239 .read
= vmxnet3_io_bar0_read
,
2240 .write
= vmxnet3_io_bar0_write
,
2241 .endianness
= DEVICE_LITTLE_ENDIAN
,
2243 .min_access_size
= 4,
2244 .max_access_size
= 4,
2248 static const MemoryRegionOps b1_ops
= {
2249 .read
= vmxnet3_io_bar1_read
,
2250 .write
= vmxnet3_io_bar1_write
,
2251 .endianness
= DEVICE_LITTLE_ENDIAN
,
2253 .min_access_size
= 4,
2254 .max_access_size
= 4,
2258 static uint8_t *vmxnet3_device_serial_num(VMXNET3State
*s
)
2260 static uint64_t dsn_payload
;
2261 uint8_t *dsnp
= (uint8_t *)&dsn_payload
;
2264 dsnp
[1] = s
->conf
.macaddr
.a
[3];
2265 dsnp
[2] = s
->conf
.macaddr
.a
[4];
2266 dsnp
[3] = s
->conf
.macaddr
.a
[5];
2267 dsnp
[4] = s
->conf
.macaddr
.a
[0];
2268 dsnp
[5] = s
->conf
.macaddr
.a
[1];
2269 dsnp
[6] = s
->conf
.macaddr
.a
[2];
2274 static void vmxnet3_pci_realize(PCIDevice
*pci_dev
, Error
**errp
)
2276 DeviceState
*dev
= DEVICE(pci_dev
);
2277 VMXNET3State
*s
= VMXNET3(pci_dev
);
2279 VMW_CBPRN("Starting init...");
2281 memory_region_init_io(&s
->bar0
, OBJECT(s
), &b0_ops
, s
,
2282 "vmxnet3-b0", VMXNET3_PT_REG_SIZE
);
2283 pci_register_bar(pci_dev
, VMXNET3_BAR0_IDX
,
2284 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
2286 memory_region_init_io(&s
->bar1
, OBJECT(s
), &b1_ops
, s
,
2287 "vmxnet3-b1", VMXNET3_VD_REG_SIZE
);
2288 pci_register_bar(pci_dev
, VMXNET3_BAR1_IDX
,
2289 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar1
);
2291 memory_region_init(&s
->msix_bar
, OBJECT(s
), "vmxnet3-msix-bar",
2292 VMXNET3_MSIX_BAR_SIZE
);
2293 pci_register_bar(pci_dev
, VMXNET3_MSIX_BAR_IDX
,
2294 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->msix_bar
);
2296 vmxnet3_reset_interrupt_states(s
);
2298 /* Interrupt pin A */
2299 pci_dev
->config
[PCI_INTERRUPT_PIN
] = 0x01;
2301 if (!vmxnet3_init_msix(s
)) {
2302 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2305 if (!vmxnet3_init_msi(s
)) {
2306 VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
2309 vmxnet3_net_init(s
);
2311 if (pci_is_express(pci_dev
)) {
2312 if (pci_bus_is_express(pci_dev
->bus
)) {
2313 pcie_endpoint_cap_init(pci_dev
, VMXNET3_EXP_EP_OFFSET
);
2316 pcie_add_capability(pci_dev
, PCI_EXT_CAP_ID_DSN
, 0x1,
2317 VMXNET3_DSN_OFFSET
, PCI_EXT_CAP_DSN_SIZEOF
);
2318 memcpy(pci_dev
->config
+ VMXNET3_DSN_OFFSET
+ 4,
2319 vmxnet3_device_serial_num(s
), sizeof(uint64_t));
2322 register_savevm(dev
, "vmxnet3-msix", -1, 1,
2323 vmxnet3_msix_save
, vmxnet3_msix_load
, s
);
2326 static void vmxnet3_instance_init(Object
*obj
)
2328 VMXNET3State
*s
= VMXNET3(obj
);
2329 device_add_bootindex_property(obj
, &s
->conf
.bootindex
,
2330 "bootindex", "/ethernet-phy@0",
2334 static void vmxnet3_pci_uninit(PCIDevice
*pci_dev
)
2336 DeviceState
*dev
= DEVICE(pci_dev
);
2337 VMXNET3State
*s
= VMXNET3(pci_dev
);
2339 VMW_CBPRN("Starting uninit...");
2341 unregister_savevm(dev
, "vmxnet3-msix", s
);
2343 vmxnet3_net_uninit(s
);
2345 vmxnet3_cleanup_msix(s
);
2347 vmxnet3_cleanup_msi(s
);
2350 static void vmxnet3_qdev_reset(DeviceState
*dev
)
2352 PCIDevice
*d
= PCI_DEVICE(dev
);
2353 VMXNET3State
*s
= VMXNET3(d
);
2355 VMW_CBPRN("Starting QDEV reset...");
2359 static bool vmxnet3_mc_list_needed(void *opaque
)
2364 static int vmxnet3_mcast_list_pre_load(void *opaque
)
2366 VMXNET3State
*s
= opaque
;
2368 s
->mcast_list
= g_malloc(s
->mcast_list_buff_size
);
2374 static void vmxnet3_pre_save(void *opaque
)
2376 VMXNET3State
*s
= opaque
;
2378 s
->mcast_list_buff_size
= s
->mcast_list_len
* sizeof(MACAddr
);
2381 static const VMStateDescription vmxstate_vmxnet3_mcast_list
= {
2382 .name
= "vmxnet3/mcast_list",
2384 .minimum_version_id
= 1,
2385 .pre_load
= vmxnet3_mcast_list_pre_load
,
2386 .needed
= vmxnet3_mc_list_needed
,
2387 .fields
= (VMStateField
[]) {
2388 VMSTATE_VBUFFER_UINT32(mcast_list
, VMXNET3State
, 0, NULL
, 0,
2389 mcast_list_buff_size
),
2390 VMSTATE_END_OF_LIST()
2394 static void vmxnet3_get_ring_from_file(QEMUFile
*f
, Vmxnet3Ring
*r
)
2396 r
->pa
= qemu_get_be64(f
);
2397 r
->size
= qemu_get_be32(f
);
2398 r
->cell_size
= qemu_get_be32(f
);
2399 r
->next
= qemu_get_be32(f
);
2400 r
->gen
= qemu_get_byte(f
);
2403 static void vmxnet3_put_ring_to_file(QEMUFile
*f
, Vmxnet3Ring
*r
)
2405 qemu_put_be64(f
, r
->pa
);
2406 qemu_put_be32(f
, r
->size
);
2407 qemu_put_be32(f
, r
->cell_size
);
2408 qemu_put_be32(f
, r
->next
);
2409 qemu_put_byte(f
, r
->gen
);
2412 static void vmxnet3_get_tx_stats_from_file(QEMUFile
*f
,
2413 struct UPT1_TxStats
*tx_stat
)
2415 tx_stat
->TSOPktsTxOK
= qemu_get_be64(f
);
2416 tx_stat
->TSOBytesTxOK
= qemu_get_be64(f
);
2417 tx_stat
->ucastPktsTxOK
= qemu_get_be64(f
);
2418 tx_stat
->ucastBytesTxOK
= qemu_get_be64(f
);
2419 tx_stat
->mcastPktsTxOK
= qemu_get_be64(f
);
2420 tx_stat
->mcastBytesTxOK
= qemu_get_be64(f
);
2421 tx_stat
->bcastPktsTxOK
= qemu_get_be64(f
);
2422 tx_stat
->bcastBytesTxOK
= qemu_get_be64(f
);
2423 tx_stat
->pktsTxError
= qemu_get_be64(f
);
2424 tx_stat
->pktsTxDiscard
= qemu_get_be64(f
);
2427 static void vmxnet3_put_tx_stats_to_file(QEMUFile
*f
,
2428 struct UPT1_TxStats
*tx_stat
)
2430 qemu_put_be64(f
, tx_stat
->TSOPktsTxOK
);
2431 qemu_put_be64(f
, tx_stat
->TSOBytesTxOK
);
2432 qemu_put_be64(f
, tx_stat
->ucastPktsTxOK
);
2433 qemu_put_be64(f
, tx_stat
->ucastBytesTxOK
);
2434 qemu_put_be64(f
, tx_stat
->mcastPktsTxOK
);
2435 qemu_put_be64(f
, tx_stat
->mcastBytesTxOK
);
2436 qemu_put_be64(f
, tx_stat
->bcastPktsTxOK
);
2437 qemu_put_be64(f
, tx_stat
->bcastBytesTxOK
);
2438 qemu_put_be64(f
, tx_stat
->pktsTxError
);
2439 qemu_put_be64(f
, tx_stat
->pktsTxDiscard
);
2442 static int vmxnet3_get_txq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2444 Vmxnet3TxqDescr
*r
= pv
;
2446 vmxnet3_get_ring_from_file(f
, &r
->tx_ring
);
2447 vmxnet3_get_ring_from_file(f
, &r
->comp_ring
);
2448 r
->intr_idx
= qemu_get_byte(f
);
2449 r
->tx_stats_pa
= qemu_get_be64(f
);
2451 vmxnet3_get_tx_stats_from_file(f
, &r
->txq_stats
);
2456 static void vmxnet3_put_txq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2458 Vmxnet3TxqDescr
*r
= pv
;
2460 vmxnet3_put_ring_to_file(f
, &r
->tx_ring
);
2461 vmxnet3_put_ring_to_file(f
, &r
->comp_ring
);
2462 qemu_put_byte(f
, r
->intr_idx
);
2463 qemu_put_be64(f
, r
->tx_stats_pa
);
2464 vmxnet3_put_tx_stats_to_file(f
, &r
->txq_stats
);
2467 static const VMStateInfo txq_descr_info
= {
2468 .name
= "txq_descr",
2469 .get
= vmxnet3_get_txq_descr
,
2470 .put
= vmxnet3_put_txq_descr
2473 static void vmxnet3_get_rx_stats_from_file(QEMUFile
*f
,
2474 struct UPT1_RxStats
*rx_stat
)
2476 rx_stat
->LROPktsRxOK
= qemu_get_be64(f
);
2477 rx_stat
->LROBytesRxOK
= qemu_get_be64(f
);
2478 rx_stat
->ucastPktsRxOK
= qemu_get_be64(f
);
2479 rx_stat
->ucastBytesRxOK
= qemu_get_be64(f
);
2480 rx_stat
->mcastPktsRxOK
= qemu_get_be64(f
);
2481 rx_stat
->mcastBytesRxOK
= qemu_get_be64(f
);
2482 rx_stat
->bcastPktsRxOK
= qemu_get_be64(f
);
2483 rx_stat
->bcastBytesRxOK
= qemu_get_be64(f
);
2484 rx_stat
->pktsRxOutOfBuf
= qemu_get_be64(f
);
2485 rx_stat
->pktsRxError
= qemu_get_be64(f
);
2488 static void vmxnet3_put_rx_stats_to_file(QEMUFile
*f
,
2489 struct UPT1_RxStats
*rx_stat
)
2491 qemu_put_be64(f
, rx_stat
->LROPktsRxOK
);
2492 qemu_put_be64(f
, rx_stat
->LROBytesRxOK
);
2493 qemu_put_be64(f
, rx_stat
->ucastPktsRxOK
);
2494 qemu_put_be64(f
, rx_stat
->ucastBytesRxOK
);
2495 qemu_put_be64(f
, rx_stat
->mcastPktsRxOK
);
2496 qemu_put_be64(f
, rx_stat
->mcastBytesRxOK
);
2497 qemu_put_be64(f
, rx_stat
->bcastPktsRxOK
);
2498 qemu_put_be64(f
, rx_stat
->bcastBytesRxOK
);
2499 qemu_put_be64(f
, rx_stat
->pktsRxOutOfBuf
);
2500 qemu_put_be64(f
, rx_stat
->pktsRxError
);
2503 static int vmxnet3_get_rxq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2505 Vmxnet3RxqDescr
*r
= pv
;
2508 for (i
= 0; i
< VMXNET3_RX_RINGS_PER_QUEUE
; i
++) {
2509 vmxnet3_get_ring_from_file(f
, &r
->rx_ring
[i
]);
2512 vmxnet3_get_ring_from_file(f
, &r
->comp_ring
);
2513 r
->intr_idx
= qemu_get_byte(f
);
2514 r
->rx_stats_pa
= qemu_get_be64(f
);
2516 vmxnet3_get_rx_stats_from_file(f
, &r
->rxq_stats
);
2521 static void vmxnet3_put_rxq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2523 Vmxnet3RxqDescr
*r
= pv
;
2526 for (i
= 0; i
< VMXNET3_RX_RINGS_PER_QUEUE
; i
++) {
2527 vmxnet3_put_ring_to_file(f
, &r
->rx_ring
[i
]);
2530 vmxnet3_put_ring_to_file(f
, &r
->comp_ring
);
2531 qemu_put_byte(f
, r
->intr_idx
);
2532 qemu_put_be64(f
, r
->rx_stats_pa
);
2533 vmxnet3_put_rx_stats_to_file(f
, &r
->rxq_stats
);
2536 static int vmxnet3_post_load(void *opaque
, int version_id
)
2538 VMXNET3State
*s
= opaque
;
2539 PCIDevice
*d
= PCI_DEVICE(s
);
2541 vmxnet_tx_pkt_init(&s
->tx_pkt
, s
->max_tx_frags
, s
->peer_has_vhdr
);
2542 vmxnet_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
2545 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2546 VMW_WRPRN("Failed to re-use MSI-X vectors");
2547 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2548 s
->msix_used
= false;
2553 vmxnet3_validate_queues(s
);
2554 vmxnet3_validate_interrupts(s
);
2559 static const VMStateInfo rxq_descr_info
= {
2560 .name
= "rxq_descr",
2561 .get
= vmxnet3_get_rxq_descr
,
2562 .put
= vmxnet3_put_rxq_descr
2565 static int vmxnet3_get_int_state(QEMUFile
*f
, void *pv
, size_t size
)
2567 Vmxnet3IntState
*r
= pv
;
2569 r
->is_masked
= qemu_get_byte(f
);
2570 r
->is_pending
= qemu_get_byte(f
);
2571 r
->is_asserted
= qemu_get_byte(f
);
2576 static void vmxnet3_put_int_state(QEMUFile
*f
, void *pv
, size_t size
)
2578 Vmxnet3IntState
*r
= pv
;
2580 qemu_put_byte(f
, r
->is_masked
);
2581 qemu_put_byte(f
, r
->is_pending
);
2582 qemu_put_byte(f
, r
->is_asserted
);
2585 static const VMStateInfo int_state_info
= {
2586 .name
= "int_state",
2587 .get
= vmxnet3_get_int_state
,
2588 .put
= vmxnet3_put_int_state
2591 static bool vmxnet3_vmstate_need_pcie_device(void *opaque
)
2593 VMXNET3State
*s
= VMXNET3(opaque
);
2595 return !(s
->compat_flags
& VMXNET3_COMPAT_FLAG_DISABLE_PCIE
);
2598 static bool vmxnet3_vmstate_test_pci_device(void *opaque
, int version_id
)
2600 return !vmxnet3_vmstate_need_pcie_device(opaque
);
2603 static const VMStateDescription vmstate_vmxnet3_pcie_device
= {
2604 .name
= "vmxnet3/pcie",
2606 .minimum_version_id
= 1,
2607 .needed
= vmxnet3_vmstate_need_pcie_device
,
2608 .fields
= (VMStateField
[]) {
2609 VMSTATE_PCIE_DEVICE(parent_obj
, VMXNET3State
),
2610 VMSTATE_END_OF_LIST()
2614 static const VMStateDescription vmstate_vmxnet3
= {
2617 .minimum_version_id
= 1,
2618 .pre_save
= vmxnet3_pre_save
,
2619 .post_load
= vmxnet3_post_load
,
2620 .fields
= (VMStateField
[]) {
2621 VMSTATE_STRUCT_TEST(parent_obj
, VMXNET3State
,
2622 vmxnet3_vmstate_test_pci_device
, 0,
2623 vmstate_pci_device
, PCIDevice
),
2624 VMSTATE_BOOL(rx_packets_compound
, VMXNET3State
),
2625 VMSTATE_BOOL(rx_vlan_stripping
, VMXNET3State
),
2626 VMSTATE_BOOL(lro_supported
, VMXNET3State
),
2627 VMSTATE_UINT32(rx_mode
, VMXNET3State
),
2628 VMSTATE_UINT32(mcast_list_len
, VMXNET3State
),
2629 VMSTATE_UINT32(mcast_list_buff_size
, VMXNET3State
),
2630 VMSTATE_UINT32_ARRAY(vlan_table
, VMXNET3State
, VMXNET3_VFT_SIZE
),
2631 VMSTATE_UINT32(mtu
, VMXNET3State
),
2632 VMSTATE_UINT16(max_rx_frags
, VMXNET3State
),
2633 VMSTATE_UINT32(max_tx_frags
, VMXNET3State
),
2634 VMSTATE_UINT8(event_int_idx
, VMXNET3State
),
2635 VMSTATE_BOOL(auto_int_masking
, VMXNET3State
),
2636 VMSTATE_UINT8(txq_num
, VMXNET3State
),
2637 VMSTATE_UINT8(rxq_num
, VMXNET3State
),
2638 VMSTATE_UINT32(device_active
, VMXNET3State
),
2639 VMSTATE_UINT32(last_command
, VMXNET3State
),
2640 VMSTATE_UINT32(link_status_and_speed
, VMXNET3State
),
2641 VMSTATE_UINT32(temp_mac
, VMXNET3State
),
2642 VMSTATE_UINT64(drv_shmem
, VMXNET3State
),
2643 VMSTATE_UINT64(temp_shared_guest_driver_memory
, VMXNET3State
),
2645 VMSTATE_ARRAY(txq_descr
, VMXNET3State
,
2646 VMXNET3_DEVICE_MAX_TX_QUEUES
, 0, txq_descr_info
,
2648 VMSTATE_ARRAY(rxq_descr
, VMXNET3State
,
2649 VMXNET3_DEVICE_MAX_RX_QUEUES
, 0, rxq_descr_info
,
2651 VMSTATE_ARRAY(interrupt_states
, VMXNET3State
, VMXNET3_MAX_INTRS
,
2652 0, int_state_info
, Vmxnet3IntState
),
2654 VMSTATE_END_OF_LIST()
2656 .subsections
= (const VMStateDescription
*[]) {
2657 &vmxstate_vmxnet3_mcast_list
,
2658 &vmstate_vmxnet3_pcie_device
,
2663 static Property vmxnet3_properties
[] = {
2664 DEFINE_NIC_PROPERTIES(VMXNET3State
, conf
),
2665 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State
, compat_flags
,
2666 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT
, false),
2667 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State
, compat_flags
,
2668 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT
, false),
2669 DEFINE_PROP_END_OF_LIST(),
2672 static void vmxnet3_realize(DeviceState
*qdev
, Error
**errp
)
2674 VMXNET3Class
*vc
= VMXNET3_DEVICE_GET_CLASS(qdev
);
2675 PCIDevice
*pci_dev
= PCI_DEVICE(qdev
);
2676 VMXNET3State
*s
= VMXNET3(qdev
);
2678 if (!(s
->compat_flags
& VMXNET3_COMPAT_FLAG_DISABLE_PCIE
)) {
2679 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2682 vc
->parent_dc_realize(qdev
, errp
);
2685 static void vmxnet3_class_init(ObjectClass
*class, void *data
)
2687 DeviceClass
*dc
= DEVICE_CLASS(class);
2688 PCIDeviceClass
*c
= PCI_DEVICE_CLASS(class);
2689 VMXNET3Class
*vc
= VMXNET3_DEVICE_CLASS(class);
2691 c
->realize
= vmxnet3_pci_realize
;
2692 c
->exit
= vmxnet3_pci_uninit
;
2693 c
->vendor_id
= PCI_VENDOR_ID_VMWARE
;
2694 c
->device_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2695 c
->revision
= PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION
;
2696 c
->class_id
= PCI_CLASS_NETWORK_ETHERNET
;
2697 c
->subsystem_vendor_id
= PCI_VENDOR_ID_VMWARE
;
2698 c
->subsystem_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2699 vc
->parent_dc_realize
= dc
->realize
;
2700 dc
->realize
= vmxnet3_realize
;
2701 dc
->desc
= "VMWare Paravirtualized Ethernet v3";
2702 dc
->reset
= vmxnet3_qdev_reset
;
2703 dc
->vmsd
= &vmstate_vmxnet3
;
2704 dc
->props
= vmxnet3_properties
;
2705 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
2708 static const TypeInfo vmxnet3_info
= {
2709 .name
= TYPE_VMXNET3
,
2710 .parent
= TYPE_PCI_DEVICE
,
2711 .class_size
= sizeof(VMXNET3Class
),
2712 .instance_size
= sizeof(VMXNET3State
),
2713 .class_init
= vmxnet3_class_init
,
2714 .instance_init
= vmxnet3_instance_init
,
2717 static void vmxnet3_register_types(void)
2719 VMW_CBPRN("vmxnet3_register_types called...");
2720 type_register_static(&vmxnet3_info
);
2723 type_init(vmxnet3_register_types
)