ide: also reset io_buffer_index for writes
[qemu/cris-port.git] / hw / piix_pci.c
blob358da58a800651e1cdcc3258fda33424f5caca9b
1 /*
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "hw.h"
26 #include "pc.h"
27 #include "pci.h"
28 #include "pci_host.h"
29 #include "isa.h"
30 #include "sysbus.h"
31 #include "range.h"
34 * I440FX chipset data sheet.
35 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
38 typedef PCIHostState I440FXState;
40 typedef struct PIIX3State {
41 PCIDevice dev;
42 int pci_irq_levels[4];
43 qemu_irq *pic;
44 } PIIX3State;
46 struct PCII440FXState {
47 PCIDevice dev;
48 target_phys_addr_t isa_page_descs[384 / 4];
49 uint8_t smm_enabled;
50 PIIX3State *piix3;
54 #define I440FX_PAM 0x59
55 #define I440FX_PAM_SIZE 7
56 #define I440FX_SMRAM 0x72
58 static void piix3_set_irq(void *opaque, int irq_num, int level);
60 /* return the global irq number corresponding to a given device irq
61 pin. We could also use the bus number to have a more precise
62 mapping. */
63 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
65 int slot_addend;
66 slot_addend = (pci_dev->devfn >> 3) - 1;
67 return (irq_num + slot_addend) & 3;
70 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
72 uint32_t addr;
74 // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
75 switch(r) {
76 case 3:
77 /* RAM */
78 cpu_register_physical_memory(start, end - start,
79 start);
80 break;
81 case 1:
82 /* ROM (XXX: not quite correct) */
83 cpu_register_physical_memory(start, end - start,
84 start | IO_MEM_ROM);
85 break;
86 case 2:
87 case 0:
88 /* XXX: should distinguish read/write cases */
89 for(addr = start; addr < end; addr += 4096) {
90 cpu_register_physical_memory(addr, 4096,
91 d->isa_page_descs[(addr - 0xa0000) >> 12]);
93 break;
97 static void i440fx_update_memory_mappings(PCII440FXState *d)
99 int i, r;
100 uint32_t smram, addr;
102 update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
103 for(i = 0; i < 12; i++) {
104 r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
105 update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
107 smram = d->dev.config[I440FX_SMRAM];
108 if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
109 cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
110 } else {
111 for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
112 cpu_register_physical_memory(addr, 4096,
113 d->isa_page_descs[(addr - 0xa0000) >> 12]);
118 static void i440fx_set_smm(int val, void *arg)
120 PCII440FXState *d = arg;
122 val = (val != 0);
123 if (d->smm_enabled != val) {
124 d->smm_enabled = val;
125 i440fx_update_memory_mappings(d);
130 /* XXX: suppress when better memory API. We make the assumption that
131 no device (in particular the VGA) changes the memory mappings in
132 the 0xa0000-0x100000 range */
133 void i440fx_init_memory_mappings(PCII440FXState *d)
135 int i;
136 for(i = 0; i < 96; i++) {
137 d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
141 static void i440fx_write_config(PCIDevice *dev,
142 uint32_t address, uint32_t val, int len)
144 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
146 /* XXX: implement SMRAM.D_LOCK */
147 pci_default_write_config(dev, address, val, len);
148 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
149 range_covers_byte(address, len, I440FX_SMRAM)) {
150 i440fx_update_memory_mappings(d);
154 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
156 PCII440FXState *d = opaque;
157 int ret, i;
159 ret = pci_device_load(&d->dev, f);
160 if (ret < 0)
161 return ret;
162 i440fx_update_memory_mappings(d);
163 qemu_get_8s(f, &d->smm_enabled);
165 if (version_id == 2)
166 for (i = 0; i < 4; i++)
167 d->piix3->pci_irq_levels[i] = qemu_get_be32(f);
169 return 0;
172 static int i440fx_post_load(void *opaque, int version_id)
174 PCII440FXState *d = opaque;
176 i440fx_update_memory_mappings(d);
177 return 0;
180 static const VMStateDescription vmstate_i440fx = {
181 .name = "I440FX",
182 .version_id = 3,
183 .minimum_version_id = 3,
184 .minimum_version_id_old = 1,
185 .load_state_old = i440fx_load_old,
186 .post_load = i440fx_post_load,
187 .fields = (VMStateField []) {
188 VMSTATE_PCI_DEVICE(dev, PCII440FXState),
189 VMSTATE_UINT8(smm_enabled, PCII440FXState),
190 VMSTATE_END_OF_LIST()
194 static int i440fx_pcihost_initfn(SysBusDevice *dev)
196 I440FXState *s = FROM_SYSBUS(I440FXState, dev);
198 pci_host_conf_register_ioport(0xcf8, s);
200 pci_host_data_register_ioport(0xcfc, s);
201 return 0;
204 static int i440fx_initfn(PCIDevice *dev)
206 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
208 pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
209 pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
210 d->dev.config[0x08] = 0x02; // revision
211 pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
213 d->dev.config[I440FX_SMRAM] = 0x02;
215 cpu_smm_register(&i440fx_set_smm, d);
216 return 0;
219 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
221 DeviceState *dev;
222 PCIBus *b;
223 PCIDevice *d;
224 I440FXState *s;
225 PIIX3State *piix3;
227 dev = qdev_create(NULL, "i440FX-pcihost");
228 s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
229 b = pci_bus_new(&s->busdev.qdev, NULL, 0);
230 s->bus = b;
231 qdev_init_nofail(dev);
233 d = pci_create_simple(b, 0, "i440FX");
234 *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
236 piix3 = DO_UPCAST(PIIX3State, dev,
237 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
238 piix3->pic = pic;
239 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
240 (*pi440fx_state)->piix3 = piix3;
242 *piix3_devfn = piix3->dev.devfn;
244 ram_size = ram_size / 8 / 1024 / 1024;
245 if (ram_size > 255)
246 ram_size = 255;
247 (*pi440fx_state)->dev.config[0x57]=ram_size;
249 return b;
252 /* PIIX3 PCI to ISA bridge */
254 static void piix3_set_irq(void *opaque, int irq_num, int level)
256 int i, pic_irq, pic_level;
257 PIIX3State *piix3 = opaque;
259 piix3->pci_irq_levels[irq_num] = level;
261 /* now we change the pic irq level according to the piix irq mappings */
262 /* XXX: optimize */
263 pic_irq = piix3->dev.config[0x60 + irq_num];
264 if (pic_irq < 16) {
265 /* The pic level is the logical OR of all the PCI irqs mapped
266 to it */
267 pic_level = 0;
268 for (i = 0; i < 4; i++) {
269 if (pic_irq == piix3->dev.config[0x60 + i])
270 pic_level |= piix3->pci_irq_levels[i];
272 qemu_set_irq(piix3->pic[pic_irq], pic_level);
276 static void piix3_reset(void *opaque)
278 PIIX3State *d = opaque;
279 uint8_t *pci_conf = d->dev.config;
281 pci_conf[0x04] = 0x07; // master, memory and I/O
282 pci_conf[0x05] = 0x00;
283 pci_conf[0x06] = 0x00;
284 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
285 pci_conf[0x4c] = 0x4d;
286 pci_conf[0x4e] = 0x03;
287 pci_conf[0x4f] = 0x00;
288 pci_conf[0x60] = 0x80;
289 pci_conf[0x61] = 0x80;
290 pci_conf[0x62] = 0x80;
291 pci_conf[0x63] = 0x80;
292 pci_conf[0x69] = 0x02;
293 pci_conf[0x70] = 0x80;
294 pci_conf[0x76] = 0x0c;
295 pci_conf[0x77] = 0x0c;
296 pci_conf[0x78] = 0x02;
297 pci_conf[0x79] = 0x00;
298 pci_conf[0x80] = 0x00;
299 pci_conf[0x82] = 0x00;
300 pci_conf[0xa0] = 0x08;
301 pci_conf[0xa2] = 0x00;
302 pci_conf[0xa3] = 0x00;
303 pci_conf[0xa4] = 0x00;
304 pci_conf[0xa5] = 0x00;
305 pci_conf[0xa6] = 0x00;
306 pci_conf[0xa7] = 0x00;
307 pci_conf[0xa8] = 0x0f;
308 pci_conf[0xaa] = 0x00;
309 pci_conf[0xab] = 0x00;
310 pci_conf[0xac] = 0x00;
311 pci_conf[0xae] = 0x00;
313 memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
316 static const VMStateDescription vmstate_piix3 = {
317 .name = "PIIX3",
318 .version_id = 3,
319 .minimum_version_id = 2,
320 .minimum_version_id_old = 2,
321 .fields = (VMStateField []) {
322 VMSTATE_PCI_DEVICE(dev, PIIX3State),
323 VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
324 VMSTATE_END_OF_LIST()
328 static int piix3_initfn(PCIDevice *dev)
330 PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
331 uint8_t *pci_conf;
333 isa_bus_new(&d->dev.qdev);
335 pci_conf = d->dev.config;
336 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
337 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
338 pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
340 qemu_register_reset(piix3_reset, d);
341 return 0;
344 static PCIDeviceInfo i440fx_info[] = {
346 .qdev.name = "i440FX",
347 .qdev.desc = "Host bridge",
348 .qdev.size = sizeof(PCII440FXState),
349 .qdev.vmsd = &vmstate_i440fx,
350 .qdev.no_user = 1,
351 .no_hotplug = 1,
352 .init = i440fx_initfn,
353 .config_write = i440fx_write_config,
355 .qdev.name = "PIIX3",
356 .qdev.desc = "ISA bridge",
357 .qdev.size = sizeof(PIIX3State),
358 .qdev.vmsd = &vmstate_piix3,
359 .qdev.no_user = 1,
360 .no_hotplug = 1,
361 .init = piix3_initfn,
363 /* end of list */
367 static SysBusDeviceInfo i440fx_pcihost_info = {
368 .init = i440fx_pcihost_initfn,
369 .qdev.name = "i440FX-pcihost",
370 .qdev.fw_name = "pci",
371 .qdev.size = sizeof(I440FXState),
372 .qdev.no_user = 1,
375 static void i440fx_register(void)
377 sysbus_register_withprop(&i440fx_pcihost_info);
378 pci_qdev_register_many(i440fx_info);
380 device_init(i440fx_register);