hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "hw/arm/xlnx-zynqmp.h"
  19 #include "hw/intc/arm_gic_common.h"
  20 #include "exec/address-spaces.h"
  21
  22 #define GIC_NUM_SPI_INTR 160
  23
  24 #define ARM_PHYS_TIMER_PPI  30
  25 #define ARM_VIRT_TIMER_PPI  27
  26
  27 #define GIC_BASE_ADDR       0xf9000000
  28 #define GIC_DIST_ADDR       0xf9010000
  29 #define GIC_CPU_ADDR        0xf9020000
  30
  31 #define SATA_INTR           133
  32 #define SATA_ADDR           0xFD0C0000
  33 #define SATA_NUM_PORTS      2
  34
  35 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  36     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  37 };
  38
  39 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  40     57, 59, 61, 63,
  41 };
  42
  43 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  44     0xFF000000, 0xFF010000,
  45 };
  46
  47 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  48     21, 22,
  49 };
  50
  51 typedef struct XlnxZynqMPGICRegion {
  52     int region_index;
  53     uint32_t address;
  54 } XlnxZynqMPGICRegion;
  55
  56 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
  57     { .region_index = 0, .address = GIC_DIST_ADDR, },
  58     { .region_index = 1, .address = GIC_CPU_ADDR,  },
  59 };
  60
  61 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
  62 {
  63     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
  64 }
  65
  66 static void xlnx_zynqmp_init(Object *obj)
  67 {
  68     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
  69     int i;
  70
  71     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
  72         object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
  73                           "cortex-a53-" TYPE_ARM_CPU);
  74         object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
  75                                   &error_abort);
  76     }
  77
  78     for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
  79         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
  80                           "cortex-r5-" TYPE_ARM_CPU);
  81         object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
  82                                   &error_abort);
  83     }
  84
  85     object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
  86     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
  87
  88     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
  89         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
  90         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
  91     }
  92
  93     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
  94         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
  95         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
  96     }
  97
  98     object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
  99     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
 100 }
 101
 102 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 103 {
 104     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 105     MemoryRegion *system_memory = get_system_memory();
 106     uint8_t i;
 107     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 108     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 109     Error *err = NULL;
 110
 111     /* Create the four OCM banks */
 112     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 113         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 114
 115         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 116                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 117         vmstate_register_ram_global(&s->ocm_ram[i]);
 118         memory_region_add_subregion(get_system_memory(),
 119                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 120                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 121                                     &s->ocm_ram[i]);
 122
 123         g_free(ocm_name);
 124     }
 125
 126     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 127     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 128     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
 129     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 130     if (err) {
 131         error_propagate(errp, err);
 132         return;
 133     }
 134     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 135     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 136         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 137         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 138         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
 139         uint32_t addr = r->address;
 140         int j;
 141
 142         sysbus_mmio_map(gic, r->region_index, addr);
 143
 144         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 145             MemoryRegion *alias = &s->gic_mr[i][j];
 146
 147             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 148             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 149                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
 150             memory_region_add_subregion(system_memory, addr, alias);
 151         }
 152     }
 153
 154     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 155         qemu_irq irq;
 156         char *name;
 157
 158         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 159                                 "psci-conduit", &error_abort);
 160
 161         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 162         if (strcmp(name, boot_cpu)) {
 163             /* Secondary CPUs start in PSCI powered-down state */
 164             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
 165                                      "start-powered-off", &error_abort);
 166         } else {
 167             s->boot_cpu_ptr = &s->apu_cpu[i];
 168         }
 169         g_free(name);
 170
 171         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
 172                                 "reset-cbar", &error_abort);
 173         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
 174                                  &err);
 175         if (err) {
 176             error_propagate(errp, err);
 177             return;
 178         }
 179
 180         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 181                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 182                                             ARM_CPU_IRQ));
 183         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 184                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 185         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
 186         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 187                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 188         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
 189     }
 190
 191     for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
 192         char *name;
 193
 194         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 195         if (strcmp(name, boot_cpu)) {
 196             /* Secondary CPUs start in PSCI powered-down state */
 197             object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
 198                                      "start-powered-off", &error_abort);
 199         } else {
 200             s->boot_cpu_ptr = &s->rpu_cpu[i];
 201         }
 202         g_free(name);
 203
 204         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
 205                                  &error_abort);
 206         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
 207                                  &err);
 208         if (err) {
 209             error_propagate(errp, err);
 210             return;
 211         }
 212     }
 213
 214     if (!s->boot_cpu_ptr) {
 215         error_setg(errp, "ZynqMP Boot cpu %s not found\n", boot_cpu);
 216         return;
 217     }
 218
 219     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 220         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 221     }
 222
 223     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 224         NICInfo *nd = &nd_table[i];
 225
 226         if (nd->used) {
 227             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 228             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 229         }
 230         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 231         if (err) {
 232             error_propagate(errp, err);
 233             return;
 234         }
 235         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 236         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 237                            gic_spi[gem_intr[i]]);
 238     }
 239
 240     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 241         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 242         if (err) {
 243             error_propagate(errp, err);
 244             return;
 245         }
 246         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 247         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 248                            gic_spi[uart_intr[i]]);
 249     }
 250
 251     object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
 252                             &error_abort);
 253     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 254     if (err) {
 255         error_propagate(errp, err);
 256         return;
 257     }
 258
 259     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 260     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 261 }
 262
 263 static Property xlnx_zynqmp_props[] = {
 264     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 265     DEFINE_PROP_END_OF_LIST()
 266 };
 267
 268 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 269 {
 270     DeviceClass *dc = DEVICE_CLASS(oc);
 271
 272     dc->props = xlnx_zynqmp_props;
 273     dc->realize = xlnx_zynqmp_realize;
 274 }
 275
 276 static const TypeInfo xlnx_zynqmp_type_info = {
 277     .name = TYPE_XLNX_ZYNQMP,
 278     .parent = TYPE_DEVICE,
 279     .instance_size = sizeof(XlnxZynqMPState),
 280     .instance_init = xlnx_zynqmp_init,
 281     .class_init = xlnx_zynqmp_class_init,
 282 };
 283
 284 static void xlnx_zynqmp_register_types(void)
 285 {
 286     type_register_static(&xlnx_zynqmp_type_info);
 287 }
 288
 289 type_init(xlnx_zynqmp_register_types)