hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "isa.h"
  29 #include "sysbus.h"
  30
  31 typedef uint32_t pci_addr_t;
  32 #include "pci_host.h"
  33
  34 typedef PCIHostState I440FXState;
  35
  36 static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
  37 {
  38     I440FXState *s = opaque;
  39     s->config_reg = val;
  40 }
  41
  42 static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
  43 {
  44     I440FXState *s = opaque;
  45     return s->config_reg;
  46 }
  47
  48 static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);
  49
  50 /* return the global irq number corresponding to a given device irq
  51    pin. We could also use the bus number to have a more precise
  52    mapping. */
  53 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
  54 {
  55     int slot_addend;
  56     slot_addend = (pci_dev->devfn >> 3) - 1;
  57     return (irq_num + slot_addend) & 3;
  58 }
  59
  60 static target_phys_addr_t isa_page_descs[384 / 4];
  61 static uint8_t smm_enabled;
  62 static int pci_irq_levels[4];
  63
  64 static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
  65 {
  66     uint32_t addr;
  67
  68     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  69     switch(r) {
  70     case 3:
  71         /* RAM */
  72         cpu_register_physical_memory(start, end - start,
  73                                      start);
  74         break;
  75     case 1:
  76         /* ROM (XXX: not quite correct) */
  77         cpu_register_physical_memory(start, end - start,
  78                                      start | IO_MEM_ROM);
  79         break;
  80     case 2:
  81     case 0:
  82         /* XXX: should distinguish read/write cases */
  83         for(addr = start; addr < end; addr += 4096) {
  84             cpu_register_physical_memory(addr, 4096,
  85                                          isa_page_descs[(addr - 0xa0000) >> 12]);
  86         }
  87         break;
  88     }
  89 }
  90
  91 static void i440fx_update_memory_mappings(PCIDevice *d)
  92 {
  93     int i, r;
  94     uint32_t smram, addr;
  95
  96     update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
  97     for(i = 0; i < 12; i++) {
  98         r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
  99         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 100     }
 101     smram = d->config[0x72];
 102     if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 103         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 104     } else {
 105         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 106             cpu_register_physical_memory(addr, 4096,
 107                                          isa_page_descs[(addr - 0xa0000) >> 12]);
 108         }
 109     }
 110 }
 111
 112 void i440fx_set_smm(PCIDevice *d, int val)
 113 {
 114     val = (val != 0);
 115     if (smm_enabled != val) {
 116         smm_enabled = val;
 117         i440fx_update_memory_mappings(d);
 118     }
 119 }
 120
 121
 122 /* XXX: suppress when better memory API. We make the assumption that
 123    no device (in particular the VGA) changes the memory mappings in
 124    the 0xa0000-0x100000 range */
 125 void i440fx_init_memory_mappings(PCIDevice *d)
 126 {
 127     int i;
 128     for(i = 0; i < 96; i++) {
 129         isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 130     }
 131 }
 132
 133 static void i440fx_write_config(PCIDevice *d,
 134                                 uint32_t address, uint32_t val, int len)
 135 {
 136     /* XXX: implement SMRAM.D_LOCK */
 137     pci_default_write_config(d, address, val, len);
 138     if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
 139         i440fx_update_memory_mappings(d);
 140 }
 141
 142 static void i440fx_save(QEMUFile* f, void *opaque)
 143 {
 144     PCIDevice *d = opaque;
 145     int i;
 146
 147     pci_device_save(d, f);
 148     qemu_put_8s(f, &smm_enabled);
 149
 150     for (i = 0; i < 4; i++)
 151         qemu_put_be32(f, pci_irq_levels[i]);
 152 }
 153
 154 static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
 155 {
 156     PCIDevice *d = opaque;
 157     int ret, i;
 158
 159     if (version_id > 2)
 160         return -EINVAL;
 161     ret = pci_device_load(d, f);
 162     if (ret < 0)
 163         return ret;
 164     i440fx_update_memory_mappings(d);
 165     qemu_get_8s(f, &smm_enabled);
 166
 167     if (version_id >= 2)
 168         for (i = 0; i < 4; i++)
 169             pci_irq_levels[i] = qemu_get_be32(f);
 170
 171     return 0;
 172 }
 173
 174 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 175 {
 176     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 177
 178     register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
 179     register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
 180
 181     register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
 182     register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
 183     register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
 184     register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
 185     register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
 186     register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
 187     return 0;
 188 }
 189
 190 static int i440fx_initfn(PCIDevice *d)
 191 {
 192     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
 193     pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441);
 194     d->config[0x08] = 0x02; // revision
 195     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 196     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 197
 198     d->config[0x72] = 0x02; /* SMRAM */
 199
 200     register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
 201     return 0;
 202 }
 203
 204 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
 205 {
 206     DeviceState *dev;
 207     PCIBus *b;
 208     PCIDevice *d;
 209     I440FXState *s;
 210
 211     dev = qdev_create(NULL, "i440FX-pcihost");
 212     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 213     b = pci_register_bus(&s->busdev.qdev, "pci.0",
 214                          piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
 215     s->bus = b;
 216     qdev_init(dev);
 217
 218     d = pci_create_simple(b, 0, "i440FX");
 219     *pi440fx_state = d;
 220
 221     return b;
 222 }
 223
 224 /* PIIX3 PCI to ISA bridge */
 225
 226 static PCIDevice *piix3_dev;
 227 PCIDevice *piix4_dev;
 228
 229 static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
 230 {
 231     int i, pic_irq, pic_level;
 232
 233     pci_irq_levels[irq_num] = level;
 234
 235     /* now we change the pic irq level according to the piix irq mappings */
 236     /* XXX: optimize */
 237     pic_irq = piix3_dev->config[0x60 + irq_num];
 238     if (pic_irq < 16) {
 239         /* The pic level is the logical OR of all the PCI irqs mapped
 240            to it */
 241         pic_level = 0;
 242         for (i = 0; i < 4; i++) {
 243             if (pic_irq == piix3_dev->config[0x60 + i])
 244                 pic_level |= pci_irq_levels[i];
 245         }
 246         qemu_set_irq(pic[pic_irq], pic_level);
 247     }
 248 }
 249
 250 static void piix3_reset(void *opaque)
 251 {
 252     PCIDevice *d = opaque;
 253     uint8_t *pci_conf = d->config;
 254
 255     pci_conf[0x04] = 0x07; // master, memory and I/O
 256     pci_conf[0x05] = 0x00;
 257     pci_conf[0x06] = 0x00;
 258     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 259     pci_conf[0x4c] = 0x4d;
 260     pci_conf[0x4e] = 0x03;
 261     pci_conf[0x4f] = 0x00;
 262     pci_conf[0x60] = 0x80;
 263     pci_conf[0x61] = 0x80;
 264     pci_conf[0x62] = 0x80;
 265     pci_conf[0x63] = 0x80;
 266     pci_conf[0x69] = 0x02;
 267     pci_conf[0x70] = 0x80;
 268     pci_conf[0x76] = 0x0c;
 269     pci_conf[0x77] = 0x0c;
 270     pci_conf[0x78] = 0x02;
 271     pci_conf[0x79] = 0x00;
 272     pci_conf[0x80] = 0x00;
 273     pci_conf[0x82] = 0x00;
 274     pci_conf[0xa0] = 0x08;
 275     pci_conf[0xa2] = 0x00;
 276     pci_conf[0xa3] = 0x00;
 277     pci_conf[0xa4] = 0x00;
 278     pci_conf[0xa5] = 0x00;
 279     pci_conf[0xa6] = 0x00;
 280     pci_conf[0xa7] = 0x00;
 281     pci_conf[0xa8] = 0x0f;
 282     pci_conf[0xaa] = 0x00;
 283     pci_conf[0xab] = 0x00;
 284     pci_conf[0xac] = 0x00;
 285     pci_conf[0xae] = 0x00;
 286
 287     memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
 288 }
 289
 290 static void piix4_reset(void *opaque)
 291 {
 292     PCIDevice *d = opaque;
 293     uint8_t *pci_conf = d->config;
 294
 295     pci_conf[0x04] = 0x07; // master, memory and I/O
 296     pci_conf[0x05] = 0x00;
 297     pci_conf[0x06] = 0x00;
 298     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 299     pci_conf[0x4c] = 0x4d;
 300     pci_conf[0x4e] = 0x03;
 301     pci_conf[0x4f] = 0x00;
 302     pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
 303     pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
 304     pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
 305     pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
 306     pci_conf[0x69] = 0x02;
 307     pci_conf[0x70] = 0x80;
 308     pci_conf[0x76] = 0x0c;
 309     pci_conf[0x77] = 0x0c;
 310     pci_conf[0x78] = 0x02;
 311     pci_conf[0x79] = 0x00;
 312     pci_conf[0x80] = 0x00;
 313     pci_conf[0x82] = 0x00;
 314     pci_conf[0xa0] = 0x08;
 315     pci_conf[0xa2] = 0x00;
 316     pci_conf[0xa3] = 0x00;
 317     pci_conf[0xa4] = 0x00;
 318     pci_conf[0xa5] = 0x00;
 319     pci_conf[0xa6] = 0x00;
 320     pci_conf[0xa7] = 0x00;
 321     pci_conf[0xa8] = 0x0f;
 322     pci_conf[0xaa] = 0x00;
 323     pci_conf[0xab] = 0x00;
 324     pci_conf[0xac] = 0x00;
 325     pci_conf[0xae] = 0x00;
 326
 327     memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
 328 }
 329
 330 static void piix_save(QEMUFile* f, void *opaque)
 331 {
 332     PCIDevice *d = opaque;
 333     pci_device_save(d, f);
 334 }
 335
 336 static int piix_load(QEMUFile* f, void *opaque, int version_id)
 337 {
 338     PCIDevice *d = opaque;
 339     if (version_id != 2)
 340         return -EINVAL;
 341     return pci_device_load(d, f);
 342 }
 343
 344 static int piix3_initfn(PCIDevice *d)
 345 {
 346     uint8_t *pci_conf;
 347
 348     isa_bus_new(&d->qdev);
 349     register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
 350
 351     pci_conf = d->config;
 352     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 353     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 354     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 355     pci_conf[PCI_HEADER_TYPE] =
 356         PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
 357
 358     piix3_dev = d;
 359     piix3_reset(d);
 360     qemu_register_reset(piix3_reset, d);
 361     return 0;
 362 }
 363
 364 static int piix4_initfn(PCIDevice *d)
 365 {
 366     uint8_t *pci_conf;
 367
 368     register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
 369
 370     pci_conf = d->config;
 371     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 372     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
 373     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 374     pci_conf[PCI_HEADER_TYPE] =
 375         PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
 376
 377     piix4_dev = d;
 378     piix4_reset(d);
 379     qemu_register_reset(piix4_reset, d);
 380     return 0;
 381 }
 382
 383 int piix3_init(PCIBus *bus, int devfn)
 384 {
 385     PCIDevice *d;
 386
 387     d = pci_create_simple(bus, devfn, "PIIX3");
 388     return d->devfn;
 389 }
 390
 391 int piix4_init(PCIBus *bus, int devfn)
 392 {
 393     PCIDevice *d;
 394
 395     d = pci_create_simple(bus, devfn, "PIIX4");
 396     return d->devfn;
 397 }
 398
 399 static PCIDeviceInfo i440fx_info[] = {
 400     {
 401         .qdev.name    = "i440FX",
 402         .qdev.desc    = "Host bridge",
 403         .qdev.size    = sizeof(PCIDevice),
 404         .qdev.no_user = 1,
 405         .init         = i440fx_initfn,
 406         .config_write = i440fx_write_config,
 407     },{
 408         .qdev.name    = "PIIX3",
 409         .qdev.desc    = "ISA bridge",
 410         .qdev.size    = sizeof(PCIDevice),
 411         .qdev.no_user = 1,
 412         .init         = piix3_initfn,
 413     },{
 414         .qdev.name    = "PIIX4",
 415         .qdev.desc    = "ISA bridge",
 416         .qdev.size    = sizeof(PCIDevice),
 417         .qdev.no_user = 1,
 418         .init         = piix4_initfn,
 419     },{
 420         /* end of list */
 421     }
 422 };
 423
 424 static SysBusDeviceInfo i440fx_pcihost_info = {
 425     .init         = i440fx_pcihost_initfn,
 426     .qdev.name    = "i440FX-pcihost",
 427     .qdev.size    = sizeof(I440FXState),
 428     .qdev.no_user = 1,
 429 };
 430
 431 static void i440fx_register(void)
 432 {
 433     sysbus_register_withprop(&i440fx_pcihost_info);
 434     pci_qdev_register_many(i440fx_info);
 435 }
 436 device_init(i440fx_register);