hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31 #ifdef DEBUG_PCI
  32 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  33 #else
  34 # define PCI_DPRINTF(format, ...)       do { } while (0)
  35 #endif
  36
  37 struct PCIBus {
  38     BusState qbus;
  39     int bus_num;
  40     int devfn_min;
  41     pci_set_irq_fn set_irq;
  42     pci_map_irq_fn map_irq;
  43     uint32_t config_reg; /* XXX: suppress */
  44     /* low level pic */
  45     SetIRQFunc *low_set_irq;
  46     qemu_irq *irq_opaque;
  47     PCIDevice *devices[256];
  48     PCIDevice *parent_dev;
  49     PCIBus *next;
  50     /* The bus IRQ state is the logical OR of the connected devices.
  51        Keep a count of the number of devices with raised IRQs.  */
  52     int nirq;
  53     int *irq_count;
  54 };
  55
  56 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  57
  58 static struct BusInfo pci_bus_info = {
  59     .name       = "PCI",
  60     .size       = sizeof(PCIBus),
  61     .print_dev  = pcibus_dev_print,
  62     .props      = (Property[]) {
  63         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  64         DEFINE_PROP_END_OF_LIST()
  65     }
  66 };
  67
  68 static void pci_update_mappings(PCIDevice *d);
  69 static void pci_set_irq(void *opaque, int irq_num, int level);
  70
  71 target_phys_addr_t pci_mem_base;
  72 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  73 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  74 static PCIBus *first_bus;
  75
  76 static const VMStateDescription vmstate_pcibus = {
  77     .name = "PCIBUS",
  78     .version_id = 1,
  79     .minimum_version_id = 1,
  80     .minimum_version_id_old = 1,
  81     .fields      = (VMStateField []) {
  82         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  83         VMSTATE_INT32_VARRAY(irq_count, PCIBus, nirq),
  84         VMSTATE_END_OF_LIST()
  85     }
  86 };
  87
  88 static void pci_bus_reset(void *opaque)
  89 {
  90     PCIBus *bus = opaque;
  91     int i;
  92
  93     for (i = 0; i < bus->nirq; i++) {
  94         bus->irq_count[i] = 0;
  95     }
  96     for (i = 0; i < 256; i++) {
  97         if (bus->devices[i])
  98             memset(bus->devices[i]->irq_state, 0,
  99                    sizeof(bus->devices[i]->irq_state));
 100     }
 101 }
 102
 103 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 104                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 105                          qemu_irq *pic, int devfn_min, int nirq)
 106 {
 107     PCIBus *bus;
 108     static int nbus = 0;
 109
 110     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
 111     bus->set_irq = set_irq;
 112     bus->map_irq = map_irq;
 113     bus->irq_opaque = pic;
 114     bus->devfn_min = devfn_min;
 115     bus->nirq = nirq;
 116     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 117     bus->next = first_bus;
 118     first_bus = bus;
 119     vmstate_register(nbus++, &vmstate_pcibus, bus);
 120     qemu_register_reset(pci_bus_reset, bus);
 121     return bus;
 122 }
 123
 124 static PCIBus *pci_register_secondary_bus(PCIDevice *dev,
 125                                           pci_map_irq_fn map_irq,
 126                                           const char *name)
 127 {
 128     PCIBus *bus;
 129
 130     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, &dev->qdev, name));
 131     bus->map_irq = map_irq;
 132     bus->parent_dev = dev;
 133     bus->next = dev->bus->next;
 134     dev->bus->next = bus;
 135     return bus;
 136 }
 137
 138 int pci_bus_num(PCIBus *s)
 139 {
 140     return s->bus_num;
 141 }
 142
 143 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 144 {
 145     PCIDevice *s = container_of(pv, PCIDevice, config);
 146     uint8_t config[size];
 147     int i;
 148
 149     qemu_get_buffer(f, config, size);
 150     for (i = 0; i < size; ++i)
 151         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 152             return -EINVAL;
 153     memcpy(s->config, config, size);
 154
 155     pci_update_mappings(s);
 156
 157     return 0;
 158 }
 159
 160 /* just put buffer */
 161 static void put_pci_config_device(QEMUFile *f, const void *pv, size_t size)
 162 {
 163     const uint8_t *v = pv;
 164     qemu_put_buffer(f, v, size);
 165 }
 166
 167 static VMStateInfo vmstate_info_pci_config = {
 168     .name = "pci config",
 169     .get  = get_pci_config_device,
 170     .put  = put_pci_config_device,
 171 };
 172
 173 const VMStateDescription vmstate_pci_device = {
 174     .name = "PCIDevice",
 175     .version_id = 2,
 176     .minimum_version_id = 1,
 177     .minimum_version_id_old = 1,
 178     .fields      = (VMStateField []) {
 179         VMSTATE_INT32_LE(version_id, PCIDevice),
 180         VMSTATE_SINGLE(config, PCIDevice, 0, vmstate_info_pci_config,
 181                        typeof_field(PCIDevice,config)),
 182         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, 4, 2),
 183         VMSTATE_END_OF_LIST()
 184     }
 185 };
 186
 187 void pci_device_save(PCIDevice *s, QEMUFile *f)
 188 {
 189     vmstate_save_state(f, &vmstate_pci_device, s);
 190 }
 191
 192 int pci_device_load(PCIDevice *s, QEMUFile *f)
 193 {
 194     return vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
 195 }
 196
 197 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 198 {
 199     uint16_t *id;
 200
 201     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 202     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 203     id[1] = cpu_to_le16(pci_default_sub_device_id);
 204     return 0;
 205 }
 206
 207 /*
 208  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 209  */
 210 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 211 {
 212     const char *p;
 213     char *e;
 214     unsigned long val;
 215     unsigned long dom = 0, bus = 0;
 216     unsigned slot = 0;
 217
 218     p = addr;
 219     val = strtoul(p, &e, 16);
 220     if (e == p)
 221         return -1;
 222     if (*e == ':') {
 223         bus = val;
 224         p = e + 1;
 225         val = strtoul(p, &e, 16);
 226         if (e == p)
 227             return -1;
 228         if (*e == ':') {
 229             dom = bus;
 230             bus = val;
 231             p = e + 1;
 232             val = strtoul(p, &e, 16);
 233             if (e == p)
 234                 return -1;
 235         }
 236     }
 237
 238     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 239         return -1;
 240
 241     slot = val;
 242
 243     if (*e)
 244         return -1;
 245
 246     /* Note: QEMU doesn't implement domains other than 0 */
 247     if (dom != 0 || pci_find_bus(bus) == NULL)
 248         return -1;
 249
 250     *domp = dom;
 251     *busp = bus;
 252     *slotp = slot;
 253     return 0;
 254 }
 255
 256 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 257                      unsigned *slotp)
 258 {
 259     /* strip legacy tag */
 260     if (!strncmp(addr, "pci_addr=", 9)) {
 261         addr += 9;
 262     }
 263     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 264         monitor_printf(mon, "Invalid pci address\n");
 265         return -1;
 266     }
 267     return 0;
 268 }
 269
 270 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 271 {
 272     int dom, bus;
 273     unsigned slot;
 274
 275     if (!devaddr) {
 276         *devfnp = -1;
 277         return pci_find_bus(0);
 278     }
 279
 280     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 281         return NULL;
 282     }
 283
 284     *devfnp = slot << 3;
 285     return pci_find_bus(bus);
 286 }
 287
 288 static void pci_init_cmask(PCIDevice *dev)
 289 {
 290     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 291     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 292     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 293     dev->cmask[PCI_REVISION_ID] = 0xff;
 294     dev->cmask[PCI_CLASS_PROG] = 0xff;
 295     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 296     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 297     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 298 }
 299
 300 static void pci_init_wmask(PCIDevice *dev)
 301 {
 302     int i;
 303     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 304     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 305     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 306                               | PCI_COMMAND_MASTER;
 307     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 308         dev->wmask[i] = 0xff;
 309 }
 310
 311 /* -1 for devfn means auto assign */
 312 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 313                                          const char *name, int devfn,
 314                                          PCIConfigReadFunc *config_read,
 315                                          PCIConfigWriteFunc *config_write)
 316 {
 317     if (devfn < 0) {
 318         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 319             if (!bus->devices[devfn])
 320                 goto found;
 321         }
 322         return NULL;
 323     found: ;
 324     } else if (bus->devices[devfn]) {
 325         return NULL;
 326     }
 327     pci_dev->bus = bus;
 328     pci_dev->devfn = devfn;
 329     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 330     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 331     pci_set_default_subsystem_id(pci_dev);
 332     pci_init_cmask(pci_dev);
 333     pci_init_wmask(pci_dev);
 334
 335     if (!config_read)
 336         config_read = pci_default_read_config;
 337     if (!config_write)
 338         config_write = pci_default_write_config;
 339     pci_dev->config_read = config_read;
 340     pci_dev->config_write = config_write;
 341     bus->devices[devfn] = pci_dev;
 342     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 343     pci_dev->version_id = 2; /* Current pci device vmstate version */
 344     return pci_dev;
 345 }
 346
 347 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 348                                int instance_size, int devfn,
 349                                PCIConfigReadFunc *config_read,
 350                                PCIConfigWriteFunc *config_write)
 351 {
 352     PCIDevice *pci_dev;
 353
 354     pci_dev = qemu_mallocz(instance_size);
 355     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 356                                      config_read, config_write);
 357     return pci_dev;
 358 }
 359 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 360 {
 361     return addr + pci_mem_base;
 362 }
 363
 364 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 365 {
 366     PCIIORegion *r;
 367     int i;
 368
 369     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 370         r = &pci_dev->io_regions[i];
 371         if (!r->size || r->addr == -1)
 372             continue;
 373         if (r->type == PCI_ADDRESS_SPACE_IO) {
 374             isa_unassign_ioport(r->addr, r->size);
 375         } else {
 376             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 377                                                      r->size,
 378                                                      IO_MEM_UNASSIGNED);
 379         }
 380     }
 381 }
 382
 383 int pci_unregister_device(PCIDevice *pci_dev)
 384 {
 385     int ret = 0;
 386
 387     if (pci_dev->unregister)
 388         ret = pci_dev->unregister(pci_dev);
 389     if (ret)
 390         return ret;
 391
 392     pci_unregister_io_regions(pci_dev);
 393
 394     qemu_free_irqs(pci_dev->irq);
 395     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 396     qdev_free(&pci_dev->qdev);
 397     return 0;
 398 }
 399
 400 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 401                             uint32_t size, int type,
 402                             PCIMapIORegionFunc *map_func)
 403 {
 404     PCIIORegion *r;
 405     uint32_t addr;
 406     uint32_t wmask;
 407
 408     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 409         return;
 410
 411     if (size & (size-1)) {
 412         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 413                     "type=0x%x, size=0x%x\n", type, size);
 414         exit(1);
 415     }
 416
 417     r = &pci_dev->io_regions[region_num];
 418     r->addr = -1;
 419     r->size = size;
 420     r->type = type;
 421     r->map_func = map_func;
 422
 423     wmask = ~(size - 1);
 424     if (region_num == PCI_ROM_SLOT) {
 425         addr = 0x30;
 426         /* ROM enable bit is writeable */
 427         wmask |= 1;
 428     } else {
 429         addr = 0x10 + region_num * 4;
 430     }
 431     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 432     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 433     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 434 }
 435
 436 static void pci_update_mappings(PCIDevice *d)
 437 {
 438     PCIIORegion *r;
 439     int cmd, i;
 440     uint32_t last_addr, new_addr, config_ofs;
 441
 442     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 443     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 444         r = &d->io_regions[i];
 445         if (i == PCI_ROM_SLOT) {
 446             config_ofs = 0x30;
 447         } else {
 448             config_ofs = 0x10 + i * 4;
 449         }
 450         if (r->size != 0) {
 451             if (r->type & PCI_ADDRESS_SPACE_IO) {
 452                 if (cmd & PCI_COMMAND_IO) {
 453                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 454                                                          config_ofs));
 455                     new_addr = new_addr & ~(r->size - 1);
 456                     last_addr = new_addr + r->size - 1;
 457                     /* NOTE: we have only 64K ioports on PC */
 458                     if (last_addr <= new_addr || new_addr == 0 ||
 459                         last_addr >= 0x10000) {
 460                         new_addr = -1;
 461                     }
 462                 } else {
 463                     new_addr = -1;
 464                 }
 465             } else {
 466                 if (cmd & PCI_COMMAND_MEMORY) {
 467                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 468                                                          config_ofs));
 469                     /* the ROM slot has a specific enable bit */
 470                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 471                         goto no_mem_map;
 472                     new_addr = new_addr & ~(r->size - 1);
 473                     last_addr = new_addr + r->size - 1;
 474                     /* NOTE: we do not support wrapping */
 475                     /* XXX: as we cannot support really dynamic
 476                        mappings, we handle specific values as invalid
 477                        mappings. */
 478                     if (last_addr <= new_addr || new_addr == 0 ||
 479                         last_addr == -1) {
 480                         new_addr = -1;
 481                     }
 482                 } else {
 483                 no_mem_map:
 484                     new_addr = -1;
 485                 }
 486             }
 487             /* now do the real mapping */
 488             if (new_addr != r->addr) {
 489                 if (r->addr != -1) {
 490                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 491                         int class;
 492                         /* NOTE: specific hack for IDE in PC case:
 493                            only one byte must be mapped. */
 494                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 495                         if (class == 0x0101 && r->size == 4) {
 496                             isa_unassign_ioport(r->addr + 2, 1);
 497                         } else {
 498                             isa_unassign_ioport(r->addr, r->size);
 499                         }
 500                     } else {
 501                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 502                                                      r->size,
 503                                                      IO_MEM_UNASSIGNED);
 504                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 505                     }
 506                 }
 507                 r->addr = new_addr;
 508                 if (r->addr != -1) {
 509                     r->map_func(d, i, r->addr, r->size, r->type);
 510                 }
 511             }
 512         }
 513     }
 514 }
 515
 516 uint32_t pci_default_read_config(PCIDevice *d,
 517                                  uint32_t address, int len)
 518 {
 519     uint32_t val;
 520
 521     switch(len) {
 522     default:
 523     case 4:
 524         if (address <= 0xfc) {
 525             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 526             break;
 527         }
 528         /* fall through */
 529     case 2:
 530         if (address <= 0xfe) {
 531             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 532             break;
 533         }
 534         /* fall through */
 535     case 1:
 536         val = d->config[address];
 537         break;
 538     }
 539     return val;
 540 }
 541
 542 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 543 {
 544     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 545     int i;
 546
 547     /* not efficient, but simple */
 548     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 549     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 550         uint8_t wmask = d->wmask[addr];
 551         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 552     }
 553     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 554         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 555             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 556         pci_update_mappings(d);
 557 }
 558
 559 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 560 {
 561     PCIBus *s = opaque;
 562     PCIDevice *pci_dev;
 563     int config_addr, bus_num;
 564
 565 #if 0
 566     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 567                 addr, val, len);
 568 #endif
 569     bus_num = (addr >> 16) & 0xff;
 570     while (s && s->bus_num != bus_num)
 571         s = s->next;
 572     if (!s)
 573         return;
 574     pci_dev = s->devices[(addr >> 8) & 0xff];
 575     if (!pci_dev)
 576         return;
 577     config_addr = addr & 0xff;
 578     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 579                 pci_dev->name, config_addr, val, len);
 580     pci_dev->config_write(pci_dev, config_addr, val, len);
 581 }
 582
 583 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 584 {
 585     PCIBus *s = opaque;
 586     PCIDevice *pci_dev;
 587     int config_addr, bus_num;
 588     uint32_t val;
 589
 590     bus_num = (addr >> 16) & 0xff;
 591     while (s && s->bus_num != bus_num)
 592         s= s->next;
 593     if (!s)
 594         goto fail;
 595     pci_dev = s->devices[(addr >> 8) & 0xff];
 596     if (!pci_dev) {
 597     fail:
 598         switch(len) {
 599         case 1:
 600             val = 0xff;
 601             break;
 602         case 2:
 603             val = 0xffff;
 604             break;
 605         default:
 606         case 4:
 607             val = 0xffffffff;
 608             break;
 609         }
 610         goto the_end;
 611     }
 612     config_addr = addr & 0xff;
 613     val = pci_dev->config_read(pci_dev, config_addr, len);
 614     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 615                 pci_dev->name, config_addr, val, len);
 616  the_end:
 617 #if 0
 618     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 619                 addr, val, len);
 620 #endif
 621     return val;
 622 }
 623
 624 /***********************************************************/
 625 /* generic PCI irq support */
 626
 627 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 628 static void pci_set_irq(void *opaque, int irq_num, int level)
 629 {
 630     PCIDevice *pci_dev = opaque;
 631     PCIBus *bus;
 632     int change;
 633
 634     change = level - pci_dev->irq_state[irq_num];
 635     if (!change)
 636         return;
 637
 638     pci_dev->irq_state[irq_num] = level;
 639     for (;;) {
 640         bus = pci_dev->bus;
 641         irq_num = bus->map_irq(pci_dev, irq_num);
 642         if (bus->set_irq)
 643             break;
 644         pci_dev = bus->parent_dev;
 645     }
 646     bus->irq_count[irq_num] += change;
 647     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 648 }
 649
 650 /***********************************************************/
 651 /* monitor info on PCI */
 652
 653 typedef struct {
 654     uint16_t class;
 655     const char *desc;
 656 } pci_class_desc;
 657
 658 static const pci_class_desc pci_class_descriptions[] =
 659 {
 660     { 0x0100, "SCSI controller"},
 661     { 0x0101, "IDE controller"},
 662     { 0x0102, "Floppy controller"},
 663     { 0x0103, "IPI controller"},
 664     { 0x0104, "RAID controller"},
 665     { 0x0106, "SATA controller"},
 666     { 0x0107, "SAS controller"},
 667     { 0x0180, "Storage controller"},
 668     { 0x0200, "Ethernet controller"},
 669     { 0x0201, "Token Ring controller"},
 670     { 0x0202, "FDDI controller"},
 671     { 0x0203, "ATM controller"},
 672     { 0x0280, "Network controller"},
 673     { 0x0300, "VGA controller"},
 674     { 0x0301, "XGA controller"},
 675     { 0x0302, "3D controller"},
 676     { 0x0380, "Display controller"},
 677     { 0x0400, "Video controller"},
 678     { 0x0401, "Audio controller"},
 679     { 0x0402, "Phone"},
 680     { 0x0480, "Multimedia controller"},
 681     { 0x0500, "RAM controller"},
 682     { 0x0501, "Flash controller"},
 683     { 0x0580, "Memory controller"},
 684     { 0x0600, "Host bridge"},
 685     { 0x0601, "ISA bridge"},
 686     { 0x0602, "EISA bridge"},
 687     { 0x0603, "MC bridge"},
 688     { 0x0604, "PCI bridge"},
 689     { 0x0605, "PCMCIA bridge"},
 690     { 0x0606, "NUBUS bridge"},
 691     { 0x0607, "CARDBUS bridge"},
 692     { 0x0608, "RACEWAY bridge"},
 693     { 0x0680, "Bridge"},
 694     { 0x0c03, "USB controller"},
 695     { 0, NULL}
 696 };
 697
 698 static void pci_info_device(PCIDevice *d)
 699 {
 700     Monitor *mon = cur_mon;
 701     int i, class;
 702     PCIIORegion *r;
 703     const pci_class_desc *desc;
 704
 705     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 706                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 707     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 708     monitor_printf(mon, "    ");
 709     desc = pci_class_descriptions;
 710     while (desc->desc && class != desc->class)
 711         desc++;
 712     if (desc->desc) {
 713         monitor_printf(mon, "%s", desc->desc);
 714     } else {
 715         monitor_printf(mon, "Class %04x", class);
 716     }
 717     monitor_printf(mon, ": PCI device %04x:%04x\n",
 718            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 719            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 720
 721     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 722         monitor_printf(mon, "      IRQ %d.\n",
 723                        d->config[PCI_INTERRUPT_LINE]);
 724     }
 725     if (class == 0x0604) {
 726         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 727     }
 728     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 729         r = &d->io_regions[i];
 730         if (r->size != 0) {
 731             monitor_printf(mon, "      BAR%d: ", i);
 732             if (r->type & PCI_ADDRESS_SPACE_IO) {
 733                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 734                                r->addr, r->addr + r->size - 1);
 735             } else {
 736                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 737                                r->addr, r->addr + r->size - 1);
 738             }
 739         }
 740     }
 741     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 742     if (class == 0x0604 && d->config[0x19] != 0) {
 743         pci_for_each_device(d->config[0x19], pci_info_device);
 744     }
 745 }
 746
 747 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 748 {
 749     PCIBus *bus = first_bus;
 750     PCIDevice *d;
 751     int devfn;
 752
 753     while (bus && bus->bus_num != bus_num)
 754         bus = bus->next;
 755     if (bus) {
 756         for(devfn = 0; devfn < 256; devfn++) {
 757             d = bus->devices[devfn];
 758             if (d)
 759                 fn(d);
 760         }
 761     }
 762 }
 763
 764 void pci_info(Monitor *mon)
 765 {
 766     pci_for_each_device(0, pci_info_device);
 767 }
 768
 769 PCIDevice *pci_create(const char *name, const char *devaddr)
 770 {
 771     PCIBus *bus;
 772     int devfn;
 773     DeviceState *dev;
 774
 775     bus = pci_get_bus_devfn(&devfn, devaddr);
 776     if (!bus) {
 777         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 778                 devaddr, name);
 779         exit(1);
 780     }
 781
 782     dev = qdev_create(&bus->qbus, name);
 783     qdev_prop_set_uint32(dev, "addr", devfn);
 784     return (PCIDevice *)dev;
 785 }
 786
 787 static const char * const pci_nic_models[] = {
 788     "ne2k_pci",
 789     "i82551",
 790     "i82557b",
 791     "i82559er",
 792     "rtl8139",
 793     "e1000",
 794     "pcnet",
 795     "virtio",
 796     NULL
 797 };
 798
 799 static const char * const pci_nic_names[] = {
 800     "ne2k_pci",
 801     "i82551",
 802     "i82557b",
 803     "i82559er",
 804     "rtl8139",
 805     "e1000",
 806     "pcnet",
 807     "virtio-net-pci",
 808     NULL
 809 };
 810
 811 /* Initialize a PCI NIC.  */
 812 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 813                         const char *default_devaddr)
 814 {
 815     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 816     PCIDevice *pci_dev;
 817     DeviceState *dev;
 818     int i;
 819
 820     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 821
 822     for (i = 0; pci_nic_models[i]; i++) {
 823         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 824             pci_dev = pci_create(pci_nic_names[i], devaddr);
 825             dev = &pci_dev->qdev;
 826             if (nd->id)
 827                 dev->id = qemu_strdup(nd->id);
 828             dev->nd = nd;
 829             qdev_init(dev);
 830             nd->private = dev;
 831             return pci_dev;
 832         }
 833     }
 834
 835     return NULL;
 836 }
 837
 838 typedef struct {
 839     PCIDevice dev;
 840     PCIBus *bus;
 841 } PCIBridge;
 842
 843 static void pci_bridge_write_config(PCIDevice *d,
 844                              uint32_t address, uint32_t val, int len)
 845 {
 846     PCIBridge *s = (PCIBridge *)d;
 847
 848     pci_default_write_config(d, address, val, len);
 849     s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
 850 }
 851
 852 PCIBus *pci_find_bus(int bus_num)
 853 {
 854     PCIBus *bus = first_bus;
 855
 856     while (bus && bus->bus_num != bus_num)
 857         bus = bus->next;
 858
 859     return bus;
 860 }
 861
 862 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 863 {
 864     PCIBus *bus = pci_find_bus(bus_num);
 865
 866     if (!bus)
 867         return NULL;
 868
 869     return bus->devices[PCI_DEVFN(slot, function)];
 870 }
 871
 872 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 873                         pci_map_irq_fn map_irq, const char *name)
 874 {
 875     PCIBridge *s;
 876     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 877                                          devfn, NULL, pci_bridge_write_config);
 878
 879     pci_config_set_vendor_id(s->dev.config, vid);
 880     pci_config_set_device_id(s->dev.config, did);
 881
 882     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 883     s->dev.config[0x05] = 0x00;
 884     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 885     s->dev.config[0x07] = 0x00; // status = fast devsel
 886     s->dev.config[0x08] = 0x00; // revision
 887     s->dev.config[0x09] = 0x00; // programming i/f
 888     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 889     s->dev.config[0x0D] = 0x10; // latency_timer
 890     s->dev.config[PCI_HEADER_TYPE] =
 891         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 892     s->dev.config[0x1E] = 0xa0; // secondary status
 893
 894     s->bus = pci_register_secondary_bus(&s->dev, map_irq, name);
 895     return s->bus;
 896 }
 897
 898 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 899 {
 900     PCIDevice *pci_dev = (PCIDevice *)qdev;
 901     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 902     PCIBus *bus;
 903     int devfn;
 904
 905     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 906     devfn = pci_dev->devfn;
 907     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
 908                                      info->config_read, info->config_write);
 909     assert(pci_dev);
 910     return info->init(pci_dev);
 911 }
 912
 913 void pci_qdev_register(PCIDeviceInfo *info)
 914 {
 915     info->qdev.init = pci_qdev_init;
 916     info->qdev.bus_info = &pci_bus_info;
 917     qdev_register(&info->qdev);
 918 }
 919
 920 void pci_qdev_register_many(PCIDeviceInfo *info)
 921 {
 922     while (info->qdev.name) {
 923         pci_qdev_register(info);
 924         info++;
 925     }
 926 }
 927
 928 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 929 {
 930     DeviceState *dev;
 931
 932     dev = qdev_create(&bus->qbus, name);
 933     qdev_prop_set_uint32(dev, "addr", devfn);
 934     qdev_init(dev);
 935
 936     return (PCIDevice *)dev;
 937 }
 938
 939 static int pci_find_space(PCIDevice *pdev, uint8_t size)
 940 {
 941     int offset = PCI_CONFIG_HEADER_SIZE;
 942     int i;
 943     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 944         if (pdev->used[i])
 945             offset = i + 1;
 946         else if (i - offset + 1 == size)
 947             return offset;
 948     return 0;
 949 }
 950
 951 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
 952                                         uint8_t *prev_p)
 953 {
 954     uint8_t next, prev;
 955
 956     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
 957         return 0;
 958
 959     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
 960          prev = next + PCI_CAP_LIST_NEXT)
 961         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
 962             break;
 963
 964     if (prev_p)
 965         *prev_p = prev;
 966     return next;
 967 }
 968
 969 /* Reserve space and add capability to the linked list in pci config space */
 970 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 971 {
 972     uint8_t offset = pci_find_space(pdev, size);
 973     uint8_t *config = pdev->config + offset;
 974     if (!offset)
 975         return -ENOSPC;
 976     config[PCI_CAP_LIST_ID] = cap_id;
 977     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
 978     pdev->config[PCI_CAPABILITY_LIST] = offset;
 979     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
 980     memset(pdev->used + offset, 0xFF, size);
 981     /* Make capability read-only by default */
 982     memset(pdev->wmask + offset, 0, size);
 983     /* Check capability by default */
 984     memset(pdev->cmask + offset, 0xFF, size);
 985     return offset;
 986 }
 987
 988 /* Unlink capability from the pci config space. */
 989 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 990 {
 991     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
 992     if (!offset)
 993         return;
 994     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
 995     /* Make capability writeable again */
 996     memset(pdev->wmask + offset, 0xff, size);
 997     /* Clear cmask as device-specific registers can't be checked */
 998     memset(pdev->cmask + offset, 0, size);
 999     memset(pdev->used + offset, 0, size);
1000
1001     if (!pdev->config[PCI_CAPABILITY_LIST])
1002         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1003 }
1004
1005 /* Reserve space for capability at a known offset (to call after load). */
1006 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1007 {
1008     memset(pdev->used + offset, 0xff, size);
1009 }
1010
1011 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1012 {
1013     return pci_find_capability_list(pdev, cap_id, NULL);
1014 }
1015
1016 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1017 {
1018     PCIDevice *d = (PCIDevice *)dev;
1019     const pci_class_desc *desc;
1020     char ctxt[64];
1021     PCIIORegion *r;
1022     int i, class;
1023
1024     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1025     desc = pci_class_descriptions;
1026     while (desc->desc && class != desc->class)
1027         desc++;
1028     if (desc->desc) {
1029         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1030     } else {
1031         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1032     }
1033
1034     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1035                    "pci id %04x:%04x (sub %04x:%04x)\n",
1036                    indent, "", ctxt,
1037                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1038                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1039                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1040                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1041                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1042     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1043         r = &d->io_regions[i];
1044         if (!r->size)
1045             continue;
1046         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1047                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1048                        r->addr, r->addr + r->size - 1);
1049     }
1050 }