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memory: add parameter errp to memory_region_init_ram
[qemu/cris-port.git] / exec.c
blob2b9c4c5ab6cbbf32f96fb5cca9581f15a871b70c
1 /*
2 * Virtual page mapping
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "config.h"
20 #ifndef _WIN32
21 #include <sys/types.h>
22 #include <sys/mman.h>
23 #endif
24
25 #include "qemu-common.h"
26 #include "cpu.h"
27 #include "tcg.h"
28 #include "hw/hw.h"
29 #include "hw/qdev.h"
30 #include "qemu/osdep.h"
31 #include "sysemu/kvm.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/xen/xen.h"
34 #include "qemu/timer.h"
35 #include "qemu/config-file.h"
36 #include "qemu/error-report.h"
37 #include "exec/memory.h"
38 #include "sysemu/dma.h"
39 #include "exec/address-spaces.h"
40 #if defined(CONFIG_USER_ONLY)
41 #include <qemu.h>
42 #else /* !CONFIG_USER_ONLY */
43 #include "sysemu/xen-mapcache.h"
44 #include "trace.h"
45 #endif
46 #include "exec/cpu-all.h"
47
48 #include "exec/cputlb.h"
49 #include "translate-all.h"
50
51 #include "exec/memory-internal.h"
52 #include "exec/ram_addr.h"
53
54 #include "qemu/range.h"
55
56 //#define DEBUG_SUBPAGE
57
58 #if !defined(CONFIG_USER_ONLY)
59 static bool in_migration;
60
61 RAMList ram_list = { .blocks = QTAILQ_HEAD_INITIALIZER(ram_list.blocks) };
62
63 static MemoryRegion *system_memory;
64 static MemoryRegion *system_io;
65
66 AddressSpace address_space_io;
67 AddressSpace address_space_memory;
68
69 MemoryRegion io_mem_rom, io_mem_notdirty;
70 static MemoryRegion io_mem_unassigned;
71
72 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
73 #define RAM_PREALLOC (1 << 0)
74
75 /* RAM is mmap-ed with MAP_SHARED */
76 #define RAM_SHARED (1 << 1)
77
78 #endif
79
80 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
81 /* current CPU in the current thread. It is only valid inside
82 cpu_exec() */
83 DEFINE_TLS(CPUState *, current_cpu);
84 /* 0 = Do not count executed instructions.
85 1 = Precise instruction counting.
86 2 = Adaptive rate instruction counting. */
87 int use_icount;
88
89 #if !defined(CONFIG_USER_ONLY)
90
91 typedef struct PhysPageEntry PhysPageEntry;
92
93 struct PhysPageEntry {
94 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
95 uint32_t skip : 6;
96 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
97 uint32_t ptr : 26;
98 };
99
100 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
101
102 /* Size of the L2 (and L3, etc) page tables. */
103 #define ADDR_SPACE_BITS 64
104
105 #define P_L2_BITS 9
106 #define P_L2_SIZE (1 << P_L2_BITS)
107
108 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
109
110 typedef PhysPageEntry Node[P_L2_SIZE];
111
112 typedef struct PhysPageMap {
113 unsigned sections_nb;
114 unsigned sections_nb_alloc;
115 unsigned nodes_nb;
116 unsigned nodes_nb_alloc;
117 Node *nodes;
118 MemoryRegionSection *sections;
119 } PhysPageMap;
120
121 struct AddressSpaceDispatch {
122 /* This is a multi-level map on the physical address space.
123 * The bottom level has pointers to MemoryRegionSections.
124 */
125 PhysPageEntry phys_map;
126 PhysPageMap map;
127 AddressSpace *as;
128 };
129
130 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
131 typedef struct subpage_t {
132 MemoryRegion iomem;
133 AddressSpace *as;
134 hwaddr base;
135 uint16_t sub_section[TARGET_PAGE_SIZE];
136 } subpage_t;
137
138 #define PHYS_SECTION_UNASSIGNED 0
139 #define PHYS_SECTION_NOTDIRTY 1
140 #define PHYS_SECTION_ROM 2
141 #define PHYS_SECTION_WATCH 3
142
143 static void io_mem_init(void);
144 static void memory_map_init(void);
145 static void tcg_commit(MemoryListener *listener);
146
147 static MemoryRegion io_mem_watch;
148 #endif
149
150 #if !defined(CONFIG_USER_ONLY)
151
152 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
153 {
154 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
155 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc * 2, 16);
156 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
157 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
158 }
159 }
160
161 static uint32_t phys_map_node_alloc(PhysPageMap *map)
162 {
163 unsigned i;
164 uint32_t ret;
165
166 ret = map->nodes_nb++;
167 assert(ret != PHYS_MAP_NODE_NIL);
168 assert(ret != map->nodes_nb_alloc);
169 for (i = 0; i < P_L2_SIZE; ++i) {
170 map->nodes[ret][i].skip = 1;
171 map->nodes[ret][i].ptr = PHYS_MAP_NODE_NIL;
172 }
173 return ret;
174 }
175
176 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
177 hwaddr *index, hwaddr *nb, uint16_t leaf,
178 int level)
179 {
180 PhysPageEntry *p;
181 int i;
182 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
183
184 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
185 lp->ptr = phys_map_node_alloc(map);
186 p = map->nodes[lp->ptr];
187 if (level == 0) {
188 for (i = 0; i < P_L2_SIZE; i++) {
189 p[i].skip = 0;
190 p[i].ptr = PHYS_SECTION_UNASSIGNED;
191 }
192 }
193 } else {
194 p = map->nodes[lp->ptr];
195 }
196 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
197
198 while (*nb && lp < &p[P_L2_SIZE]) {
199 if ((*index & (step - 1)) == 0 && *nb >= step) {
200 lp->skip = 0;
201 lp->ptr = leaf;
202 *index += step;
203 *nb -= step;
204 } else {
205 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
206 }
207 ++lp;
208 }
209 }
210
211 static void phys_page_set(AddressSpaceDispatch *d,
212 hwaddr index, hwaddr nb,
213 uint16_t leaf)
214 {
215 /* Wildly overreserve - it doesn't matter much. */
216 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
217
218 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
219 }
220
221 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
222 * and update our entry so we can skip it and go directly to the destination.
223 */
224 static void phys_page_compact(PhysPageEntry *lp, Node *nodes, unsigned long *compacted)
225 {
226 unsigned valid_ptr = P_L2_SIZE;
227 int valid = 0;
228 PhysPageEntry *p;
229 int i;
230
231 if (lp->ptr == PHYS_MAP_NODE_NIL) {
232 return;
233 }
234
235 p = nodes[lp->ptr];
236 for (i = 0; i < P_L2_SIZE; i++) {
237 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
238 continue;
239 }
240
241 valid_ptr = i;
242 valid++;
243 if (p[i].skip) {
244 phys_page_compact(&p[i], nodes, compacted);
245 }
246 }
247
248 /* We can only compress if there's only one child. */
249 if (valid != 1) {
250 return;
251 }
252
253 assert(valid_ptr < P_L2_SIZE);
254
255 /* Don't compress if it won't fit in the # of bits we have. */
256 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
257 return;
258 }
259
260 lp->ptr = p[valid_ptr].ptr;
261 if (!p[valid_ptr].skip) {
262 /* If our only child is a leaf, make this a leaf. */
263 /* By design, we should have made this node a leaf to begin with so we
264 * should never reach here.
265 * But since it's so simple to handle this, let's do it just in case we
266 * change this rule.
267 */
268 lp->skip = 0;
269 } else {
270 lp->skip += p[valid_ptr].skip;
271 }
272 }
273
274 static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb)
275 {
276 DECLARE_BITMAP(compacted, nodes_nb);
277
278 if (d->phys_map.skip) {
279 phys_page_compact(&d->phys_map, d->map.nodes, compacted);
280 }
281 }
282
283 static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr addr,
284 Node *nodes, MemoryRegionSection *sections)
285 {
286 PhysPageEntry *p;
287 hwaddr index = addr >> TARGET_PAGE_BITS;
288 int i;
289
290 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
291 if (lp.ptr == PHYS_MAP_NODE_NIL) {
292 return &sections[PHYS_SECTION_UNASSIGNED];
293 }
294 p = nodes[lp.ptr];
295 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
296 }
297
298 if (sections[lp.ptr].size.hi ||
299 range_covers_byte(sections[lp.ptr].offset_within_address_space,
300 sections[lp.ptr].size.lo, addr)) {
301 return &sections[lp.ptr];
302 } else {
303 return &sections[PHYS_SECTION_UNASSIGNED];
304 }
305 }
306
307 bool memory_region_is_unassigned(MemoryRegion *mr)
308 {
309 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
310 && mr != &io_mem_watch;
311 }
312
313 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
314 hwaddr addr,
315 bool resolve_subpage)
316 {
317 MemoryRegionSection *section;
318 subpage_t *subpage;
319
320 section = phys_page_find(d->phys_map, addr, d->map.nodes, d->map.sections);
321 if (resolve_subpage && section->mr->subpage) {
322 subpage = container_of(section->mr, subpage_t, iomem);
323 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
324 }
325 return section;
326 }
327
328 static MemoryRegionSection *
329 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
330 hwaddr *plen, bool resolve_subpage)
331 {
332 MemoryRegionSection *section;
333 Int128 diff;
334
335 section = address_space_lookup_region(d, addr, resolve_subpage);
336 /* Compute offset within MemoryRegionSection */
337 addr -= section->offset_within_address_space;
338
339 /* Compute offset within MemoryRegion */
340 *xlat = addr + section->offset_within_region;
341
342 diff = int128_sub(section->mr->size, int128_make64(addr));
343 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
344 return section;
345 }
346
347 static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write)
348 {
349 if (memory_region_is_ram(mr)) {
350 return !(is_write && mr->readonly);
351 }
352 if (memory_region_is_romd(mr)) {
353 return !is_write;
354 }
355
356 return false;
357 }
358
359 MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
360 hwaddr *xlat, hwaddr *plen,
361 bool is_write)
362 {
363 IOMMUTLBEntry iotlb;
364 MemoryRegionSection *section;
365 MemoryRegion *mr;
366 hwaddr len = *plen;
367
368 for (;;) {
369 section = address_space_translate_internal(as->dispatch, addr, &addr, plen, true);
370 mr = section->mr;
371
372 if (!mr->iommu_ops) {
373 break;
374 }
375
376 iotlb = mr->iommu_ops->translate(mr, addr, is_write);
377 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
378 | (addr & iotlb.addr_mask));
379 len = MIN(len, (addr | iotlb.addr_mask) - addr + 1);
380 if (!(iotlb.perm & (1 << is_write))) {
381 mr = &io_mem_unassigned;
382 break;
383 }
384
385 as = iotlb.target_as;
386 }
387
388 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
389 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
390 len = MIN(page, len);
391 }
392
393 *plen = len;
394 *xlat = addr;
395 return mr;
396 }
397
398 MemoryRegionSection *
399 address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat,
400 hwaddr *plen)
401 {
402 MemoryRegionSection *section;
403 section = address_space_translate_internal(as->dispatch, addr, xlat, plen, false);
404
405 assert(!section->mr->iommu_ops);
406 return section;
407 }
408 #endif
409
410 void cpu_exec_init_all(void)
411 {
412 #if !defined(CONFIG_USER_ONLY)
413 qemu_mutex_init(&ram_list.mutex);
414 memory_map_init();
415 io_mem_init();
416 #endif
417 }
418
419 #if !defined(CONFIG_USER_ONLY)
420
421 static int cpu_common_post_load(void *opaque, int version_id)
422 {
423 CPUState *cpu = opaque;
424
425 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
426 version_id is increased. */
427 cpu->interrupt_request &= ~0x01;
428 tlb_flush(cpu, 1);
429
430 return 0;
431 }
432
433 static int cpu_common_pre_load(void *opaque)
434 {
435 CPUState *cpu = opaque;
436
437 cpu->exception_index = 0;
438
439 return 0;
440 }
441
442 static bool cpu_common_exception_index_needed(void *opaque)
443 {
444 CPUState *cpu = opaque;
445
446 return cpu->exception_index != 0;
447 }
448
449 static const VMStateDescription vmstate_cpu_common_exception_index = {
450 .name = "cpu_common/exception_index",
451 .version_id = 1,
452 .minimum_version_id = 1,
453 .fields = (VMStateField[]) {
454 VMSTATE_INT32(exception_index, CPUState),
455 VMSTATE_END_OF_LIST()
456 }
457 };
458
459 const VMStateDescription vmstate_cpu_common = {
460 .name = "cpu_common",
461 .version_id = 1,
462 .minimum_version_id = 1,
463 .pre_load = cpu_common_pre_load,
464 .post_load = cpu_common_post_load,
465 .fields = (VMStateField[]) {
466 VMSTATE_UINT32(halted, CPUState),
467 VMSTATE_UINT32(interrupt_request, CPUState),
468 VMSTATE_END_OF_LIST()
469 },
470 .subsections = (VMStateSubsection[]) {
471 {
472 .vmsd = &vmstate_cpu_common_exception_index,
473 .needed = cpu_common_exception_index_needed,
474 } , {
475 /* empty */
476 }
477 }
478 };
479
480 #endif
481
482 CPUState *qemu_get_cpu(int index)
483 {
484 CPUState *cpu;
485
486 CPU_FOREACH(cpu) {
487 if (cpu->cpu_index == index) {
488 return cpu;
489 }
490 }
491
492 return NULL;
493 }
494
495 #if !defined(CONFIG_USER_ONLY)
496 void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as)
497 {
498 /* We only support one address space per cpu at the moment. */
499 assert(cpu->as == as);
500
501 if (cpu->tcg_as_listener) {
502 memory_listener_unregister(cpu->tcg_as_listener);
503 } else {
504 cpu->tcg_as_listener = g_new0(MemoryListener, 1);
505 }
506 cpu->tcg_as_listener->commit = tcg_commit;
507 memory_listener_register(cpu->tcg_as_listener, as);
508 }
509 #endif
510
511 void cpu_exec_init(CPUArchState *env)
512 {
513 CPUState *cpu = ENV_GET_CPU(env);
514 CPUClass *cc = CPU_GET_CLASS(cpu);
515 CPUState *some_cpu;
516 int cpu_index;
517
518 #if defined(CONFIG_USER_ONLY)
519 cpu_list_lock();
520 #endif
521 cpu_index = 0;
522 CPU_FOREACH(some_cpu) {
523 cpu_index++;
524 }
525 cpu->cpu_index = cpu_index;
526 cpu->numa_node = 0;
527 QTAILQ_INIT(&cpu->breakpoints);
528 QTAILQ_INIT(&cpu->watchpoints);
529 #ifndef CONFIG_USER_ONLY
530 cpu->as = &address_space_memory;
531 cpu->thread_id = qemu_get_thread_id();
532 #endif
533 QTAILQ_INSERT_TAIL(&cpus, cpu, node);
534 #if defined(CONFIG_USER_ONLY)
535 cpu_list_unlock();
536 #endif
537 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
538 vmstate_register(NULL, cpu_index, &vmstate_cpu_common, cpu);
539 }
540 #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
541 register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
542 cpu_save, cpu_load, env);
543 assert(cc->vmsd == NULL);
544 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
545 #endif
546 if (cc->vmsd != NULL) {
547 vmstate_register(NULL, cpu_index, cc->vmsd, cpu);
548 }
549 }
550
551 #if defined(TARGET_HAS_ICE)
552 #if defined(CONFIG_USER_ONLY)
553 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
554 {
555 tb_invalidate_phys_page_range(pc, pc + 1, 0);
556 }
557 #else
558 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
559 {
560 hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
561 if (phys != -1) {
562 tb_invalidate_phys_addr(cpu->as,
563 phys | (pc & ~TARGET_PAGE_MASK));
564 }
565 }
566 #endif
567 #endif /* TARGET_HAS_ICE */
568
569 #if defined(CONFIG_USER_ONLY)
570 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
571
572 {
573 }
574
575 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
576 int flags, CPUWatchpoint **watchpoint)
577 {
578 return -ENOSYS;
579 }
580 #else
581 /* Add a watchpoint. */
582 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
583 int flags, CPUWatchpoint **watchpoint)
584 {
585 vaddr len_mask = ~(len - 1);
586 CPUWatchpoint *wp;
587
588 /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
589 if ((len & (len - 1)) || (addr & ~len_mask) ||
590 len == 0 || len > TARGET_PAGE_SIZE) {
591 error_report("tried to set invalid watchpoint at %"
592 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
593 return -EINVAL;
594 }
595 wp = g_malloc(sizeof(*wp));
596
597 wp->vaddr = addr;
598 wp->len_mask = len_mask;
599 wp->flags = flags;
600
601 /* keep all GDB-injected watchpoints in front */
602 if (flags & BP_GDB) {
603 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
604 } else {
605 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
606 }
607
608 tlb_flush_page(cpu, addr);
609
610 if (watchpoint)
611 *watchpoint = wp;
612 return 0;
613 }
614
615 /* Remove a specific watchpoint. */
616 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
617 int flags)
618 {
619 vaddr len_mask = ~(len - 1);
620 CPUWatchpoint *wp;
621
622 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
623 if (addr == wp->vaddr && len_mask == wp->len_mask
624 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
625 cpu_watchpoint_remove_by_ref(cpu, wp);
626 return 0;
627 }
628 }
629 return -ENOENT;
630 }
631
632 /* Remove a specific watchpoint by reference. */
633 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
634 {
635 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
636
637 tlb_flush_page(cpu, watchpoint->vaddr);
638
639 g_free(watchpoint);
640 }
641
642 /* Remove all matching watchpoints. */
643 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
644 {
645 CPUWatchpoint *wp, *next;
646
647 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
648 if (wp->flags & mask) {
649 cpu_watchpoint_remove_by_ref(cpu, wp);
650 }
651 }
652 }
653 #endif
654
655 /* Add a breakpoint. */
656 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
657 CPUBreakpoint **breakpoint)
658 {
659 #if defined(TARGET_HAS_ICE)
660 CPUBreakpoint *bp;
661
662 bp = g_malloc(sizeof(*bp));
663
664 bp->pc = pc;
665 bp->flags = flags;
666
667 /* keep all GDB-injected breakpoints in front */
668 if (flags & BP_GDB) {
669 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
670 } else {
671 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
672 }
673
674 breakpoint_invalidate(cpu, pc);
675
676 if (breakpoint) {
677 *breakpoint = bp;
678 }
679 return 0;
680 #else
681 return -ENOSYS;
682 #endif
683 }
684
685 /* Remove a specific breakpoint. */
686 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
687 {
688 #if defined(TARGET_HAS_ICE)
689 CPUBreakpoint *bp;
690
691 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
692 if (bp->pc == pc && bp->flags == flags) {
693 cpu_breakpoint_remove_by_ref(cpu, bp);
694 return 0;
695 }
696 }
697 return -ENOENT;
698 #else
699 return -ENOSYS;
700 #endif
701 }
702
703 /* Remove a specific breakpoint by reference. */
704 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
705 {
706 #if defined(TARGET_HAS_ICE)
707 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
708
709 breakpoint_invalidate(cpu, breakpoint->pc);
710
711 g_free(breakpoint);
712 #endif
713 }
714
715 /* Remove all matching breakpoints. */
716 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
717 {
718 #if defined(TARGET_HAS_ICE)
719 CPUBreakpoint *bp, *next;
720
721 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
722 if (bp->flags & mask) {
723 cpu_breakpoint_remove_by_ref(cpu, bp);
724 }
725 }
726 #endif
727 }
728
729 /* enable or disable single step mode. EXCP_DEBUG is returned by the
730 CPU loop after each instruction */
731 void cpu_single_step(CPUState *cpu, int enabled)
732 {
733 #if defined(TARGET_HAS_ICE)
734 if (cpu->singlestep_enabled != enabled) {
735 cpu->singlestep_enabled = enabled;
736 if (kvm_enabled()) {
737 kvm_update_guest_debug(cpu, 0);
738 } else {
739 /* must flush all the translated code to avoid inconsistencies */
740 /* XXX: only flush what is necessary */
741 CPUArchState *env = cpu->env_ptr;
742 tb_flush(env);
743 }
744 }
745 #endif
746 }
747
748 void cpu_abort(CPUState *cpu, const char *fmt, ...)
749 {
750 va_list ap;
751 va_list ap2;
752
753 va_start(ap, fmt);
754 va_copy(ap2, ap);
755 fprintf(stderr, "qemu: fatal: ");
756 vfprintf(stderr, fmt, ap);
757 fprintf(stderr, "\n");
758 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
759 if (qemu_log_enabled()) {
760 qemu_log("qemu: fatal: ");
761 qemu_log_vprintf(fmt, ap2);
762 qemu_log("\n");
763 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
764 qemu_log_flush();
765 qemu_log_close();
766 }
767 va_end(ap2);
768 va_end(ap);
769 #if defined(CONFIG_USER_ONLY)
770 {
771 struct sigaction act;
772 sigfillset(&act.sa_mask);
773 act.sa_handler = SIG_DFL;
774 sigaction(SIGABRT, &act, NULL);
775 }
776 #endif
777 abort();
778 }
779
780 #if !defined(CONFIG_USER_ONLY)
781 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
782 {
783 RAMBlock *block;
784
785 /* The list is protected by the iothread lock here. */
786 block = ram_list.mru_block;
787 if (block && addr - block->offset < block->length) {
788 goto found;
789 }
790 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
791 if (addr - block->offset < block->length) {
792 goto found;
793 }
794 }
795
796 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
797 abort();
798
799 found:
800 ram_list.mru_block = block;
801 return block;
802 }
803
804 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
805 {
806 ram_addr_t start1;
807 RAMBlock *block;
808 ram_addr_t end;
809
810 end = TARGET_PAGE_ALIGN(start + length);
811 start &= TARGET_PAGE_MASK;
812
813 block = qemu_get_ram_block(start);
814 assert(block == qemu_get_ram_block(end - 1));
815 start1 = (uintptr_t)block->host + (start - block->offset);
816 cpu_tlb_reset_dirty_all(start1, length);
817 }
818
819 /* Note: start and end must be within the same ram block. */
820 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t length,
821 unsigned client)
822 {
823 if (length == 0)
824 return;
825 cpu_physical_memory_clear_dirty_range(start, length, client);
826
827 if (tcg_enabled()) {
828 tlb_reset_dirty_range_all(start, length);
829 }
830 }
831
832 static void cpu_physical_memory_set_dirty_tracking(bool enable)
833 {
834 in_migration = enable;
835 }
836
837 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
838 MemoryRegionSection *section,
839 target_ulong vaddr,
840 hwaddr paddr, hwaddr xlat,
841 int prot,
842 target_ulong *address)
843 {
844 hwaddr iotlb;
845 CPUWatchpoint *wp;
846
847 if (memory_region_is_ram(section->mr)) {
848 /* Normal RAM. */
849 iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
850 + xlat;
851 if (!section->readonly) {
852 iotlb |= PHYS_SECTION_NOTDIRTY;
853 } else {
854 iotlb |= PHYS_SECTION_ROM;
855 }
856 } else {
857 iotlb = section - section->address_space->dispatch->map.sections;
858 iotlb += xlat;
859 }
860
861 /* Make accesses to pages with watchpoints go via the
862 watchpoint trap routines. */
863 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
864 if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
865 /* Avoid trapping reads of pages with a write breakpoint. */
866 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
867 iotlb = PHYS_SECTION_WATCH + paddr;
868 *address |= TLB_MMIO;
869 break;
870 }
871 }
872 }
873
874 return iotlb;
875 }
876 #endif /* defined(CONFIG_USER_ONLY) */
877
878 #if !defined(CONFIG_USER_ONLY)
879
880 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
881 uint16_t section);
882 static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
883
884 static void *(*phys_mem_alloc)(size_t size) = qemu_anon_ram_alloc;
885
886 /*
887 * Set a custom physical guest memory alloator.
888 * Accelerators with unusual needs may need this. Hopefully, we can
889 * get rid of it eventually.
890 */
891 void phys_mem_set_alloc(void *(*alloc)(size_t))
892 {
893 phys_mem_alloc = alloc;
894 }
895
896 static uint16_t phys_section_add(PhysPageMap *map,
897 MemoryRegionSection *section)
898 {
899 /* The physical section number is ORed with a page-aligned
900 * pointer to produce the iotlb entries. Thus it should
901 * never overflow into the page-aligned value.
902 */
903 assert(map->sections_nb < TARGET_PAGE_SIZE);
904
905 if (map->sections_nb == map->sections_nb_alloc) {
906 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
907 map->sections = g_renew(MemoryRegionSection, map->sections,
908 map->sections_nb_alloc);
909 }
910 map->sections[map->sections_nb] = *section;
911 memory_region_ref(section->mr);
912 return map->sections_nb++;
913 }
914
915 static void phys_section_destroy(MemoryRegion *mr)
916 {
917 memory_region_unref(mr);
918
919 if (mr->subpage) {
920 subpage_t *subpage = container_of(mr, subpage_t, iomem);
921 object_unref(OBJECT(&subpage->iomem));
922 g_free(subpage);
923 }
924 }
925
926 static void phys_sections_free(PhysPageMap *map)
927 {
928 while (map->sections_nb > 0) {
929 MemoryRegionSection *section = &map->sections[--map->sections_nb];
930 phys_section_destroy(section->mr);
931 }
932 g_free(map->sections);
933 g_free(map->nodes);
934 }
935
936 static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
937 {
938 subpage_t *subpage;
939 hwaddr base = section->offset_within_address_space
940 & TARGET_PAGE_MASK;
941 MemoryRegionSection *existing = phys_page_find(d->phys_map, base,
942 d->map.nodes, d->map.sections);
943 MemoryRegionSection subsection = {
944 .offset_within_address_space = base,
945 .size = int128_make64(TARGET_PAGE_SIZE),
946 };
947 hwaddr start, end;
948
949 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
950
951 if (!(existing->mr->subpage)) {
952 subpage = subpage_init(d->as, base);
953 subsection.address_space = d->as;
954 subsection.mr = &subpage->iomem;
955 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
956 phys_section_add(&d->map, &subsection));
957 } else {
958 subpage = container_of(existing->mr, subpage_t, iomem);
959 }
960 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
961 end = start + int128_get64(section->size) - 1;
962 subpage_register(subpage, start, end,
963 phys_section_add(&d->map, section));
964 }
965
966
967 static void register_multipage(AddressSpaceDispatch *d,
968 MemoryRegionSection *section)
969 {
970 hwaddr start_addr = section->offset_within_address_space;
971 uint16_t section_index = phys_section_add(&d->map, section);
972 uint64_t num_pages = int128_get64(int128_rshift(section->size,
973 TARGET_PAGE_BITS));
974
975 assert(num_pages);
976 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
977 }
978
979 static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
980 {
981 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
982 AddressSpaceDispatch *d = as->next_dispatch;
983 MemoryRegionSection now = *section, remain = *section;
984 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
985
986 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
987 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
988 - now.offset_within_address_space;
989
990 now.size = int128_min(int128_make64(left), now.size);
991 register_subpage(d, &now);
992 } else {
993 now.size = int128_zero();
994 }
995 while (int128_ne(remain.size, now.size)) {
996 remain.size = int128_sub(remain.size, now.size);
997 remain.offset_within_address_space += int128_get64(now.size);
998 remain.offset_within_region += int128_get64(now.size);
999 now = remain;
1000 if (int128_lt(remain.size, page_size)) {
1001 register_subpage(d, &now);
1002 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1003 now.size = page_size;
1004 register_subpage(d, &now);
1005 } else {
1006 now.size = int128_and(now.size, int128_neg(page_size));
1007 register_multipage(d, &now);
1008 }
1009 }
1010 }
1011
1012 void qemu_flush_coalesced_mmio_buffer(void)
1013 {
1014 if (kvm_enabled())
1015 kvm_flush_coalesced_mmio_buffer();
1016 }
1017
1018 void qemu_mutex_lock_ramlist(void)
1019 {
1020 qemu_mutex_lock(&ram_list.mutex);
1021 }
1022
1023 void qemu_mutex_unlock_ramlist(void)
1024 {
1025 qemu_mutex_unlock(&ram_list.mutex);
1026 }
1027
1028 #ifdef __linux__
1029
1030 #include <sys/vfs.h>
1031
1032 #define HUGETLBFS_MAGIC 0x958458f6
1033
1034 static long gethugepagesize(const char *path)
1035 {
1036 struct statfs fs;
1037 int ret;
1038
1039 do {
1040 ret = statfs(path, &fs);
1041 } while (ret != 0 && errno == EINTR);
1042
1043 if (ret != 0) {
1044 perror(path);
1045 return 0;
1046 }
1047
1048 if (fs.f_type != HUGETLBFS_MAGIC)
1049 fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path);
1050
1051 return fs.f_bsize;
1052 }
1053
1054 static void *file_ram_alloc(RAMBlock *block,
1055 ram_addr_t memory,
1056 const char *path,
1057 Error **errp)
1058 {
1059 char *filename;
1060 char *sanitized_name;
1061 char *c;
1062 void *area;
1063 int fd;
1064 unsigned long hpagesize;
1065
1066 hpagesize = gethugepagesize(path);
1067 if (!hpagesize) {
1068 goto error;
1069 }
1070
1071 if (memory < hpagesize) {
1072 return NULL;
1073 }
1074
1075 if (kvm_enabled() && !kvm_has_sync_mmu()) {
1076 error_setg(errp,
1077 "host lacks kvm mmu notifiers, -mem-path unsupported");
1078 goto error;
1079 }
1080
1081 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1082 sanitized_name = g_strdup(memory_region_name(block->mr));
1083 for (c = sanitized_name; *c != '\0'; c++) {
1084 if (*c == '/')
1085 *c = '_';
1086 }
1087
1088 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1089 sanitized_name);
1090 g_free(sanitized_name);
1091
1092 fd = mkstemp(filename);
1093 if (fd < 0) {
1094 error_setg_errno(errp, errno,
1095 "unable to create backing store for hugepages");
1096 g_free(filename);
1097 goto error;
1098 }
1099 unlink(filename);
1100 g_free(filename);
1101
1102 memory = (memory+hpagesize-1) & ~(hpagesize-1);
1103
1104 /*
1105 * ftruncate is not supported by hugetlbfs in older
1106 * hosts, so don't bother bailing out on errors.
1107 * If anything goes wrong with it under other filesystems,
1108 * mmap will fail.
1109 */
1110 if (ftruncate(fd, memory)) {
1111 perror("ftruncate");
1112 }
1113
1114 area = mmap(0, memory, PROT_READ | PROT_WRITE,
1115 (block->flags & RAM_SHARED ? MAP_SHARED : MAP_PRIVATE),
1116 fd, 0);
1117 if (area == MAP_FAILED) {
1118 error_setg_errno(errp, errno,
1119 "unable to map backing store for hugepages");
1120 close(fd);
1121 goto error;
1122 }
1123
1124 if (mem_prealloc) {
1125 os_mem_prealloc(fd, area, memory);
1126 }
1127
1128 block->fd = fd;
1129 return area;
1130
1131 error:
1132 if (mem_prealloc) {
1133 exit(1);
1134 }
1135 return NULL;
1136 }
1137 #endif
1138
1139 static ram_addr_t find_ram_offset(ram_addr_t size)
1140 {
1141 RAMBlock *block, *next_block;
1142 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1143
1144 assert(size != 0); /* it would hand out same offset multiple times */
1145
1146 if (QTAILQ_EMPTY(&ram_list.blocks))
1147 return 0;
1148
1149 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1150 ram_addr_t end, next = RAM_ADDR_MAX;
1151
1152 end = block->offset + block->length;
1153
1154 QTAILQ_FOREACH(next_block, &ram_list.blocks, next) {
1155 if (next_block->offset >= end) {
1156 next = MIN(next, next_block->offset);
1157 }
1158 }
1159 if (next - end >= size && next - end < mingap) {
1160 offset = end;
1161 mingap = next - end;
1162 }
1163 }
1164
1165 if (offset == RAM_ADDR_MAX) {
1166 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1167 (uint64_t)size);
1168 abort();
1169 }
1170
1171 return offset;
1172 }
1173
1174 ram_addr_t last_ram_offset(void)
1175 {
1176 RAMBlock *block;
1177 ram_addr_t last = 0;
1178
1179 QTAILQ_FOREACH(block, &ram_list.blocks, next)
1180 last = MAX(last, block->offset + block->length);
1181
1182 return last;
1183 }
1184
1185 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1186 {
1187 int ret;
1188
1189 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1190 if (!qemu_opt_get_bool(qemu_get_machine_opts(),
1191 "dump-guest-core", true)) {
1192 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1193 if (ret) {
1194 perror("qemu_madvise");
1195 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1196 "but dump_guest_core=off specified\n");
1197 }
1198 }
1199 }
1200
1201 static RAMBlock *find_ram_block(ram_addr_t addr)
1202 {
1203 RAMBlock *block;
1204
1205 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1206 if (block->offset == addr) {
1207 return block;
1208 }
1209 }
1210
1211 return NULL;
1212 }
1213
1214 void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev)
1215 {
1216 RAMBlock *new_block = find_ram_block(addr);
1217 RAMBlock *block;
1218
1219 assert(new_block);
1220 assert(!new_block->idstr[0]);
1221
1222 if (dev) {
1223 char *id = qdev_get_dev_path(dev);
1224 if (id) {
1225 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1226 g_free(id);
1227 }
1228 }
1229 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1230
1231 /* This assumes the iothread lock is taken here too. */
1232 qemu_mutex_lock_ramlist();
1233 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1234 if (block != new_block && !strcmp(block->idstr, new_block->idstr)) {
1235 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1236 new_block->idstr);
1237 abort();
1238 }
1239 }
1240 qemu_mutex_unlock_ramlist();
1241 }
1242
1243 void qemu_ram_unset_idstr(ram_addr_t addr)
1244 {
1245 RAMBlock *block = find_ram_block(addr);
1246
1247 if (block) {
1248 memset(block->idstr, 0, sizeof(block->idstr));
1249 }
1250 }
1251
1252 static int memory_try_enable_merging(void *addr, size_t len)
1253 {
1254 if (!qemu_opt_get_bool(qemu_get_machine_opts(), "mem-merge", true)) {
1255 /* disabled by the user */
1256 return 0;
1257 }
1258
1259 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1260 }
1261
1262 static ram_addr_t ram_block_add(RAMBlock *new_block, Error **errp)
1263 {
1264 RAMBlock *block;
1265 ram_addr_t old_ram_size, new_ram_size;
1266
1267 old_ram_size = last_ram_offset() >> TARGET_PAGE_BITS;
1268
1269 /* This assumes the iothread lock is taken here too. */
1270 qemu_mutex_lock_ramlist();
1271 new_block->offset = find_ram_offset(new_block->length);
1272
1273 if (!new_block->host) {
1274 if (xen_enabled()) {
1275 xen_ram_alloc(new_block->offset, new_block->length, new_block->mr);
1276 } else {
1277 new_block->host = phys_mem_alloc(new_block->length);
1278 if (!new_block->host) {
1279 error_setg_errno(errp, errno,
1280 "cannot set up guest memory '%s'",
1281 memory_region_name(new_block->mr));
1282 qemu_mutex_unlock_ramlist();
1283 return -1;
1284 }
1285 memory_try_enable_merging(new_block->host, new_block->length);
1286 }
1287 }
1288
1289 /* Keep the list sorted from biggest to smallest block. */
1290 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1291 if (block->length < new_block->length) {
1292 break;
1293 }
1294 }
1295 if (block) {
1296 QTAILQ_INSERT_BEFORE(block, new_block, next);
1297 } else {
1298 QTAILQ_INSERT_TAIL(&ram_list.blocks, new_block, next);
1299 }
1300 ram_list.mru_block = NULL;
1301
1302 ram_list.version++;
1303 qemu_mutex_unlock_ramlist();
1304
1305 new_ram_size = last_ram_offset() >> TARGET_PAGE_BITS;
1306
1307 if (new_ram_size > old_ram_size) {
1308 int i;
1309 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1310 ram_list.dirty_memory[i] =
1311 bitmap_zero_extend(ram_list.dirty_memory[i],
1312 old_ram_size, new_ram_size);
1313 }
1314 }
1315 cpu_physical_memory_set_dirty_range(new_block->offset, new_block->length);
1316
1317 qemu_ram_setup_dump(new_block->host, new_block->length);
1318 qemu_madvise(new_block->host, new_block->length, QEMU_MADV_HUGEPAGE);
1319 qemu_madvise(new_block->host, new_block->length, QEMU_MADV_DONTFORK);
1320
1321 if (kvm_enabled()) {
1322 kvm_setup_guest_memory(new_block->host, new_block->length);
1323 }
1324
1325 return new_block->offset;
1326 }
1327
1328 #ifdef __linux__
1329 ram_addr_t qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
1330 bool share, const char *mem_path,
1331 Error **errp)
1332 {
1333 RAMBlock *new_block;
1334 ram_addr_t addr;
1335 Error *local_err = NULL;
1336
1337 if (xen_enabled()) {
1338 error_setg(errp, "-mem-path not supported with Xen");
1339 return -1;
1340 }
1341
1342 if (phys_mem_alloc != qemu_anon_ram_alloc) {
1343 /*
1344 * file_ram_alloc() needs to allocate just like
1345 * phys_mem_alloc, but we haven't bothered to provide
1346 * a hook there.
1347 */
1348 error_setg(errp,
1349 "-mem-path not supported with this accelerator");
1350 return -1;
1351 }
1352
1353 size = TARGET_PAGE_ALIGN(size);
1354 new_block = g_malloc0(sizeof(*new_block));
1355 new_block->mr = mr;
1356 new_block->length = size;
1357 new_block->flags = share ? RAM_SHARED : 0;
1358 new_block->host = file_ram_alloc(new_block, size,
1359 mem_path, errp);
1360 if (!new_block->host) {
1361 g_free(new_block);
1362 return -1;
1363 }
1364
1365 addr = ram_block_add(new_block, &local_err);
1366 if (local_err) {
1367 g_free(new_block);
1368 error_propagate(errp, local_err);
1369 return -1;
1370 }
1371 return addr;
1372 }
1373 #endif
1374
1375 ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
1376 MemoryRegion *mr, Error **errp)
1377 {
1378 RAMBlock *new_block;
1379 ram_addr_t addr;
1380 Error *local_err = NULL;
1381
1382 size = TARGET_PAGE_ALIGN(size);
1383 new_block = g_malloc0(sizeof(*new_block));
1384 new_block->mr = mr;
1385 new_block->length = size;
1386 new_block->fd = -1;
1387 new_block->host = host;
1388 if (host) {
1389 new_block->flags |= RAM_PREALLOC;
1390 }
1391 addr = ram_block_add(new_block, &local_err);
1392 if (local_err) {
1393 g_free(new_block);
1394 error_propagate(errp, local_err);
1395 return -1;
1396 }
1397 return addr;
1398 }
1399
1400 ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp)
1401 {
1402 return qemu_ram_alloc_from_ptr(size, NULL, mr, errp);
1403 }
1404
1405 void qemu_ram_free_from_ptr(ram_addr_t addr)
1406 {
1407 RAMBlock *block;
1408
1409 /* This assumes the iothread lock is taken here too. */
1410 qemu_mutex_lock_ramlist();
1411 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1412 if (addr == block->offset) {
1413 QTAILQ_REMOVE(&ram_list.blocks, block, next);
1414 ram_list.mru_block = NULL;
1415 ram_list.version++;
1416 g_free(block);
1417 break;
1418 }
1419 }
1420 qemu_mutex_unlock_ramlist();
1421 }
1422
1423 void qemu_ram_free(ram_addr_t addr)
1424 {
1425 RAMBlock *block;
1426
1427 /* This assumes the iothread lock is taken here too. */
1428 qemu_mutex_lock_ramlist();
1429 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1430 if (addr == block->offset) {
1431 QTAILQ_REMOVE(&ram_list.blocks, block, next);
1432 ram_list.mru_block = NULL;
1433 ram_list.version++;
1434 if (block->flags & RAM_PREALLOC) {
1435 ;
1436 } else if (xen_enabled()) {
1437 xen_invalidate_map_cache_entry(block->host);
1438 #ifndef _WIN32
1439 } else if (block->fd >= 0) {
1440 munmap(block->host, block->length);
1441 close(block->fd);
1442 #endif
1443 } else {
1444 qemu_anon_ram_free(block->host, block->length);
1445 }
1446 g_free(block);
1447 break;
1448 }
1449 }
1450 qemu_mutex_unlock_ramlist();
1451
1452 }
1453
1454 #ifndef _WIN32
1455 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
1456 {
1457 RAMBlock *block;
1458 ram_addr_t offset;
1459 int flags;
1460 void *area, *vaddr;
1461
1462 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1463 offset = addr - block->offset;
1464 if (offset < block->length) {
1465 vaddr = block->host + offset;
1466 if (block->flags & RAM_PREALLOC) {
1467 ;
1468 } else if (xen_enabled()) {
1469 abort();
1470 } else {
1471 flags = MAP_FIXED;
1472 munmap(vaddr, length);
1473 if (block->fd >= 0) {
1474 flags |= (block->flags & RAM_SHARED ?
1475 MAP_SHARED : MAP_PRIVATE);
1476 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1477 flags, block->fd, offset);
1478 } else {
1479 /*
1480 * Remap needs to match alloc. Accelerators that
1481 * set phys_mem_alloc never remap. If they did,
1482 * we'd need a remap hook here.
1483 */
1484 assert(phys_mem_alloc == qemu_anon_ram_alloc);
1485
1486 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
1487 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1488 flags, -1, 0);
1489 }
1490 if (area != vaddr) {
1491 fprintf(stderr, "Could not remap addr: "
1492 RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
1493 length, addr);
1494 exit(1);
1495 }
1496 memory_try_enable_merging(vaddr, length);
1497 qemu_ram_setup_dump(vaddr, length);
1498 }
1499 return;
1500 }
1501 }
1502 }
1503 #endif /* !_WIN32 */
1504
1505 int qemu_get_ram_fd(ram_addr_t addr)
1506 {
1507 RAMBlock *block = qemu_get_ram_block(addr);
1508
1509 return block->fd;
1510 }
1511
1512 void *qemu_get_ram_block_host_ptr(ram_addr_t addr)
1513 {
1514 RAMBlock *block = qemu_get_ram_block(addr);
1515
1516 return block->host;
1517 }
1518
1519 /* Return a host pointer to ram allocated with qemu_ram_alloc.
1520 With the exception of the softmmu code in this file, this should
1521 only be used for local memory (e.g. video ram) that the device owns,
1522 and knows it isn't going to access beyond the end of the block.
1523
1524 It should not be used for general purpose DMA.
1525 Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
1526 */
1527 void *qemu_get_ram_ptr(ram_addr_t addr)
1528 {
1529 RAMBlock *block = qemu_get_ram_block(addr);
1530
1531 if (xen_enabled()) {
1532 /* We need to check if the requested address is in the RAM
1533 * because we don't want to map the entire memory in QEMU.
1534 * In that case just map until the end of the page.
1535 */
1536 if (block->offset == 0) {
1537 return xen_map_cache(addr, 0, 0);
1538 } else if (block->host == NULL) {
1539 block->host =
1540 xen_map_cache(block->offset, block->length, 1);
1541 }
1542 }
1543 return block->host + (addr - block->offset);
1544 }
1545
1546 /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr
1547 * but takes a size argument */
1548 static void *qemu_ram_ptr_length(ram_addr_t addr, hwaddr *size)
1549 {
1550 if (*size == 0) {
1551 return NULL;
1552 }
1553 if (xen_enabled()) {
1554 return xen_map_cache(addr, *size, 1);
1555 } else {
1556 RAMBlock *block;
1557
1558 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1559 if (addr - block->offset < block->length) {
1560 if (addr - block->offset + *size > block->length)
1561 *size = block->length - addr + block->offset;
1562 return block->host + (addr - block->offset);
1563 }
1564 }
1565
1566 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1567 abort();
1568 }
1569 }
1570
1571 /* Some of the softmmu routines need to translate from a host pointer
1572 (typically a TLB entry) back to a ram offset. */
1573 MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr)
1574 {
1575 RAMBlock *block;
1576 uint8_t *host = ptr;
1577
1578 if (xen_enabled()) {
1579 *ram_addr = xen_ram_addr_from_mapcache(ptr);
1580 return qemu_get_ram_block(*ram_addr)->mr;
1581 }
1582
1583 block = ram_list.mru_block;
1584 if (block && block->host && host - block->host < block->length) {
1585 goto found;
1586 }
1587
1588 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1589 /* This case append when the block is not mapped. */
1590 if (block->host == NULL) {
1591 continue;
1592 }
1593 if (host - block->host < block->length) {
1594 goto found;
1595 }
1596 }
1597
1598 return NULL;
1599
1600 found:
1601 *ram_addr = block->offset + (host - block->host);
1602 return block->mr;
1603 }
1604
1605 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
1606 uint64_t val, unsigned size)
1607 {
1608 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
1609 tb_invalidate_phys_page_fast(ram_addr, size);
1610 }
1611 switch (size) {
1612 case 1:
1613 stb_p(qemu_get_ram_ptr(ram_addr), val);
1614 break;
1615 case 2:
1616 stw_p(qemu_get_ram_ptr(ram_addr), val);
1617 break;
1618 case 4:
1619 stl_p(qemu_get_ram_ptr(ram_addr), val);
1620 break;
1621 default:
1622 abort();
1623 }
1624 cpu_physical_memory_set_dirty_range_nocode(ram_addr, size);
1625 /* we remove the notdirty callback only if the code has been
1626 flushed */
1627 if (!cpu_physical_memory_is_clean(ram_addr)) {
1628 CPUArchState *env = current_cpu->env_ptr;
1629 tlb_set_dirty(env, current_cpu->mem_io_vaddr);
1630 }
1631 }
1632
1633 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
1634 unsigned size, bool is_write)
1635 {
1636 return is_write;
1637 }
1638
1639 static const MemoryRegionOps notdirty_mem_ops = {
1640 .write = notdirty_mem_write,
1641 .valid.accepts = notdirty_mem_accepts,
1642 .endianness = DEVICE_NATIVE_ENDIAN,
1643 };
1644
1645 /* Generate a debug exception if a watchpoint has been hit. */
1646 static void check_watchpoint(int offset, int len_mask, int flags)
1647 {
1648 CPUState *cpu = current_cpu;
1649 CPUArchState *env = cpu->env_ptr;
1650 target_ulong pc, cs_base;
1651 target_ulong vaddr;
1652 CPUWatchpoint *wp;
1653 int cpu_flags;
1654
1655 if (cpu->watchpoint_hit) {
1656 /* We re-entered the check after replacing the TB. Now raise
1657 * the debug interrupt so that is will trigger after the
1658 * current instruction. */
1659 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
1660 return;
1661 }
1662 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
1663 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1664 if ((vaddr == (wp->vaddr & len_mask) ||
1665 (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
1666 wp->flags |= BP_WATCHPOINT_HIT;
1667 if (!cpu->watchpoint_hit) {
1668 cpu->watchpoint_hit = wp;
1669 tb_check_watchpoint(cpu);
1670 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
1671 cpu->exception_index = EXCP_DEBUG;
1672 cpu_loop_exit(cpu);
1673 } else {
1674 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
1675 tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
1676 cpu_resume_from_signal(cpu, NULL);
1677 }
1678 }
1679 } else {
1680 wp->flags &= ~BP_WATCHPOINT_HIT;
1681 }
1682 }
1683 }
1684
1685 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
1686 so these check for a hit then pass through to the normal out-of-line
1687 phys routines. */
1688 static uint64_t watch_mem_read(void *opaque, hwaddr addr,
1689 unsigned size)
1690 {
1691 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
1692 switch (size) {
1693 case 1: return ldub_phys(&address_space_memory, addr);
1694 case 2: return lduw_phys(&address_space_memory, addr);
1695 case 4: return ldl_phys(&address_space_memory, addr);
1696 default: abort();
1697 }
1698 }
1699
1700 static void watch_mem_write(void *opaque, hwaddr addr,
1701 uint64_t val, unsigned size)
1702 {
1703 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
1704 switch (size) {
1705 case 1:
1706 stb_phys(&address_space_memory, addr, val);
1707 break;
1708 case 2:
1709 stw_phys(&address_space_memory, addr, val);
1710 break;
1711 case 4:
1712 stl_phys(&address_space_memory, addr, val);
1713 break;
1714 default: abort();
1715 }
1716 }
1717
1718 static const MemoryRegionOps watch_mem_ops = {
1719 .read = watch_mem_read,
1720 .write = watch_mem_write,
1721 .endianness = DEVICE_NATIVE_ENDIAN,
1722 };
1723
1724 static uint64_t subpage_read(void *opaque, hwaddr addr,
1725 unsigned len)
1726 {
1727 subpage_t *subpage = opaque;
1728 uint8_t buf[4];
1729
1730 #if defined(DEBUG_SUBPAGE)
1731 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
1732 subpage, len, addr);
1733 #endif
1734 address_space_read(subpage->as, addr + subpage->base, buf, len);
1735 switch (len) {
1736 case 1:
1737 return ldub_p(buf);
1738 case 2:
1739 return lduw_p(buf);
1740 case 4:
1741 return ldl_p(buf);
1742 default:
1743 abort();
1744 }
1745 }
1746
1747 static void subpage_write(void *opaque, hwaddr addr,
1748 uint64_t value, unsigned len)
1749 {
1750 subpage_t *subpage = opaque;
1751 uint8_t buf[4];
1752
1753 #if defined(DEBUG_SUBPAGE)
1754 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
1755 " value %"PRIx64"\n",
1756 __func__, subpage, len, addr, value);
1757 #endif
1758 switch (len) {
1759 case 1:
1760 stb_p(buf, value);
1761 break;
1762 case 2:
1763 stw_p(buf, value);
1764 break;
1765 case 4:
1766 stl_p(buf, value);
1767 break;
1768 default:
1769 abort();
1770 }
1771 address_space_write(subpage->as, addr + subpage->base, buf, len);
1772 }
1773
1774 static bool subpage_accepts(void *opaque, hwaddr addr,
1775 unsigned len, bool is_write)
1776 {
1777 subpage_t *subpage = opaque;
1778 #if defined(DEBUG_SUBPAGE)
1779 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
1780 __func__, subpage, is_write ? 'w' : 'r', len, addr);
1781 #endif
1782
1783 return address_space_access_valid(subpage->as, addr + subpage->base,
1784 len, is_write);
1785 }
1786
1787 static const MemoryRegionOps subpage_ops = {
1788 .read = subpage_read,
1789 .write = subpage_write,
1790 .valid.accepts = subpage_accepts,
1791 .endianness = DEVICE_NATIVE_ENDIAN,
1792 };
1793
1794 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1795 uint16_t section)
1796 {
1797 int idx, eidx;
1798
1799 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
1800 return -1;
1801 idx = SUBPAGE_IDX(start);
1802 eidx = SUBPAGE_IDX(end);
1803 #if defined(DEBUG_SUBPAGE)
1804 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
1805 __func__, mmio, start, end, idx, eidx, section);
1806 #endif
1807 for (; idx <= eidx; idx++) {
1808 mmio->sub_section[idx] = section;
1809 }
1810
1811 return 0;
1812 }
1813
1814 static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
1815 {
1816 subpage_t *mmio;
1817
1818 mmio = g_malloc0(sizeof(subpage_t));
1819
1820 mmio->as = as;
1821 mmio->base = base;
1822 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
1823 NULL, TARGET_PAGE_SIZE);
1824 mmio->iomem.subpage = true;
1825 #if defined(DEBUG_SUBPAGE)
1826 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
1827 mmio, base, TARGET_PAGE_SIZE);
1828 #endif
1829 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
1830
1831 return mmio;
1832 }
1833
1834 static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as,
1835 MemoryRegion *mr)
1836 {
1837 assert(as);
1838 MemoryRegionSection section = {
1839 .address_space = as,
1840 .mr = mr,
1841 .offset_within_address_space = 0,
1842 .offset_within_region = 0,
1843 .size = int128_2_64(),
1844 };
1845
1846 return phys_section_add(map, &section);
1847 }
1848
1849 MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index)
1850 {
1851 return as->dispatch->map.sections[index & ~TARGET_PAGE_MASK].mr;
1852 }
1853
1854 static void io_mem_init(void)
1855 {
1856 memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);
1857 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
1858 NULL, UINT64_MAX);
1859 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
1860 NULL, UINT64_MAX);
1861 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
1862 NULL, UINT64_MAX);
1863 }
1864
1865 static void mem_begin(MemoryListener *listener)
1866 {
1867 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1868 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
1869 uint16_t n;
1870
1871 n = dummy_section(&d->map, as, &io_mem_unassigned);
1872 assert(n == PHYS_SECTION_UNASSIGNED);
1873 n = dummy_section(&d->map, as, &io_mem_notdirty);
1874 assert(n == PHYS_SECTION_NOTDIRTY);
1875 n = dummy_section(&d->map, as, &io_mem_rom);
1876 assert(n == PHYS_SECTION_ROM);
1877 n = dummy_section(&d->map, as, &io_mem_watch);
1878 assert(n == PHYS_SECTION_WATCH);
1879
1880 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
1881 d->as = as;
1882 as->next_dispatch = d;
1883 }
1884
1885 static void mem_commit(MemoryListener *listener)
1886 {
1887 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1888 AddressSpaceDispatch *cur = as->dispatch;
1889 AddressSpaceDispatch *next = as->next_dispatch;
1890
1891 phys_page_compact_all(next, next->map.nodes_nb);
1892
1893 as->dispatch = next;
1894
1895 if (cur) {
1896 phys_sections_free(&cur->map);
1897 g_free(cur);
1898 }
1899 }
1900
1901 static void tcg_commit(MemoryListener *listener)
1902 {
1903 CPUState *cpu;
1904
1905 /* since each CPU stores ram addresses in its TLB cache, we must
1906 reset the modified entries */
1907 /* XXX: slow ! */
1908 CPU_FOREACH(cpu) {
1909 /* FIXME: Disentangle the cpu.h circular files deps so we can
1910 directly get the right CPU from listener. */
1911 if (cpu->tcg_as_listener != listener) {
1912 continue;
1913 }
1914 tlb_flush(cpu, 1);
1915 }
1916 }
1917
1918 static void core_log_global_start(MemoryListener *listener)
1919 {
1920 cpu_physical_memory_set_dirty_tracking(true);
1921 }
1922
1923 static void core_log_global_stop(MemoryListener *listener)
1924 {
1925 cpu_physical_memory_set_dirty_tracking(false);
1926 }
1927
1928 static MemoryListener core_memory_listener = {
1929 .log_global_start = core_log_global_start,
1930 .log_global_stop = core_log_global_stop,
1931 .priority = 1,
1932 };
1933
1934 void address_space_init_dispatch(AddressSpace *as)
1935 {
1936 as->dispatch = NULL;
1937 as->dispatch_listener = (MemoryListener) {
1938 .begin = mem_begin,
1939 .commit = mem_commit,
1940 .region_add = mem_add,
1941 .region_nop = mem_add,
1942 .priority = 0,
1943 };
1944 memory_listener_register(&as->dispatch_listener, as);
1945 }
1946
1947 void address_space_destroy_dispatch(AddressSpace *as)
1948 {
1949 AddressSpaceDispatch *d = as->dispatch;
1950
1951 memory_listener_unregister(&as->dispatch_listener);
1952 g_free(d);
1953 as->dispatch = NULL;
1954 }
1955
1956 static void memory_map_init(void)
1957 {
1958 system_memory = g_malloc(sizeof(*system_memory));
1959
1960 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
1961 address_space_init(&address_space_memory, system_memory, "memory");
1962
1963 system_io = g_malloc(sizeof(*system_io));
1964 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
1965 65536);
1966 address_space_init(&address_space_io, system_io, "I/O");
1967
1968 memory_listener_register(&core_memory_listener, &address_space_memory);
1969 }
1970
1971 MemoryRegion *get_system_memory(void)
1972 {
1973 return system_memory;
1974 }
1975
1976 MemoryRegion *get_system_io(void)
1977 {
1978 return system_io;
1979 }
1980
1981 #endif /* !defined(CONFIG_USER_ONLY) */
1982
1983 /* physical memory access (slow version, mainly for debug) */
1984 #if defined(CONFIG_USER_ONLY)
1985 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
1986 uint8_t *buf, int len, int is_write)
1987 {
1988 int l, flags;
1989 target_ulong page;
1990 void * p;
1991
1992 while (len > 0) {
1993 page = addr & TARGET_PAGE_MASK;
1994 l = (page + TARGET_PAGE_SIZE) - addr;
1995 if (l > len)
1996 l = len;
1997 flags = page_get_flags(page);
1998 if (!(flags & PAGE_VALID))
1999 return -1;
2000 if (is_write) {
2001 if (!(flags & PAGE_WRITE))
2002 return -1;
2003 /* XXX: this code should not depend on lock_user */
2004 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2005 return -1;
2006 memcpy(p, buf, l);
2007 unlock_user(p, addr, l);
2008 } else {
2009 if (!(flags & PAGE_READ))
2010 return -1;
2011 /* XXX: this code should not depend on lock_user */
2012 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2013 return -1;
2014 memcpy(buf, p, l);
2015 unlock_user(p, addr, 0);
2016 }
2017 len -= l;
2018 buf += l;
2019 addr += l;
2020 }
2021 return 0;
2022 }
2023
2024 #else
2025
2026 static void invalidate_and_set_dirty(hwaddr addr,
2027 hwaddr length)
2028 {
2029 if (cpu_physical_memory_is_clean(addr)) {
2030 /* invalidate code */
2031 tb_invalidate_phys_page_range(addr, addr + length, 0);
2032 /* set dirty bit */
2033 cpu_physical_memory_set_dirty_range_nocode(addr, length);
2034 }
2035 xen_modified_memory(addr, length);
2036 }
2037
2038 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2039 {
2040 unsigned access_size_max = mr->ops->valid.max_access_size;
2041
2042 /* Regions are assumed to support 1-4 byte accesses unless
2043 otherwise specified. */
2044 if (access_size_max == 0) {
2045 access_size_max = 4;
2046 }
2047
2048 /* Bound the maximum access by the alignment of the address. */
2049 if (!mr->ops->impl.unaligned) {
2050 unsigned align_size_max = addr & -addr;
2051 if (align_size_max != 0 && align_size_max < access_size_max) {
2052 access_size_max = align_size_max;
2053 }
2054 }
2055
2056 /* Don't attempt accesses larger than the maximum. */
2057 if (l > access_size_max) {
2058 l = access_size_max;
2059 }
2060 if (l & (l - 1)) {
2061 l = 1 << (qemu_fls(l) - 1);
2062 }
2063
2064 return l;
2065 }
2066
2067 bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
2068 int len, bool is_write)
2069 {
2070 hwaddr l;
2071 uint8_t *ptr;
2072 uint64_t val;
2073 hwaddr addr1;
2074 MemoryRegion *mr;
2075 bool error = false;
2076
2077 while (len > 0) {
2078 l = len;
2079 mr = address_space_translate(as, addr, &addr1, &l, is_write);
2080
2081 if (is_write) {
2082 if (!memory_access_is_direct(mr, is_write)) {
2083 l = memory_access_size(mr, l, addr1);
2084 /* XXX: could force current_cpu to NULL to avoid
2085 potential bugs */
2086 switch (l) {
2087 case 8:
2088 /* 64 bit write access */
2089 val = ldq_p(buf);
2090 error |= io_mem_write(mr, addr1, val, 8);
2091 break;
2092 case 4:
2093 /* 32 bit write access */
2094 val = ldl_p(buf);
2095 error |= io_mem_write(mr, addr1, val, 4);
2096 break;
2097 case 2:
2098 /* 16 bit write access */
2099 val = lduw_p(buf);
2100 error |= io_mem_write(mr, addr1, val, 2);
2101 break;
2102 case 1:
2103 /* 8 bit write access */
2104 val = ldub_p(buf);
2105 error |= io_mem_write(mr, addr1, val, 1);
2106 break;
2107 default:
2108 abort();
2109 }
2110 } else {
2111 addr1 += memory_region_get_ram_addr(mr);
2112 /* RAM case */
2113 ptr = qemu_get_ram_ptr(addr1);
2114 memcpy(ptr, buf, l);
2115 invalidate_and_set_dirty(addr1, l);
2116 }
2117 } else {
2118 if (!memory_access_is_direct(mr, is_write)) {
2119 /* I/O case */
2120 l = memory_access_size(mr, l, addr1);
2121 switch (l) {
2122 case 8:
2123 /* 64 bit read access */
2124 error |= io_mem_read(mr, addr1, &val, 8);
2125 stq_p(buf, val);
2126 break;
2127 case 4:
2128 /* 32 bit read access */
2129 error |= io_mem_read(mr, addr1, &val, 4);
2130 stl_p(buf, val);
2131 break;
2132 case 2:
2133 /* 16 bit read access */
2134 error |= io_mem_read(mr, addr1, &val, 2);
2135 stw_p(buf, val);
2136 break;
2137 case 1:
2138 /* 8 bit read access */
2139 error |= io_mem_read(mr, addr1, &val, 1);
2140 stb_p(buf, val);
2141 break;
2142 default:
2143 abort();
2144 }
2145 } else {
2146 /* RAM case */
2147 ptr = qemu_get_ram_ptr(mr->ram_addr + addr1);
2148 memcpy(buf, ptr, l);
2149 }
2150 }
2151 len -= l;
2152 buf += l;
2153 addr += l;
2154 }
2155
2156 return error;
2157 }
2158
2159 bool address_space_write(AddressSpace *as, hwaddr addr,
2160 const uint8_t *buf, int len)
2161 {
2162 return address_space_rw(as, addr, (uint8_t *)buf, len, true);
2163 }
2164
2165 bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
2166 {
2167 return address_space_rw(as, addr, buf, len, false);
2168 }
2169
2170
2171 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
2172 int len, int is_write)
2173 {
2174 address_space_rw(&address_space_memory, addr, buf, len, is_write);
2175 }
2176
2177 enum write_rom_type {
2178 WRITE_DATA,
2179 FLUSH_CACHE,
2180 };
2181
2182 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
2183 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
2184 {
2185 hwaddr l;
2186 uint8_t *ptr;
2187 hwaddr addr1;
2188 MemoryRegion *mr;
2189
2190 while (len > 0) {
2191 l = len;
2192 mr = address_space_translate(as, addr, &addr1, &l, true);
2193
2194 if (!(memory_region_is_ram(mr) ||
2195 memory_region_is_romd(mr))) {
2196 /* do nothing */
2197 } else {
2198 addr1 += memory_region_get_ram_addr(mr);
2199 /* ROM/RAM case */
2200 ptr = qemu_get_ram_ptr(addr1);
2201 switch (type) {
2202 case WRITE_DATA:
2203 memcpy(ptr, buf, l);
2204 invalidate_and_set_dirty(addr1, l);
2205 break;
2206 case FLUSH_CACHE:
2207 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
2208 break;
2209 }
2210 }
2211 len -= l;
2212 buf += l;
2213 addr += l;
2214 }
2215 }
2216
2217 /* used for ROM loading : can write in RAM and ROM */
2218 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
2219 const uint8_t *buf, int len)
2220 {
2221 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
2222 }
2223
2224 void cpu_flush_icache_range(hwaddr start, int len)
2225 {
2226 /*
2227 * This function should do the same thing as an icache flush that was
2228 * triggered from within the guest. For TCG we are always cache coherent,
2229 * so there is no need to flush anything. For KVM / Xen we need to flush
2230 * the host's instruction cache at least.
2231 */
2232 if (tcg_enabled()) {
2233 return;
2234 }
2235
2236 cpu_physical_memory_write_rom_internal(&address_space_memory,
2237 start, NULL, len, FLUSH_CACHE);
2238 }
2239
2240 typedef struct {
2241 MemoryRegion *mr;
2242 void *buffer;
2243 hwaddr addr;
2244 hwaddr len;
2245 } BounceBuffer;
2246
2247 static BounceBuffer bounce;
2248
2249 typedef struct MapClient {
2250 void *opaque;
2251 void (*callback)(void *opaque);
2252 QLIST_ENTRY(MapClient) link;
2253 } MapClient;
2254
2255 static QLIST_HEAD(map_client_list, MapClient) map_client_list
2256 = QLIST_HEAD_INITIALIZER(map_client_list);
2257
2258 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
2259 {
2260 MapClient *client = g_malloc(sizeof(*client));
2261
2262 client->opaque = opaque;
2263 client->callback = callback;
2264 QLIST_INSERT_HEAD(&map_client_list, client, link);
2265 return client;
2266 }
2267
2268 static void cpu_unregister_map_client(void *_client)
2269 {
2270 MapClient *client = (MapClient *)_client;
2271
2272 QLIST_REMOVE(client, link);
2273 g_free(client);
2274 }
2275
2276 static void cpu_notify_map_clients(void)
2277 {
2278 MapClient *client;
2279
2280 while (!QLIST_EMPTY(&map_client_list)) {
2281 client = QLIST_FIRST(&map_client_list);
2282 client->callback(client->opaque);
2283 cpu_unregister_map_client(client);
2284 }
2285 }
2286
2287 bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
2288 {
2289 MemoryRegion *mr;
2290 hwaddr l, xlat;
2291
2292 while (len > 0) {
2293 l = len;
2294 mr = address_space_translate(as, addr, &xlat, &l, is_write);
2295 if (!memory_access_is_direct(mr, is_write)) {
2296 l = memory_access_size(mr, l, addr);
2297 if (!memory_region_access_valid(mr, xlat, l, is_write)) {
2298 return false;
2299 }
2300 }
2301
2302 len -= l;
2303 addr += l;
2304 }
2305 return true;
2306 }
2307
2308 /* Map a physical memory region into a host virtual address.
2309 * May map a subset of the requested range, given by and returned in *plen.
2310 * May return NULL if resources needed to perform the mapping are exhausted.
2311 * Use only for reads OR writes - not for read-modify-write operations.
2312 * Use cpu_register_map_client() to know when retrying the map operation is
2313 * likely to succeed.
2314 */
2315 void *address_space_map(AddressSpace *as,
2316 hwaddr addr,
2317 hwaddr *plen,
2318 bool is_write)
2319 {
2320 hwaddr len = *plen;
2321 hwaddr done = 0;
2322 hwaddr l, xlat, base;
2323 MemoryRegion *mr, *this_mr;
2324 ram_addr_t raddr;
2325
2326 if (len == 0) {
2327 return NULL;
2328 }
2329
2330 l = len;
2331 mr = address_space_translate(as, addr, &xlat, &l, is_write);
2332 if (!memory_access_is_direct(mr, is_write)) {
2333 if (bounce.buffer) {
2334 return NULL;
2335 }
2336 /* Avoid unbounded allocations */
2337 l = MIN(l, TARGET_PAGE_SIZE);
2338 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
2339 bounce.addr = addr;
2340 bounce.len = l;
2341
2342 memory_region_ref(mr);
2343 bounce.mr = mr;
2344 if (!is_write) {
2345 address_space_read(as, addr, bounce.buffer, l);
2346 }
2347
2348 *plen = l;
2349 return bounce.buffer;
2350 }
2351
2352 base = xlat;
2353 raddr = memory_region_get_ram_addr(mr);
2354
2355 for (;;) {
2356 len -= l;
2357 addr += l;
2358 done += l;
2359 if (len == 0) {
2360 break;
2361 }
2362
2363 l = len;
2364 this_mr = address_space_translate(as, addr, &xlat, &l, is_write);
2365 if (this_mr != mr || xlat != base + done) {
2366 break;
2367 }
2368 }
2369
2370 memory_region_ref(mr);
2371 *plen = done;
2372 return qemu_ram_ptr_length(raddr + base, plen);
2373 }
2374
2375 /* Unmaps a memory region previously mapped by address_space_map().
2376 * Will also mark the memory as dirty if is_write == 1. access_len gives
2377 * the amount of memory that was actually read or written by the caller.
2378 */
2379 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
2380 int is_write, hwaddr access_len)
2381 {
2382 if (buffer != bounce.buffer) {
2383 MemoryRegion *mr;
2384 ram_addr_t addr1;
2385
2386 mr = qemu_ram_addr_from_host(buffer, &addr1);
2387 assert(mr != NULL);
2388 if (is_write) {
2389 invalidate_and_set_dirty(addr1, access_len);
2390 }
2391 if (xen_enabled()) {
2392 xen_invalidate_map_cache_entry(buffer);
2393 }
2394 memory_region_unref(mr);
2395 return;
2396 }
2397 if (is_write) {
2398 address_space_write(as, bounce.addr, bounce.buffer, access_len);
2399 }
2400 qemu_vfree(bounce.buffer);
2401 bounce.buffer = NULL;
2402 memory_region_unref(bounce.mr);
2403 cpu_notify_map_clients();
2404 }
2405
2406 void *cpu_physical_memory_map(hwaddr addr,
2407 hwaddr *plen,
2408 int is_write)
2409 {
2410 return address_space_map(&address_space_memory, addr, plen, is_write);
2411 }
2412
2413 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
2414 int is_write, hwaddr access_len)
2415 {
2416 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
2417 }
2418
2419 /* warning: addr must be aligned */
2420 static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr,
2421 enum device_endian endian)
2422 {
2423 uint8_t *ptr;
2424 uint64_t val;
2425 MemoryRegion *mr;
2426 hwaddr l = 4;
2427 hwaddr addr1;
2428
2429 mr = address_space_translate(as, addr, &addr1, &l, false);
2430 if (l < 4 || !memory_access_is_direct(mr, false)) {
2431 /* I/O case */
2432 io_mem_read(mr, addr1, &val, 4);
2433 #if defined(TARGET_WORDS_BIGENDIAN)
2434 if (endian == DEVICE_LITTLE_ENDIAN) {
2435 val = bswap32(val);
2436 }
2437 #else
2438 if (endian == DEVICE_BIG_ENDIAN) {
2439 val = bswap32(val);
2440 }
2441 #endif
2442 } else {
2443 /* RAM case */
2444 ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr)
2445 & TARGET_PAGE_MASK)
2446 + addr1);
2447 switch (endian) {
2448 case DEVICE_LITTLE_ENDIAN:
2449 val = ldl_le_p(ptr);
2450 break;
2451 case DEVICE_BIG_ENDIAN:
2452 val = ldl_be_p(ptr);
2453 break;
2454 default:
2455 val = ldl_p(ptr);
2456 break;
2457 }
2458 }
2459 return val;
2460 }
2461
2462 uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
2463 {
2464 return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
2465 }
2466
2467 uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
2468 {
2469 return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
2470 }
2471
2472 uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
2473 {
2474 return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
2475 }
2476
2477 /* warning: addr must be aligned */
2478 static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr,
2479 enum device_endian endian)
2480 {
2481 uint8_t *ptr;
2482 uint64_t val;
2483 MemoryRegion *mr;
2484 hwaddr l = 8;
2485 hwaddr addr1;
2486
2487 mr = address_space_translate(as, addr, &addr1, &l,
2488 false);
2489 if (l < 8 || !memory_access_is_direct(mr, false)) {
2490 /* I/O case */
2491 io_mem_read(mr, addr1, &val, 8);
2492 #if defined(TARGET_WORDS_BIGENDIAN)
2493 if (endian == DEVICE_LITTLE_ENDIAN) {
2494 val = bswap64(val);
2495 }
2496 #else
2497 if (endian == DEVICE_BIG_ENDIAN) {
2498 val = bswap64(val);
2499 }
2500 #endif
2501 } else {
2502 /* RAM case */
2503 ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr)
2504 & TARGET_PAGE_MASK)
2505 + addr1);
2506 switch (endian) {
2507 case DEVICE_LITTLE_ENDIAN:
2508 val = ldq_le_p(ptr);
2509 break;
2510 case DEVICE_BIG_ENDIAN:
2511 val = ldq_be_p(ptr);
2512 break;
2513 default:
2514 val = ldq_p(ptr);
2515 break;
2516 }
2517 }
2518 return val;
2519 }
2520
2521 uint64_t ldq_phys(AddressSpace *as, hwaddr addr)
2522 {
2523 return ldq_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
2524 }
2525
2526 uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr)
2527 {
2528 return ldq_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
2529 }
2530
2531 uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr)
2532 {
2533 return ldq_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
2534 }
2535
2536 /* XXX: optimize */
2537 uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
2538 {
2539 uint8_t val;
2540 address_space_rw(as, addr, &val, 1, 0);
2541 return val;
2542 }
2543
2544 /* warning: addr must be aligned */
2545 static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr,
2546 enum device_endian endian)
2547 {
2548 uint8_t *ptr;
2549 uint64_t val;
2550 MemoryRegion *mr;
2551 hwaddr l = 2;
2552 hwaddr addr1;
2553
2554 mr = address_space_translate(as, addr, &addr1, &l,
2555 false);
2556 if (l < 2 || !memory_access_is_direct(mr, false)) {
2557 /* I/O case */
2558 io_mem_read(mr, addr1, &val, 2);
2559 #if defined(TARGET_WORDS_BIGENDIAN)
2560 if (endian == DEVICE_LITTLE_ENDIAN) {
2561 val = bswap16(val);
2562 }
2563 #else
2564 if (endian == DEVICE_BIG_ENDIAN) {
2565 val = bswap16(val);
2566 }
2567 #endif
2568 } else {
2569 /* RAM case */
2570 ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr)
2571 & TARGET_PAGE_MASK)
2572 + addr1);
2573 switch (endian) {
2574 case DEVICE_LITTLE_ENDIAN:
2575 val = lduw_le_p(ptr);
2576 break;
2577 case DEVICE_BIG_ENDIAN:
2578 val = lduw_be_p(ptr);
2579 break;
2580 default:
2581 val = lduw_p(ptr);
2582 break;
2583 }
2584 }
2585 return val;
2586 }
2587
2588 uint32_t lduw_phys(AddressSpace *as, hwaddr addr)
2589 {
2590 return lduw_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN);
2591 }
2592
2593 uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr)
2594 {
2595 return lduw_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN);
2596 }
2597
2598 uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
2599 {
2600 return lduw_phys_internal(as, addr, DEVICE_BIG_ENDIAN);
2601 }
2602
2603 /* warning: addr must be aligned. The ram page is not masked as dirty
2604 and the code inside is not invalidated. It is useful if the dirty
2605 bits are used to track modified PTEs */
2606 void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
2607 {
2608 uint8_t *ptr;
2609 MemoryRegion *mr;
2610 hwaddr l = 4;
2611 hwaddr addr1;
2612
2613 mr = address_space_translate(as, addr, &addr1, &l,
2614 true);
2615 if (l < 4 || !memory_access_is_direct(mr, true)) {
2616 io_mem_write(mr, addr1, val, 4);
2617 } else {
2618 addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
2619 ptr = qemu_get_ram_ptr(addr1);
2620 stl_p(ptr, val);
2621
2622 if (unlikely(in_migration)) {
2623 if (cpu_physical_memory_is_clean(addr1)) {
2624 /* invalidate code */
2625 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
2626 /* set dirty bit */
2627 cpu_physical_memory_set_dirty_range_nocode(addr1, 4);
2628 }
2629 }
2630 }
2631 }
2632
2633 /* warning: addr must be aligned */
2634 static inline void stl_phys_internal(AddressSpace *as,
2635 hwaddr addr, uint32_t val,
2636 enum device_endian endian)
2637 {
2638 uint8_t *ptr;
2639 MemoryRegion *mr;
2640 hwaddr l = 4;
2641 hwaddr addr1;
2642
2643 mr = address_space_translate(as, addr, &addr1, &l,
2644 true);
2645 if (l < 4 || !memory_access_is_direct(mr, true)) {
2646 #if defined(TARGET_WORDS_BIGENDIAN)
2647 if (endian == DEVICE_LITTLE_ENDIAN) {
2648 val = bswap32(val);
2649 }
2650 #else
2651 if (endian == DEVICE_BIG_ENDIAN) {
2652 val = bswap32(val);
2653 }
2654 #endif
2655 io_mem_write(mr, addr1, val, 4);
2656 } else {
2657 /* RAM case */
2658 addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
2659 ptr = qemu_get_ram_ptr(addr1);
2660 switch (endian) {
2661 case DEVICE_LITTLE_ENDIAN:
2662 stl_le_p(ptr, val);
2663 break;
2664 case DEVICE_BIG_ENDIAN:
2665 stl_be_p(ptr, val);
2666 break;
2667 default:
2668 stl_p(ptr, val);
2669 break;
2670 }
2671 invalidate_and_set_dirty(addr1, 4);
2672 }
2673 }
2674
2675 void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val)
2676 {
2677 stl_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
2678 }
2679
2680 void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
2681 {
2682 stl_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
2683 }
2684
2685 void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
2686 {
2687 stl_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
2688 }
2689
2690 /* XXX: optimize */
2691 void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
2692 {
2693 uint8_t v = val;
2694 address_space_rw(as, addr, &v, 1, 1);
2695 }
2696
2697 /* warning: addr must be aligned */
2698 static inline void stw_phys_internal(AddressSpace *as,
2699 hwaddr addr, uint32_t val,
2700 enum device_endian endian)
2701 {
2702 uint8_t *ptr;
2703 MemoryRegion *mr;
2704 hwaddr l = 2;
2705 hwaddr addr1;
2706
2707 mr = address_space_translate(as, addr, &addr1, &l, true);
2708 if (l < 2 || !memory_access_is_direct(mr, true)) {
2709 #if defined(TARGET_WORDS_BIGENDIAN)
2710 if (endian == DEVICE_LITTLE_ENDIAN) {
2711 val = bswap16(val);
2712 }
2713 #else
2714 if (endian == DEVICE_BIG_ENDIAN) {
2715 val = bswap16(val);
2716 }
2717 #endif
2718 io_mem_write(mr, addr1, val, 2);
2719 } else {
2720 /* RAM case */
2721 addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
2722 ptr = qemu_get_ram_ptr(addr1);
2723 switch (endian) {
2724 case DEVICE_LITTLE_ENDIAN:
2725 stw_le_p(ptr, val);
2726 break;
2727 case DEVICE_BIG_ENDIAN:
2728 stw_be_p(ptr, val);
2729 break;
2730 default:
2731 stw_p(ptr, val);
2732 break;
2733 }
2734 invalidate_and_set_dirty(addr1, 2);
2735 }
2736 }
2737
2738 void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val)
2739 {
2740 stw_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
2741 }
2742
2743 void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
2744 {
2745 stw_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
2746 }
2747
2748 void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
2749 {
2750 stw_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
2751 }
2752
2753 /* XXX: optimize */
2754 void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
2755 {
2756 val = tswap64(val);
2757 address_space_rw(as, addr, (void *) &val, 8, 1);
2758 }
2759
2760 void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
2761 {
2762 val = cpu_to_le64(val);
2763 address_space_rw(as, addr, (void *) &val, 8, 1);
2764 }
2765
2766 void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
2767 {
2768 val = cpu_to_be64(val);
2769 address_space_rw(as, addr, (void *) &val, 8, 1);
2770 }
2771
2772 /* virtual memory access for debug (includes writing to ROM) */
2773 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2774 uint8_t *buf, int len, int is_write)
2775 {
2776 int l;
2777 hwaddr phys_addr;
2778 target_ulong page;
2779
2780 while (len > 0) {
2781 page = addr & TARGET_PAGE_MASK;
2782 phys_addr = cpu_get_phys_page_debug(cpu, page);
2783 /* if no physical page mapped, return an error */
2784 if (phys_addr == -1)
2785 return -1;
2786 l = (page + TARGET_PAGE_SIZE) - addr;
2787 if (l > len)
2788 l = len;
2789 phys_addr += (addr & ~TARGET_PAGE_MASK);
2790 if (is_write) {
2791 cpu_physical_memory_write_rom(cpu->as, phys_addr, buf, l);
2792 } else {
2793 address_space_rw(cpu->as, phys_addr, buf, l, 0);
2794 }
2795 len -= l;
2796 buf += l;
2797 addr += l;
2798 }
2799 return 0;
2800 }
2801 #endif
2802
2803 /*
2804 * A helper function for the _utterly broken_ virtio device model to find out if
2805 * it's running on a big endian machine. Don't do this at home kids!
2806 */
2807 bool target_words_bigendian(void);
2808 bool target_words_bigendian(void)
2809 {
2810 #if defined(TARGET_WORDS_BIGENDIAN)
2811 return true;
2812 #else
2813 return false;
2814 #endif
2815 }
2816
2817 #ifndef CONFIG_USER_ONLY
2818 bool cpu_physical_memory_is_io(hwaddr phys_addr)
2819 {
2820 MemoryRegion*mr;
2821 hwaddr l = 1;
2822
2823 mr = address_space_translate(&address_space_memory,
2824 phys_addr, &phys_addr, &l, false);
2825
2826 return !(memory_region_is_ram(mr) ||
2827 memory_region_is_romd(mr));
2828 }
2829
2830 void qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
2831 {
2832 RAMBlock *block;
2833
2834 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
2835 func(block->host, block->offset, block->length, opaque);
2836 }
2837 }
2838 #endif
CRIS target port of Qemu