4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
26 #include "exec/cpu_ldst.h"
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
31 #include "trace-tcg.h"
34 //#define DEBUG_DISPATCH 1
36 /* Fake floating point. */
37 #define tcg_gen_mov_f64 tcg_gen_mov_i64
38 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
39 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
41 #define DEFO32(name, offset) static TCGv QREG_##name;
42 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
43 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
49 static TCGv_i32 cpu_halted
;
50 static TCGv_i32 cpu_exception_index
;
52 static TCGv_ptr cpu_env
;
54 static char cpu_reg_names
[3*8*3 + 5*4];
55 static TCGv cpu_dregs
[8];
56 static TCGv cpu_aregs
[8];
57 static TCGv_i64 cpu_fregs
[8];
58 static TCGv_i64 cpu_macc
[4];
60 #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]
61 #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]
62 #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]
63 #define MACREG(acc) cpu_macc[acc]
64 #define QREG_SP cpu_aregs[7]
66 static TCGv NULL_QREG
;
67 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
68 /* Used to distinguish stores from bad addressing modes. */
69 static TCGv store_dummy
;
71 #include "exec/gen-icount.h"
73 void m68k_tcg_init(void)
78 #define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
79 #define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
80 #define DEFF64(name, offset) DEFO64(name, offset)
86 cpu_halted
= tcg_global_mem_new_i32(TCG_AREG0
,
87 -offsetof(M68kCPU
, env
) +
88 offsetof(CPUState
, halted
), "HALTED");
89 cpu_exception_index
= tcg_global_mem_new_i32(TCG_AREG0
,
90 -offsetof(M68kCPU
, env
) +
91 offsetof(CPUState
, exception_index
),
94 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
97 for (i
= 0; i
< 8; i
++) {
99 cpu_dregs
[i
] = tcg_global_mem_new(TCG_AREG0
,
100 offsetof(CPUM68KState
, dregs
[i
]), p
);
102 sprintf(p
, "A%d", i
);
103 cpu_aregs
[i
] = tcg_global_mem_new(TCG_AREG0
,
104 offsetof(CPUM68KState
, aregs
[i
]), p
);
106 sprintf(p
, "F%d", i
);
107 cpu_fregs
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
108 offsetof(CPUM68KState
, fregs
[i
]), p
);
111 for (i
= 0; i
< 4; i
++) {
112 sprintf(p
, "ACC%d", i
);
113 cpu_macc
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
114 offsetof(CPUM68KState
, macc
[i
]), p
);
118 NULL_QREG
= tcg_global_mem_new(TCG_AREG0
, -4, "NULL");
119 store_dummy
= tcg_global_mem_new(TCG_AREG0
, -8, "NULL");
122 /* internal defines */
123 typedef struct DisasContext
{
125 target_ulong insn_pc
; /* Start of the current instruction. */
131 struct TranslationBlock
*tb
;
132 int singlestep_enabled
;
137 #define DISAS_JUMP_NEXT 4
139 #if defined(CONFIG_USER_ONLY)
142 #define IS_USER(s) s->user
145 /* XXX: move that elsewhere */
146 /* ??? Fix exceptions. */
147 static void *gen_throws_exception
;
148 #define gen_last_qop NULL
156 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
158 #ifdef DEBUG_DISPATCH
159 #define DISAS_INSN(name) \
160 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
162 static void disas_##name(CPUM68KState *env, DisasContext *s, \
165 qemu_log("Dispatch " #name "\n"); \
166 real_disas_##name(s, env, insn); \
168 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
171 #define DISAS_INSN(name) \
172 static void disas_##name(CPUM68KState *env, DisasContext *s, \
176 /* Generate a load from the specified address. Narrow values are
177 sign extended to full register width. */
178 static inline TCGv
gen_load(DisasContext
* s
, int opsize
, TCGv addr
, int sign
)
181 int index
= IS_USER(s
);
182 tmp
= tcg_temp_new_i32();
186 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
188 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
192 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
194 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
198 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
201 g_assert_not_reached();
203 gen_throws_exception
= gen_last_qop
;
207 static inline TCGv_i64
gen_load64(DisasContext
* s
, TCGv addr
)
210 int index
= IS_USER(s
);
211 tmp
= tcg_temp_new_i64();
212 tcg_gen_qemu_ldf64(tmp
, addr
, index
);
213 gen_throws_exception
= gen_last_qop
;
217 /* Generate a store. */
218 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
)
220 int index
= IS_USER(s
);
223 tcg_gen_qemu_st8(val
, addr
, index
);
226 tcg_gen_qemu_st16(val
, addr
, index
);
230 tcg_gen_qemu_st32(val
, addr
, index
);
233 g_assert_not_reached();
235 gen_throws_exception
= gen_last_qop
;
238 static inline void gen_store64(DisasContext
*s
, TCGv addr
, TCGv_i64 val
)
240 int index
= IS_USER(s
);
241 tcg_gen_qemu_stf64(val
, addr
, index
);
242 gen_throws_exception
= gen_last_qop
;
251 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
252 otherwise generate a store. */
253 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
256 if (what
== EA_STORE
) {
257 gen_store(s
, opsize
, addr
, val
);
260 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
);
264 /* Read a 32-bit immediate constant. */
265 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
268 im
= ((uint32_t)cpu_lduw_code(env
, s
->pc
)) << 16;
270 im
|= cpu_lduw_code(env
, s
->pc
);
275 /* Calculate and address index. */
276 static TCGv
gen_addr_index(uint16_t ext
, TCGv tmp
)
281 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
282 if ((ext
& 0x800) == 0) {
283 tcg_gen_ext16s_i32(tmp
, add
);
286 scale
= (ext
>> 9) & 3;
288 tcg_gen_shli_i32(tmp
, add
, scale
);
294 /* Handle a base + index + displacement effective addresss.
295 A NULL_QREG base means pc-relative. */
296 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
305 ext
= cpu_lduw_code(env
, s
->pc
);
308 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
312 /* full extension word format */
313 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
316 if ((ext
& 0x30) > 0x10) {
317 /* base displacement */
318 if ((ext
& 0x30) == 0x20) {
319 bd
= (int16_t)cpu_lduw_code(env
, s
->pc
);
322 bd
= read_im32(env
, s
);
327 tmp
= tcg_temp_new();
328 if ((ext
& 0x44) == 0) {
330 add
= gen_addr_index(ext
, tmp
);
334 if ((ext
& 0x80) == 0) {
335 /* base not suppressed */
336 if (IS_NULL_QREG(base
)) {
337 base
= tcg_const_i32(offset
+ bd
);
340 if (!IS_NULL_QREG(add
)) {
341 tcg_gen_add_i32(tmp
, add
, base
);
347 if (!IS_NULL_QREG(add
)) {
349 tcg_gen_addi_i32(tmp
, add
, bd
);
353 add
= tcg_const_i32(bd
);
355 if ((ext
& 3) != 0) {
356 /* memory indirect */
357 base
= gen_load(s
, OS_LONG
, add
, 0);
358 if ((ext
& 0x44) == 4) {
359 add
= gen_addr_index(ext
, tmp
);
360 tcg_gen_add_i32(tmp
, add
, base
);
366 /* outer displacement */
367 if ((ext
& 3) == 2) {
368 od
= (int16_t)cpu_lduw_code(env
, s
->pc
);
371 od
= read_im32(env
, s
);
377 tcg_gen_addi_i32(tmp
, add
, od
);
382 /* brief extension word format */
383 tmp
= tcg_temp_new();
384 add
= gen_addr_index(ext
, tmp
);
385 if (!IS_NULL_QREG(base
)) {
386 tcg_gen_add_i32(tmp
, add
, base
);
388 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
390 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
397 /* Update the CPU env CC_OP state. */
398 static inline void gen_flush_cc_op(DisasContext
*s
)
400 if (s
->cc_op
!= CC_OP_DYNAMIC
)
401 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
404 /* Evaluate all the CC flags. */
405 static inline void gen_flush_flags(DisasContext
*s
)
407 if (s
->cc_op
== CC_OP_FLAGS
)
410 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
411 s
->cc_op
= CC_OP_FLAGS
;
414 static void gen_logic_cc(DisasContext
*s
, TCGv val
)
416 tcg_gen_mov_i32(QREG_CC_DEST
, val
);
417 s
->cc_op
= CC_OP_LOGIC
;
420 static void gen_update_cc_add(TCGv dest
, TCGv src
)
422 tcg_gen_mov_i32(QREG_CC_DEST
, dest
);
423 tcg_gen_mov_i32(QREG_CC_SRC
, src
);
426 static inline int opsize_bytes(int opsize
)
429 case OS_BYTE
: return 1;
430 case OS_WORD
: return 2;
431 case OS_LONG
: return 4;
432 case OS_SINGLE
: return 4;
433 case OS_DOUBLE
: return 8;
435 g_assert_not_reached();
439 /* Assign value to a register. If the width is less than the register width
440 only the low part of the register is set. */
441 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
446 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
447 tmp
= tcg_temp_new();
448 tcg_gen_ext8u_i32(tmp
, val
);
449 tcg_gen_or_i32(reg
, reg
, tmp
);
452 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
453 tmp
= tcg_temp_new();
454 tcg_gen_ext16u_i32(tmp
, val
);
455 tcg_gen_or_i32(reg
, reg
, tmp
);
459 tcg_gen_mov_i32(reg
, val
);
462 g_assert_not_reached();
466 /* Sign or zero extend a value. */
467 static inline TCGv
gen_extend(TCGv val
, int opsize
, int sign
)
473 tmp
= tcg_temp_new();
475 tcg_gen_ext8s_i32(tmp
, val
);
477 tcg_gen_ext8u_i32(tmp
, val
);
480 tmp
= tcg_temp_new();
482 tcg_gen_ext16s_i32(tmp
, val
);
484 tcg_gen_ext16u_i32(tmp
, val
);
491 g_assert_not_reached();
496 /* Generate code for an "effective address". Does not adjust the base
497 register for autoincrement addressing modes. */
498 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
506 switch ((insn
>> 3) & 7) {
507 case 0: /* Data register direct. */
508 case 1: /* Address register direct. */
510 case 2: /* Indirect register */
511 case 3: /* Indirect postincrement. */
512 return AREG(insn
, 0);
513 case 4: /* Indirect predecrememnt. */
515 tmp
= tcg_temp_new();
516 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
518 case 5: /* Indirect displacement. */
520 tmp
= tcg_temp_new();
521 ext
= cpu_lduw_code(env
, s
->pc
);
523 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
525 case 6: /* Indirect index + displacement. */
527 return gen_lea_indexed(env
, s
, reg
);
530 case 0: /* Absolute short. */
531 offset
= cpu_ldsw_code(env
, s
->pc
);
533 return tcg_const_i32(offset
);
534 case 1: /* Absolute long. */
535 offset
= read_im32(env
, s
);
536 return tcg_const_i32(offset
);
537 case 2: /* pc displacement */
539 offset
+= cpu_ldsw_code(env
, s
->pc
);
541 return tcg_const_i32(offset
);
542 case 3: /* pc index+displacement. */
543 return gen_lea_indexed(env
, s
, NULL_QREG
);
544 case 4: /* Immediate. */
549 /* Should never happen. */
553 /* Helper function for gen_ea. Reuse the computed address between the
554 for read/write operands. */
555 static inline TCGv
gen_ea_once(CPUM68KState
*env
, DisasContext
*s
,
556 uint16_t insn
, int opsize
, TCGv val
,
557 TCGv
*addrp
, ea_what what
)
561 if (addrp
&& what
== EA_STORE
) {
564 tmp
= gen_lea(env
, s
, insn
, opsize
);
565 if (IS_NULL_QREG(tmp
))
570 return gen_ldst(s
, opsize
, tmp
, val
, what
);
573 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
574 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
575 ADDRP is non-null for readwrite operands. */
576 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
577 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
583 switch ((insn
>> 3) & 7) {
584 case 0: /* Data register direct. */
586 if (what
== EA_STORE
) {
587 gen_partset_reg(opsize
, reg
, val
);
590 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
592 case 1: /* Address register direct. */
594 if (what
== EA_STORE
) {
595 tcg_gen_mov_i32(reg
, val
);
598 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
600 case 2: /* Indirect register */
602 return gen_ldst(s
, opsize
, reg
, val
, what
);
603 case 3: /* Indirect postincrement. */
605 result
= gen_ldst(s
, opsize
, reg
, val
, what
);
606 /* ??? This is not exception safe. The instruction may still
607 fault after this point. */
608 if (what
== EA_STORE
|| !addrp
)
609 tcg_gen_addi_i32(reg
, reg
, opsize_bytes(opsize
));
611 case 4: /* Indirect predecrememnt. */
614 if (addrp
&& what
== EA_STORE
) {
617 tmp
= gen_lea(env
, s
, insn
, opsize
);
618 if (IS_NULL_QREG(tmp
))
623 result
= gen_ldst(s
, opsize
, tmp
, val
, what
);
624 /* ??? This is not exception safe. The instruction may still
625 fault after this point. */
626 if (what
== EA_STORE
|| !addrp
) {
628 tcg_gen_mov_i32(reg
, tmp
);
632 case 5: /* Indirect displacement. */
633 case 6: /* Indirect index + displacement. */
634 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
637 case 0: /* Absolute short. */
638 case 1: /* Absolute long. */
639 case 2: /* pc displacement */
640 case 3: /* pc index+displacement. */
641 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
642 case 4: /* Immediate. */
643 /* Sign extend values for consistency. */
646 if (what
== EA_LOADS
) {
647 offset
= cpu_ldsb_code(env
, s
->pc
+ 1);
649 offset
= cpu_ldub_code(env
, s
->pc
+ 1);
654 if (what
== EA_LOADS
) {
655 offset
= cpu_ldsw_code(env
, s
->pc
);
657 offset
= cpu_lduw_code(env
, s
->pc
);
662 offset
= read_im32(env
, s
);
665 g_assert_not_reached();
667 return tcg_const_i32(offset
);
672 /* Should never happen. */
676 /* This generates a conditional branch, clobbering all temporaries. */
677 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
681 /* TODO: Optimize compare/branch pairs rather than always flushing
682 flag state to CC_OP_FLAGS. */
690 case 2: /* HI (!C && !Z) */
691 tmp
= tcg_temp_new();
692 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_C
| CCF_Z
);
693 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
695 case 3: /* LS (C || Z) */
696 tmp
= tcg_temp_new();
697 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_C
| CCF_Z
);
698 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
700 case 4: /* CC (!C) */
701 tmp
= tcg_temp_new();
702 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_C
);
703 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
706 tmp
= tcg_temp_new();
707 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_C
);
708 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
710 case 6: /* NE (!Z) */
711 tmp
= tcg_temp_new();
712 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_Z
);
713 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
716 tmp
= tcg_temp_new();
717 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_Z
);
718 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
720 case 8: /* VC (!V) */
721 tmp
= tcg_temp_new();
722 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_V
);
723 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
726 tmp
= tcg_temp_new();
727 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_V
);
728 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
730 case 10: /* PL (!N) */
731 tmp
= tcg_temp_new();
732 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_N
);
733 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
735 case 11: /* MI (N) */
736 tmp
= tcg_temp_new();
737 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_N
);
738 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
740 case 12: /* GE (!(N ^ V)) */
741 tmp
= tcg_temp_new();
742 assert(CCF_V
== (CCF_N
>> 2));
743 tcg_gen_shri_i32(tmp
, QREG_CC_DEST
, 2);
744 tcg_gen_xor_i32(tmp
, tmp
, QREG_CC_DEST
);
745 tcg_gen_andi_i32(tmp
, tmp
, CCF_V
);
746 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
748 case 13: /* LT (N ^ V) */
749 tmp
= tcg_temp_new();
750 assert(CCF_V
== (CCF_N
>> 2));
751 tcg_gen_shri_i32(tmp
, QREG_CC_DEST
, 2);
752 tcg_gen_xor_i32(tmp
, tmp
, QREG_CC_DEST
);
753 tcg_gen_andi_i32(tmp
, tmp
, CCF_V
);
754 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
756 case 14: /* GT (!(Z || (N ^ V))) */
757 tmp
= tcg_temp_new();
758 assert(CCF_V
== (CCF_N
>> 2));
759 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_N
);
760 tcg_gen_shri_i32(tmp
, tmp
, 2);
761 tcg_gen_xor_i32(tmp
, tmp
, QREG_CC_DEST
);
762 tcg_gen_andi_i32(tmp
, tmp
, CCF_V
| CCF_Z
);
763 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
765 case 15: /* LE (Z || (N ^ V)) */
766 tmp
= tcg_temp_new();
767 assert(CCF_V
== (CCF_N
>> 2));
768 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_N
);
769 tcg_gen_shri_i32(tmp
, tmp
, 2);
770 tcg_gen_xor_i32(tmp
, tmp
, QREG_CC_DEST
);
771 tcg_gen_andi_i32(tmp
, tmp
, CCF_V
| CCF_Z
);
772 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
775 /* Should ever happen. */
786 l1
= gen_new_label();
787 cond
= (insn
>> 8) & 0xf;
789 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
790 /* This is safe because we modify the reg directly, with no other values
792 gen_jmpcc(s
, cond
^ 1, l1
);
793 tcg_gen_ori_i32(reg
, reg
, 0xff);
797 /* Force a TB lookup after an instruction that changes the CPU state. */
798 static void gen_lookup_tb(DisasContext
*s
)
801 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
802 s
->is_jmp
= DISAS_UPDATE
;
805 /* Generate a jump to an immediate address. */
806 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
809 tcg_gen_movi_i32(QREG_PC
, dest
);
810 s
->is_jmp
= DISAS_JUMP
;
813 /* Generate a jump to the address in qreg DEST. */
814 static void gen_jmp(DisasContext
*s
, TCGv dest
)
817 tcg_gen_mov_i32(QREG_PC
, dest
);
818 s
->is_jmp
= DISAS_JUMP
;
821 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
824 gen_jmp_im(s
, where
);
825 gen_helper_raise_exception(cpu_env
, tcg_const_i32(nr
));
828 static inline void gen_addr_fault(DisasContext
*s
)
830 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
833 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
834 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
835 op_sign ? EA_LOADS : EA_LOADU); \
836 if (IS_NULL_QREG(result)) { \
842 #define DEST_EA(env, insn, opsize, val, addrp) do { \
843 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
844 if (IS_NULL_QREG(ea_result)) { \
850 /* Generate a jump to an immediate address. */
851 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
853 TranslationBlock
*tb
;
856 if (unlikely(s
->singlestep_enabled
)) {
857 gen_exception(s
, dest
, EXCP_DEBUG
);
858 } else if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
859 (s
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
861 tcg_gen_movi_i32(QREG_PC
, dest
);
862 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
867 s
->is_jmp
= DISAS_TB_JUMP
;
870 DISAS_INSN(undef_mac
)
872 gen_exception(s
, s
->pc
- 2, EXCP_LINEA
);
875 DISAS_INSN(undef_fpu
)
877 gen_exception(s
, s
->pc
- 2, EXCP_LINEF
);
882 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
884 gen_exception(s
, s
->pc
- 2, EXCP_UNSUPPORTED
);
885 cpu_abort(CPU(cpu
), "Illegal instruction: %04x @ %08x", insn
, s
->pc
- 2);
895 sign
= (insn
& 0x100) != 0;
897 tmp
= tcg_temp_new();
899 tcg_gen_ext16s_i32(tmp
, reg
);
901 tcg_gen_ext16u_i32(tmp
, reg
);
902 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
903 tcg_gen_mul_i32(tmp
, tmp
, src
);
904 tcg_gen_mov_i32(reg
, tmp
);
905 /* Unlike m68k, coldfire always clears the overflow bit. */
906 gen_logic_cc(s
, tmp
);
916 sign
= (insn
& 0x100) != 0;
919 tcg_gen_ext16s_i32(QREG_DIV1
, reg
);
921 tcg_gen_ext16u_i32(QREG_DIV1
, reg
);
923 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
924 tcg_gen_mov_i32(QREG_DIV2
, src
);
926 gen_helper_divs(cpu_env
, tcg_const_i32(1));
928 gen_helper_divu(cpu_env
, tcg_const_i32(1));
931 tmp
= tcg_temp_new();
932 src
= tcg_temp_new();
933 tcg_gen_ext16u_i32(tmp
, QREG_DIV1
);
934 tcg_gen_shli_i32(src
, QREG_DIV2
, 16);
935 tcg_gen_or_i32(reg
, tmp
, src
);
936 s
->cc_op
= CC_OP_FLAGS
;
946 ext
= cpu_lduw_code(env
, s
->pc
);
949 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
954 tcg_gen_mov_i32(QREG_DIV1
, num
);
955 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
956 tcg_gen_mov_i32(QREG_DIV2
, den
);
958 gen_helper_divs(cpu_env
, tcg_const_i32(0));
960 gen_helper_divu(cpu_env
, tcg_const_i32(0));
962 if ((ext
& 7) == ((ext
>> 12) & 7)) {
964 tcg_gen_mov_i32 (reg
, QREG_DIV1
);
967 tcg_gen_mov_i32 (reg
, QREG_DIV2
);
969 s
->cc_op
= CC_OP_FLAGS
;
981 add
= (insn
& 0x4000) != 0;
983 dest
= tcg_temp_new();
985 SRC_EA(env
, tmp
, OS_LONG
, 0, &addr
);
989 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
992 tcg_gen_add_i32(dest
, tmp
, src
);
993 gen_helper_xflag_lt(QREG_CC_X
, dest
, src
);
994 s
->cc_op
= CC_OP_ADD
;
996 gen_helper_xflag_lt(QREG_CC_X
, tmp
, src
);
997 tcg_gen_sub_i32(dest
, tmp
, src
);
998 s
->cc_op
= CC_OP_SUB
;
1000 gen_update_cc_add(dest
, src
);
1002 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1004 tcg_gen_mov_i32(reg
, dest
);
1009 /* Reverse the order of the bits in REG. */
1013 reg
= DREG(insn
, 0);
1014 gen_helper_bitrev(reg
, reg
);
1017 DISAS_INSN(bitop_reg
)
1027 if ((insn
& 0x38) != 0)
1031 op
= (insn
>> 6) & 3;
1032 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1033 src2
= DREG(insn
, 9);
1034 dest
= tcg_temp_new();
1037 tmp
= tcg_temp_new();
1038 if (opsize
== OS_BYTE
)
1039 tcg_gen_andi_i32(tmp
, src2
, 7);
1041 tcg_gen_andi_i32(tmp
, src2
, 31);
1043 tmp
= tcg_temp_new();
1044 tcg_gen_shr_i32(tmp
, src1
, src2
);
1045 tcg_gen_andi_i32(tmp
, tmp
, 1);
1046 tcg_gen_shli_i32(tmp
, tmp
, 2);
1047 /* Clear CCF_Z if bit set. */
1048 tcg_gen_ori_i32(QREG_CC_DEST
, QREG_CC_DEST
, CCF_Z
);
1049 tcg_gen_xor_i32(QREG_CC_DEST
, QREG_CC_DEST
, tmp
);
1051 tcg_gen_shl_i32(tmp
, tcg_const_i32(1), src2
);
1054 tcg_gen_xor_i32(dest
, src1
, tmp
);
1057 tcg_gen_not_i32(tmp
, tmp
);
1058 tcg_gen_and_i32(dest
, src1
, tmp
);
1061 tcg_gen_or_i32(dest
, src1
, tmp
);
1067 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1073 reg
= DREG(insn
, 0);
1075 gen_helper_sats(reg
, reg
, QREG_CC_DEST
);
1076 gen_logic_cc(s
, reg
);
1079 static void gen_push(DisasContext
*s
, TCGv val
)
1083 tmp
= tcg_temp_new();
1084 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1085 gen_store(s
, OS_LONG
, tmp
, val
);
1086 tcg_gen_mov_i32(QREG_SP
, tmp
);
1098 mask
= cpu_lduw_code(env
, s
->pc
);
1100 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1101 if (IS_NULL_QREG(tmp
)) {
1105 addr
= tcg_temp_new();
1106 tcg_gen_mov_i32(addr
, tmp
);
1107 is_load
= ((insn
& 0x0400) != 0);
1108 for (i
= 0; i
< 16; i
++, mask
>>= 1) {
1115 tmp
= gen_load(s
, OS_LONG
, addr
, 0);
1116 tcg_gen_mov_i32(reg
, tmp
);
1118 gen_store(s
, OS_LONG
, addr
, reg
);
1121 tcg_gen_addi_i32(addr
, addr
, 4);
1126 DISAS_INSN(bitop_im
)
1136 if ((insn
& 0x38) != 0)
1140 op
= (insn
>> 6) & 3;
1142 bitnum
= cpu_lduw_code(env
, s
->pc
);
1144 if (bitnum
& 0xff00) {
1145 disas_undef(env
, s
, insn
);
1149 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1152 if (opsize
== OS_BYTE
)
1158 tmp
= tcg_temp_new();
1159 assert (CCF_Z
== (1 << 2));
1161 tcg_gen_shri_i32(tmp
, src1
, bitnum
- 2);
1162 else if (bitnum
< 2)
1163 tcg_gen_shli_i32(tmp
, src1
, 2 - bitnum
);
1165 tcg_gen_mov_i32(tmp
, src1
);
1166 tcg_gen_andi_i32(tmp
, tmp
, CCF_Z
);
1167 /* Clear CCF_Z if bit set. */
1168 tcg_gen_ori_i32(QREG_CC_DEST
, QREG_CC_DEST
, CCF_Z
);
1169 tcg_gen_xor_i32(QREG_CC_DEST
, QREG_CC_DEST
, tmp
);
1173 tcg_gen_xori_i32(tmp
, src1
, mask
);
1176 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
1179 tcg_gen_ori_i32(tmp
, src1
, mask
);
1184 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
1188 DISAS_INSN(arith_im
)
1196 op
= (insn
>> 9) & 7;
1197 SRC_EA(env
, src1
, OS_LONG
, 0, (op
== 6) ? NULL
: &addr
);
1198 im
= read_im32(env
, s
);
1199 dest
= tcg_temp_new();
1202 tcg_gen_ori_i32(dest
, src1
, im
);
1203 gen_logic_cc(s
, dest
);
1206 tcg_gen_andi_i32(dest
, src1
, im
);
1207 gen_logic_cc(s
, dest
);
1210 tcg_gen_mov_i32(dest
, src1
);
1211 gen_helper_xflag_lt(QREG_CC_X
, dest
, tcg_const_i32(im
));
1212 tcg_gen_subi_i32(dest
, dest
, im
);
1213 gen_update_cc_add(dest
, tcg_const_i32(im
));
1214 s
->cc_op
= CC_OP_SUB
;
1217 tcg_gen_mov_i32(dest
, src1
);
1218 tcg_gen_addi_i32(dest
, dest
, im
);
1219 gen_update_cc_add(dest
, tcg_const_i32(im
));
1220 gen_helper_xflag_lt(QREG_CC_X
, dest
, tcg_const_i32(im
));
1221 s
->cc_op
= CC_OP_ADD
;
1224 tcg_gen_xori_i32(dest
, src1
, im
);
1225 gen_logic_cc(s
, dest
);
1228 tcg_gen_mov_i32(dest
, src1
);
1229 tcg_gen_subi_i32(dest
, dest
, im
);
1230 gen_update_cc_add(dest
, tcg_const_i32(im
));
1231 s
->cc_op
= CC_OP_SUB
;
1237 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1245 reg
= DREG(insn
, 0);
1246 tcg_gen_bswap32_i32(reg
, reg
);
1256 switch (insn
>> 12) {
1257 case 1: /* move.b */
1260 case 2: /* move.l */
1263 case 3: /* move.w */
1269 SRC_EA(env
, src
, opsize
, 1, NULL
);
1270 op
= (insn
>> 6) & 7;
1273 /* The value will already have been sign extended. */
1274 dest
= AREG(insn
, 9);
1275 tcg_gen_mov_i32(dest
, src
);
1279 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
1280 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
1281 /* This will be correct because loads sign extend. */
1282 gen_logic_cc(s
, src
);
1291 reg
= DREG(insn
, 0);
1292 gen_helper_subx_cc(reg
, cpu_env
, tcg_const_i32(0), reg
);
1300 reg
= AREG(insn
, 9);
1301 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1302 if (IS_NULL_QREG(tmp
)) {
1306 tcg_gen_mov_i32(reg
, tmp
);
1313 switch ((insn
>> 6) & 3) {
1326 DEST_EA(env
, insn
, opsize
, tcg_const_i32(0), NULL
);
1327 gen_logic_cc(s
, tcg_const_i32(0));
1330 static TCGv
gen_get_ccr(DisasContext
*s
)
1335 dest
= tcg_temp_new();
1336 tcg_gen_shli_i32(dest
, QREG_CC_X
, 4);
1337 tcg_gen_or_i32(dest
, dest
, QREG_CC_DEST
);
1341 DISAS_INSN(move_from_ccr
)
1346 ccr
= gen_get_ccr(s
);
1347 reg
= DREG(insn
, 0);
1348 gen_partset_reg(OS_WORD
, reg
, ccr
);
1356 reg
= DREG(insn
, 0);
1357 src1
= tcg_temp_new();
1358 tcg_gen_mov_i32(src1
, reg
);
1359 tcg_gen_neg_i32(reg
, src1
);
1360 s
->cc_op
= CC_OP_SUB
;
1361 gen_update_cc_add(reg
, src1
);
1362 gen_helper_xflag_lt(QREG_CC_X
, tcg_const_i32(0), src1
);
1363 s
->cc_op
= CC_OP_SUB
;
1366 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
1368 tcg_gen_movi_i32(QREG_CC_DEST
, val
& 0xf);
1369 tcg_gen_movi_i32(QREG_CC_X
, (val
& 0x10) >> 4);
1371 gen_helper_set_sr(cpu_env
, tcg_const_i32(val
& 0xff00));
1375 static void gen_set_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1381 s
->cc_op
= CC_OP_FLAGS
;
1382 if ((insn
& 0x38) == 0)
1384 tmp
= tcg_temp_new();
1385 reg
= DREG(insn
, 0);
1386 tcg_gen_andi_i32(QREG_CC_DEST
, reg
, 0xf);
1387 tcg_gen_shri_i32(tmp
, reg
, 4);
1388 tcg_gen_andi_i32(QREG_CC_X
, tmp
, 1);
1390 gen_helper_set_sr(cpu_env
, reg
);
1393 else if ((insn
& 0x3f) == 0x3c)
1396 val
= cpu_lduw_code(env
, s
->pc
);
1398 gen_set_sr_im(s
, val
, ccr_only
);
1401 disas_undef(env
, s
, insn
);
1404 DISAS_INSN(move_to_ccr
)
1406 gen_set_sr(env
, s
, insn
, 1);
1413 reg
= DREG(insn
, 0);
1414 tcg_gen_not_i32(reg
, reg
);
1415 gen_logic_cc(s
, reg
);
1424 src1
= tcg_temp_new();
1425 src2
= tcg_temp_new();
1426 reg
= DREG(insn
, 0);
1427 tcg_gen_shli_i32(src1
, reg
, 16);
1428 tcg_gen_shri_i32(src2
, reg
, 16);
1429 tcg_gen_or_i32(reg
, src1
, src2
);
1430 gen_logic_cc(s
, reg
);
1437 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1438 if (IS_NULL_QREG(tmp
)) {
1451 reg
= DREG(insn
, 0);
1452 op
= (insn
>> 6) & 7;
1453 tmp
= tcg_temp_new();
1455 tcg_gen_ext16s_i32(tmp
, reg
);
1457 tcg_gen_ext8s_i32(tmp
, reg
);
1459 gen_partset_reg(OS_WORD
, reg
, tmp
);
1461 tcg_gen_mov_i32(reg
, tmp
);
1462 gen_logic_cc(s
, tmp
);
1470 switch ((insn
>> 6) & 3) {
1483 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
1484 gen_logic_cc(s
, tmp
);
1489 /* Implemented as a NOP. */
1494 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
1497 /* ??? This should be atomic. */
1504 dest
= tcg_temp_new();
1505 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
1506 gen_logic_cc(s
, src1
);
1507 tcg_gen_ori_i32(dest
, src1
, 0x80);
1508 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1518 /* The upper 32 bits of the product are discarded, so
1519 muls.l and mulu.l are functionally equivalent. */
1520 ext
= cpu_lduw_code(env
, s
->pc
);
1523 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1526 reg
= DREG(ext
, 12);
1527 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
1528 dest
= tcg_temp_new();
1529 tcg_gen_mul_i32(dest
, src1
, reg
);
1530 tcg_gen_mov_i32(reg
, dest
);
1531 /* Unlike m68k, coldfire always clears the overflow bit. */
1532 gen_logic_cc(s
, dest
);
1541 offset
= cpu_ldsw_code(env
, s
->pc
);
1543 reg
= AREG(insn
, 0);
1544 tmp
= tcg_temp_new();
1545 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1546 gen_store(s
, OS_LONG
, tmp
, reg
);
1547 if ((insn
& 7) != 7)
1548 tcg_gen_mov_i32(reg
, tmp
);
1549 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
1558 src
= tcg_temp_new();
1559 reg
= AREG(insn
, 0);
1560 tcg_gen_mov_i32(src
, reg
);
1561 tmp
= gen_load(s
, OS_LONG
, src
, 0);
1562 tcg_gen_mov_i32(reg
, tmp
);
1563 tcg_gen_addi_i32(QREG_SP
, src
, 4);
1574 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
1575 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
1583 /* Load the target address first to ensure correct exception
1585 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1586 if (IS_NULL_QREG(tmp
)) {
1590 if ((insn
& 0x40) == 0) {
1592 gen_push(s
, tcg_const_i32(s
->pc
));
1605 SRC_EA(env
, src1
, OS_LONG
, 0, &addr
);
1606 val
= (insn
>> 9) & 7;
1609 dest
= tcg_temp_new();
1610 tcg_gen_mov_i32(dest
, src1
);
1611 if ((insn
& 0x38) == 0x08) {
1612 /* Don't update condition codes if the destination is an
1613 address register. */
1614 if (insn
& 0x0100) {
1615 tcg_gen_subi_i32(dest
, dest
, val
);
1617 tcg_gen_addi_i32(dest
, dest
, val
);
1620 src2
= tcg_const_i32(val
);
1621 if (insn
& 0x0100) {
1622 gen_helper_xflag_lt(QREG_CC_X
, dest
, src2
);
1623 tcg_gen_subi_i32(dest
, dest
, val
);
1624 s
->cc_op
= CC_OP_SUB
;
1626 tcg_gen_addi_i32(dest
, dest
, val
);
1627 gen_helper_xflag_lt(QREG_CC_X
, dest
, src2
);
1628 s
->cc_op
= CC_OP_ADD
;
1630 gen_update_cc_add(dest
, src2
);
1632 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1638 case 2: /* One extension word. */
1641 case 3: /* Two extension words. */
1644 case 4: /* No extension words. */
1647 disas_undef(env
, s
, insn
);
1659 op
= (insn
>> 8) & 0xf;
1660 offset
= (int8_t)insn
;
1662 offset
= cpu_ldsw_code(env
, s
->pc
);
1664 } else if (offset
== -1) {
1665 offset
= read_im32(env
, s
);
1669 gen_push(s
, tcg_const_i32(s
->pc
));
1674 l1
= gen_new_label();
1675 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
1676 gen_jmp_tb(s
, 1, base
+ offset
);
1678 gen_jmp_tb(s
, 0, s
->pc
);
1680 /* Unconditional branch. */
1681 gen_jmp_tb(s
, 0, base
+ offset
);
1690 tcg_gen_movi_i32(DREG(insn
, 9), val
);
1691 gen_logic_cc(s
, tcg_const_i32(val
));
1704 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
1705 reg
= DREG(insn
, 9);
1706 tcg_gen_mov_i32(reg
, src
);
1707 gen_logic_cc(s
, src
);
1717 reg
= DREG(insn
, 9);
1718 dest
= tcg_temp_new();
1720 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
1721 tcg_gen_or_i32(dest
, src
, reg
);
1722 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1724 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1725 tcg_gen_or_i32(dest
, src
, reg
);
1726 tcg_gen_mov_i32(reg
, dest
);
1728 gen_logic_cc(s
, dest
);
1736 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1737 reg
= AREG(insn
, 9);
1738 tcg_gen_sub_i32(reg
, reg
, src
);
1747 reg
= DREG(insn
, 9);
1748 src
= DREG(insn
, 0);
1749 gen_helper_subx_cc(reg
, cpu_env
, reg
, src
);
1757 val
= (insn
>> 9) & 7;
1760 src
= tcg_const_i32(val
);
1761 gen_logic_cc(s
, src
);
1762 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
1773 op
= (insn
>> 6) & 3;
1777 s
->cc_op
= CC_OP_CMPB
;
1781 s
->cc_op
= CC_OP_CMPW
;
1785 s
->cc_op
= CC_OP_SUB
;
1790 SRC_EA(env
, src
, opsize
, 1, NULL
);
1791 reg
= DREG(insn
, 9);
1792 dest
= tcg_temp_new();
1793 tcg_gen_sub_i32(dest
, reg
, src
);
1794 gen_update_cc_add(dest
, src
);
1809 SRC_EA(env
, src
, opsize
, 1, NULL
);
1810 reg
= AREG(insn
, 9);
1811 dest
= tcg_temp_new();
1812 tcg_gen_sub_i32(dest
, reg
, src
);
1813 gen_update_cc_add(dest
, src
);
1814 s
->cc_op
= CC_OP_SUB
;
1824 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
1825 reg
= DREG(insn
, 9);
1826 dest
= tcg_temp_new();
1827 tcg_gen_xor_i32(dest
, src
, reg
);
1828 gen_logic_cc(s
, dest
);
1829 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1839 reg
= DREG(insn
, 9);
1840 dest
= tcg_temp_new();
1842 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
1843 tcg_gen_and_i32(dest
, src
, reg
);
1844 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1846 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1847 tcg_gen_and_i32(dest
, src
, reg
);
1848 tcg_gen_mov_i32(reg
, dest
);
1850 gen_logic_cc(s
, dest
);
1858 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1859 reg
= AREG(insn
, 9);
1860 tcg_gen_add_i32(reg
, reg
, src
);
1869 reg
= DREG(insn
, 9);
1870 src
= DREG(insn
, 0);
1871 gen_helper_addx_cc(reg
, cpu_env
, reg
, src
);
1872 s
->cc_op
= CC_OP_FLAGS
;
1875 /* TODO: This could be implemented without helper functions. */
1876 DISAS_INSN(shift_im
)
1882 reg
= DREG(insn
, 0);
1883 tmp
= (insn
>> 9) & 7;
1886 shift
= tcg_const_i32(tmp
);
1887 /* No need to flush flags becuse we know we will set C flag. */
1889 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
1892 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
1894 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
1897 s
->cc_op
= CC_OP_SHIFT
;
1900 DISAS_INSN(shift_reg
)
1905 reg
= DREG(insn
, 0);
1906 shift
= DREG(insn
, 9);
1907 /* Shift by zero leaves C flag unmodified. */
1910 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
1913 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
1915 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
1918 s
->cc_op
= CC_OP_SHIFT
;
1924 reg
= DREG(insn
, 0);
1925 gen_logic_cc(s
, reg
);
1926 gen_helper_ff1(reg
, reg
);
1929 static TCGv
gen_get_sr(DisasContext
*s
)
1934 ccr
= gen_get_ccr(s
);
1935 sr
= tcg_temp_new();
1936 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
1937 tcg_gen_or_i32(sr
, sr
, ccr
);
1947 ext
= cpu_lduw_code(env
, s
->pc
);
1949 if (ext
!= 0x46FC) {
1950 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
1953 ext
= cpu_lduw_code(env
, s
->pc
);
1955 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
1956 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
1959 gen_push(s
, gen_get_sr(s
));
1960 gen_set_sr_im(s
, ext
, 0);
1963 DISAS_INSN(move_from_sr
)
1969 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
1973 reg
= DREG(insn
, 0);
1974 gen_partset_reg(OS_WORD
, reg
, sr
);
1977 DISAS_INSN(move_to_sr
)
1980 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
1983 gen_set_sr(env
, s
, insn
, 0);
1987 DISAS_INSN(move_from_usp
)
1990 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
1993 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
1994 offsetof(CPUM68KState
, sp
[M68K_USP
]));
1997 DISAS_INSN(move_to_usp
)
2000 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2003 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
2004 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2009 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
2017 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2021 ext
= cpu_lduw_code(env
, s
->pc
);
2024 gen_set_sr_im(s
, ext
, 0);
2025 tcg_gen_movi_i32(cpu_halted
, 1);
2026 gen_exception(s
, s
->pc
, EXCP_HLT
);
2032 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2035 gen_exception(s
, s
->pc
- 2, EXCP_RTE
);
2044 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2048 ext
= cpu_lduw_code(env
, s
->pc
);
2052 reg
= AREG(ext
, 12);
2054 reg
= DREG(ext
, 12);
2056 gen_helper_movec(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
2063 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2066 /* ICache fetch. Implement as no-op. */
2072 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2075 /* Cache push/invalidate. Implement as no-op. */
2080 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2085 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2088 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2091 /* TODO: Implement wdebug. */
2092 cpu_abort(CPU(cpu
), "WDEBUG not implemented");
2097 gen_exception(s
, s
->pc
- 2, EXCP_TRAP0
+ (insn
& 0xf));
2100 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2101 immediately before the next FP instruction is executed. */
2115 ext
= cpu_lduw_code(env
, s
->pc
);
2117 opmode
= ext
& 0x7f;
2118 switch ((ext
>> 13) & 7) {
2123 case 3: /* fmove out */
2125 tmp32
= tcg_temp_new_i32();
2127 /* ??? TODO: Proper behavior on overflow. */
2128 switch ((ext
>> 10) & 7) {
2131 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2135 gen_helper_f64_to_f32(tmp32
, cpu_env
, src
);
2139 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2141 case 5: /* OS_DOUBLE */
2142 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2143 switch ((insn
>> 3) & 7) {
2148 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2151 offset
= cpu_ldsw_code(env
, s
->pc
);
2153 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2158 gen_store64(s
, tmp32
, src
);
2159 switch ((insn
>> 3) & 7) {
2161 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2162 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2165 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2168 tcg_temp_free_i32(tmp32
);
2172 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2177 DEST_EA(env
, insn
, opsize
, tmp32
, NULL
);
2178 tcg_temp_free_i32(tmp32
);
2180 case 4: /* fmove to control register. */
2181 switch ((ext
>> 10) & 7) {
2183 /* Not implemented. Ignore writes. */
2188 cpu_abort(NULL
, "Unimplemented: fmove to control %d",
2192 case 5: /* fmove from control register. */
2193 switch ((ext
>> 10) & 7) {
2195 /* Not implemented. Always return zero. */
2196 tmp32
= tcg_const_i32(0);
2201 cpu_abort(NULL
, "Unimplemented: fmove from control %d",
2205 DEST_EA(env
, insn
, OS_LONG
, tmp32
, NULL
);
2207 case 6: /* fmovem */
2213 if ((ext
& 0x1f00) != 0x1000 || (ext
& 0xff) == 0)
2215 tmp32
= gen_lea(env
, s
, insn
, OS_LONG
);
2216 if (IS_NULL_QREG(tmp32
)) {
2220 addr
= tcg_temp_new_i32();
2221 tcg_gen_mov_i32(addr
, tmp32
);
2223 for (i
= 0; i
< 8; i
++) {
2226 if (ext
& (1 << 13)) {
2228 tcg_gen_qemu_stf64(dest
, addr
, IS_USER(s
));
2231 tcg_gen_qemu_ldf64(dest
, addr
, IS_USER(s
));
2233 if (ext
& (mask
- 1))
2234 tcg_gen_addi_i32(addr
, addr
, 8);
2238 tcg_temp_free_i32(addr
);
2242 if (ext
& (1 << 14)) {
2243 /* Source effective address. */
2244 switch ((ext
>> 10) & 7) {
2245 case 0: opsize
= OS_LONG
; break;
2246 case 1: opsize
= OS_SINGLE
; break;
2247 case 4: opsize
= OS_WORD
; break;
2248 case 5: opsize
= OS_DOUBLE
; break;
2249 case 6: opsize
= OS_BYTE
; break;
2253 if (opsize
== OS_DOUBLE
) {
2254 tmp32
= tcg_temp_new_i32();
2255 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2256 switch ((insn
>> 3) & 7) {
2261 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2264 offset
= cpu_ldsw_code(env
, s
->pc
);
2266 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2269 offset
= cpu_ldsw_code(env
, s
->pc
);
2270 offset
+= s
->pc
- 2;
2272 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2277 src
= gen_load64(s
, tmp32
);
2278 switch ((insn
>> 3) & 7) {
2280 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2281 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2284 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2287 tcg_temp_free_i32(tmp32
);
2289 SRC_EA(env
, tmp32
, opsize
, 1, NULL
);
2290 src
= tcg_temp_new_i64();
2295 gen_helper_i32_to_f64(src
, cpu_env
, tmp32
);
2298 gen_helper_f32_to_f64(src
, cpu_env
, tmp32
);
2303 /* Source register. */
2304 src
= FREG(ext
, 10);
2306 dest
= FREG(ext
, 7);
2307 res
= tcg_temp_new_i64();
2309 tcg_gen_mov_f64(res
, dest
);
2313 case 0: case 0x40: case 0x44: /* fmove */
2314 tcg_gen_mov_f64(res
, src
);
2317 gen_helper_iround_f64(res
, cpu_env
, src
);
2320 case 3: /* fintrz */
2321 gen_helper_itrunc_f64(res
, cpu_env
, src
);
2324 case 4: case 0x41: case 0x45: /* fsqrt */
2325 gen_helper_sqrt_f64(res
, cpu_env
, src
);
2327 case 0x18: case 0x58: case 0x5c: /* fabs */
2328 gen_helper_abs_f64(res
, src
);
2330 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2331 gen_helper_chs_f64(res
, src
);
2333 case 0x20: case 0x60: case 0x64: /* fdiv */
2334 gen_helper_div_f64(res
, cpu_env
, res
, src
);
2336 case 0x22: case 0x62: case 0x66: /* fadd */
2337 gen_helper_add_f64(res
, cpu_env
, res
, src
);
2339 case 0x23: case 0x63: case 0x67: /* fmul */
2340 gen_helper_mul_f64(res
, cpu_env
, res
, src
);
2342 case 0x28: case 0x68: case 0x6c: /* fsub */
2343 gen_helper_sub_f64(res
, cpu_env
, res
, src
);
2345 case 0x38: /* fcmp */
2346 gen_helper_sub_cmp_f64(res
, cpu_env
, res
, src
);
2350 case 0x3a: /* ftst */
2351 tcg_gen_mov_f64(res
, src
);
2358 if (ext
& (1 << 14)) {
2359 tcg_temp_free_i64(src
);
2362 if (opmode
& 0x40) {
2363 if ((opmode
& 0x4) != 0)
2365 } else if ((s
->fpcr
& M68K_FPCR_PREC
) == 0) {
2370 TCGv tmp
= tcg_temp_new_i32();
2371 gen_helper_f64_to_f32(tmp
, cpu_env
, res
);
2372 gen_helper_f32_to_f64(res
, cpu_env
, tmp
);
2373 tcg_temp_free_i32(tmp
);
2375 tcg_gen_mov_f64(QREG_FP_RESULT
, res
);
2377 tcg_gen_mov_f64(dest
, res
);
2379 tcg_temp_free_i64(res
);
2382 /* FIXME: Is this right for offset addressing modes? */
2384 disas_undef_fpu(env
, s
, insn
);
2395 offset
= cpu_ldsw_code(env
, s
->pc
);
2397 if (insn
& (1 << 6)) {
2398 offset
= (offset
<< 16) | cpu_lduw_code(env
, s
->pc
);
2402 l1
= gen_new_label();
2403 /* TODO: Raise BSUN exception. */
2404 flag
= tcg_temp_new();
2405 gen_helper_compare_f64(flag
, cpu_env
, QREG_FP_RESULT
);
2406 /* Jump to l1 if condition is true. */
2407 switch (insn
& 0xf) {
2410 case 1: /* eq (=0) */
2411 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2413 case 2: /* ogt (=1) */
2414 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(1), l1
);
2416 case 3: /* oge (=0 or =1) */
2417 tcg_gen_brcond_i32(TCG_COND_LEU
, flag
, tcg_const_i32(1), l1
);
2419 case 4: /* olt (=-1) */
2420 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(0), l1
);
2422 case 5: /* ole (=-1 or =0) */
2423 tcg_gen_brcond_i32(TCG_COND_LE
, flag
, tcg_const_i32(0), l1
);
2425 case 6: /* ogl (=-1 or =1) */
2426 tcg_gen_andi_i32(flag
, flag
, 1);
2427 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2429 case 7: /* or (=2) */
2430 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(2), l1
);
2432 case 8: /* un (<2) */
2433 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(2), l1
);
2435 case 9: /* ueq (=0 or =2) */
2436 tcg_gen_andi_i32(flag
, flag
, 1);
2437 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2439 case 10: /* ugt (>0) */
2440 tcg_gen_brcond_i32(TCG_COND_GT
, flag
, tcg_const_i32(0), l1
);
2442 case 11: /* uge (>=0) */
2443 tcg_gen_brcond_i32(TCG_COND_GE
, flag
, tcg_const_i32(0), l1
);
2445 case 12: /* ult (=-1 or =2) */
2446 tcg_gen_brcond_i32(TCG_COND_GEU
, flag
, tcg_const_i32(2), l1
);
2448 case 13: /* ule (!=1) */
2449 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(1), l1
);
2451 case 14: /* ne (!=0) */
2452 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2458 gen_jmp_tb(s
, 0, s
->pc
);
2460 gen_jmp_tb(s
, 1, addr
+ offset
);
2463 DISAS_INSN(frestore
)
2465 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2467 /* TODO: Implement frestore. */
2468 cpu_abort(CPU(cpu
), "FRESTORE not implemented");
2473 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2475 /* TODO: Implement fsave. */
2476 cpu_abort(CPU(cpu
), "FSAVE not implemented");
2479 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
2481 TCGv tmp
= tcg_temp_new();
2482 if (s
->env
->macsr
& MACSR_FI
) {
2484 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
2486 tcg_gen_shli_i32(tmp
, val
, 16);
2487 } else if (s
->env
->macsr
& MACSR_SU
) {
2489 tcg_gen_sari_i32(tmp
, val
, 16);
2491 tcg_gen_ext16s_i32(tmp
, val
);
2494 tcg_gen_shri_i32(tmp
, val
, 16);
2496 tcg_gen_ext16u_i32(tmp
, val
);
2501 static void gen_mac_clear_flags(void)
2503 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
2504 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
2520 s
->mactmp
= tcg_temp_new_i64();
2524 ext
= cpu_lduw_code(env
, s
->pc
);
2527 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
2528 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
2529 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
2530 disas_undef(env
, s
, insn
);
2534 /* MAC with load. */
2535 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2536 addr
= tcg_temp_new();
2537 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
2538 /* Load the value now to ensure correct exception behavior.
2539 Perform writeback after reading the MAC inputs. */
2540 loadval
= gen_load(s
, OS_LONG
, addr
, 0);
2543 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
2544 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
2546 loadval
= addr
= NULL_QREG
;
2547 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
2548 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2551 gen_mac_clear_flags();
2554 /* Disabled because conditional branches clobber temporary vars. */
2555 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
2556 /* Skip the multiply if we know we will ignore it. */
2557 l1
= gen_new_label();
2558 tmp
= tcg_temp_new();
2559 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
2560 gen_op_jmp_nz32(tmp
, l1
);
2564 if ((ext
& 0x0800) == 0) {
2566 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
2567 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
2569 if (s
->env
->macsr
& MACSR_FI
) {
2570 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
2572 if (s
->env
->macsr
& MACSR_SU
)
2573 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
2575 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
2576 switch ((ext
>> 9) & 3) {
2578 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
2581 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
2587 /* Save the overflow flag from the multiply. */
2588 saved_flags
= tcg_temp_new();
2589 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
2591 saved_flags
= NULL_QREG
;
2595 /* Disabled because conditional branches clobber temporary vars. */
2596 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
2597 /* Skip the accumulate if the value is already saturated. */
2598 l1
= gen_new_label();
2599 tmp
= tcg_temp_new();
2600 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
2601 gen_op_jmp_nz32(tmp
, l1
);
2606 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2608 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2610 if (s
->env
->macsr
& MACSR_FI
)
2611 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
2612 else if (s
->env
->macsr
& MACSR_SU
)
2613 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
2615 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
2618 /* Disabled because conditional branches clobber temporary vars. */
2624 /* Dual accumulate variant. */
2625 acc
= (ext
>> 2) & 3;
2626 /* Restore the overflow flag from the multiplier. */
2627 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
2629 /* Disabled because conditional branches clobber temporary vars. */
2630 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
2631 /* Skip the accumulate if the value is already saturated. */
2632 l1
= gen_new_label();
2633 tmp
= tcg_temp_new();
2634 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
2635 gen_op_jmp_nz32(tmp
, l1
);
2639 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2641 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2642 if (s
->env
->macsr
& MACSR_FI
)
2643 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
2644 else if (s
->env
->macsr
& MACSR_SU
)
2645 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
2647 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
2649 /* Disabled because conditional branches clobber temporary vars. */
2654 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
2658 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
2659 tcg_gen_mov_i32(rw
, loadval
);
2660 /* FIXME: Should address writeback happen with the masked or
2662 switch ((insn
>> 3) & 7) {
2663 case 3: /* Post-increment. */
2664 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
2666 case 4: /* Pre-decrement. */
2667 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2672 DISAS_INSN(from_mac
)
2678 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2679 accnum
= (insn
>> 9) & 3;
2680 acc
= MACREG(accnum
);
2681 if (s
->env
->macsr
& MACSR_FI
) {
2682 gen_helper_get_macf(rx
, cpu_env
, acc
);
2683 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
2684 tcg_gen_extrl_i64_i32(rx
, acc
);
2685 } else if (s
->env
->macsr
& MACSR_SU
) {
2686 gen_helper_get_macs(rx
, acc
);
2688 gen_helper_get_macu(rx
, acc
);
2691 tcg_gen_movi_i64(acc
, 0);
2692 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
2696 DISAS_INSN(move_mac
)
2698 /* FIXME: This can be done without a helper. */
2702 dest
= tcg_const_i32((insn
>> 9) & 3);
2703 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
2704 gen_mac_clear_flags();
2705 gen_helper_mac_set_flags(cpu_env
, dest
);
2708 DISAS_INSN(from_macsr
)
2712 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2713 tcg_gen_mov_i32(reg
, QREG_MACSR
);
2716 DISAS_INSN(from_mask
)
2719 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2720 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
2723 DISAS_INSN(from_mext
)
2727 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2728 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
2729 if (s
->env
->macsr
& MACSR_FI
)
2730 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
2732 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
2735 DISAS_INSN(macsr_to_ccr
)
2737 tcg_gen_movi_i32(QREG_CC_X
, 0);
2738 tcg_gen_andi_i32(QREG_CC_DEST
, QREG_MACSR
, 0xf);
2739 s
->cc_op
= CC_OP_FLAGS
;
2747 accnum
= (insn
>> 9) & 3;
2748 acc
= MACREG(accnum
);
2749 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2750 if (s
->env
->macsr
& MACSR_FI
) {
2751 tcg_gen_ext_i32_i64(acc
, val
);
2752 tcg_gen_shli_i64(acc
, acc
, 8);
2753 } else if (s
->env
->macsr
& MACSR_SU
) {
2754 tcg_gen_ext_i32_i64(acc
, val
);
2756 tcg_gen_extu_i32_i64(acc
, val
);
2758 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
2759 gen_mac_clear_flags();
2760 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
2763 DISAS_INSN(to_macsr
)
2766 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2767 gen_helper_set_macsr(cpu_env
, val
);
2774 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2775 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
2782 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2783 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
2784 if (s
->env
->macsr
& MACSR_FI
)
2785 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
2786 else if (s
->env
->macsr
& MACSR_SU
)
2787 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
2789 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
2792 static disas_proc opcode_table
[65536];
2795 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
2801 /* Sanity check. All set bits must be included in the mask. */
2802 if (opcode
& ~mask
) {
2804 "qemu internal error: bogus opcode definition %04x/%04x\n",
2808 /* This could probably be cleverer. For now just optimize the case where
2809 the top bits are known. */
2810 /* Find the first zero bit in the mask. */
2812 while ((i
& mask
) != 0)
2814 /* Iterate over all combinations of this and lower bits. */
2819 from
= opcode
& ~(i
- 1);
2821 for (i
= from
; i
< to
; i
++) {
2822 if ((i
& mask
) == opcode
)
2823 opcode_table
[i
] = proc
;
2827 /* Register m68k opcode handlers. Order is important.
2828 Later insn override earlier ones. */
2829 void register_m68k_insns (CPUM68KState
*env
)
2831 #define INSN(name, opcode, mask, feature) do { \
2832 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2833 register_opcode(disas_##name, 0x##opcode, 0x##mask); \
2835 INSN(undef
, 0000, 0000, CF_ISA_A
);
2836 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
2837 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
2838 INSN(bitop_reg
, 0100, f1c0
, CF_ISA_A
);
2839 INSN(bitop_reg
, 0140, f1c0
, CF_ISA_A
);
2840 INSN(bitop_reg
, 0180, f1c0
, CF_ISA_A
);
2841 INSN(bitop_reg
, 01c0
, f1c0
, CF_ISA_A
);
2842 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
2843 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
2844 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
2845 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
2846 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
2847 INSN(bitop_im
, 0800, ffc0
, CF_ISA_A
);
2848 INSN(bitop_im
, 0840, ffc0
, CF_ISA_A
);
2849 INSN(bitop_im
, 0880, ffc0
, CF_ISA_A
);
2850 INSN(bitop_im
, 08c0
, ffc0
, CF_ISA_A
);
2851 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
2852 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
2853 INSN(move
, 1000, f000
, CF_ISA_A
);
2854 INSN(move
, 2000, f000
, CF_ISA_A
);
2855 INSN(move
, 3000, f000
, CF_ISA_A
);
2856 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
2857 INSN(negx
, 4080, fff8
, CF_ISA_A
);
2858 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
2859 INSN(lea
, 41c0
, f1c0
, CF_ISA_A
);
2860 INSN(clr
, 4200, ff00
, CF_ISA_A
);
2861 INSN(undef
, 42c0
, ffc0
, CF_ISA_A
);
2862 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
2863 INSN(neg
, 4480, fff8
, CF_ISA_A
);
2864 INSN(move_to_ccr
, 44c0
, ffc0
, CF_ISA_A
);
2865 INSN(not, 4680, fff8
, CF_ISA_A
);
2866 INSN(move_to_sr
, 46c0
, ffc0
, CF_ISA_A
);
2867 INSN(pea
, 4840, ffc0
, CF_ISA_A
);
2868 INSN(swap
, 4840, fff8
, CF_ISA_A
);
2869 INSN(movem
, 48c0
, fbc0
, CF_ISA_A
);
2870 INSN(ext
, 4880, fff8
, CF_ISA_A
);
2871 INSN(ext
, 48c0
, fff8
, CF_ISA_A
);
2872 INSN(ext
, 49c0
, fff8
, CF_ISA_A
);
2873 INSN(tst
, 4a00
, ff00
, CF_ISA_A
);
2874 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
2875 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
2876 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
2877 INSN(illegal
, 4afc
, ffff
, CF_ISA_A
);
2878 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
2879 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
2880 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
2881 INSN(trap
, 4e40
, fff0
, CF_ISA_A
);
2882 INSN(link
, 4e50
, fff8
, CF_ISA_A
);
2883 INSN(unlk
, 4e58
, fff8
, CF_ISA_A
);
2884 INSN(move_to_usp
, 4e60
, fff8
, USP
);
2885 INSN(move_from_usp
, 4e68
, fff8
, USP
);
2886 INSN(nop
, 4e71
, ffff
, CF_ISA_A
);
2887 INSN(stop
, 4e72
, ffff
, CF_ISA_A
);
2888 INSN(rte
, 4e73
, ffff
, CF_ISA_A
);
2889 INSN(rts
, 4e75
, ffff
, CF_ISA_A
);
2890 INSN(movec
, 4e7b
, ffff
, CF_ISA_A
);
2891 INSN(jump
, 4e80
, ffc0
, CF_ISA_A
);
2892 INSN(jump
, 4ec0
, ffc0
, CF_ISA_A
);
2893 INSN(addsubq
, 5180, f1c0
, CF_ISA_A
);
2894 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
);
2895 INSN(addsubq
, 5080, f1c0
, CF_ISA_A
);
2896 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
2898 /* Branch instructions. */
2899 INSN(branch
, 6000, f000
, CF_ISA_A
);
2900 /* Disable long branch instructions, then add back the ones we want. */
2901 INSN(undef
, 60ff
, f0ff
, CF_ISA_A
); /* All long branches. */
2902 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
2903 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
2904 INSN(branch
, 60ff
, ffff
, BRAL
);
2906 INSN(moveq
, 7000, f100
, CF_ISA_A
);
2907 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
2908 INSN(or, 8000, f000
, CF_ISA_A
);
2909 INSN(divw
, 80c0
, f0c0
, CF_ISA_A
);
2910 INSN(addsub
, 9000, f000
, CF_ISA_A
);
2911 INSN(subx
, 9180, f1f8
, CF_ISA_A
);
2912 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
2914 INSN(undef_mac
, a000
, f000
, CF_ISA_A
);
2915 INSN(mac
, a000
, f100
, CF_EMAC
);
2916 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
2917 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
2918 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
2919 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
2920 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
2921 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
2922 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
2923 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
2924 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
2925 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
2927 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
2928 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
2929 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
2930 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
2931 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
2932 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
2933 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
2934 INSN(and, c000
, f000
, CF_ISA_A
);
2935 INSN(mulw
, c0c0
, f0c0
, CF_ISA_A
);
2936 INSN(addsub
, d000
, f000
, CF_ISA_A
);
2937 INSN(addx
, d180
, f1f8
, CF_ISA_A
);
2938 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
2939 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
2940 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
2941 INSN(undef_fpu
, f000
, f000
, CF_ISA_A
);
2942 INSN(fpu
, f200
, ffc0
, CF_FPU
);
2943 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
2944 INSN(frestore
, f340
, ffc0
, CF_FPU
);
2945 INSN(fsave
, f340
, ffc0
, CF_FPU
);
2946 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
2947 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
2948 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
2949 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
2953 /* ??? Some of this implementation is not exception safe. We should always
2954 write back the result to memory before setting the condition codes. */
2955 static void disas_m68k_insn(CPUM68KState
* env
, DisasContext
*s
)
2959 insn
= cpu_lduw_code(env
, s
->pc
);
2962 opcode_table
[insn
](env
, s
, insn
);
2965 /* generate intermediate code for basic block 'tb'. */
2966 void gen_intermediate_code(CPUM68KState
*env
, TranslationBlock
*tb
)
2968 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2969 CPUState
*cs
= CPU(cpu
);
2970 DisasContext dc1
, *dc
= &dc1
;
2971 target_ulong pc_start
;
2976 /* generate intermediate code */
2982 dc
->is_jmp
= DISAS_NEXT
;
2984 dc
->cc_op
= CC_OP_DYNAMIC
;
2985 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
2986 dc
->fpcr
= env
->fpcr
;
2987 dc
->user
= (env
->sr
& SR_S
) == 0;
2990 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2991 if (max_insns
== 0) {
2992 max_insns
= CF_COUNT_MASK
;
2994 if (max_insns
> TCG_MAX_INSNS
) {
2995 max_insns
= TCG_MAX_INSNS
;
3000 pc_offset
= dc
->pc
- pc_start
;
3001 gen_throws_exception
= NULL
;
3002 tcg_gen_insn_start(dc
->pc
);
3005 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
3006 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
3007 dc
->is_jmp
= DISAS_JUMP
;
3008 /* The address covered by the breakpoint must be included in
3009 [tb->pc, tb->pc + tb->size) in order to for it to be
3010 properly cleared -- thus we increment the PC here so that
3011 the logic setting tb->size below does the right thing. */
3016 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3020 dc
->insn_pc
= dc
->pc
;
3021 disas_m68k_insn(env
, dc
);
3022 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
3023 !cs
->singlestep_enabled
&&
3025 (pc_offset
) < (TARGET_PAGE_SIZE
- 32) &&
3026 num_insns
< max_insns
);
3028 if (tb
->cflags
& CF_LAST_IO
)
3030 if (unlikely(cs
->singlestep_enabled
)) {
3031 /* Make sure the pc is updated, and raise a debug exception. */
3033 gen_flush_cc_op(dc
);
3034 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
3036 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
3038 switch(dc
->is_jmp
) {
3040 gen_flush_cc_op(dc
);
3041 gen_jmp_tb(dc
, 0, dc
->pc
);
3046 gen_flush_cc_op(dc
);
3047 /* indicate that the hash table must be used to find the next TB */
3051 /* nothing more to generate */
3055 gen_tb_end(tb
, num_insns
);
3058 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
3059 qemu_log("----------------\n");
3060 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3061 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
3065 tb
->size
= dc
->pc
- pc_start
;
3066 tb
->icount
= num_insns
;
3069 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
3072 M68kCPU
*cpu
= M68K_CPU(cs
);
3073 CPUM68KState
*env
= &cpu
->env
;
3077 for (i
= 0; i
< 8; i
++)
3079 u
.d
= env
->fregs
[i
];
3080 cpu_fprintf (f
, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3081 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
3082 i
, u
.l
.upper
, u
.l
.lower
, *(double *)&u
.d
);
3084 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
3086 cpu_fprintf (f
, "SR = %04x %c%c%c%c%c ", sr
, (sr
& 0x10) ? 'X' : '-',
3087 (sr
& CCF_N
) ? 'N' : '-', (sr
& CCF_Z
) ? 'Z' : '-',
3088 (sr
& CCF_V
) ? 'V' : '-', (sr
& CCF_C
) ? 'C' : '-');
3089 cpu_fprintf (f
, "FPRESULT = %12g\n", *(double *)&env
->fp_result
);
3092 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,