2 * i.MX31 Vectored Interrupt Controller
4 * Note this is NOT the PL192 provided by ARM, but
5 * a custom implementation by Freescale.
7 * Copyright (c) 2008 OKL
8 * Copyright (c) 2011 NICTA Pty Ltd
9 * Originally written by Hans Jiang
10 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
12 * This code is licensed under the GPL version 2 or later. See
13 * the COPYING file in the top-level directory.
15 * TODO: implement vectors.
18 #include "qemu/osdep.h"
19 #include "hw/intc/imx_avic.h"
21 #ifndef DEBUG_IMX_AVIC
22 #define DEBUG_IMX_AVIC 0
25 #define DPRINTF(fmt, args...) \
27 if (DEBUG_IMX_AVIC) { \
28 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_AVIC, \
33 static const VMStateDescription vmstate_imx_avic
= {
34 .name
= TYPE_IMX_AVIC
,
36 .minimum_version_id
= 1,
37 .fields
= (VMStateField
[]) {
38 VMSTATE_UINT64(pending
, IMXAVICState
),
39 VMSTATE_UINT64(enabled
, IMXAVICState
),
40 VMSTATE_UINT64(is_fiq
, IMXAVICState
),
41 VMSTATE_UINT32(intcntl
, IMXAVICState
),
42 VMSTATE_UINT32(intmask
, IMXAVICState
),
43 VMSTATE_UINT32_ARRAY(prio
, IMXAVICState
, PRIO_WORDS
),
48 static inline int imx_avic_prio(IMXAVICState
*s
, int irq
)
50 uint32_t word
= irq
/ PRIO_PER_WORD
;
51 uint32_t part
= 4 * (irq
% PRIO_PER_WORD
);
52 return 0xf & (s
->prio
[word
] >> part
);
55 /* Update interrupts. */
56 static void imx_avic_update(IMXAVICState
*s
)
59 uint64_t new = s
->pending
& s
->enabled
;
62 flags
= new & s
->is_fiq
;
63 qemu_set_irq(s
->fiq
, !!flags
);
65 flags
= new & ~s
->is_fiq
;
66 if (!flags
|| (s
->intmask
== 0x1f)) {
67 qemu_set_irq(s
->irq
, !!flags
);
72 * Take interrupt if there's a pending interrupt with
73 * priority higher than the value of intmask
75 for (i
= 0; i
< IMX_AVIC_NUM_IRQS
; i
++) {
76 if (flags
& (1UL << i
)) {
77 if (imx_avic_prio(s
, i
) > s
->intmask
) {
78 qemu_set_irq(s
->irq
, 1);
83 qemu_set_irq(s
->irq
, 0);
86 static void imx_avic_set_irq(void *opaque
, int irq
, int level
)
88 IMXAVICState
*s
= (IMXAVICState
*)opaque
;
91 DPRINTF("Raising IRQ %d, prio %d\n",
92 irq
, imx_avic_prio(s
, irq
));
93 s
->pending
|= (1ULL << irq
);
95 DPRINTF("Clearing IRQ %d, prio %d\n",
96 irq
, imx_avic_prio(s
, irq
));
97 s
->pending
&= ~(1ULL << irq
);
104 static uint64_t imx_avic_read(void *opaque
,
105 hwaddr offset
, unsigned size
)
107 IMXAVICState
*s
= (IMXAVICState
*)opaque
;
109 DPRINTF("read(offset = 0x%" HWADDR_PRIx
")\n", offset
);
111 switch (offset
>> 2) {
112 case 0: /* INTCNTL */
115 case 1: /* Normal Interrupt Mask Register, NIMASK */
118 case 2: /* Interrupt Enable Number Register, INTENNUM */
119 case 3: /* Interrupt Disable Number Register, INTDISNUM */
122 case 4: /* Interrupt Enabled Number Register High */
123 return s
->enabled
>> 32;
125 case 5: /* Interrupt Enabled Number Register Low */
126 return s
->enabled
& 0xffffffffULL
;
128 case 6: /* Interrupt Type Register High */
129 return s
->is_fiq
>> 32;
131 case 7: /* Interrupt Type Register Low */
132 return s
->is_fiq
& 0xffffffffULL
;
134 case 8: /* Normal Interrupt Priority Register 7 */
135 case 9: /* Normal Interrupt Priority Register 6 */
136 case 10:/* Normal Interrupt Priority Register 5 */
137 case 11:/* Normal Interrupt Priority Register 4 */
138 case 12:/* Normal Interrupt Priority Register 3 */
139 case 13:/* Normal Interrupt Priority Register 2 */
140 case 14:/* Normal Interrupt Priority Register 1 */
141 case 15:/* Normal Interrupt Priority Register 0 */
142 return s
->prio
[15-(offset
>>2)];
144 case 16: /* Normal interrupt vector and status register */
147 * This returns the highest priority
148 * outstanding interrupt. Where there is more than
149 * one pending IRQ with the same priority,
150 * take the highest numbered one.
152 uint64_t flags
= s
->pending
& s
->enabled
& ~s
->is_fiq
;
156 for (i
= 63; i
>= 0; --i
) {
157 if (flags
& (1ULL<<i
)) {
158 int irq_prio
= imx_avic_prio(s
, i
);
159 if (irq_prio
> prio
) {
166 imx_avic_set_irq(s
, irq
, 0);
167 return irq
<< 16 | prio
;
169 return 0xffffffffULL
;
171 case 17:/* Fast Interrupt vector and status register */
173 uint64_t flags
= s
->pending
& s
->enabled
& s
->is_fiq
;
174 int i
= ctz64(flags
);
176 imx_avic_set_irq(opaque
, i
, 0);
179 return 0xffffffffULL
;
181 case 18:/* Interrupt source register high */
182 return s
->pending
>> 32;
184 case 19:/* Interrupt source register low */
185 return s
->pending
& 0xffffffffULL
;
187 case 20:/* Interrupt Force Register high */
188 case 21:/* Interrupt Force Register low */
191 case 22:/* Normal Interrupt Pending Register High */
192 return (s
->pending
& s
->enabled
& ~s
->is_fiq
) >> 32;
194 case 23:/* Normal Interrupt Pending Register Low */
195 return (s
->pending
& s
->enabled
& ~s
->is_fiq
) & 0xffffffffULL
;
197 case 24: /* Fast Interrupt Pending Register High */
198 return (s
->pending
& s
->enabled
& s
->is_fiq
) >> 32;
200 case 25: /* Fast Interrupt Pending Register Low */
201 return (s
->pending
& s
->enabled
& s
->is_fiq
) & 0xffffffffULL
;
203 case 0x40: /* AVIC vector 0, use for WFI WAR */
207 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
208 HWADDR_PRIx
"\n", TYPE_IMX_AVIC
, __func__
, offset
);
213 static void imx_avic_write(void *opaque
, hwaddr offset
,
214 uint64_t val
, unsigned size
)
216 IMXAVICState
*s
= (IMXAVICState
*)opaque
;
218 /* Vector Registers not yet supported */
219 if (offset
>= 0x100 && offset
<= 0x2fc) {
220 qemu_log_mask(LOG_UNIMP
, "[%s]%s: vector %d ignored\n",
221 TYPE_IMX_AVIC
, __func__
, (int)((offset
- 0x100) >> 2));
225 DPRINTF("(0x%" HWADDR_PRIx
") = 0x%x\n", offset
, (unsigned int)val
);
227 switch (offset
>> 2) {
228 case 0: /* Interrupt Control Register, INTCNTL */
229 s
->intcntl
= val
& (ABFEN
| NIDIS
| FIDIS
| NIAD
| FIAD
| NM
);
230 if (s
->intcntl
& ABFEN
) {
231 s
->intcntl
&= ~(val
& ABFLAG
);
235 case 1: /* Normal Interrupt Mask Register, NIMASK */
236 s
->intmask
= val
& 0x1f;
239 case 2: /* Interrupt Enable Number Register, INTENNUM */
240 DPRINTF("enable(%d)\n", (int)val
);
242 s
->enabled
|= (1ULL << val
);
245 case 3: /* Interrupt Disable Number Register, INTDISNUM */
246 DPRINTF("disable(%d)\n", (int)val
);
248 s
->enabled
&= ~(1ULL << val
);
251 case 4: /* Interrupt Enable Number Register High */
252 s
->enabled
= (s
->enabled
& 0xffffffffULL
) | (val
<< 32);
255 case 5: /* Interrupt Enable Number Register Low */
256 s
->enabled
= (s
->enabled
& 0xffffffff00000000ULL
) | val
;
259 case 6: /* Interrupt Type Register High */
260 s
->is_fiq
= (s
->is_fiq
& 0xffffffffULL
) | (val
<< 32);
263 case 7: /* Interrupt Type Register Low */
264 s
->is_fiq
= (s
->is_fiq
& 0xffffffff00000000ULL
) | val
;
267 case 8: /* Normal Interrupt Priority Register 7 */
268 case 9: /* Normal Interrupt Priority Register 6 */
269 case 10:/* Normal Interrupt Priority Register 5 */
270 case 11:/* Normal Interrupt Priority Register 4 */
271 case 12:/* Normal Interrupt Priority Register 3 */
272 case 13:/* Normal Interrupt Priority Register 2 */
273 case 14:/* Normal Interrupt Priority Register 1 */
274 case 15:/* Normal Interrupt Priority Register 0 */
275 s
->prio
[15-(offset
>>2)] = val
;
278 /* Read-only registers, writes ignored */
279 case 16:/* Normal Interrupt Vector and Status register */
280 case 17:/* Fast Interrupt vector and status register */
281 case 18:/* Interrupt source register high */
282 case 19:/* Interrupt source register low */
285 case 20:/* Interrupt Force Register high */
286 s
->pending
= (s
->pending
& 0xffffffffULL
) | (val
<< 32);
289 case 21:/* Interrupt Force Register low */
290 s
->pending
= (s
->pending
& 0xffffffff00000000ULL
) | val
;
293 case 22:/* Normal Interrupt Pending Register High */
294 case 23:/* Normal Interrupt Pending Register Low */
295 case 24: /* Fast Interrupt Pending Register High */
296 case 25: /* Fast Interrupt Pending Register Low */
300 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
301 HWADDR_PRIx
"\n", TYPE_IMX_AVIC
, __func__
, offset
);
306 static const MemoryRegionOps imx_avic_ops
= {
307 .read
= imx_avic_read
,
308 .write
= imx_avic_write
,
309 .endianness
= DEVICE_NATIVE_ENDIAN
,
312 static void imx_avic_reset(DeviceState
*dev
)
314 IMXAVICState
*s
= IMX_AVIC(dev
);
321 memset(s
->prio
, 0, sizeof s
->prio
);
324 static int imx_avic_init(SysBusDevice
*sbd
)
326 DeviceState
*dev
= DEVICE(sbd
);
327 IMXAVICState
*s
= IMX_AVIC(dev
);
329 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_avic_ops
, s
,
330 TYPE_IMX_AVIC
, 0x1000);
331 sysbus_init_mmio(sbd
, &s
->iomem
);
333 qdev_init_gpio_in(dev
, imx_avic_set_irq
, IMX_AVIC_NUM_IRQS
);
334 sysbus_init_irq(sbd
, &s
->irq
);
335 sysbus_init_irq(sbd
, &s
->fiq
);
341 static void imx_avic_class_init(ObjectClass
*klass
, void *data
)
343 DeviceClass
*dc
= DEVICE_CLASS(klass
);
344 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
345 k
->init
= imx_avic_init
;
346 dc
->vmsd
= &vmstate_imx_avic
;
347 dc
->reset
= imx_avic_reset
;
348 dc
->desc
= "i.MX Advanced Vector Interrupt Controller";
351 static const TypeInfo imx_avic_info
= {
352 .name
= TYPE_IMX_AVIC
,
353 .parent
= TYPE_SYS_BUS_DEVICE
,
354 .instance_size
= sizeof(IMXAVICState
),
355 .class_init
= imx_avic_class_init
,
358 static void imx_avic_register_types(void)
360 type_register_static(&imx_avic_info
);
363 type_init(imx_avic_register_types
)