2 #include "host-utils.h"
7 //#define DEBUG_UNALIGNED
8 //#define DEBUG_UNASSIGNED
11 //#define DEBUG_PSTATE
14 #define DPRINTF_MMU(fmt, ...) \
15 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
17 #define DPRINTF_MMU(fmt, ...) do {} while (0)
21 #define DPRINTF_MXCC(fmt, ...) \
22 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
24 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
28 #define DPRINTF_ASI(fmt, ...) \
29 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
33 #define DPRINTF_PSTATE(fmt, ...) \
34 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
36 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
41 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
43 #define AM_CHECK(env1) (1)
47 #define DT0 (env->dt0)
48 #define DT1 (env->dt1)
49 #define QT0 (env->qt0)
50 #define QT1 (env->qt1)
52 #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
53 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
54 int is_asi
, int size
);
57 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
58 // Calculates TSB pointer value for fault page size 8k or 64k
59 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
60 uint64_t tag_access_register
,
63 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
64 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
65 int tsb_size
= tsb_register
& 0xf;
67 // discard lower 13 bits which hold tag access context
68 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
71 uint64_t tsb_base_mask
= ~0x1fffULL
;
72 uint64_t va
= tag_access_va
;
74 // move va bits to correct position
75 if (page_size
== 8*1024) {
77 } else if (page_size
== 64*1024) {
82 tsb_base_mask
<<= tsb_size
;
85 // calculate tsb_base mask and adjust va if split is in use
87 if (page_size
== 8*1024) {
88 va
&= ~(1ULL << (13 + tsb_size
));
89 } else if (page_size
== 64*1024) {
90 va
|= (1ULL << (13 + tsb_size
));
95 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
98 // Calculates tag target register value by reordering bits
99 // in tag access register
100 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
102 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
105 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
106 uint64_t tlb_tag
, uint64_t tlb_tte
,
109 target_ulong mask
, size
, va
, offset
;
111 // flush page range if translation is valid
112 if (TTE_IS_VALID(tlb
->tte
)) {
114 mask
= 0xffffffffffffe000ULL
;
115 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
118 va
= tlb
->tag
& mask
;
120 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
121 tlb_flush_page(env1
, va
+ offset
);
129 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
130 const char* strmmu
, CPUState
*env1
)
136 int is_demap_context
= (demap_addr
>> 6) & 1;
139 switch ((demap_addr
>> 4) & 3) {
141 context
= env1
->dmmu
.mmu_primary_context
;
144 context
= env1
->dmmu
.mmu_secondary_context
;
154 for (i
= 0; i
< 64; i
++) {
155 if (TTE_IS_VALID(tlb
[i
].tte
)) {
157 if (is_demap_context
) {
158 // will remove non-global entries matching context value
159 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
160 !tlb_compare_context(&tlb
[i
], context
)) {
165 // will remove any entry matching VA
166 mask
= 0xffffffffffffe000ULL
;
167 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
169 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
173 // entry should be global or matching context value
174 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
175 !tlb_compare_context(&tlb
[i
], context
)) {
180 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
182 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
189 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
190 uint64_t tlb_tag
, uint64_t tlb_tte
,
191 const char* strmmu
, CPUState
*env1
)
193 unsigned int i
, replace_used
;
195 // Try replacing invalid entry
196 for (i
= 0; i
< 64; i
++) {
197 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
198 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
200 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
207 // All entries are valid, try replacing unlocked entry
209 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
211 // Used entries are not replaced on first pass
213 for (i
= 0; i
< 64; i
++) {
214 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
216 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
218 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
219 strmmu
, (replace_used
?"used":"unused"), i
);
226 // Now reset used bit and search for unused entries again
228 for (i
= 0; i
< 64; i
++) {
229 TTE_SET_UNUSED(tlb
[i
].tte
);
234 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
241 static inline target_ulong
address_mask(CPUState
*env1
, target_ulong addr
)
243 #ifdef TARGET_SPARC64
245 addr
&= 0xffffffffULL
;
250 static void raise_exception(int tt
)
252 env
->exception_index
= tt
;
256 void HELPER(raise_exception
)(int tt
)
261 void helper_check_align(target_ulong addr
, uint32_t align
)
264 #ifdef DEBUG_UNALIGNED
265 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
266 "\n", addr
, env
->pc
);
268 raise_exception(TT_UNALIGNED
);
272 #define F_HELPER(name, p) void helper_f##name##p(void)
274 #define F_BINOP(name) \
275 float32 helper_f ## name ## s (float32 src1, float32 src2) \
277 return float32_ ## name (src1, src2, &env->fp_status); \
281 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
285 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
294 void helper_fsmuld(float32 src1
, float32 src2
)
296 DT0
= float64_mul(float32_to_float64(src1
, &env
->fp_status
),
297 float32_to_float64(src2
, &env
->fp_status
),
301 void helper_fdmulq(void)
303 QT0
= float128_mul(float64_to_float128(DT0
, &env
->fp_status
),
304 float64_to_float128(DT1
, &env
->fp_status
),
308 float32
helper_fnegs(float32 src
)
310 return float32_chs(src
);
313 #ifdef TARGET_SPARC64
316 DT0
= float64_chs(DT1
);
321 QT0
= float128_chs(QT1
);
325 /* Integer to float conversion. */
326 float32
helper_fitos(int32_t src
)
328 return int32_to_float32(src
, &env
->fp_status
);
331 void helper_fitod(int32_t src
)
333 DT0
= int32_to_float64(src
, &env
->fp_status
);
336 void helper_fitoq(int32_t src
)
338 QT0
= int32_to_float128(src
, &env
->fp_status
);
341 #ifdef TARGET_SPARC64
342 float32
helper_fxtos(void)
344 return int64_to_float32(*((int64_t *)&DT1
), &env
->fp_status
);
349 DT0
= int64_to_float64(*((int64_t *)&DT1
), &env
->fp_status
);
354 QT0
= int64_to_float128(*((int64_t *)&DT1
), &env
->fp_status
);
359 /* floating point conversion */
360 float32
helper_fdtos(void)
362 return float64_to_float32(DT1
, &env
->fp_status
);
365 void helper_fstod(float32 src
)
367 DT0
= float32_to_float64(src
, &env
->fp_status
);
370 float32
helper_fqtos(void)
372 return float128_to_float32(QT1
, &env
->fp_status
);
375 void helper_fstoq(float32 src
)
377 QT0
= float32_to_float128(src
, &env
->fp_status
);
380 void helper_fqtod(void)
382 DT0
= float128_to_float64(QT1
, &env
->fp_status
);
385 void helper_fdtoq(void)
387 QT0
= float64_to_float128(DT1
, &env
->fp_status
);
390 /* Float to integer conversion. */
391 int32_t helper_fstoi(float32 src
)
393 return float32_to_int32_round_to_zero(src
, &env
->fp_status
);
396 int32_t helper_fdtoi(void)
398 return float64_to_int32_round_to_zero(DT1
, &env
->fp_status
);
401 int32_t helper_fqtoi(void)
403 return float128_to_int32_round_to_zero(QT1
, &env
->fp_status
);
406 #ifdef TARGET_SPARC64
407 void helper_fstox(float32 src
)
409 *((int64_t *)&DT0
) = float32_to_int64_round_to_zero(src
, &env
->fp_status
);
412 void helper_fdtox(void)
414 *((int64_t *)&DT0
) = float64_to_int64_round_to_zero(DT1
, &env
->fp_status
);
417 void helper_fqtox(void)
419 *((int64_t *)&DT0
) = float128_to_int64_round_to_zero(QT1
, &env
->fp_status
);
422 void helper_faligndata(void)
426 tmp
= (*((uint64_t *)&DT0
)) << ((env
->gsr
& 7) * 8);
427 /* on many architectures a shift of 64 does nothing */
428 if ((env
->gsr
& 7) != 0) {
429 tmp
|= (*((uint64_t *)&DT1
)) >> (64 - (env
->gsr
& 7) * 8);
431 *((uint64_t *)&DT0
) = tmp
;
434 #ifdef HOST_WORDS_BIGENDIAN
435 #define VIS_B64(n) b[7 - (n)]
436 #define VIS_W64(n) w[3 - (n)]
437 #define VIS_SW64(n) sw[3 - (n)]
438 #define VIS_L64(n) l[1 - (n)]
439 #define VIS_B32(n) b[3 - (n)]
440 #define VIS_W32(n) w[1 - (n)]
442 #define VIS_B64(n) b[n]
443 #define VIS_W64(n) w[n]
444 #define VIS_SW64(n) sw[n]
445 #define VIS_L64(n) l[n]
446 #define VIS_B32(n) b[n]
447 #define VIS_W32(n) w[n]
465 void helper_fpmerge(void)
472 // Reverse calculation order to handle overlap
473 d
.VIS_B64(7) = s
.VIS_B64(3);
474 d
.VIS_B64(6) = d
.VIS_B64(3);
475 d
.VIS_B64(5) = s
.VIS_B64(2);
476 d
.VIS_B64(4) = d
.VIS_B64(2);
477 d
.VIS_B64(3) = s
.VIS_B64(1);
478 d
.VIS_B64(2) = d
.VIS_B64(1);
479 d
.VIS_B64(1) = s
.VIS_B64(0);
480 //d.VIS_B64(0) = d.VIS_B64(0);
485 void helper_fmul8x16(void)
494 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
495 if ((tmp & 0xff) > 0x7f) \
497 d.VIS_W64(r) = tmp >> 8;
508 void helper_fmul8x16al(void)
517 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
518 if ((tmp & 0xff) > 0x7f) \
520 d.VIS_W64(r) = tmp >> 8;
531 void helper_fmul8x16au(void)
540 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
541 if ((tmp & 0xff) > 0x7f) \
543 d.VIS_W64(r) = tmp >> 8;
554 void helper_fmul8sux16(void)
563 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
564 if ((tmp & 0xff) > 0x7f) \
566 d.VIS_W64(r) = tmp >> 8;
577 void helper_fmul8ulx16(void)
586 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
587 if ((tmp & 0xff) > 0x7f) \
589 d.VIS_W64(r) = tmp >> 8;
600 void helper_fmuld8sux16(void)
609 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
610 if ((tmp & 0xff) > 0x7f) \
614 // Reverse calculation order to handle overlap
622 void helper_fmuld8ulx16(void)
631 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
632 if ((tmp & 0xff) > 0x7f) \
636 // Reverse calculation order to handle overlap
644 void helper_fexpand(void)
649 s
.l
= (uint32_t)(*(uint64_t *)&DT0
& 0xffffffff);
651 d
.VIS_W64(0) = s
.VIS_B32(0) << 4;
652 d
.VIS_W64(1) = s
.VIS_B32(1) << 4;
653 d
.VIS_W64(2) = s
.VIS_B32(2) << 4;
654 d
.VIS_W64(3) = s
.VIS_B32(3) << 4;
659 #define VIS_HELPER(name, F) \
660 void name##16(void) \
667 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
668 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
669 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
670 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
675 uint32_t name##16s(uint32_t src1, uint32_t src2) \
682 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
683 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
688 void name##32(void) \
695 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
696 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
701 uint32_t name##32s(uint32_t src1, uint32_t src2) \
713 #define FADD(a, b) ((a) + (b))
714 #define FSUB(a, b) ((a) - (b))
715 VIS_HELPER(helper_fpadd
, FADD
)
716 VIS_HELPER(helper_fpsub
, FSUB
)
718 #define VIS_CMPHELPER(name, F) \
719 void name##16(void) \
726 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
727 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
728 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
729 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
734 void name##32(void) \
741 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
742 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
747 #define FCMPGT(a, b) ((a) > (b))
748 #define FCMPEQ(a, b) ((a) == (b))
749 #define FCMPLE(a, b) ((a) <= (b))
750 #define FCMPNE(a, b) ((a) != (b))
752 VIS_CMPHELPER(helper_fcmpgt
, FCMPGT
)
753 VIS_CMPHELPER(helper_fcmpeq
, FCMPEQ
)
754 VIS_CMPHELPER(helper_fcmple
, FCMPLE
)
755 VIS_CMPHELPER(helper_fcmpne
, FCMPNE
)
758 void helper_check_ieee_exceptions(void)
762 status
= get_float_exception_flags(&env
->fp_status
);
764 /* Copy IEEE 754 flags into FSR */
765 if (status
& float_flag_invalid
)
767 if (status
& float_flag_overflow
)
769 if (status
& float_flag_underflow
)
771 if (status
& float_flag_divbyzero
)
773 if (status
& float_flag_inexact
)
776 if ((env
->fsr
& FSR_CEXC_MASK
) & ((env
->fsr
& FSR_TEM_MASK
) >> 23)) {
777 /* Unmasked exception, generate a trap */
778 env
->fsr
|= FSR_FTT_IEEE_EXCP
;
779 raise_exception(TT_FP_EXCP
);
781 /* Accumulate exceptions */
782 env
->fsr
|= (env
->fsr
& FSR_CEXC_MASK
) << 5;
787 void helper_clear_float_exceptions(void)
789 set_float_exception_flags(0, &env
->fp_status
);
792 float32
helper_fabss(float32 src
)
794 return float32_abs(src
);
797 #ifdef TARGET_SPARC64
798 void helper_fabsd(void)
800 DT0
= float64_abs(DT1
);
803 void helper_fabsq(void)
805 QT0
= float128_abs(QT1
);
809 float32
helper_fsqrts(float32 src
)
811 return float32_sqrt(src
, &env
->fp_status
);
814 void helper_fsqrtd(void)
816 DT0
= float64_sqrt(DT1
, &env
->fp_status
);
819 void helper_fsqrtq(void)
821 QT0
= float128_sqrt(QT1
, &env
->fp_status
);
824 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
825 void glue(helper_, name) (void) \
827 target_ulong new_fsr; \
829 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
830 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
831 case float_relation_unordered: \
832 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
833 if ((env->fsr & FSR_NVM) || TRAP) { \
834 env->fsr |= new_fsr; \
835 env->fsr |= FSR_NVC; \
836 env->fsr |= FSR_FTT_IEEE_EXCP; \
837 raise_exception(TT_FP_EXCP); \
839 env->fsr |= FSR_NVA; \
842 case float_relation_less: \
843 new_fsr = FSR_FCC0 << FS; \
845 case float_relation_greater: \
846 new_fsr = FSR_FCC1 << FS; \
852 env->fsr |= new_fsr; \
854 #define GEN_FCMPS(name, size, FS, TRAP) \
855 void glue(helper_, name)(float32 src1, float32 src2) \
857 target_ulong new_fsr; \
859 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
860 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
861 case float_relation_unordered: \
862 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
863 if ((env->fsr & FSR_NVM) || TRAP) { \
864 env->fsr |= new_fsr; \
865 env->fsr |= FSR_NVC; \
866 env->fsr |= FSR_FTT_IEEE_EXCP; \
867 raise_exception(TT_FP_EXCP); \
869 env->fsr |= FSR_NVA; \
872 case float_relation_less: \
873 new_fsr = FSR_FCC0 << FS; \
875 case float_relation_greater: \
876 new_fsr = FSR_FCC1 << FS; \
882 env->fsr |= new_fsr; \
885 GEN_FCMPS(fcmps
, float32
, 0, 0);
886 GEN_FCMP(fcmpd
, float64
, DT0
, DT1
, 0, 0);
888 GEN_FCMPS(fcmpes
, float32
, 0, 1);
889 GEN_FCMP(fcmped
, float64
, DT0
, DT1
, 0, 1);
891 GEN_FCMP(fcmpq
, float128
, QT0
, QT1
, 0, 0);
892 GEN_FCMP(fcmpeq
, float128
, QT0
, QT1
, 0, 1);
894 static uint32_t compute_all_flags(void)
896 return env
->psr
& PSR_ICC
;
899 static uint32_t compute_C_flags(void)
901 return env
->psr
& PSR_CARRY
;
904 static inline uint32_t get_NZ_icc(int32_t dst
)
910 } else if (dst
< 0) {
916 #ifdef TARGET_SPARC64
917 static uint32_t compute_all_flags_xcc(void)
919 return env
->xcc
& PSR_ICC
;
922 static uint32_t compute_C_flags_xcc(void)
924 return env
->xcc
& PSR_CARRY
;
927 static inline uint32_t get_NZ_xcc(target_long dst
)
933 } else if (dst
< 0) {
940 static inline uint32_t get_V_div_icc(target_ulong src2
)
950 static uint32_t compute_all_div(void)
954 ret
= get_NZ_icc(CC_DST
);
955 ret
|= get_V_div_icc(CC_SRC2
);
959 static uint32_t compute_C_div(void)
964 static inline uint32_t get_C_add_icc(uint32_t dst
, uint32_t src1
)
974 static inline uint32_t get_C_addx_icc(uint32_t dst
, uint32_t src1
,
979 if (((src1
& src2
) | (~dst
& (src1
| src2
))) & (1U << 31)) {
985 static inline uint32_t get_V_add_icc(uint32_t dst
, uint32_t src1
,
990 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1U << 31)) {
996 #ifdef TARGET_SPARC64
997 static inline uint32_t get_C_add_xcc(target_ulong dst
, target_ulong src1
)
1007 static inline uint32_t get_C_addx_xcc(target_ulong dst
, target_ulong src1
,
1012 if (((src1
& src2
) | (~dst
& (src1
| src2
))) & (1ULL << 63)) {
1018 static inline uint32_t get_V_add_xcc(target_ulong dst
, target_ulong src1
,
1023 if (((src1
^ src2
^ -1) & (src1
^ dst
)) & (1ULL << 63)) {
1029 static uint32_t compute_all_add_xcc(void)
1033 ret
= get_NZ_xcc(CC_DST
);
1034 ret
|= get_C_add_xcc(CC_DST
, CC_SRC
);
1035 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1039 static uint32_t compute_C_add_xcc(void)
1041 return get_C_add_xcc(CC_DST
, CC_SRC
);
1045 static uint32_t compute_all_add(void)
1049 ret
= get_NZ_icc(CC_DST
);
1050 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1051 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1055 static uint32_t compute_C_add(void)
1057 return get_C_add_icc(CC_DST
, CC_SRC
);
1060 #ifdef TARGET_SPARC64
1061 static uint32_t compute_all_addx_xcc(void)
1065 ret
= get_NZ_xcc(CC_DST
);
1066 ret
|= get_C_addx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1067 ret
|= get_V_add_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1071 static uint32_t compute_C_addx_xcc(void)
1075 ret
= get_C_addx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1080 static uint32_t compute_all_addx(void)
1084 ret
= get_NZ_icc(CC_DST
);
1085 ret
|= get_C_addx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1086 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1090 static uint32_t compute_C_addx(void)
1094 ret
= get_C_addx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1098 static inline uint32_t get_V_tag_icc(target_ulong src1
, target_ulong src2
)
1102 if ((src1
| src2
) & 0x3) {
1108 static uint32_t compute_all_tadd(void)
1112 ret
= get_NZ_icc(CC_DST
);
1113 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1114 ret
|= get_V_add_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1115 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1119 static uint32_t compute_all_taddtv(void)
1123 ret
= get_NZ_icc(CC_DST
);
1124 ret
|= get_C_add_icc(CC_DST
, CC_SRC
);
1128 static inline uint32_t get_C_sub_icc(uint32_t src1
, uint32_t src2
)
1138 static inline uint32_t get_C_subx_icc(uint32_t dst
, uint32_t src1
,
1143 if (((~src1
& src2
) | (dst
& (~src1
| src2
))) & (1U << 31)) {
1149 static inline uint32_t get_V_sub_icc(uint32_t dst
, uint32_t src1
,
1154 if (((src1
^ src2
) & (src1
^ dst
)) & (1U << 31)) {
1161 #ifdef TARGET_SPARC64
1162 static inline uint32_t get_C_sub_xcc(target_ulong src1
, target_ulong src2
)
1172 static inline uint32_t get_C_subx_xcc(target_ulong dst
, target_ulong src1
,
1177 if (((~src1
& src2
) | (dst
& (~src1
| src2
))) & (1ULL << 63)) {
1183 static inline uint32_t get_V_sub_xcc(target_ulong dst
, target_ulong src1
,
1188 if (((src1
^ src2
) & (src1
^ dst
)) & (1ULL << 63)) {
1194 static uint32_t compute_all_sub_xcc(void)
1198 ret
= get_NZ_xcc(CC_DST
);
1199 ret
|= get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1200 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1204 static uint32_t compute_C_sub_xcc(void)
1206 return get_C_sub_xcc(CC_SRC
, CC_SRC2
);
1210 static uint32_t compute_all_sub(void)
1214 ret
= get_NZ_icc(CC_DST
);
1215 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1216 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1220 static uint32_t compute_C_sub(void)
1222 return get_C_sub_icc(CC_SRC
, CC_SRC2
);
1225 #ifdef TARGET_SPARC64
1226 static uint32_t compute_all_subx_xcc(void)
1230 ret
= get_NZ_xcc(CC_DST
);
1231 ret
|= get_C_subx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1232 ret
|= get_V_sub_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1236 static uint32_t compute_C_subx_xcc(void)
1240 ret
= get_C_subx_xcc(CC_DST
, CC_SRC
, CC_SRC2
);
1245 static uint32_t compute_all_subx(void)
1249 ret
= get_NZ_icc(CC_DST
);
1250 ret
|= get_C_subx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1251 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1255 static uint32_t compute_C_subx(void)
1259 ret
= get_C_subx_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1263 static uint32_t compute_all_tsub(void)
1267 ret
= get_NZ_icc(CC_DST
);
1268 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1269 ret
|= get_V_sub_icc(CC_DST
, CC_SRC
, CC_SRC2
);
1270 ret
|= get_V_tag_icc(CC_SRC
, CC_SRC2
);
1274 static uint32_t compute_all_tsubtv(void)
1278 ret
= get_NZ_icc(CC_DST
);
1279 ret
|= get_C_sub_icc(CC_SRC
, CC_SRC2
);
1283 static uint32_t compute_all_logic(void)
1285 return get_NZ_icc(CC_DST
);
1288 static uint32_t compute_C_logic(void)
1293 #ifdef TARGET_SPARC64
1294 static uint32_t compute_all_logic_xcc(void)
1296 return get_NZ_xcc(CC_DST
);
1300 typedef struct CCTable
{
1301 uint32_t (*compute_all
)(void); /* return all the flags */
1302 uint32_t (*compute_c
)(void); /* return the C flag */
1305 static const CCTable icc_table
[CC_OP_NB
] = {
1306 /* CC_OP_DYNAMIC should never happen */
1307 [CC_OP_FLAGS
] = { compute_all_flags
, compute_C_flags
},
1308 [CC_OP_DIV
] = { compute_all_div
, compute_C_div
},
1309 [CC_OP_ADD
] = { compute_all_add
, compute_C_add
},
1310 [CC_OP_ADDX
] = { compute_all_addx
, compute_C_addx
},
1311 [CC_OP_TADD
] = { compute_all_tadd
, compute_C_add
},
1312 [CC_OP_TADDTV
] = { compute_all_taddtv
, compute_C_add
},
1313 [CC_OP_SUB
] = { compute_all_sub
, compute_C_sub
},
1314 [CC_OP_SUBX
] = { compute_all_subx
, compute_C_subx
},
1315 [CC_OP_TSUB
] = { compute_all_tsub
, compute_C_sub
},
1316 [CC_OP_TSUBTV
] = { compute_all_tsubtv
, compute_C_sub
},
1317 [CC_OP_LOGIC
] = { compute_all_logic
, compute_C_logic
},
1320 #ifdef TARGET_SPARC64
1321 static const CCTable xcc_table
[CC_OP_NB
] = {
1322 /* CC_OP_DYNAMIC should never happen */
1323 [CC_OP_FLAGS
] = { compute_all_flags_xcc
, compute_C_flags_xcc
},
1324 [CC_OP_DIV
] = { compute_all_logic_xcc
, compute_C_logic
},
1325 [CC_OP_ADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1326 [CC_OP_ADDX
] = { compute_all_addx_xcc
, compute_C_addx_xcc
},
1327 [CC_OP_TADD
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1328 [CC_OP_TADDTV
] = { compute_all_add_xcc
, compute_C_add_xcc
},
1329 [CC_OP_SUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1330 [CC_OP_SUBX
] = { compute_all_subx_xcc
, compute_C_subx_xcc
},
1331 [CC_OP_TSUB
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1332 [CC_OP_TSUBTV
] = { compute_all_sub_xcc
, compute_C_sub_xcc
},
1333 [CC_OP_LOGIC
] = { compute_all_logic_xcc
, compute_C_logic
},
1337 void helper_compute_psr(void)
1341 new_psr
= icc_table
[CC_OP
].compute_all();
1343 #ifdef TARGET_SPARC64
1344 new_psr
= xcc_table
[CC_OP
].compute_all();
1347 CC_OP
= CC_OP_FLAGS
;
1350 uint32_t helper_compute_C_icc(void)
1354 ret
= icc_table
[CC_OP
].compute_c() >> PSR_CARRY_SHIFT
;
1358 static inline void memcpy32(target_ulong
*dst
, const target_ulong
*src
)
1370 static void set_cwp(int new_cwp
)
1372 /* put the modified wrap registers at their proper location */
1373 if (env
->cwp
== env
->nwindows
- 1) {
1374 memcpy32(env
->regbase
, env
->regbase
+ env
->nwindows
* 16);
1378 /* put the wrap registers at their temporary location */
1379 if (new_cwp
== env
->nwindows
- 1) {
1380 memcpy32(env
->regbase
+ env
->nwindows
* 16, env
->regbase
);
1382 env
->regwptr
= env
->regbase
+ (new_cwp
* 16);
1385 void cpu_set_cwp(CPUState
*env1
, int new_cwp
)
1387 CPUState
*saved_env
;
1395 static target_ulong
get_psr(void)
1397 helper_compute_psr();
1399 #if !defined (TARGET_SPARC64)
1400 return env
->version
| (env
->psr
& PSR_ICC
) |
1401 (env
->psref
? PSR_EF
: 0) |
1402 (env
->psrpil
<< 8) |
1403 (env
->psrs
? PSR_S
: 0) |
1404 (env
->psrps
? PSR_PS
: 0) |
1405 (env
->psret
? PSR_ET
: 0) | env
->cwp
;
1407 return env
->psr
& PSR_ICC
;
1411 target_ulong
cpu_get_psr(CPUState
*env1
)
1413 CPUState
*saved_env
;
1423 static void put_psr(target_ulong val
)
1425 env
->psr
= val
& PSR_ICC
;
1426 #if !defined (TARGET_SPARC64)
1427 env
->psref
= (val
& PSR_EF
)? 1 : 0;
1428 env
->psrpil
= (val
& PSR_PIL
) >> 8;
1430 #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
1431 cpu_check_irqs(env
);
1433 #if !defined (TARGET_SPARC64)
1434 env
->psrs
= (val
& PSR_S
)? 1 : 0;
1435 env
->psrps
= (val
& PSR_PS
)? 1 : 0;
1436 env
->psret
= (val
& PSR_ET
)? 1 : 0;
1437 set_cwp(val
& PSR_CWP
);
1439 env
->cc_op
= CC_OP_FLAGS
;
1442 void cpu_put_psr(CPUState
*env1
, target_ulong val
)
1444 CPUState
*saved_env
;
1452 static int cwp_inc(int cwp
)
1454 if (unlikely(cwp
>= env
->nwindows
)) {
1455 cwp
-= env
->nwindows
;
1460 int cpu_cwp_inc(CPUState
*env1
, int cwp
)
1462 CPUState
*saved_env
;
1472 static int cwp_dec(int cwp
)
1474 if (unlikely(cwp
< 0)) {
1475 cwp
+= env
->nwindows
;
1480 int cpu_cwp_dec(CPUState
*env1
, int cwp
)
1482 CPUState
*saved_env
;
1492 #ifdef TARGET_SPARC64
1493 GEN_FCMPS(fcmps_fcc1
, float32
, 22, 0);
1494 GEN_FCMP(fcmpd_fcc1
, float64
, DT0
, DT1
, 22, 0);
1495 GEN_FCMP(fcmpq_fcc1
, float128
, QT0
, QT1
, 22, 0);
1497 GEN_FCMPS(fcmps_fcc2
, float32
, 24, 0);
1498 GEN_FCMP(fcmpd_fcc2
, float64
, DT0
, DT1
, 24, 0);
1499 GEN_FCMP(fcmpq_fcc2
, float128
, QT0
, QT1
, 24, 0);
1501 GEN_FCMPS(fcmps_fcc3
, float32
, 26, 0);
1502 GEN_FCMP(fcmpd_fcc3
, float64
, DT0
, DT1
, 26, 0);
1503 GEN_FCMP(fcmpq_fcc3
, float128
, QT0
, QT1
, 26, 0);
1505 GEN_FCMPS(fcmpes_fcc1
, float32
, 22, 1);
1506 GEN_FCMP(fcmped_fcc1
, float64
, DT0
, DT1
, 22, 1);
1507 GEN_FCMP(fcmpeq_fcc1
, float128
, QT0
, QT1
, 22, 1);
1509 GEN_FCMPS(fcmpes_fcc2
, float32
, 24, 1);
1510 GEN_FCMP(fcmped_fcc2
, float64
, DT0
, DT1
, 24, 1);
1511 GEN_FCMP(fcmpeq_fcc2
, float128
, QT0
, QT1
, 24, 1);
1513 GEN_FCMPS(fcmpes_fcc3
, float32
, 26, 1);
1514 GEN_FCMP(fcmped_fcc3
, float64
, DT0
, DT1
, 26, 1);
1515 GEN_FCMP(fcmpeq_fcc3
, float128
, QT0
, QT1
, 26, 1);
1519 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1521 static void dump_mxcc(CPUState
*env
)
1523 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1525 env
->mxccdata
[0], env
->mxccdata
[1],
1526 env
->mxccdata
[2], env
->mxccdata
[3]);
1527 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1529 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
1531 env
->mxccregs
[0], env
->mxccregs
[1],
1532 env
->mxccregs
[2], env
->mxccregs
[3],
1533 env
->mxccregs
[4], env
->mxccregs
[5],
1534 env
->mxccregs
[6], env
->mxccregs
[7]);
1538 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1539 && defined(DEBUG_ASI)
1540 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
1546 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
1547 addr
, asi
, r1
& 0xff);
1550 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
1551 addr
, asi
, r1
& 0xffff);
1554 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
1555 addr
, asi
, r1
& 0xffffffff);
1558 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
1565 #ifndef TARGET_SPARC64
1566 #ifndef CONFIG_USER_ONLY
1567 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
1570 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1571 uint32_t last_addr
= addr
;
1574 helper_check_align(addr
, size
- 1);
1576 case 2: /* SuperSparc MXCC registers */
1578 case 0x01c00a00: /* MXCC control register */
1580 ret
= env
->mxccregs
[3];
1582 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1585 case 0x01c00a04: /* MXCC control register */
1587 ret
= env
->mxccregs
[3];
1589 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1592 case 0x01c00c00: /* Module reset register */
1594 ret
= env
->mxccregs
[5];
1595 // should we do something here?
1597 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1600 case 0x01c00f00: /* MBus port address register */
1602 ret
= env
->mxccregs
[7];
1604 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1608 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1612 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1613 "addr = %08x -> ret = %" PRIx64
","
1614 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
1619 case 3: /* MMU probe */
1623 mmulev
= (addr
>> 8) & 15;
1627 ret
= mmu_probe(env
, addr
, mmulev
);
1628 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
1632 case 4: /* read MMU regs */
1634 int reg
= (addr
>> 8) & 0x1f;
1636 ret
= env
->mmuregs
[reg
];
1637 if (reg
== 3) /* Fault status cleared on read */
1638 env
->mmuregs
[3] = 0;
1639 else if (reg
== 0x13) /* Fault status read */
1640 ret
= env
->mmuregs
[3];
1641 else if (reg
== 0x14) /* Fault address read */
1642 ret
= env
->mmuregs
[4];
1643 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
1646 case 5: // Turbosparc ITLB Diagnostic
1647 case 6: // Turbosparc DTLB Diagnostic
1648 case 7: // Turbosparc IOTLB Diagnostic
1650 case 9: /* Supervisor code access */
1653 ret
= ldub_code(addr
);
1656 ret
= lduw_code(addr
);
1660 ret
= ldl_code(addr
);
1663 ret
= ldq_code(addr
);
1667 case 0xa: /* User data access */
1670 ret
= ldub_user(addr
);
1673 ret
= lduw_user(addr
);
1677 ret
= ldl_user(addr
);
1680 ret
= ldq_user(addr
);
1684 case 0xb: /* Supervisor data access */
1687 ret
= ldub_kernel(addr
);
1690 ret
= lduw_kernel(addr
);
1694 ret
= ldl_kernel(addr
);
1697 ret
= ldq_kernel(addr
);
1701 case 0xc: /* I-cache tag */
1702 case 0xd: /* I-cache data */
1703 case 0xe: /* D-cache tag */
1704 case 0xf: /* D-cache data */
1706 case 0x20: /* MMU passthrough */
1709 ret
= ldub_phys(addr
);
1712 ret
= lduw_phys(addr
);
1716 ret
= ldl_phys(addr
);
1719 ret
= ldq_phys(addr
);
1723 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1726 ret
= ldub_phys((target_phys_addr_t
)addr
1727 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1730 ret
= lduw_phys((target_phys_addr_t
)addr
1731 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1735 ret
= ldl_phys((target_phys_addr_t
)addr
1736 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1739 ret
= ldq_phys((target_phys_addr_t
)addr
1740 | ((target_phys_addr_t
)(asi
& 0xf) << 32));
1744 case 0x30: // Turbosparc secondary cache diagnostic
1745 case 0x31: // Turbosparc RAM snoop
1746 case 0x32: // Turbosparc page table descriptor diagnostic
1747 case 0x39: /* data cache diagnostic register */
1748 case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
1751 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1753 int reg
= (addr
>> 8) & 3;
1756 case 0: /* Breakpoint Value (Addr) */
1757 ret
= env
->mmubpregs
[reg
];
1759 case 1: /* Breakpoint Mask */
1760 ret
= env
->mmubpregs
[reg
];
1762 case 2: /* Breakpoint Control */
1763 ret
= env
->mmubpregs
[reg
];
1765 case 3: /* Breakpoint Status */
1766 ret
= env
->mmubpregs
[reg
];
1767 env
->mmubpregs
[reg
] = 0ULL;
1770 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
1774 case 8: /* User code access, XXX */
1776 do_unassigned_access(addr
, 0, 0, asi
, size
);
1786 ret
= (int16_t) ret
;
1789 ret
= (int32_t) ret
;
1796 dump_asi("read ", last_addr
, asi
, size
, ret
);
1801 void helper_st_asi(target_ulong addr
, uint64_t val
, int asi
, int size
)
1803 helper_check_align(addr
, size
- 1);
1805 case 2: /* SuperSparc MXCC registers */
1807 case 0x01c00000: /* MXCC stream data register 0 */
1809 env
->mxccdata
[0] = val
;
1811 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1814 case 0x01c00008: /* MXCC stream data register 1 */
1816 env
->mxccdata
[1] = val
;
1818 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1821 case 0x01c00010: /* MXCC stream data register 2 */
1823 env
->mxccdata
[2] = val
;
1825 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1828 case 0x01c00018: /* MXCC stream data register 3 */
1830 env
->mxccdata
[3] = val
;
1832 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1835 case 0x01c00100: /* MXCC stream source */
1837 env
->mxccregs
[0] = val
;
1839 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1841 env
->mxccdata
[0] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1843 env
->mxccdata
[1] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1845 env
->mxccdata
[2] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1847 env
->mxccdata
[3] = ldq_phys((env
->mxccregs
[0] & 0xffffffffULL
) +
1850 case 0x01c00200: /* MXCC stream destination */
1852 env
->mxccregs
[1] = val
;
1854 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1856 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 0,
1858 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 8,
1860 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 16,
1862 stq_phys((env
->mxccregs
[1] & 0xffffffffULL
) + 24,
1865 case 0x01c00a00: /* MXCC control register */
1867 env
->mxccregs
[3] = val
;
1869 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1872 case 0x01c00a04: /* MXCC control register */
1874 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
1877 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1880 case 0x01c00e00: /* MXCC error register */
1881 // writing a 1 bit clears the error
1883 env
->mxccregs
[6] &= ~val
;
1885 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1888 case 0x01c00f00: /* MBus port address register */
1890 env
->mxccregs
[7] = val
;
1892 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr
,
1896 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr
,
1900 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
1901 asi
, size
, addr
, val
);
1906 case 3: /* MMU flush */
1910 mmulev
= (addr
>> 8) & 15;
1911 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
1913 case 0: // flush page
1914 tlb_flush_page(env
, addr
& 0xfffff000);
1916 case 1: // flush segment (256k)
1917 case 2: // flush region (16M)
1918 case 3: // flush context (4G)
1919 case 4: // flush entire
1930 case 4: /* write MMU regs */
1932 int reg
= (addr
>> 8) & 0x1f;
1935 oldreg
= env
->mmuregs
[reg
];
1937 case 0: // Control Register
1938 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1940 // Mappings generated during no-fault mode or MMU
1941 // disabled mode are invalid in normal mode
1942 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
1943 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)))
1946 case 1: // Context Table Pointer Register
1947 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
1949 case 2: // Context Register
1950 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
1951 if (oldreg
!= env
->mmuregs
[reg
]) {
1952 /* we flush when the MMU context changes because
1953 QEMU has no MMU context support */
1957 case 3: // Synchronous Fault Status Register with Clear
1958 case 4: // Synchronous Fault Address Register
1960 case 0x10: // TLB Replacement Control Register
1961 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
1963 case 0x13: // Synchronous Fault Status Register with Read and Clear
1964 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
1966 case 0x14: // Synchronous Fault Address Register
1967 env
->mmuregs
[4] = val
;
1970 env
->mmuregs
[reg
] = val
;
1973 if (oldreg
!= env
->mmuregs
[reg
]) {
1974 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1975 reg
, oldreg
, env
->mmuregs
[reg
]);
1982 case 5: // Turbosparc ITLB Diagnostic
1983 case 6: // Turbosparc DTLB Diagnostic
1984 case 7: // Turbosparc IOTLB Diagnostic
1986 case 0xa: /* User data access */
1989 stb_user(addr
, val
);
1992 stw_user(addr
, val
);
1996 stl_user(addr
, val
);
1999 stq_user(addr
, val
);
2003 case 0xb: /* Supervisor data access */
2006 stb_kernel(addr
, val
);
2009 stw_kernel(addr
, val
);
2013 stl_kernel(addr
, val
);
2016 stq_kernel(addr
, val
);
2020 case 0xc: /* I-cache tag */
2021 case 0xd: /* I-cache data */
2022 case 0xe: /* D-cache tag */
2023 case 0xf: /* D-cache data */
2024 case 0x10: /* I/D-cache flush page */
2025 case 0x11: /* I/D-cache flush segment */
2026 case 0x12: /* I/D-cache flush region */
2027 case 0x13: /* I/D-cache flush context */
2028 case 0x14: /* I/D-cache flush user */
2030 case 0x17: /* Block copy, sta access */
2036 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
2038 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
2039 temp
= ldl_kernel(src
);
2040 stl_kernel(dst
, temp
);
2044 case 0x1f: /* Block fill, stda access */
2047 // fill 32 bytes with val
2049 uint32_t dst
= addr
& 7;
2051 for (i
= 0; i
< 32; i
+= 8, dst
+= 8)
2052 stq_kernel(dst
, val
);
2055 case 0x20: /* MMU passthrough */
2059 stb_phys(addr
, val
);
2062 stw_phys(addr
, val
);
2066 stl_phys(addr
, val
);
2069 stq_phys(addr
, val
);
2074 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
2078 stb_phys((target_phys_addr_t
)addr
2079 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2082 stw_phys((target_phys_addr_t
)addr
2083 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2087 stl_phys((target_phys_addr_t
)addr
2088 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2091 stq_phys((target_phys_addr_t
)addr
2092 | ((target_phys_addr_t
)(asi
& 0xf) << 32), val
);
2097 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
2098 case 0x31: // store buffer data, Ross RT620 I-cache flush or
2099 // Turbosparc snoop RAM
2100 case 0x32: // store buffer control or Turbosparc page table
2101 // descriptor diagnostic
2102 case 0x36: /* I-cache flash clear */
2103 case 0x37: /* D-cache flash clear */
2104 case 0x4c: /* breakpoint action */
2106 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
2108 int reg
= (addr
>> 8) & 3;
2111 case 0: /* Breakpoint Value (Addr) */
2112 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
2114 case 1: /* Breakpoint Mask */
2115 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
2117 case 2: /* Breakpoint Control */
2118 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
2120 case 3: /* Breakpoint Status */
2121 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
2124 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
2128 case 8: /* User code access, XXX */
2129 case 9: /* Supervisor code access, XXX */
2131 do_unassigned_access(addr
, 1, 0, asi
, size
);
2135 dump_asi("write", addr
, asi
, size
, val
);
2139 #endif /* CONFIG_USER_ONLY */
2140 #else /* TARGET_SPARC64 */
2142 #ifdef CONFIG_USER_ONLY
2143 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2146 #if defined(DEBUG_ASI)
2147 target_ulong last_addr
= addr
;
2151 raise_exception(TT_PRIV_ACT
);
2153 helper_check_align(addr
, size
- 1);
2154 addr
= address_mask(env
, addr
);
2157 case 0x82: // Primary no-fault
2158 case 0x8a: // Primary no-fault LE
2159 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
2161 dump_asi("read ", last_addr
, asi
, size
, ret
);
2166 case 0x80: // Primary
2167 case 0x88: // Primary LE
2171 ret
= ldub_raw(addr
);
2174 ret
= lduw_raw(addr
);
2177 ret
= ldl_raw(addr
);
2181 ret
= ldq_raw(addr
);
2186 case 0x83: // Secondary no-fault
2187 case 0x8b: // Secondary no-fault LE
2188 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
2190 dump_asi("read ", last_addr
, asi
, size
, ret
);
2195 case 0x81: // Secondary
2196 case 0x89: // Secondary LE
2203 /* Convert from little endian */
2205 case 0x88: // Primary LE
2206 case 0x89: // Secondary LE
2207 case 0x8a: // Primary no-fault LE
2208 case 0x8b: // Secondary no-fault LE
2226 /* Convert to signed number */
2233 ret
= (int16_t) ret
;
2236 ret
= (int32_t) ret
;
2243 dump_asi("read ", last_addr
, asi
, size
, ret
);
2248 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2251 dump_asi("write", addr
, asi
, size
, val
);
2254 raise_exception(TT_PRIV_ACT
);
2256 helper_check_align(addr
, size
- 1);
2257 addr
= address_mask(env
, addr
);
2259 /* Convert to little endian */
2261 case 0x88: // Primary LE
2262 case 0x89: // Secondary LE
2281 case 0x80: // Primary
2282 case 0x88: // Primary LE
2301 case 0x81: // Secondary
2302 case 0x89: // Secondary LE
2306 case 0x82: // Primary no-fault, RO
2307 case 0x83: // Secondary no-fault, RO
2308 case 0x8a: // Primary no-fault LE, RO
2309 case 0x8b: // Secondary no-fault LE, RO
2311 do_unassigned_access(addr
, 1, 0, 1, size
);
2316 #else /* CONFIG_USER_ONLY */
2318 uint64_t helper_ld_asi(target_ulong addr
, int asi
, int size
, int sign
)
2321 #if defined(DEBUG_ASI)
2322 target_ulong last_addr
= addr
;
2327 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2328 || (cpu_has_hypervisor(env
)
2329 && asi
>= 0x30 && asi
< 0x80
2330 && !(env
->hpstate
& HS_PRIV
)))
2331 raise_exception(TT_PRIV_ACT
);
2333 helper_check_align(addr
, size
- 1);
2335 case 0x82: // Primary no-fault
2336 case 0x8a: // Primary no-fault LE
2337 case 0x83: // Secondary no-fault
2338 case 0x8b: // Secondary no-fault LE
2340 /* secondary space access has lowest asi bit equal to 1 */
2341 int access_mmu_idx
= ( asi
& 1 ) ? MMU_KERNEL_IDX
2342 : MMU_KERNEL_SECONDARY_IDX
;
2344 if (cpu_get_phys_page_nofault(env
, addr
, access_mmu_idx
) == -1ULL) {
2346 dump_asi("read ", last_addr
, asi
, size
, ret
);
2352 case 0x10: // As if user primary
2353 case 0x11: // As if user secondary
2354 case 0x18: // As if user primary LE
2355 case 0x19: // As if user secondary LE
2356 case 0x80: // Primary
2357 case 0x81: // Secondary
2358 case 0x88: // Primary LE
2359 case 0x89: // Secondary LE
2360 case 0xe2: // UA2007 Primary block init
2361 case 0xe3: // UA2007 Secondary block init
2362 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2363 if (cpu_hypervisor_mode(env
)) {
2366 ret
= ldub_hypv(addr
);
2369 ret
= lduw_hypv(addr
);
2372 ret
= ldl_hypv(addr
);
2376 ret
= ldq_hypv(addr
);
2380 /* secondary space access has lowest asi bit equal to 1 */
2384 ret
= ldub_kernel_secondary(addr
);
2387 ret
= lduw_kernel_secondary(addr
);
2390 ret
= ldl_kernel_secondary(addr
);
2394 ret
= ldq_kernel_secondary(addr
);
2400 ret
= ldub_kernel(addr
);
2403 ret
= lduw_kernel(addr
);
2406 ret
= ldl_kernel(addr
);
2410 ret
= ldq_kernel(addr
);
2416 /* secondary space access has lowest asi bit equal to 1 */
2420 ret
= ldub_user_secondary(addr
);
2423 ret
= lduw_user_secondary(addr
);
2426 ret
= ldl_user_secondary(addr
);
2430 ret
= ldq_user_secondary(addr
);
2436 ret
= ldub_user(addr
);
2439 ret
= lduw_user(addr
);
2442 ret
= ldl_user(addr
);
2446 ret
= ldq_user(addr
);
2452 case 0x14: // Bypass
2453 case 0x15: // Bypass, non-cacheable
2454 case 0x1c: // Bypass LE
2455 case 0x1d: // Bypass, non-cacheable LE
2459 ret
= ldub_phys(addr
);
2462 ret
= lduw_phys(addr
);
2465 ret
= ldl_phys(addr
);
2469 ret
= ldq_phys(addr
);
2474 case 0x24: // Nucleus quad LDD 128 bit atomic
2475 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2476 // Only ldda allowed
2477 raise_exception(TT_ILL_INSN
);
2479 case 0x04: // Nucleus
2480 case 0x0c: // Nucleus Little Endian (LE)
2484 ret
= ldub_nucleus(addr
);
2487 ret
= lduw_nucleus(addr
);
2490 ret
= ldl_nucleus(addr
);
2494 ret
= ldq_nucleus(addr
);
2499 case 0x4a: // UPA config
2505 case 0x50: // I-MMU regs
2507 int reg
= (addr
>> 3) & 0xf;
2510 // I-TSB Tag Target register
2511 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
2513 ret
= env
->immuregs
[reg
];
2518 case 0x51: // I-MMU 8k TSB pointer
2520 // env->immuregs[5] holds I-MMU TSB register value
2521 // env->immuregs[6] holds I-MMU Tag Access register value
2522 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2526 case 0x52: // I-MMU 64k TSB pointer
2528 // env->immuregs[5] holds I-MMU TSB register value
2529 // env->immuregs[6] holds I-MMU Tag Access register value
2530 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
2534 case 0x55: // I-MMU data access
2536 int reg
= (addr
>> 3) & 0x3f;
2538 ret
= env
->itlb
[reg
].tte
;
2541 case 0x56: // I-MMU tag read
2543 int reg
= (addr
>> 3) & 0x3f;
2545 ret
= env
->itlb
[reg
].tag
;
2548 case 0x58: // D-MMU regs
2550 int reg
= (addr
>> 3) & 0xf;
2553 // D-TSB Tag Target register
2554 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
2556 ret
= env
->dmmuregs
[reg
];
2560 case 0x59: // D-MMU 8k TSB pointer
2562 // env->dmmuregs[5] holds D-MMU TSB register value
2563 // env->dmmuregs[6] holds D-MMU Tag Access register value
2564 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2568 case 0x5a: // D-MMU 64k TSB pointer
2570 // env->dmmuregs[5] holds D-MMU TSB register value
2571 // env->dmmuregs[6] holds D-MMU Tag Access register value
2572 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
2576 case 0x5d: // D-MMU data access
2578 int reg
= (addr
>> 3) & 0x3f;
2580 ret
= env
->dtlb
[reg
].tte
;
2583 case 0x5e: // D-MMU tag read
2585 int reg
= (addr
>> 3) & 0x3f;
2587 ret
= env
->dtlb
[reg
].tag
;
2590 case 0x46: // D-cache data
2591 case 0x47: // D-cache tag access
2592 case 0x4b: // E-cache error enable
2593 case 0x4c: // E-cache asynchronous fault status
2594 case 0x4d: // E-cache asynchronous fault address
2595 case 0x4e: // E-cache tag data
2596 case 0x66: // I-cache instruction access
2597 case 0x67: // I-cache tag access
2598 case 0x6e: // I-cache predecode
2599 case 0x6f: // I-cache LRU etc.
2600 case 0x76: // E-cache tag
2601 case 0x7e: // E-cache tag
2603 case 0x5b: // D-MMU data pointer
2604 case 0x48: // Interrupt dispatch, RO
2605 case 0x49: // Interrupt data receive
2606 case 0x7f: // Incoming interrupt vector, RO
2609 case 0x54: // I-MMU data in, WO
2610 case 0x57: // I-MMU demap, WO
2611 case 0x5c: // D-MMU data in, WO
2612 case 0x5f: // D-MMU demap, WO
2613 case 0x77: // Interrupt vector, WO
2615 do_unassigned_access(addr
, 0, 0, 1, size
);
2620 /* Convert from little endian */
2622 case 0x0c: // Nucleus Little Endian (LE)
2623 case 0x18: // As if user primary LE
2624 case 0x19: // As if user secondary LE
2625 case 0x1c: // Bypass LE
2626 case 0x1d: // Bypass, non-cacheable LE
2627 case 0x88: // Primary LE
2628 case 0x89: // Secondary LE
2629 case 0x8a: // Primary no-fault LE
2630 case 0x8b: // Secondary no-fault LE
2648 /* Convert to signed number */
2655 ret
= (int16_t) ret
;
2658 ret
= (int32_t) ret
;
2665 dump_asi("read ", last_addr
, asi
, size
, ret
);
2670 void helper_st_asi(target_ulong addr
, target_ulong val
, int asi
, int size
)
2673 dump_asi("write", addr
, asi
, size
, val
);
2678 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2679 || (cpu_has_hypervisor(env
)
2680 && asi
>= 0x30 && asi
< 0x80
2681 && !(env
->hpstate
& HS_PRIV
)))
2682 raise_exception(TT_PRIV_ACT
);
2684 helper_check_align(addr
, size
- 1);
2685 /* Convert to little endian */
2687 case 0x0c: // Nucleus Little Endian (LE)
2688 case 0x18: // As if user primary LE
2689 case 0x19: // As if user secondary LE
2690 case 0x1c: // Bypass LE
2691 case 0x1d: // Bypass, non-cacheable LE
2692 case 0x88: // Primary LE
2693 case 0x89: // Secondary LE
2712 case 0x10: // As if user primary
2713 case 0x11: // As if user secondary
2714 case 0x18: // As if user primary LE
2715 case 0x19: // As if user secondary LE
2716 case 0x80: // Primary
2717 case 0x81: // Secondary
2718 case 0x88: // Primary LE
2719 case 0x89: // Secondary LE
2720 case 0xe2: // UA2007 Primary block init
2721 case 0xe3: // UA2007 Secondary block init
2722 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
2723 if (cpu_hypervisor_mode(env
)) {
2726 stb_hypv(addr
, val
);
2729 stw_hypv(addr
, val
);
2732 stl_hypv(addr
, val
);
2736 stq_hypv(addr
, val
);
2740 /* secondary space access has lowest asi bit equal to 1 */
2744 stb_kernel_secondary(addr
, val
);
2747 stw_kernel_secondary(addr
, val
);
2750 stl_kernel_secondary(addr
, val
);
2754 stq_kernel_secondary(addr
, val
);
2760 stb_kernel(addr
, val
);
2763 stw_kernel(addr
, val
);
2766 stl_kernel(addr
, val
);
2770 stq_kernel(addr
, val
);
2776 /* secondary space access has lowest asi bit equal to 1 */
2780 stb_user_secondary(addr
, val
);
2783 stw_user_secondary(addr
, val
);
2786 stl_user_secondary(addr
, val
);
2790 stq_user_secondary(addr
, val
);
2796 stb_user(addr
, val
);
2799 stw_user(addr
, val
);
2802 stl_user(addr
, val
);
2806 stq_user(addr
, val
);
2812 case 0x14: // Bypass
2813 case 0x15: // Bypass, non-cacheable
2814 case 0x1c: // Bypass LE
2815 case 0x1d: // Bypass, non-cacheable LE
2819 stb_phys(addr
, val
);
2822 stw_phys(addr
, val
);
2825 stl_phys(addr
, val
);
2829 stq_phys(addr
, val
);
2834 case 0x24: // Nucleus quad LDD 128 bit atomic
2835 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2836 // Only ldda allowed
2837 raise_exception(TT_ILL_INSN
);
2839 case 0x04: // Nucleus
2840 case 0x0c: // Nucleus Little Endian (LE)
2844 stb_nucleus(addr
, val
);
2847 stw_nucleus(addr
, val
);
2850 stl_nucleus(addr
, val
);
2854 stq_nucleus(addr
, val
);
2860 case 0x4a: // UPA config
2868 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
2869 // Mappings generated during D/I MMU disabled mode are
2870 // invalid in normal mode
2871 if (oldreg
!= env
->lsu
) {
2872 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
2881 case 0x50: // I-MMU regs
2883 int reg
= (addr
>> 3) & 0xf;
2886 oldreg
= env
->immuregs
[reg
];
2890 case 1: // Not in I-MMU
2895 val
= 0; // Clear SFSR
2896 env
->immu
.sfsr
= val
;
2900 case 5: // TSB access
2901 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
2902 PRIx64
"\n", env
->immu
.tsb
, val
);
2903 env
->immu
.tsb
= val
;
2905 case 6: // Tag access
2906 env
->immu
.tag_access
= val
;
2915 if (oldreg
!= env
->immuregs
[reg
]) {
2916 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
2917 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
2924 case 0x54: // I-MMU data in
2925 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
2927 case 0x55: // I-MMU data access
2931 unsigned int i
= (addr
>> 3) & 0x3f;
2933 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
2936 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
2941 case 0x57: // I-MMU demap
2942 demap_tlb(env
->itlb
, addr
, "immu", env
);
2944 case 0x58: // D-MMU regs
2946 int reg
= (addr
>> 3) & 0xf;
2949 oldreg
= env
->dmmuregs
[reg
];
2955 if ((val
& 1) == 0) {
2956 val
= 0; // Clear SFSR, Fault address
2959 env
->dmmu
.sfsr
= val
;
2961 case 1: // Primary context
2962 env
->dmmu
.mmu_primary_context
= val
;
2963 /* can be optimized to only flush MMU_USER_IDX
2964 and MMU_KERNEL_IDX entries */
2967 case 2: // Secondary context
2968 env
->dmmu
.mmu_secondary_context
= val
;
2969 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
2970 and MMU_KERNEL_SECONDARY_IDX entries */
2973 case 5: // TSB access
2974 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
2975 PRIx64
"\n", env
->dmmu
.tsb
, val
);
2976 env
->dmmu
.tsb
= val
;
2978 case 6: // Tag access
2979 env
->dmmu
.tag_access
= val
;
2981 case 7: // Virtual Watchpoint
2982 case 8: // Physical Watchpoint
2984 env
->dmmuregs
[reg
] = val
;
2988 if (oldreg
!= env
->dmmuregs
[reg
]) {
2989 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
2990 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
2997 case 0x5c: // D-MMU data in
2998 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
3000 case 0x5d: // D-MMU data access
3002 unsigned int i
= (addr
>> 3) & 0x3f;
3004 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
3007 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
3012 case 0x5f: // D-MMU demap
3013 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
3015 case 0x49: // Interrupt data receive
3018 case 0x46: // D-cache data
3019 case 0x47: // D-cache tag access
3020 case 0x4b: // E-cache error enable
3021 case 0x4c: // E-cache asynchronous fault status
3022 case 0x4d: // E-cache asynchronous fault address
3023 case 0x4e: // E-cache tag data
3024 case 0x66: // I-cache instruction access
3025 case 0x67: // I-cache tag access
3026 case 0x6e: // I-cache predecode
3027 case 0x6f: // I-cache LRU etc.
3028 case 0x76: // E-cache tag
3029 case 0x7e: // E-cache tag
3031 case 0x51: // I-MMU 8k TSB pointer, RO
3032 case 0x52: // I-MMU 64k TSB pointer, RO
3033 case 0x56: // I-MMU tag read, RO
3034 case 0x59: // D-MMU 8k TSB pointer, RO
3035 case 0x5a: // D-MMU 64k TSB pointer, RO
3036 case 0x5b: // D-MMU data pointer, RO
3037 case 0x5e: // D-MMU tag read, RO
3038 case 0x48: // Interrupt dispatch, RO
3039 case 0x7f: // Incoming interrupt vector, RO
3040 case 0x82: // Primary no-fault, RO
3041 case 0x83: // Secondary no-fault, RO
3042 case 0x8a: // Primary no-fault LE, RO
3043 case 0x8b: // Secondary no-fault LE, RO
3045 do_unassigned_access(addr
, 1, 0, 1, size
);
3049 #endif /* CONFIG_USER_ONLY */
3051 void helper_ldda_asi(target_ulong addr
, int asi
, int rd
)
3053 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
3054 || (cpu_has_hypervisor(env
)
3055 && asi
>= 0x30 && asi
< 0x80
3056 && !(env
->hpstate
& HS_PRIV
)))
3057 raise_exception(TT_PRIV_ACT
);
3060 #if !defined(CONFIG_USER_ONLY)
3061 case 0x24: // Nucleus quad LDD 128 bit atomic
3062 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3063 helper_check_align(addr
, 0xf);
3065 env
->gregs
[1] = ldq_nucleus(addr
+ 8);
3067 bswap64s(&env
->gregs
[1]);
3068 } else if (rd
< 8) {
3069 env
->gregs
[rd
] = ldq_nucleus(addr
);
3070 env
->gregs
[rd
+ 1] = ldq_nucleus(addr
+ 8);
3072 bswap64s(&env
->gregs
[rd
]);
3073 bswap64s(&env
->gregs
[rd
+ 1]);
3076 env
->regwptr
[rd
] = ldq_nucleus(addr
);
3077 env
->regwptr
[rd
+ 1] = ldq_nucleus(addr
+ 8);
3079 bswap64s(&env
->regwptr
[rd
]);
3080 bswap64s(&env
->regwptr
[rd
+ 1]);
3086 helper_check_align(addr
, 0x3);
3088 env
->gregs
[1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3090 env
->gregs
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
3091 env
->gregs
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3093 env
->regwptr
[rd
] = helper_ld_asi(addr
, asi
, 4, 0);
3094 env
->regwptr
[rd
+ 1] = helper_ld_asi(addr
+ 4, asi
, 4, 0);
3100 void helper_ldf_asi(target_ulong addr
, int asi
, int size
, int rd
)
3105 helper_check_align(addr
, 3);
3107 case 0xf0: // Block load primary
3108 case 0xf1: // Block load secondary
3109 case 0xf8: // Block load primary LE
3110 case 0xf9: // Block load secondary LE
3112 raise_exception(TT_ILL_INSN
);
3115 helper_check_align(addr
, 0x3f);
3116 for (i
= 0; i
< 16; i
++) {
3117 *(uint32_t *)&env
->fpr
[rd
++] = helper_ld_asi(addr
, asi
& 0x8f, 4,
3127 val
= helper_ld_asi(addr
, asi
, size
, 0);
3131 *((uint32_t *)&env
->fpr
[rd
]) = val
;
3134 *((int64_t *)&DT0
) = val
;
3142 void helper_stf_asi(target_ulong addr
, int asi
, int size
, int rd
)
3145 target_ulong val
= 0;
3147 helper_check_align(addr
, 3);
3149 case 0xe0: // UA2007 Block commit store primary (cache flush)
3150 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3151 case 0xf0: // Block store primary
3152 case 0xf1: // Block store secondary
3153 case 0xf8: // Block store primary LE
3154 case 0xf9: // Block store secondary LE
3156 raise_exception(TT_ILL_INSN
);
3159 helper_check_align(addr
, 0x3f);
3160 for (i
= 0; i
< 16; i
++) {
3161 val
= *(uint32_t *)&env
->fpr
[rd
++];
3162 helper_st_asi(addr
, val
, asi
& 0x8f, 4);
3174 val
= *((uint32_t *)&env
->fpr
[rd
]);
3177 val
= *((int64_t *)&DT0
);
3183 helper_st_asi(addr
, val
, asi
, size
);
3186 target_ulong
helper_cas_asi(target_ulong addr
, target_ulong val1
,
3187 target_ulong val2
, uint32_t asi
)
3191 val2
&= 0xffffffffUL
;
3192 ret
= helper_ld_asi(addr
, asi
, 4, 0);
3193 ret
&= 0xffffffffUL
;
3195 helper_st_asi(addr
, val1
& 0xffffffffUL
, asi
, 4);
3199 target_ulong
helper_casx_asi(target_ulong addr
, target_ulong val1
,
3200 target_ulong val2
, uint32_t asi
)
3204 ret
= helper_ld_asi(addr
, asi
, 8, 0);
3206 helper_st_asi(addr
, val1
, asi
, 8);
3209 #endif /* TARGET_SPARC64 */
3211 #ifndef TARGET_SPARC64
3212 void helper_rett(void)
3216 if (env
->psret
== 1)
3217 raise_exception(TT_ILL_INSN
);
3220 cwp
= cwp_inc(env
->cwp
+ 1) ;
3221 if (env
->wim
& (1 << cwp
)) {
3222 raise_exception(TT_WIN_UNF
);
3225 env
->psrs
= env
->psrps
;
3229 target_ulong
helper_udiv(target_ulong a
, target_ulong b
)
3234 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3238 raise_exception(TT_DIV_ZERO
);
3242 if (x0
> 0xffffffff) {
3251 target_ulong
helper_sdiv(target_ulong a
, target_ulong b
)
3256 x0
= (a
& 0xffffffff) | ((int64_t) (env
->y
) << 32);
3260 raise_exception(TT_DIV_ZERO
);
3264 if ((int32_t) x0
!= x0
) {
3266 return x0
< 0? 0x80000000: 0x7fffffff;
3273 void helper_stdf(target_ulong addr
, int mem_idx
)
3275 helper_check_align(addr
, 7);
3276 #if !defined(CONFIG_USER_ONLY)
3279 stfq_user(addr
, DT0
);
3282 stfq_kernel(addr
, DT0
);
3284 #ifdef TARGET_SPARC64
3286 stfq_hypv(addr
, DT0
);
3293 stfq_raw(address_mask(env
, addr
), DT0
);
3297 void helper_lddf(target_ulong addr
, int mem_idx
)
3299 helper_check_align(addr
, 7);
3300 #if !defined(CONFIG_USER_ONLY)
3303 DT0
= ldfq_user(addr
);
3306 DT0
= ldfq_kernel(addr
);
3308 #ifdef TARGET_SPARC64
3310 DT0
= ldfq_hypv(addr
);
3317 DT0
= ldfq_raw(address_mask(env
, addr
));
3321 void helper_ldqf(target_ulong addr
, int mem_idx
)
3323 // XXX add 128 bit load
3326 helper_check_align(addr
, 7);
3327 #if !defined(CONFIG_USER_ONLY)
3330 u
.ll
.upper
= ldq_user(addr
);
3331 u
.ll
.lower
= ldq_user(addr
+ 8);
3335 u
.ll
.upper
= ldq_kernel(addr
);
3336 u
.ll
.lower
= ldq_kernel(addr
+ 8);
3339 #ifdef TARGET_SPARC64
3341 u
.ll
.upper
= ldq_hypv(addr
);
3342 u
.ll
.lower
= ldq_hypv(addr
+ 8);
3350 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
3351 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
3356 void helper_stqf(target_ulong addr
, int mem_idx
)
3358 // XXX add 128 bit store
3361 helper_check_align(addr
, 7);
3362 #if !defined(CONFIG_USER_ONLY)
3366 stq_user(addr
, u
.ll
.upper
);
3367 stq_user(addr
+ 8, u
.ll
.lower
);
3371 stq_kernel(addr
, u
.ll
.upper
);
3372 stq_kernel(addr
+ 8, u
.ll
.lower
);
3374 #ifdef TARGET_SPARC64
3377 stq_hypv(addr
, u
.ll
.upper
);
3378 stq_hypv(addr
+ 8, u
.ll
.lower
);
3386 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
3387 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
3391 static inline void set_fsr(void)
3395 switch (env
->fsr
& FSR_RD_MASK
) {
3396 case FSR_RD_NEAREST
:
3397 rnd_mode
= float_round_nearest_even
;
3401 rnd_mode
= float_round_to_zero
;
3404 rnd_mode
= float_round_up
;
3407 rnd_mode
= float_round_down
;
3410 set_float_rounding_mode(rnd_mode
, &env
->fp_status
);
3413 void helper_ldfsr(uint32_t new_fsr
)
3415 env
->fsr
= (new_fsr
& FSR_LDFSR_MASK
) | (env
->fsr
& FSR_LDFSR_OLDMASK
);
3419 #ifdef TARGET_SPARC64
3420 void helper_ldxfsr(uint64_t new_fsr
)
3422 env
->fsr
= (new_fsr
& FSR_LDXFSR_MASK
) | (env
->fsr
& FSR_LDXFSR_OLDMASK
);
3427 void helper_debug(void)
3429 env
->exception_index
= EXCP_DEBUG
;
3433 #ifndef TARGET_SPARC64
3434 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3436 void helper_save(void)
3440 cwp
= cwp_dec(env
->cwp
- 1);
3441 if (env
->wim
& (1 << cwp
)) {
3442 raise_exception(TT_WIN_OVF
);
3447 void helper_restore(void)
3451 cwp
= cwp_inc(env
->cwp
+ 1);
3452 if (env
->wim
& (1 << cwp
)) {
3453 raise_exception(TT_WIN_UNF
);
3458 void helper_wrpsr(target_ulong new_psr
)
3460 if ((new_psr
& PSR_CWP
) >= env
->nwindows
) {
3461 raise_exception(TT_ILL_INSN
);
3463 cpu_put_psr(env
, new_psr
);
3467 target_ulong
helper_rdpsr(void)
3473 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3475 void helper_save(void)
3479 cwp
= cwp_dec(env
->cwp
- 1);
3480 if (env
->cansave
== 0) {
3481 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3482 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3483 ((env
->wstate
& 0x7) << 2)));
3485 if (env
->cleanwin
- env
->canrestore
== 0) {
3486 // XXX Clean windows without trap
3487 raise_exception(TT_CLRWIN
);
3496 void helper_restore(void)
3500 cwp
= cwp_inc(env
->cwp
+ 1);
3501 if (env
->canrestore
== 0) {
3502 raise_exception(TT_FILL
| (env
->otherwin
!= 0 ?
3503 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3504 ((env
->wstate
& 0x7) << 2)));
3512 void helper_flushw(void)
3514 if (env
->cansave
!= env
->nwindows
- 2) {
3515 raise_exception(TT_SPILL
| (env
->otherwin
!= 0 ?
3516 (TT_WOTHER
| ((env
->wstate
& 0x38) >> 1)):
3517 ((env
->wstate
& 0x7) << 2)));
3521 void helper_saved(void)
3524 if (env
->otherwin
== 0)
3530 void helper_restored(void)
3533 if (env
->cleanwin
< env
->nwindows
- 1)
3535 if (env
->otherwin
== 0)
3541 static target_ulong
get_ccr(void)
3547 return ((env
->xcc
>> 20) << 4) | ((psr
& PSR_ICC
) >> 20);
3550 target_ulong
cpu_get_ccr(CPUState
*env1
)
3552 CPUState
*saved_env
;
3562 static void put_ccr(target_ulong val
)
3564 target_ulong tmp
= val
;
3566 env
->xcc
= (tmp
>> 4) << 20;
3567 env
->psr
= (tmp
& 0xf) << 20;
3568 CC_OP
= CC_OP_FLAGS
;
3571 void cpu_put_ccr(CPUState
*env1
, target_ulong val
)
3573 CPUState
*saved_env
;
3581 static target_ulong
get_cwp64(void)
3583 return env
->nwindows
- 1 - env
->cwp
;
3586 target_ulong
cpu_get_cwp64(CPUState
*env1
)
3588 CPUState
*saved_env
;
3598 static void put_cwp64(int cwp
)
3600 if (unlikely(cwp
>= env
->nwindows
|| cwp
< 0)) {
3601 cwp
%= env
->nwindows
;
3603 set_cwp(env
->nwindows
- 1 - cwp
);
3606 void cpu_put_cwp64(CPUState
*env1
, int cwp
)
3608 CPUState
*saved_env
;
3616 target_ulong
helper_rdccr(void)
3621 void helper_wrccr(target_ulong new_ccr
)
3626 // CWP handling is reversed in V9, but we still use the V8 register
3628 target_ulong
helper_rdcwp(void)
3633 void helper_wrcwp(target_ulong new_cwp
)
3638 // This function uses non-native bit order
3639 #define GET_FIELD(X, FROM, TO) \
3640 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3642 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3643 #define GET_FIELD_SP(X, FROM, TO) \
3644 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3646 target_ulong
helper_array8(target_ulong pixel_addr
, target_ulong cubesize
)
3648 return (GET_FIELD_SP(pixel_addr
, 60, 63) << (17 + 2 * cubesize
)) |
3649 (GET_FIELD_SP(pixel_addr
, 39, 39 + cubesize
- 1) << (17 + cubesize
)) |
3650 (GET_FIELD_SP(pixel_addr
, 17 + cubesize
- 1, 17) << 17) |
3651 (GET_FIELD_SP(pixel_addr
, 56, 59) << 13) |
3652 (GET_FIELD_SP(pixel_addr
, 35, 38) << 9) |
3653 (GET_FIELD_SP(pixel_addr
, 13, 16) << 5) |
3654 (((pixel_addr
>> 55) & 1) << 4) |
3655 (GET_FIELD_SP(pixel_addr
, 33, 34) << 2) |
3656 GET_FIELD_SP(pixel_addr
, 11, 12);
3659 target_ulong
helper_alignaddr(target_ulong addr
, target_ulong offset
)
3663 tmp
= addr
+ offset
;
3665 env
->gsr
|= tmp
& 7ULL;
3669 target_ulong
helper_popc(target_ulong val
)
3671 return ctpop64(val
);
3674 static inline uint64_t *get_gregset(uint32_t pstate
)
3678 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3680 (pstate
& PS_IG
) ? " IG" : "",
3681 (pstate
& PS_MG
) ? " MG" : "",
3682 (pstate
& PS_AG
) ? " AG" : "");
3683 /* pass through to normal set of global registers */
3695 static inline void change_pstate(uint32_t new_pstate
)
3697 uint32_t pstate_regs
, new_pstate_regs
;
3698 uint64_t *src
, *dst
;
3700 if (env
->def
->features
& CPU_FEATURE_GL
) {
3701 // PS_AG is not implemented in this case
3702 new_pstate
&= ~PS_AG
;
3705 pstate_regs
= env
->pstate
& 0xc01;
3706 new_pstate_regs
= new_pstate
& 0xc01;
3708 if (new_pstate_regs
!= pstate_regs
) {
3709 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
3710 pstate_regs
, new_pstate_regs
);
3711 // Switch global register bank
3712 src
= get_gregset(new_pstate_regs
);
3713 dst
= get_gregset(pstate_regs
);
3714 memcpy32(dst
, env
->gregs
);
3715 memcpy32(env
->gregs
, src
);
3718 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
3721 env
->pstate
= new_pstate
;
3724 void helper_wrpstate(target_ulong new_state
)
3726 change_pstate(new_state
& 0xf3f);
3728 #if !defined(CONFIG_USER_ONLY)
3729 if (cpu_interrupts_enabled(env
)) {
3730 cpu_check_irqs(env
);
3735 void helper_wrpil(target_ulong new_pil
)
3737 #if !defined(CONFIG_USER_ONLY)
3738 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
3739 env
->psrpil
, (uint32_t)new_pil
);
3741 env
->psrpil
= new_pil
;
3743 if (cpu_interrupts_enabled(env
)) {
3744 cpu_check_irqs(env
);
3749 void helper_done(void)
3751 trap_state
* tsptr
= cpu_tsptr(env
);
3753 env
->pc
= tsptr
->tnpc
;
3754 env
->npc
= tsptr
->tnpc
+ 4;
3755 put_ccr(tsptr
->tstate
>> 32);
3756 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
3757 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
3758 put_cwp64(tsptr
->tstate
& 0xff);
3761 DPRINTF_PSTATE("... helper_done tl=%d\n", env
->tl
);
3763 #if !defined(CONFIG_USER_ONLY)
3764 if (cpu_interrupts_enabled(env
)) {
3765 cpu_check_irqs(env
);
3770 void helper_retry(void)
3772 trap_state
* tsptr
= cpu_tsptr(env
);
3774 env
->pc
= tsptr
->tpc
;
3775 env
->npc
= tsptr
->tnpc
;
3776 put_ccr(tsptr
->tstate
>> 32);
3777 env
->asi
= (tsptr
->tstate
>> 24) & 0xff;
3778 change_pstate((tsptr
->tstate
>> 8) & 0xf3f);
3779 put_cwp64(tsptr
->tstate
& 0xff);
3782 DPRINTF_PSTATE("... helper_retry tl=%d\n", env
->tl
);
3784 #if !defined(CONFIG_USER_ONLY)
3785 if (cpu_interrupts_enabled(env
)) {
3786 cpu_check_irqs(env
);
3791 static void do_modify_softint(const char* operation
, uint32_t value
)
3793 if (env
->softint
!= value
) {
3794 env
->softint
= value
;
3795 DPRINTF_PSTATE(": %s new %08x\n", operation
, env
->softint
);
3796 #if !defined(CONFIG_USER_ONLY)
3797 if (cpu_interrupts_enabled(env
)) {
3798 cpu_check_irqs(env
);
3804 void helper_set_softint(uint64_t value
)
3806 do_modify_softint("helper_set_softint", env
->softint
| (uint32_t)value
);
3809 void helper_clear_softint(uint64_t value
)
3811 do_modify_softint("helper_clear_softint", env
->softint
& (uint32_t)~value
);
3814 void helper_write_softint(uint64_t value
)
3816 do_modify_softint("helper_write_softint", (uint32_t)value
);
3820 void helper_flush(target_ulong addr
)
3823 tb_invalidate_page_range(addr
, addr
+ 8);
3826 #ifdef TARGET_SPARC64
3828 static const char * const excp_names
[0x80] = {
3829 [TT_TFAULT
] = "Instruction Access Fault",
3830 [TT_TMISS
] = "Instruction Access MMU Miss",
3831 [TT_CODE_ACCESS
] = "Instruction Access Error",
3832 [TT_ILL_INSN
] = "Illegal Instruction",
3833 [TT_PRIV_INSN
] = "Privileged Instruction",
3834 [TT_NFPU_INSN
] = "FPU Disabled",
3835 [TT_FP_EXCP
] = "FPU Exception",
3836 [TT_TOVF
] = "Tag Overflow",
3837 [TT_CLRWIN
] = "Clean Windows",
3838 [TT_DIV_ZERO
] = "Division By Zero",
3839 [TT_DFAULT
] = "Data Access Fault",
3840 [TT_DMISS
] = "Data Access MMU Miss",
3841 [TT_DATA_ACCESS
] = "Data Access Error",
3842 [TT_DPROT
] = "Data Protection Error",
3843 [TT_UNALIGNED
] = "Unaligned Memory Access",
3844 [TT_PRIV_ACT
] = "Privileged Action",
3845 [TT_EXTINT
| 0x1] = "External Interrupt 1",
3846 [TT_EXTINT
| 0x2] = "External Interrupt 2",
3847 [TT_EXTINT
| 0x3] = "External Interrupt 3",
3848 [TT_EXTINT
| 0x4] = "External Interrupt 4",
3849 [TT_EXTINT
| 0x5] = "External Interrupt 5",
3850 [TT_EXTINT
| 0x6] = "External Interrupt 6",
3851 [TT_EXTINT
| 0x7] = "External Interrupt 7",
3852 [TT_EXTINT
| 0x8] = "External Interrupt 8",
3853 [TT_EXTINT
| 0x9] = "External Interrupt 9",
3854 [TT_EXTINT
| 0xa] = "External Interrupt 10",
3855 [TT_EXTINT
| 0xb] = "External Interrupt 11",
3856 [TT_EXTINT
| 0xc] = "External Interrupt 12",
3857 [TT_EXTINT
| 0xd] = "External Interrupt 13",
3858 [TT_EXTINT
| 0xe] = "External Interrupt 14",
3859 [TT_EXTINT
| 0xf] = "External Interrupt 15",
3863 trap_state
* cpu_tsptr(CPUState
* env
)
3865 return &env
->ts
[env
->tl
& MAXTL_MASK
];
3868 void do_interrupt(CPUState
*env
)
3870 int intno
= env
->exception_index
;
3874 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
3878 if (intno
< 0 || intno
>= 0x180)
3880 else if (intno
>= 0x100)
3881 name
= "Trap Instruction";
3882 else if (intno
>= 0xc0)
3883 name
= "Window Fill";
3884 else if (intno
>= 0x80)
3885 name
= "Window Spill";
3887 name
= excp_names
[intno
];
3892 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64
" npc=%016" PRIx64
3893 " SP=%016" PRIx64
"\n",
3896 env
->npc
, env
->regwptr
[6]);
3897 log_cpu_state(env
, 0);
3904 ptr
= (uint8_t *)env
->pc
;
3905 for(i
= 0; i
< 16; i
++) {
3906 qemu_log(" %02x", ldub(ptr
+ i
));
3914 #if !defined(CONFIG_USER_ONLY)
3915 if (env
->tl
>= env
->maxtl
) {
3916 cpu_abort(env
, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
3917 " Error state", env
->exception_index
, env
->tl
, env
->maxtl
);
3921 if (env
->tl
< env
->maxtl
- 1) {
3924 env
->pstate
|= PS_RED
;
3925 if (env
->tl
< env
->maxtl
)
3928 tsptr
= cpu_tsptr(env
);
3930 tsptr
->tstate
= (get_ccr() << 32) |
3931 ((env
->asi
& 0xff) << 24) | ((env
->pstate
& 0xf3f) << 8) |
3933 tsptr
->tpc
= env
->pc
;
3934 tsptr
->tnpc
= env
->npc
;
3939 change_pstate(PS_PEF
| PS_PRIV
| PS_IG
);
3943 case TT_TMISS
... TT_TMISS
+ 3:
3944 case TT_DMISS
... TT_DMISS
+ 3:
3945 case TT_DPROT
... TT_DPROT
+ 3:
3946 change_pstate(PS_PEF
| PS_PRIV
| PS_MG
);
3949 change_pstate(PS_PEF
| PS_PRIV
| PS_AG
);
3953 if (intno
== TT_CLRWIN
) {
3954 set_cwp(cwp_dec(env
->cwp
- 1));
3955 } else if ((intno
& 0x1c0) == TT_SPILL
) {
3956 set_cwp(cwp_dec(env
->cwp
- env
->cansave
- 2));
3957 } else if ((intno
& 0x1c0) == TT_FILL
) {
3958 set_cwp(cwp_inc(env
->cwp
+ 1));
3960 env
->tbr
&= ~0x7fffULL
;
3961 env
->tbr
|= ((env
->tl
> 1) ? 1 << 14 : 0) | (intno
<< 5);
3963 env
->npc
= env
->pc
+ 4;
3964 env
->exception_index
= -1;
3968 static const char * const excp_names
[0x80] = {
3969 [TT_TFAULT
] = "Instruction Access Fault",
3970 [TT_ILL_INSN
] = "Illegal Instruction",
3971 [TT_PRIV_INSN
] = "Privileged Instruction",
3972 [TT_NFPU_INSN
] = "FPU Disabled",
3973 [TT_WIN_OVF
] = "Window Overflow",
3974 [TT_WIN_UNF
] = "Window Underflow",
3975 [TT_UNALIGNED
] = "Unaligned Memory Access",
3976 [TT_FP_EXCP
] = "FPU Exception",
3977 [TT_DFAULT
] = "Data Access Fault",
3978 [TT_TOVF
] = "Tag Overflow",
3979 [TT_EXTINT
| 0x1] = "External Interrupt 1",
3980 [TT_EXTINT
| 0x2] = "External Interrupt 2",
3981 [TT_EXTINT
| 0x3] = "External Interrupt 3",
3982 [TT_EXTINT
| 0x4] = "External Interrupt 4",
3983 [TT_EXTINT
| 0x5] = "External Interrupt 5",
3984 [TT_EXTINT
| 0x6] = "External Interrupt 6",
3985 [TT_EXTINT
| 0x7] = "External Interrupt 7",
3986 [TT_EXTINT
| 0x8] = "External Interrupt 8",
3987 [TT_EXTINT
| 0x9] = "External Interrupt 9",
3988 [TT_EXTINT
| 0xa] = "External Interrupt 10",
3989 [TT_EXTINT
| 0xb] = "External Interrupt 11",
3990 [TT_EXTINT
| 0xc] = "External Interrupt 12",
3991 [TT_EXTINT
| 0xd] = "External Interrupt 13",
3992 [TT_EXTINT
| 0xe] = "External Interrupt 14",
3993 [TT_EXTINT
| 0xf] = "External Interrupt 15",
3994 [TT_TOVF
] = "Tag Overflow",
3995 [TT_CODE_ACCESS
] = "Instruction Access Error",
3996 [TT_DATA_ACCESS
] = "Data Access Error",
3997 [TT_DIV_ZERO
] = "Division By Zero",
3998 [TT_NCP_INSN
] = "Coprocessor Disabled",
4002 void do_interrupt(CPUState
*env
)
4004 int cwp
, intno
= env
->exception_index
;
4007 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
4011 if (intno
< 0 || intno
>= 0x100)
4013 else if (intno
>= 0x80)
4014 name
= "Trap Instruction";
4016 name
= excp_names
[intno
];
4021 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
4024 env
->npc
, env
->regwptr
[6]);
4025 log_cpu_state(env
, 0);
4032 ptr
= (uint8_t *)env
->pc
;
4033 for(i
= 0; i
< 16; i
++) {
4034 qemu_log(" %02x", ldub(ptr
+ i
));
4042 #if !defined(CONFIG_USER_ONLY)
4043 if (env
->psret
== 0) {
4044 cpu_abort(env
, "Trap 0x%02x while interrupts disabled, Error state",
4045 env
->exception_index
);
4050 cwp
= cwp_dec(env
->cwp
- 1);
4052 env
->regwptr
[9] = env
->pc
;
4053 env
->regwptr
[10] = env
->npc
;
4054 env
->psrps
= env
->psrs
;
4056 env
->tbr
= (env
->tbr
& TBR_BASE_MASK
) | (intno
<< 4);
4058 env
->npc
= env
->pc
+ 4;
4059 env
->exception_index
= -1;
4063 #if !defined(CONFIG_USER_ONLY)
4065 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
4068 #define MMUSUFFIX _mmu
4069 #define ALIGNED_ONLY
4072 #include "softmmu_template.h"
4075 #include "softmmu_template.h"
4078 #include "softmmu_template.h"
4081 #include "softmmu_template.h"
4083 /* XXX: make it generic ? */
4084 static void cpu_restore_state2(void *retaddr
)
4086 TranslationBlock
*tb
;
4090 /* now we have a real cpu fault */
4091 pc
= (unsigned long)retaddr
;
4092 tb
= tb_find_pc(pc
);
4094 /* the PC is inside the translated code. It means that we have
4095 a virtual CPU fault */
4096 cpu_restore_state(tb
, env
, pc
, (void *)(long)env
->cond
);
4101 static void do_unaligned_access(target_ulong addr
, int is_write
, int is_user
,
4104 #ifdef DEBUG_UNALIGNED
4105 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
4106 "\n", addr
, env
->pc
);
4108 cpu_restore_state2(retaddr
);
4109 raise_exception(TT_UNALIGNED
);
4112 /* try to fill the TLB and return an exception if error. If retaddr is
4113 NULL, it means that the function was called in C code (i.e. not
4114 from generated code or from helper.c) */
4115 /* XXX: fix it to restore all registers */
4116 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
4119 CPUState
*saved_env
;
4121 /* XXX: hack to restore env in all cases, even if not called from
4124 env
= cpu_single_env
;
4126 ret
= cpu_sparc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
4128 cpu_restore_state2(retaddr
);
4134 #endif /* !CONFIG_USER_ONLY */
4136 #ifndef TARGET_SPARC64
4137 #if !defined(CONFIG_USER_ONLY)
4138 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
4139 int is_asi
, int size
)
4141 CPUState
*saved_env
;
4144 /* XXX: hack to restore env in all cases, even if not called from
4147 env
= cpu_single_env
;
4148 #ifdef DEBUG_UNASSIGNED
4150 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4151 " asi 0x%02x from " TARGET_FMT_lx
"\n",
4152 is_exec
? "exec" : is_write
? "write" : "read", size
,
4153 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
4155 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4156 " from " TARGET_FMT_lx
"\n",
4157 is_exec
? "exec" : is_write
? "write" : "read", size
,
4158 size
== 1 ? "" : "s", addr
, env
->pc
);
4160 /* Don't overwrite translation and access faults */
4161 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
4162 if ((fault_type
> 4) || (fault_type
== 0)) {
4163 env
->mmuregs
[3] = 0; /* Fault status register */
4165 env
->mmuregs
[3] |= 1 << 16;
4167 env
->mmuregs
[3] |= 1 << 5;
4169 env
->mmuregs
[3] |= 1 << 6;
4171 env
->mmuregs
[3] |= 1 << 7;
4172 env
->mmuregs
[3] |= (5 << 2) | 2;
4173 /* SuperSPARC will never place instruction fault addresses in the FAR */
4175 env
->mmuregs
[4] = addr
; /* Fault address register */
4178 /* overflow (same type fault was not read before another fault) */
4179 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
4180 env
->mmuregs
[3] |= 1;
4183 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
4185 raise_exception(TT_CODE_ACCESS
);
4187 raise_exception(TT_DATA_ACCESS
);
4190 /* flush neverland mappings created during no-fault mode,
4191 so the sequential MMU faults report proper fault types */
4192 if (env
->mmuregs
[0] & MMU_NF
) {
4200 #if defined(CONFIG_USER_ONLY)
4201 static void do_unassigned_access(target_ulong addr
, int is_write
, int is_exec
,
4202 int is_asi
, int size
)
4204 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
4205 int is_asi
, int size
)
4208 CPUState
*saved_env
;
4210 /* XXX: hack to restore env in all cases, even if not called from
4213 env
= cpu_single_env
;
4215 #ifdef DEBUG_UNASSIGNED
4216 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
4217 "\n", addr
, env
->pc
);
4221 raise_exception(TT_CODE_ACCESS
);
4223 raise_exception(TT_DATA_ACCESS
);
4230 #ifdef TARGET_SPARC64
4231 void helper_tick_set_count(void *opaque
, uint64_t count
)
4233 #if !defined(CONFIG_USER_ONLY)
4234 cpu_tick_set_count(opaque
, count
);
4238 uint64_t helper_tick_get_count(void *opaque
)
4240 #if !defined(CONFIG_USER_ONLY)
4241 return cpu_tick_get_count(opaque
);
4247 void helper_tick_set_limit(void *opaque
, uint64_t limit
)
4249 #if !defined(CONFIG_USER_ONLY)
4250 cpu_tick_set_limit(opaque
, limit
);