hw/rc4030.c

   1 /*
   2  * QEMU JAZZ RC4030 chipset
   3  *
   4  * Copyright (c) 2007-2009 Herve Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "qemu-timer.h"
  28
  29 /********************************************************/
  30 /* debug rc4030 */
  31
  32 //#define DEBUG_RC4030
  33 //#define DEBUG_RC4030_DMA
  34
  35 #ifdef DEBUG_RC4030
  36 #define DPRINTF(fmt, ...) \
  37 do { printf("rc4030: " fmt , ## __VA_ARGS__); } while (0)
  38 static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
  39             "network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
  40 #else
  41 #define DPRINTF(fmt, ...)
  42 #endif
  43
  44 #define RC4030_ERROR(fmt, ...) \
  45 do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  46
  47 /********************************************************/
  48 /* rc4030 emulation                                     */
  49
  50 typedef struct dma_pagetable_entry {
  51     int32_t frame;
  52     int32_t owner;
  53 } __attribute__((packed)) dma_pagetable_entry;
  54
  55 #define DMA_PAGESIZE    4096
  56 #define DMA_REG_ENABLE  1
  57 #define DMA_REG_COUNT   2
  58 #define DMA_REG_ADDRESS 3
  59
  60 #define DMA_FLAG_ENABLE     0x0001
  61 #define DMA_FLAG_MEM_TO_DEV 0x0002
  62 #define DMA_FLAG_TC_INTR    0x0100
  63 #define DMA_FLAG_MEM_INTR   0x0200
  64 #define DMA_FLAG_ADDR_INTR  0x0400
  65
  66 typedef struct rc4030State
  67 {
  68     uint32_t config; /* 0x0000: RC4030 config register */
  69     uint32_t revision; /* 0x0008: RC4030 Revision register */
  70     uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
  71
  72     /* DMA */
  73     uint32_t dma_regs[8][4];
  74     uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
  75     uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
  76
  77     /* cache */
  78     uint32_t cache_maint; /* 0x0030: Cache Maintenance */
  79     uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
  80     uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
  81     uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
  82     uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
  83     uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
  84
  85     uint32_t nmi_interrupt; /* 0x0200: interrupt source */
  86     uint32_t offset210;
  87     uint32_t nvram_protect; /* 0x0220: NV ram protect register */
  88     uint32_t rem_speed[16];
  89     uint32_t imr_jazz; /* Local bus int enable mask */
  90     uint32_t isr_jazz; /* Local bus int source */
  91
  92     /* timer */
  93     QEMUTimer *periodic_timer;
  94     uint32_t itr; /* Interval timer reload */
  95
  96     qemu_irq timer_irq;
  97     qemu_irq jazz_bus_irq;
  98 } rc4030State;
  99
 100 static void set_next_tick(rc4030State *s)
 101 {
 102     qemu_irq_lower(s->timer_irq);
 103     uint32_t tm_hz;
 104
 105     tm_hz = 1000 / (s->itr + 1);
 106
 107     qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + ticks_per_sec / tm_hz);
 108 }
 109
 110 /* called for accesses to rc4030 */
 111 static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
 112 {
 113     rc4030State *s = opaque;
 114     uint32_t val;
 115
 116     addr &= 0x3fff;
 117     switch (addr & ~0x3) {
 118     /* Global config register */
 119     case 0x0000:
 120         val = s->config;
 121         break;
 122     /* Revision register */
 123     case 0x0008:
 124         val = s->revision;
 125         break;
 126     /* Invalid Address register */
 127     case 0x0010:
 128         val = s->invalid_address_register;
 129         break;
 130     /* DMA transl. table base */
 131     case 0x0018:
 132         val = s->dma_tl_base;
 133         break;
 134     /* DMA transl. table limit */
 135     case 0x0020:
 136         val = s->dma_tl_limit;
 137         break;
 138     /* Remote Failed Address */
 139     case 0x0038:
 140         val = s->remote_failed_address;
 141         break;
 142     /* Memory Failed Address */
 143     case 0x0040:
 144         val = s->memory_failed_address;
 145         break;
 146     /* I/O Cache Byte Mask */
 147     case 0x0058:
 148         val = s->cache_bmask;
 149         /* HACK */
 150         if (s->cache_bmask == (uint32_t)-1)
 151             s->cache_bmask = 0;
 152         break;
 153     /* Remote Speed Registers */
 154     case 0x0070:
 155     case 0x0078:
 156     case 0x0080:
 157     case 0x0088:
 158     case 0x0090:
 159     case 0x0098:
 160     case 0x00a0:
 161     case 0x00a8:
 162     case 0x00b0:
 163     case 0x00b8:
 164     case 0x00c0:
 165     case 0x00c8:
 166     case 0x00d0:
 167     case 0x00d8:
 168     case 0x00e0:
 169     case 0x00e8:
 170         val = s->rem_speed[(addr - 0x0070) >> 3];
 171         break;
 172     /* DMA channel base address */
 173     case 0x0100:
 174     case 0x0108:
 175     case 0x0110:
 176     case 0x0118:
 177     case 0x0120:
 178     case 0x0128:
 179     case 0x0130:
 180     case 0x0138:
 181     case 0x0140:
 182     case 0x0148:
 183     case 0x0150:
 184     case 0x0158:
 185     case 0x0160:
 186     case 0x0168:
 187     case 0x0170:
 188     case 0x0178:
 189     case 0x0180:
 190     case 0x0188:
 191     case 0x0190:
 192     case 0x0198:
 193     case 0x01a0:
 194     case 0x01a8:
 195     case 0x01b0:
 196     case 0x01b8:
 197     case 0x01c0:
 198     case 0x01c8:
 199     case 0x01d0:
 200     case 0x01d8:
 201     case 0x01e0:
 202     case 0x01e8:
 203     case 0x01f0:
 204     case 0x01f8:
 205         {
 206             int entry = (addr - 0x0100) >> 5;
 207             int idx = (addr & 0x1f) >> 3;
 208             val = s->dma_regs[entry][idx];
 209         }
 210         break;
 211     /* Interrupt source */
 212     case 0x0200:
 213         val = s->nmi_interrupt;
 214         break;
 215     /* Error type */
 216     case 0x0208:
 217         val = 0;
 218         break;
 219     /* Offset 0x0210 */
 220     case 0x0210:
 221         val = s->offset210;
 222         break;
 223     /* NV ram protect register */
 224     case 0x0220:
 225         val = s->nvram_protect;
 226         break;
 227     /* Interval timer count */
 228     case 0x0230:
 229         val = 0;
 230         qemu_irq_lower(s->timer_irq);
 231         break;
 232     /* EISA interrupt */
 233     case 0x0238:
 234         val = 7; /* FIXME: should be read from EISA controller */
 235         break;
 236     default:
 237         RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr);
 238         val = 0;
 239         break;
 240     }
 241
 242     if ((addr & ~3) != 0x230)
 243         DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr);
 244
 245     return val;
 246 }
 247
 248 static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
 249 {
 250     uint32_t v = rc4030_readl(opaque, addr & ~0x3);
 251     if (addr & 0x2)
 252         return v >> 16;
 253     else
 254         return v & 0xffff;
 255 }
 256
 257 static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
 258 {
 259     uint32_t v = rc4030_readl(opaque, addr & ~0x3);
 260     return (v >> (8 * (addr & 0x3))) & 0xff;
 261 }
 262
 263 static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 264 {
 265     rc4030State *s = opaque;
 266     addr &= 0x3fff;
 267
 268     DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr);
 269
 270     switch (addr & ~0x3) {
 271     /* Global config register */
 272     case 0x0000:
 273         s->config = val;
 274         break;
 275     /* DMA transl. table base */
 276     case 0x0018:
 277         s->dma_tl_base = val;
 278         break;
 279     /* DMA transl. table limit */
 280     case 0x0020:
 281         s->dma_tl_limit = val;
 282         break;
 283     /* DMA transl. table invalidated */
 284     case 0x0028:
 285         break;
 286     /* Cache Maintenance */
 287     case 0x0030:
 288         s->cache_maint = val;
 289         break;
 290     /* I/O Cache Physical Tag */
 291     case 0x0048:
 292         s->cache_ptag = val;
 293         break;
 294     /* I/O Cache Logical Tag */
 295     case 0x0050:
 296         s->cache_ltag = val;
 297         break;
 298     /* I/O Cache Byte Mask */
 299     case 0x0058:
 300         s->cache_bmask |= val; /* HACK */
 301         break;
 302     /* I/O Cache Buffer Window */
 303     case 0x0060:
 304         /* HACK */
 305         if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
 306             target_phys_addr_t dest = s->cache_ptag & ~0x1;
 307             dest += (s->cache_maint & 0x3) << 3;
 308             cpu_physical_memory_rw(dest, (uint8_t*)&val, 4, 1);
 309         }
 310         break;
 311     /* Remote Speed Registers */
 312     case 0x0070:
 313     case 0x0078:
 314     case 0x0080:
 315     case 0x0088:
 316     case 0x0090:
 317     case 0x0098:
 318     case 0x00a0:
 319     case 0x00a8:
 320     case 0x00b0:
 321     case 0x00b8:
 322     case 0x00c0:
 323     case 0x00c8:
 324     case 0x00d0:
 325     case 0x00d8:
 326     case 0x00e0:
 327     case 0x00e8:
 328         s->rem_speed[(addr - 0x0070) >> 3] = val;
 329         break;
 330     /* DMA channel base address */
 331     case 0x0100:
 332     case 0x0108:
 333     case 0x0110:
 334     case 0x0118:
 335     case 0x0120:
 336     case 0x0128:
 337     case 0x0130:
 338     case 0x0138:
 339     case 0x0140:
 340     case 0x0148:
 341     case 0x0150:
 342     case 0x0158:
 343     case 0x0160:
 344     case 0x0168:
 345     case 0x0170:
 346     case 0x0178:
 347     case 0x0180:
 348     case 0x0188:
 349     case 0x0190:
 350     case 0x0198:
 351     case 0x01a0:
 352     case 0x01a8:
 353     case 0x01b0:
 354     case 0x01b8:
 355     case 0x01c0:
 356     case 0x01c8:
 357     case 0x01d0:
 358     case 0x01d8:
 359     case 0x01e0:
 360     case 0x01e8:
 361     case 0x01f0:
 362     case 0x01f8:
 363         {
 364             int entry = (addr - 0x0100) >> 5;
 365             int idx = (addr & 0x1f) >> 3;
 366             s->dma_regs[entry][idx] = val;
 367         }
 368         break;
 369     /* Offset 0x0210 */
 370     case 0x0210:
 371         s->offset210 = val;
 372         break;
 373     /* Interval timer reload */
 374     case 0x0228:
 375         s->itr = val;
 376         qemu_irq_lower(s->timer_irq);
 377         set_next_tick(s);
 378         break;
 379     /* EISA interrupt */
 380     case 0x0238:
 381         break;
 382     default:
 383         RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr);
 384         break;
 385     }
 386 }
 387
 388 static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 389 {
 390     uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
 391
 392     if (addr & 0x2)
 393         val = (val << 16) | (old_val & 0x0000ffff);
 394     else
 395         val = val | (old_val & 0xffff0000);
 396     rc4030_writel(opaque, addr & ~0x3, val);
 397 }
 398
 399 static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 400 {
 401     uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
 402
 403     switch (addr & 3) {
 404     case 0:
 405         val = val | (old_val & 0xffffff00);
 406         break;
 407     case 1:
 408         val = (val << 8) | (old_val & 0xffff00ff);
 409         break;
 410     case 2:
 411         val = (val << 16) | (old_val & 0xff00ffff);
 412         break;
 413     case 3:
 414         val = (val << 24) | (old_val & 0x00ffffff);
 415         break;
 416     }
 417     rc4030_writel(opaque, addr & ~0x3, val);
 418 }
 419
 420 static CPUReadMemoryFunc * const rc4030_read[3] = {
 421     rc4030_readb,
 422     rc4030_readw,
 423     rc4030_readl,
 424 };
 425
 426 static CPUWriteMemoryFunc * const rc4030_write[3] = {
 427     rc4030_writeb,
 428     rc4030_writew,
 429     rc4030_writel,
 430 };
 431
 432 static void update_jazz_irq(rc4030State *s)
 433 {
 434     uint16_t pending;
 435
 436     pending = s->isr_jazz & s->imr_jazz;
 437
 438 #ifdef DEBUG_RC4030
 439     if (s->isr_jazz != 0) {
 440         uint32_t irq = 0;
 441         DPRINTF("pending irqs:");
 442         for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) {
 443             if (s->isr_jazz & (1 << irq)) {
 444                 printf(" %s", irq_names[irq]);
 445                 if (!(s->imr_jazz & (1 << irq))) {
 446                     printf("(ignored)");
 447                 }
 448             }
 449         }
 450         printf("\n");
 451     }
 452 #endif
 453
 454     if (pending != 0)
 455         qemu_irq_raise(s->jazz_bus_irq);
 456     else
 457         qemu_irq_lower(s->jazz_bus_irq);
 458 }
 459
 460 static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
 461 {
 462     rc4030State *s = opaque;
 463
 464     if (level) {
 465         s->isr_jazz |= 1 << irq;
 466     } else {
 467         s->isr_jazz &= ~(1 << irq);
 468     }
 469
 470     update_jazz_irq(s);
 471 }
 472
 473 static void rc4030_periodic_timer(void *opaque)
 474 {
 475     rc4030State *s = opaque;
 476
 477     set_next_tick(s);
 478     qemu_irq_raise(s->timer_irq);
 479 }
 480
 481 static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
 482 {
 483     rc4030State *s = opaque;
 484     uint32_t val;
 485     uint32_t irq;
 486     addr &= 0xfff;
 487
 488     switch (addr) {
 489     /* Local bus int source */
 490     case 0x00: {
 491         uint32_t pending = s->isr_jazz & s->imr_jazz;
 492         val = 0;
 493         irq = 0;
 494         while (pending) {
 495             if (pending & 1) {
 496                 DPRINTF("returning irq %s\n", irq_names[irq]);
 497                 val = (irq + 1) << 2;
 498                 break;
 499             }
 500             irq++;
 501             pending >>= 1;
 502         }
 503         break;
 504     }
 505     /* Local bus int enable mask */
 506     case 0x02:
 507         val = s->imr_jazz;
 508         break;
 509     default:
 510         RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr);
 511         val = 0;
 512     }
 513
 514     DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr);
 515
 516     return val;
 517 }
 518
 519 static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
 520 {
 521     uint32_t v;
 522     v = jazzio_readw(opaque, addr & ~0x1);
 523     return (v >> (8 * (addr & 0x1))) & 0xff;
 524 }
 525
 526 static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
 527 {
 528     uint32_t v;
 529     v = jazzio_readw(opaque, addr);
 530     v |= jazzio_readw(opaque, addr + 2) << 16;
 531     return v;
 532 }
 533
 534 static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 535 {
 536     rc4030State *s = opaque;
 537     addr &= 0xfff;
 538
 539     DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr);
 540
 541     switch (addr) {
 542     /* Local bus int enable mask */
 543     case 0x02:
 544         s->imr_jazz = val;
 545         update_jazz_irq(s);
 546         break;
 547     default:
 548         RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr);
 549         break;
 550     }
 551 }
 552
 553 static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 554 {
 555     uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
 556
 557     switch (addr & 1) {
 558     case 0:
 559         val = val | (old_val & 0xff00);
 560         break;
 561     case 1:
 562         val = (val << 8) | (old_val & 0x00ff);
 563         break;
 564     }
 565     jazzio_writew(opaque, addr & ~0x1, val);
 566 }
 567
 568 static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 569 {
 570     jazzio_writew(opaque, addr, val & 0xffff);
 571     jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
 572 }
 573
 574 static CPUReadMemoryFunc * const jazzio_read[3] = {
 575     jazzio_readb,
 576     jazzio_readw,
 577     jazzio_readl,
 578 };
 579
 580 static CPUWriteMemoryFunc * const jazzio_write[3] = {
 581     jazzio_writeb,
 582     jazzio_writew,
 583     jazzio_writel,
 584 };
 585
 586 static void rc4030_reset(void *opaque)
 587 {
 588     rc4030State *s = opaque;
 589     int i;
 590
 591     s->config = 0x410; /* some boards seem to accept 0x104 too */
 592     s->revision = 1;
 593     s->invalid_address_register = 0;
 594
 595     memset(s->dma_regs, 0, sizeof(s->dma_regs));
 596     s->dma_tl_base = s->dma_tl_limit = 0;
 597
 598     s->remote_failed_address = s->memory_failed_address = 0;
 599     s->cache_maint = 0;
 600     s->cache_ptag = s->cache_ltag = 0;
 601     s->cache_bmask = 0;
 602
 603     s->offset210 = 0x18186;
 604     s->nvram_protect = 7;
 605     for (i = 0; i < 15; i++)
 606         s->rem_speed[i] = 7;
 607     s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
 608     s->isr_jazz = 0;
 609
 610     s->itr = 0;
 611
 612     qemu_irq_lower(s->timer_irq);
 613     qemu_irq_lower(s->jazz_bus_irq);
 614 }
 615
 616 static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
 617 {
 618     rc4030State* s = opaque;
 619     int i, j;
 620
 621     if (version_id != 2)
 622         return -EINVAL;
 623
 624     s->config = qemu_get_be32(f);
 625     s->invalid_address_register = qemu_get_be32(f);
 626     for (i = 0; i < 8; i++)
 627         for (j = 0; j < 4; j++)
 628             s->dma_regs[i][j] = qemu_get_be32(f);
 629     s->dma_tl_base = qemu_get_be32(f);
 630     s->dma_tl_limit = qemu_get_be32(f);
 631     s->cache_maint = qemu_get_be32(f);
 632     s->remote_failed_address = qemu_get_be32(f);
 633     s->memory_failed_address = qemu_get_be32(f);
 634     s->cache_ptag = qemu_get_be32(f);
 635     s->cache_ltag = qemu_get_be32(f);
 636     s->cache_bmask = qemu_get_be32(f);
 637     s->offset210 = qemu_get_be32(f);
 638     s->nvram_protect = qemu_get_be32(f);
 639     for (i = 0; i < 15; i++)
 640         s->rem_speed[i] = qemu_get_be32(f);
 641     s->imr_jazz = qemu_get_be32(f);
 642     s->isr_jazz = qemu_get_be32(f);
 643     s->itr = qemu_get_be32(f);
 644
 645     set_next_tick(s);
 646     update_jazz_irq(s);
 647
 648     return 0;
 649 }
 650
 651 static void rc4030_save(QEMUFile *f, void *opaque)
 652 {
 653     rc4030State* s = opaque;
 654     int i, j;
 655
 656     qemu_put_be32(f, s->config);
 657     qemu_put_be32(f, s->invalid_address_register);
 658     for (i = 0; i < 8; i++)
 659         for (j = 0; j < 4; j++)
 660             qemu_put_be32(f, s->dma_regs[i][j]);
 661     qemu_put_be32(f, s->dma_tl_base);
 662     qemu_put_be32(f, s->dma_tl_limit);
 663     qemu_put_be32(f, s->cache_maint);
 664     qemu_put_be32(f, s->remote_failed_address);
 665     qemu_put_be32(f, s->memory_failed_address);
 666     qemu_put_be32(f, s->cache_ptag);
 667     qemu_put_be32(f, s->cache_ltag);
 668     qemu_put_be32(f, s->cache_bmask);
 669     qemu_put_be32(f, s->offset210);
 670     qemu_put_be32(f, s->nvram_protect);
 671     for (i = 0; i < 15; i++)
 672         qemu_put_be32(f, s->rem_speed[i]);
 673     qemu_put_be32(f, s->imr_jazz);
 674     qemu_put_be32(f, s->isr_jazz);
 675     qemu_put_be32(f, s->itr);
 676 }
 677
 678 void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
 679 {
 680     rc4030State *s = opaque;
 681     target_phys_addr_t entry_addr;
 682     target_phys_addr_t phys_addr;
 683     dma_pagetable_entry entry;
 684     int index;
 685     int ncpy, i;
 686
 687     i = 0;
 688     for (;;) {
 689         if (i == len) {
 690             break;
 691         }
 692
 693         ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
 694         if (ncpy > len - i)
 695             ncpy = len - i;
 696
 697         /* Get DMA translation table entry */
 698         index = addr / DMA_PAGESIZE;
 699         if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) {
 700             break;
 701         }
 702         entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
 703         /* XXX: not sure. should we really use only lowest bits? */
 704         entry_addr &= 0x7fffffff;
 705         cpu_physical_memory_rw(entry_addr, (uint8_t *)&entry, sizeof(entry), 0);
 706
 707         /* Read/write data at right place */
 708         phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
 709         cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write);
 710
 711         i += ncpy;
 712         addr += ncpy;
 713     }
 714 }
 715
 716 static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
 717 {
 718     rc4030State *s = opaque;
 719     target_phys_addr_t dma_addr;
 720     int dev_to_mem;
 721
 722     s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
 723
 724     /* Check DMA channel consistency */
 725     dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
 726     if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
 727         (is_write != dev_to_mem)) {
 728         s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
 729         s->nmi_interrupt |= 1 << n;
 730         return;
 731     }
 732
 733     /* Get start address and len */
 734     if (len > s->dma_regs[n][DMA_REG_COUNT])
 735         len = s->dma_regs[n][DMA_REG_COUNT];
 736     dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
 737
 738     /* Read/write data at right place */
 739     rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write);
 740
 741     s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
 742     s->dma_regs[n][DMA_REG_COUNT] -= len;
 743
 744 #ifdef DEBUG_RC4030_DMA
 745     {
 746         int i, j;
 747         printf("rc4030 dma: Copying %d bytes %s host %p\n",
 748             len, is_write ? "from" : "to", buf);
 749         for (i = 0; i < len; i += 16) {
 750             int n = min(16, len - i);
 751             for (j = 0; j < n; j++)
 752                 printf("%02x ", buf[i + j]);
 753             while (j++ < 16)
 754                 printf("   ");
 755             printf("| ");
 756             for (j = 0; j < n; j++)
 757                 printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
 758             printf("\n");
 759         }
 760     }
 761 #endif
 762 }
 763
 764 struct rc4030DMAState {
 765     void *opaque;
 766     int n;
 767 };
 768
 769 void rc4030_dma_read(void *dma, uint8_t *buf, int len)
 770 {
 771     rc4030_dma s = dma;
 772     rc4030_do_dma(s->opaque, s->n, buf, len, 0);
 773 }
 774
 775 void rc4030_dma_write(void *dma, uint8_t *buf, int len)
 776 {
 777     rc4030_dma s = dma;
 778     rc4030_do_dma(s->opaque, s->n, buf, len, 1);
 779 }
 780
 781 static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
 782 {
 783     rc4030_dma *s;
 784     struct rc4030DMAState *p;
 785     int i;
 786
 787     s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n);
 788     p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n);
 789     for (i = 0; i < n; i++) {
 790         p->opaque = opaque;
 791         p->n = i;
 792         s[i] = p;
 793         p++;
 794     }
 795     return s;
 796 }
 797
 798 void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
 799                   qemu_irq **irqs, rc4030_dma **dmas)
 800 {
 801     rc4030State *s;
 802     int s_chipset, s_jazzio;
 803
 804     s = qemu_mallocz(sizeof(rc4030State));
 805
 806     *irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
 807     *dmas = rc4030_allocate_dmas(s, 4);
 808
 809     s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
 810     s->timer_irq = timer;
 811     s->jazz_bus_irq = jazz_bus;
 812
 813     qemu_register_reset(rc4030_reset, s);
 814     register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s);
 815     rc4030_reset(s);
 816
 817     s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s);
 818     cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
 819     s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s);
 820     cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);
 821
 822     return s;
 823 }