hw/lsi53c895a.c

   1 /*
   2  * QEMU LSI53C895A SCSI Host Bus Adapter emulation
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the LGPL.
   8  */
   9
  10 /* ??? Need to check if the {read,write}[wl] routines work properly on
  11    big-endian targets.  */
  12
  13 #include <assert.h>                             \
  14
  15 #include "hw.h"
  16 #include "pci.h"
  17 #include "scsi-disk.h"
  18 #include "block_int.h"
  19
  20 //#define DEBUG_LSI
  21 //#define DEBUG_LSI_REG
  22
  23 #ifdef DEBUG_LSI
  24 #define DPRINTF(fmt, ...) \
  25 do { printf("lsi_scsi: " fmt , ## __VA_ARGS__); } while (0)
  26 #define BADF(fmt, ...) \
  27 do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
  28 #else
  29 #define DPRINTF(fmt, ...) do {} while(0)
  30 #define BADF(fmt, ...) \
  31 do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__);} while (0)
  32 #endif
  33
  34 #define LSI_SCNTL0_TRG    0x01
  35 #define LSI_SCNTL0_AAP    0x02
  36 #define LSI_SCNTL0_EPC    0x08
  37 #define LSI_SCNTL0_WATN   0x10
  38 #define LSI_SCNTL0_START  0x20
  39
  40 #define LSI_SCNTL1_SST    0x01
  41 #define LSI_SCNTL1_IARB   0x02
  42 #define LSI_SCNTL1_AESP   0x04
  43 #define LSI_SCNTL1_RST    0x08
  44 #define LSI_SCNTL1_CON    0x10
  45 #define LSI_SCNTL1_DHP    0x20
  46 #define LSI_SCNTL1_ADB    0x40
  47 #define LSI_SCNTL1_EXC    0x80
  48
  49 #define LSI_SCNTL2_WSR    0x01
  50 #define LSI_SCNTL2_VUE0   0x02
  51 #define LSI_SCNTL2_VUE1   0x04
  52 #define LSI_SCNTL2_WSS    0x08
  53 #define LSI_SCNTL2_SLPHBEN 0x10
  54 #define LSI_SCNTL2_SLPMD  0x20
  55 #define LSI_SCNTL2_CHM    0x40
  56 #define LSI_SCNTL2_SDU    0x80
  57
  58 #define LSI_ISTAT0_DIP    0x01
  59 #define LSI_ISTAT0_SIP    0x02
  60 #define LSI_ISTAT0_INTF   0x04
  61 #define LSI_ISTAT0_CON    0x08
  62 #define LSI_ISTAT0_SEM    0x10
  63 #define LSI_ISTAT0_SIGP   0x20
  64 #define LSI_ISTAT0_SRST   0x40
  65 #define LSI_ISTAT0_ABRT   0x80
  66
  67 #define LSI_ISTAT1_SI     0x01
  68 #define LSI_ISTAT1_SRUN   0x02
  69 #define LSI_ISTAT1_FLSH   0x04
  70
  71 #define LSI_SSTAT0_SDP0   0x01
  72 #define LSI_SSTAT0_RST    0x02
  73 #define LSI_SSTAT0_WOA    0x04
  74 #define LSI_SSTAT0_LOA    0x08
  75 #define LSI_SSTAT0_AIP    0x10
  76 #define LSI_SSTAT0_OLF    0x20
  77 #define LSI_SSTAT0_ORF    0x40
  78 #define LSI_SSTAT0_ILF    0x80
  79
  80 #define LSI_SIST0_PAR     0x01
  81 #define LSI_SIST0_RST     0x02
  82 #define LSI_SIST0_UDC     0x04
  83 #define LSI_SIST0_SGE     0x08
  84 #define LSI_SIST0_RSL     0x10
  85 #define LSI_SIST0_SEL     0x20
  86 #define LSI_SIST0_CMP     0x40
  87 #define LSI_SIST0_MA      0x80
  88
  89 #define LSI_SIST1_HTH     0x01
  90 #define LSI_SIST1_GEN     0x02
  91 #define LSI_SIST1_STO     0x04
  92 #define LSI_SIST1_SBMC    0x10
  93
  94 #define LSI_SOCL_IO       0x01
  95 #define LSI_SOCL_CD       0x02
  96 #define LSI_SOCL_MSG      0x04
  97 #define LSI_SOCL_ATN      0x08
  98 #define LSI_SOCL_SEL      0x10
  99 #define LSI_SOCL_BSY      0x20
 100 #define LSI_SOCL_ACK      0x40
 101 #define LSI_SOCL_REQ      0x80
 102
 103 #define LSI_DSTAT_IID     0x01
 104 #define LSI_DSTAT_SIR     0x04
 105 #define LSI_DSTAT_SSI     0x08
 106 #define LSI_DSTAT_ABRT    0x10
 107 #define LSI_DSTAT_BF      0x20
 108 #define LSI_DSTAT_MDPE    0x40
 109 #define LSI_DSTAT_DFE     0x80
 110
 111 #define LSI_DCNTL_COM     0x01
 112 #define LSI_DCNTL_IRQD    0x02
 113 #define LSI_DCNTL_STD     0x04
 114 #define LSI_DCNTL_IRQM    0x08
 115 #define LSI_DCNTL_SSM     0x10
 116 #define LSI_DCNTL_PFEN    0x20
 117 #define LSI_DCNTL_PFF     0x40
 118 #define LSI_DCNTL_CLSE    0x80
 119
 120 #define LSI_DMODE_MAN     0x01
 121 #define LSI_DMODE_BOF     0x02
 122 #define LSI_DMODE_ERMP    0x04
 123 #define LSI_DMODE_ERL     0x08
 124 #define LSI_DMODE_DIOM    0x10
 125 #define LSI_DMODE_SIOM    0x20
 126
 127 #define LSI_CTEST2_DACK   0x01
 128 #define LSI_CTEST2_DREQ   0x02
 129 #define LSI_CTEST2_TEOP   0x04
 130 #define LSI_CTEST2_PCICIE 0x08
 131 #define LSI_CTEST2_CM     0x10
 132 #define LSI_CTEST2_CIO    0x20
 133 #define LSI_CTEST2_SIGP   0x40
 134 #define LSI_CTEST2_DDIR   0x80
 135
 136 #define LSI_CTEST5_BL2    0x04
 137 #define LSI_CTEST5_DDIR   0x08
 138 #define LSI_CTEST5_MASR   0x10
 139 #define LSI_CTEST5_DFSN   0x20
 140 #define LSI_CTEST5_BBCK   0x40
 141 #define LSI_CTEST5_ADCK   0x80
 142
 143 #define LSI_CCNTL0_DILS   0x01
 144 #define LSI_CCNTL0_DISFC  0x10
 145 #define LSI_CCNTL0_ENNDJ  0x20
 146 #define LSI_CCNTL0_PMJCTL 0x40
 147 #define LSI_CCNTL0_ENPMJ  0x80
 148
 149 #define LSI_CCNTL1_EN64DBMV  0x01
 150 #define LSI_CCNTL1_EN64TIBMV 0x02
 151 #define LSI_CCNTL1_64TIMOD   0x04
 152 #define LSI_CCNTL1_DDAC      0x08
 153 #define LSI_CCNTL1_ZMOD      0x80
 154
 155 #define LSI_CCNTL1_40BIT (LSI_CCNTL1_EN64TIBMV|LSI_CCNTL1_64TIMOD)
 156
 157 #define PHASE_DO          0
 158 #define PHASE_DI          1
 159 #define PHASE_CMD         2
 160 #define PHASE_ST          3
 161 #define PHASE_MO          6
 162 #define PHASE_MI          7
 163 #define PHASE_MASK        7
 164
 165 /* Maximum length of MSG IN data.  */
 166 #define LSI_MAX_MSGIN_LEN 8
 167
 168 /* Flag set if this is a tagged command.  */
 169 #define LSI_TAG_VALID     (1 << 16)
 170
 171 typedef struct {
 172     uint32_t tag;
 173     uint32_t pending;
 174     int out;
 175 } lsi_queue;
 176
 177 typedef struct {
 178     PCIDevice pci_dev;
 179     int mmio_io_addr;
 180     int ram_io_addr;
 181     uint32_t script_ram_base;
 182
 183     int carry; /* ??? Should this be an a visible register somewhere?  */
 184     int sense;
 185     /* Action to take at the end of a MSG IN phase.
 186        0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN.  */
 187     int msg_action;
 188     int msg_len;
 189     uint8_t msg[LSI_MAX_MSGIN_LEN];
 190     /* 0 if SCRIPTS are running or stopped.
 191      * 1 if a Wait Reselect instruction has been issued.
 192      * 2 if processing DMA from lsi_execute_script.
 193      * 3 if a DMA operation is in progress.  */
 194     int waiting;
 195     SCSIDevice *scsi_dev[LSI_MAX_DEVS];
 196     SCSIDevice *current_dev;
 197     int current_lun;
 198     /* The tag is a combination of the device ID and the SCSI tag.  */
 199     uint32_t current_tag;
 200     uint32_t current_dma_len;
 201     int command_complete;
 202     uint8_t *dma_buf;
 203     lsi_queue *queue;
 204     int queue_len;
 205     int active_commands;
 206
 207     uint32_t dsa;
 208     uint32_t temp;
 209     uint32_t dnad;
 210     uint32_t dbc;
 211     uint8_t istat0;
 212     uint8_t istat1;
 213     uint8_t dcmd;
 214     uint8_t dstat;
 215     uint8_t dien;
 216     uint8_t sist0;
 217     uint8_t sist1;
 218     uint8_t sien0;
 219     uint8_t sien1;
 220     uint8_t mbox0;
 221     uint8_t mbox1;
 222     uint8_t dfifo;
 223     uint8_t ctest2;
 224     uint8_t ctest3;
 225     uint8_t ctest4;
 226     uint8_t ctest5;
 227     uint8_t ccntl0;
 228     uint8_t ccntl1;
 229     uint32_t dsp;
 230     uint32_t dsps;
 231     uint8_t dmode;
 232     uint8_t dcntl;
 233     uint8_t scntl0;
 234     uint8_t scntl1;
 235     uint8_t scntl2;
 236     uint8_t scntl3;
 237     uint8_t sstat0;
 238     uint8_t sstat1;
 239     uint8_t scid;
 240     uint8_t sxfer;
 241     uint8_t socl;
 242     uint8_t sdid;
 243     uint8_t ssid;
 244     uint8_t sfbr;
 245     uint8_t stest1;
 246     uint8_t stest2;
 247     uint8_t stest3;
 248     uint8_t sidl;
 249     uint8_t stime0;
 250     uint8_t respid0;
 251     uint8_t respid1;
 252     uint32_t mmrs;
 253     uint32_t mmws;
 254     uint32_t sfs;
 255     uint32_t drs;
 256     uint32_t sbms;
 257     uint32_t dbms;
 258     uint32_t dnad64;
 259     uint32_t pmjad1;
 260     uint32_t pmjad2;
 261     uint32_t rbc;
 262     uint32_t ua;
 263     uint32_t ia;
 264     uint32_t sbc;
 265     uint32_t csbc;
 266     uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
 267     uint8_t sbr;
 268
 269     /* Script ram is stored as 32-bit words in host byteorder.  */
 270     uint32_t script_ram[2048];
 271 } LSIState;
 272
 273 static void lsi_soft_reset(LSIState *s)
 274 {
 275     DPRINTF("Reset\n");
 276     s->carry = 0;
 277
 278     s->waiting = 0;
 279     s->dsa = 0;
 280     s->dnad = 0;
 281     s->dbc = 0;
 282     s->temp = 0;
 283     memset(s->scratch, 0, sizeof(s->scratch));
 284     s->istat0 = 0;
 285     s->istat1 = 0;
 286     s->dcmd = 0;
 287     s->dstat = 0;
 288     s->dien = 0;
 289     s->sist0 = 0;
 290     s->sist1 = 0;
 291     s->sien0 = 0;
 292     s->sien1 = 0;
 293     s->mbox0 = 0;
 294     s->mbox1 = 0;
 295     s->dfifo = 0;
 296     s->ctest2 = 0;
 297     s->ctest3 = 0;
 298     s->ctest4 = 0;
 299     s->ctest5 = 0;
 300     s->ccntl0 = 0;
 301     s->ccntl1 = 0;
 302     s->dsp = 0;
 303     s->dsps = 0;
 304     s->dmode = 0;
 305     s->dcntl = 0;
 306     s->scntl0 = 0xc0;
 307     s->scntl1 = 0;
 308     s->scntl2 = 0;
 309     s->scntl3 = 0;
 310     s->sstat0 = 0;
 311     s->sstat1 = 0;
 312     s->scid = 7;
 313     s->sxfer = 0;
 314     s->socl = 0;
 315     s->stest1 = 0;
 316     s->stest2 = 0;
 317     s->stest3 = 0;
 318     s->sidl = 0;
 319     s->stime0 = 0;
 320     s->respid0 = 0x80;
 321     s->respid1 = 0;
 322     s->mmrs = 0;
 323     s->mmws = 0;
 324     s->sfs = 0;
 325     s->drs = 0;
 326     s->sbms = 0;
 327     s->dbms = 0;
 328     s->dnad64 = 0;
 329     s->pmjad1 = 0;
 330     s->pmjad2 = 0;
 331     s->rbc = 0;
 332     s->ua = 0;
 333     s->ia = 0;
 334     s->sbc = 0;
 335     s->csbc = 0;
 336     s->sbr = 0;
 337 }
 338
 339 static int lsi_dma_40bit(LSIState *s)
 340 {
 341     if ((s->ccntl1 & LSI_CCNTL1_40BIT) == LSI_CCNTL1_40BIT)
 342         return 1;
 343     return 0;
 344 }
 345
 346 static int lsi_dma_ti64bit(LSIState *s)
 347 {
 348     if ((s->ccntl1 & LSI_CCNTL1_EN64TIBMV) == LSI_CCNTL1_EN64TIBMV)
 349         return 1;
 350     return 0;
 351 }
 352
 353 static int lsi_dma_64bit(LSIState *s)
 354 {
 355     if ((s->ccntl1 & LSI_CCNTL1_EN64DBMV) == LSI_CCNTL1_EN64DBMV)
 356         return 1;
 357     return 0;
 358 }
 359
 360 static uint8_t lsi_reg_readb(LSIState *s, int offset);
 361 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
 362 static void lsi_execute_script(LSIState *s);
 363
 364 static inline uint32_t read_dword(LSIState *s, uint32_t addr)
 365 {
 366     uint32_t buf;
 367
 368     /* Optimize reading from SCRIPTS RAM.  */
 369     if ((addr & 0xffffe000) == s->script_ram_base) {
 370         return s->script_ram[(addr & 0x1fff) >> 2];
 371     }
 372     cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
 373     return cpu_to_le32(buf);
 374 }
 375
 376 static void lsi_stop_script(LSIState *s)
 377 {
 378     s->istat1 &= ~LSI_ISTAT1_SRUN;
 379 }
 380
 381 static void lsi_update_irq(LSIState *s)
 382 {
 383     int level;
 384     static int last_level;
 385
 386     /* It's unclear whether the DIP/SIP bits should be cleared when the
 387        Interrupt Status Registers are cleared or when istat0 is read.
 388        We currently do the formwer, which seems to work.  */
 389     level = 0;
 390     if (s->dstat) {
 391         if (s->dstat & s->dien)
 392             level = 1;
 393         s->istat0 |= LSI_ISTAT0_DIP;
 394     } else {
 395         s->istat0 &= ~LSI_ISTAT0_DIP;
 396     }
 397
 398     if (s->sist0 || s->sist1) {
 399         if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
 400             level = 1;
 401         s->istat0 |= LSI_ISTAT0_SIP;
 402     } else {
 403         s->istat0 &= ~LSI_ISTAT0_SIP;
 404     }
 405     if (s->istat0 & LSI_ISTAT0_INTF)
 406         level = 1;
 407
 408     if (level != last_level) {
 409         DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
 410                 level, s->dstat, s->sist1, s->sist0);
 411         last_level = level;
 412     }
 413     qemu_set_irq(s->pci_dev.irq[0], level);
 414 }
 415
 416 /* Stop SCRIPTS execution and raise a SCSI interrupt.  */
 417 static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
 418 {
 419     uint32_t mask0;
 420     uint32_t mask1;
 421
 422     DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
 423             stat1, stat0, s->sist1, s->sist0);
 424     s->sist0 |= stat0;
 425     s->sist1 |= stat1;
 426     /* Stop processor on fatal or unmasked interrupt.  As a special hack
 427        we don't stop processing when raising STO.  Instead continue
 428        execution and stop at the next insn that accesses the SCSI bus.  */
 429     mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
 430     mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
 431     mask1 &= ~LSI_SIST1_STO;
 432     if (s->sist0 & mask0 || s->sist1 & mask1) {
 433         lsi_stop_script(s);
 434     }
 435     lsi_update_irq(s);
 436 }
 437
 438 /* Stop SCRIPTS execution and raise a DMA interrupt.  */
 439 static void lsi_script_dma_interrupt(LSIState *s, int stat)
 440 {
 441     DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
 442     s->dstat |= stat;
 443     lsi_update_irq(s);
 444     lsi_stop_script(s);
 445 }
 446
 447 static inline void lsi_set_phase(LSIState *s, int phase)
 448 {
 449     s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
 450 }
 451
 452 static void lsi_bad_phase(LSIState *s, int out, int new_phase)
 453 {
 454     /* Trigger a phase mismatch.  */
 455     if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
 456         if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
 457             s->dsp = s->pmjad1;
 458         } else {
 459             s->dsp = s->pmjad2;
 460         }
 461         DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
 462     } else {
 463         DPRINTF("Phase mismatch interrupt\n");
 464         lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 465         lsi_stop_script(s);
 466     }
 467     lsi_set_phase(s, new_phase);
 468 }
 469
 470
 471 /* Resume SCRIPTS execution after a DMA operation.  */
 472 static void lsi_resume_script(LSIState *s)
 473 {
 474     if (s->waiting != 2) {
 475         s->waiting = 0;
 476         lsi_execute_script(s);
 477     } else {
 478         s->waiting = 0;
 479     }
 480 }
 481
 482 /* Initiate a SCSI layer data transfer.  */
 483 static void lsi_do_dma(LSIState *s, int out)
 484 {
 485     uint32_t count;
 486     target_phys_addr_t addr;
 487
 488     if (!s->current_dma_len) {
 489         /* Wait until data is available.  */
 490         DPRINTF("DMA no data available\n");
 491         return;
 492     }
 493
 494     count = s->dbc;
 495     if (count > s->current_dma_len)
 496         count = s->current_dma_len;
 497
 498     addr = s->dnad;
 499     /* both 40 and Table Indirect 64-bit DMAs store upper bits in dnad64 */
 500     if (lsi_dma_40bit(s) || lsi_dma_ti64bit(s))
 501         addr |= ((uint64_t)s->dnad64 << 32);
 502     else if (s->dbms)
 503         addr |= ((uint64_t)s->dbms << 32);
 504     else if (s->sbms)
 505         addr |= ((uint64_t)s->sbms << 32);
 506
 507     DPRINTF("DMA addr=0x" TARGET_FMT_plx " len=%d\n", addr, count);
 508     s->csbc += count;
 509     s->dnad += count;
 510     s->dbc -= count;
 511
 512     if (s->dma_buf == NULL) {
 513         s->dma_buf = s->current_dev->get_buf(s->current_dev,
 514                                              s->current_tag);
 515     }
 516
 517     /* ??? Set SFBR to first data byte.  */
 518     if (out) {
 519         cpu_physical_memory_read(addr, s->dma_buf, count);
 520     } else {
 521         cpu_physical_memory_write(addr, s->dma_buf, count);
 522     }
 523     s->current_dma_len -= count;
 524     if (s->current_dma_len == 0) {
 525         s->dma_buf = NULL;
 526         if (out) {
 527             /* Write the data.  */
 528             s->current_dev->write_data(s->current_dev, s->current_tag);
 529         } else {
 530             /* Request any remaining data.  */
 531             s->current_dev->read_data(s->current_dev, s->current_tag);
 532         }
 533     } else {
 534         s->dma_buf += count;
 535         lsi_resume_script(s);
 536     }
 537 }
 538
 539
 540 /* Add a command to the queue.  */
 541 static void lsi_queue_command(LSIState *s)
 542 {
 543     lsi_queue *p;
 544
 545     DPRINTF("Queueing tag=0x%x\n", s->current_tag);
 546     if (s->queue_len == s->active_commands) {
 547         s->queue_len++;
 548         s->queue = qemu_realloc(s->queue, s->queue_len * sizeof(lsi_queue));
 549     }
 550     p = &s->queue[s->active_commands++];
 551     p->tag = s->current_tag;
 552     p->pending = 0;
 553     p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
 554 }
 555
 556 /* Queue a byte for a MSG IN phase.  */
 557 static void lsi_add_msg_byte(LSIState *s, uint8_t data)
 558 {
 559     if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
 560         BADF("MSG IN data too long\n");
 561     } else {
 562         DPRINTF("MSG IN 0x%02x\n", data);
 563         s->msg[s->msg_len++] = data;
 564     }
 565 }
 566
 567 /* Perform reselection to continue a command.  */
 568 static void lsi_reselect(LSIState *s, uint32_t tag)
 569 {
 570     lsi_queue *p;
 571     int n;
 572     int id;
 573
 574     p = NULL;
 575     for (n = 0; n < s->active_commands; n++) {
 576         p = &s->queue[n];
 577         if (p->tag == tag)
 578             break;
 579     }
 580     if (n == s->active_commands) {
 581         BADF("Reselected non-existant command tag=0x%x\n", tag);
 582         return;
 583     }
 584     id = (tag >> 8) & 0xf;
 585     s->ssid = id | 0x80;
 586     DPRINTF("Reselected target %d\n", id);
 587     s->current_dev = s->scsi_dev[id];
 588     s->current_tag = tag;
 589     s->scntl1 |= LSI_SCNTL1_CON;
 590     lsi_set_phase(s, PHASE_MI);
 591     s->msg_action = p->out ? 2 : 3;
 592     s->current_dma_len = p->pending;
 593     s->dma_buf = NULL;
 594     lsi_add_msg_byte(s, 0x80);
 595     if (s->current_tag & LSI_TAG_VALID) {
 596         lsi_add_msg_byte(s, 0x20);
 597         lsi_add_msg_byte(s, tag & 0xff);
 598     }
 599
 600     s->active_commands--;
 601     if (n != s->active_commands) {
 602         s->queue[n] = s->queue[s->active_commands];
 603     }
 604 }
 605
 606 /* Record that data is available for a queued command.  Returns zero if
 607    the device was reselected, nonzero if the IO is deferred.  */
 608 static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg)
 609 {
 610     lsi_queue *p;
 611     int i;
 612     for (i = 0; i < s->active_commands; i++) {
 613         p = &s->queue[i];
 614         if (p->tag == tag) {
 615             if (p->pending) {
 616                 BADF("Multiple IO pending for tag %d\n", tag);
 617             }
 618             p->pending = arg;
 619             if (s->waiting == 1) {
 620                 /* Reselect device.  */
 621                 lsi_reselect(s, tag);
 622                 return 0;
 623             } else {
 624                DPRINTF("Queueing IO tag=0x%x\n", tag);
 625                 p->pending = arg;
 626                 return 1;
 627             }
 628         }
 629     }
 630     BADF("IO with unknown tag %d\n", tag);
 631     return 1;
 632 }
 633
 634 /* Callback to indicate that the SCSI layer has completed a transfer.  */
 635 static void lsi_command_complete(void *opaque, int reason, uint32_t tag,
 636                                  uint32_t arg)
 637 {
 638     LSIState *s = (LSIState *)opaque;
 639     int out;
 640
 641     out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
 642     if (reason == SCSI_REASON_DONE) {
 643         DPRINTF("Command complete sense=%d\n", (int)arg);
 644         s->sense = arg;
 645         s->command_complete = 2;
 646         if (s->waiting && s->dbc != 0) {
 647             /* Raise phase mismatch for short transfers.  */
 648             lsi_bad_phase(s, out, PHASE_ST);
 649         } else {
 650             lsi_set_phase(s, PHASE_ST);
 651         }
 652         lsi_resume_script(s);
 653         return;
 654     }
 655
 656     if (s->waiting == 1 || tag != s->current_tag) {
 657         if (lsi_queue_tag(s, tag, arg))
 658             return;
 659     }
 660     DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
 661     s->current_dma_len = arg;
 662     s->command_complete = 1;
 663     if (!s->waiting)
 664         return;
 665     if (s->waiting == 1 || s->dbc == 0) {
 666         lsi_resume_script(s);
 667     } else {
 668         lsi_do_dma(s, out);
 669     }
 670 }
 671
 672 static void lsi_do_command(LSIState *s)
 673 {
 674     uint8_t buf[16];
 675     int n;
 676
 677     DPRINTF("Send command len=%d\n", s->dbc);
 678     if (s->dbc > 16)
 679         s->dbc = 16;
 680     cpu_physical_memory_read(s->dnad, buf, s->dbc);
 681     s->sfbr = buf[0];
 682     s->command_complete = 0;
 683     n = s->current_dev->send_command(s->current_dev, s->current_tag, buf,
 684                                      s->current_lun);
 685     if (n > 0) {
 686         lsi_set_phase(s, PHASE_DI);
 687         s->current_dev->read_data(s->current_dev, s->current_tag);
 688     } else if (n < 0) {
 689         lsi_set_phase(s, PHASE_DO);
 690         s->current_dev->write_data(s->current_dev, s->current_tag);
 691     }
 692
 693     if (!s->command_complete) {
 694         if (n) {
 695             /* Command did not complete immediately so disconnect.  */
 696             lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
 697             lsi_add_msg_byte(s, 4); /* DISCONNECT */
 698             /* wait data */
 699             lsi_set_phase(s, PHASE_MI);
 700             s->msg_action = 1;
 701             lsi_queue_command(s);
 702         } else {
 703             /* wait command complete */
 704             lsi_set_phase(s, PHASE_DI);
 705         }
 706     }
 707 }
 708
 709 static void lsi_do_status(LSIState *s)
 710 {
 711     uint8_t sense;
 712     DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
 713     if (s->dbc != 1)
 714         BADF("Bad Status move\n");
 715     s->dbc = 1;
 716     sense = s->sense;
 717     s->sfbr = sense;
 718     cpu_physical_memory_write(s->dnad, &sense, 1);
 719     lsi_set_phase(s, PHASE_MI);
 720     s->msg_action = 1;
 721     lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
 722 }
 723
 724 static void lsi_disconnect(LSIState *s)
 725 {
 726     s->scntl1 &= ~LSI_SCNTL1_CON;
 727     s->sstat1 &= ~PHASE_MASK;
 728 }
 729
 730 static void lsi_do_msgin(LSIState *s)
 731 {
 732     int len;
 733     DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
 734     s->sfbr = s->msg[0];
 735     len = s->msg_len;
 736     if (len > s->dbc)
 737         len = s->dbc;
 738     cpu_physical_memory_write(s->dnad, s->msg, len);
 739     /* Linux drivers rely on the last byte being in the SIDL.  */
 740     s->sidl = s->msg[len - 1];
 741     s->msg_len -= len;
 742     if (s->msg_len) {
 743         memmove(s->msg, s->msg + len, s->msg_len);
 744     } else {
 745         /* ??? Check if ATN (not yet implemented) is asserted and maybe
 746            switch to PHASE_MO.  */
 747         switch (s->msg_action) {
 748         case 0:
 749             lsi_set_phase(s, PHASE_CMD);
 750             break;
 751         case 1:
 752             lsi_disconnect(s);
 753             break;
 754         case 2:
 755             lsi_set_phase(s, PHASE_DO);
 756             break;
 757         case 3:
 758             lsi_set_phase(s, PHASE_DI);
 759             break;
 760         default:
 761             abort();
 762         }
 763     }
 764 }
 765
 766 /* Read the next byte during a MSGOUT phase.  */
 767 static uint8_t lsi_get_msgbyte(LSIState *s)
 768 {
 769     uint8_t data;
 770     cpu_physical_memory_read(s->dnad, &data, 1);
 771     s->dnad++;
 772     s->dbc--;
 773     return data;
 774 }
 775
 776 static void lsi_do_msgout(LSIState *s)
 777 {
 778     uint8_t msg;
 779     int len;
 780
 781     DPRINTF("MSG out len=%d\n", s->dbc);
 782     while (s->dbc) {
 783         msg = lsi_get_msgbyte(s);
 784         s->sfbr = msg;
 785
 786         switch (msg) {
 787         case 0x00:
 788             DPRINTF("MSG: Disconnect\n");
 789             lsi_disconnect(s);
 790             break;
 791         case 0x08:
 792             DPRINTF("MSG: No Operation\n");
 793             lsi_set_phase(s, PHASE_CMD);
 794             break;
 795         case 0x01:
 796             len = lsi_get_msgbyte(s);
 797             msg = lsi_get_msgbyte(s);
 798             DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
 799             switch (msg) {
 800             case 1:
 801                 DPRINTF("SDTR (ignored)\n");
 802                 s->dbc -= 2;
 803                 break;
 804             case 3:
 805                 DPRINTF("WDTR (ignored)\n");
 806                 s->dbc -= 1;
 807                 break;
 808             default:
 809                 goto bad;
 810             }
 811             break;
 812         case 0x20: /* SIMPLE queue */
 813             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 814             DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff);
 815             break;
 816         case 0x21: /* HEAD of queue */
 817             BADF("HEAD queue not implemented\n");
 818             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 819             break;
 820         case 0x22: /* ORDERED queue */
 821             BADF("ORDERED queue not implemented\n");
 822             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 823             break;
 824         default:
 825             if ((msg & 0x80) == 0) {
 826                 goto bad;
 827             }
 828             s->current_lun = msg & 7;
 829             DPRINTF("Select LUN %d\n", s->current_lun);
 830             lsi_set_phase(s, PHASE_CMD);
 831             break;
 832         }
 833     }
 834     return;
 835 bad:
 836     BADF("Unimplemented message 0x%02x\n", msg);
 837     lsi_set_phase(s, PHASE_MI);
 838     lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
 839     s->msg_action = 0;
 840 }
 841
 842 /* Sign extend a 24-bit value.  */
 843 static inline int32_t sxt24(int32_t n)
 844 {
 845     return (n << 8) >> 8;
 846 }
 847
 848 #define LSI_BUF_SIZE 4096
 849 static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
 850 {
 851     int n;
 852     uint8_t buf[LSI_BUF_SIZE];
 853
 854     DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
 855     while (count) {
 856         n = (count > LSI_BUF_SIZE) ? LSI_BUF_SIZE : count;
 857         cpu_physical_memory_read(src, buf, n);
 858         cpu_physical_memory_write(dest, buf, n);
 859         src += n;
 860         dest += n;
 861         count -= n;
 862     }
 863 }
 864
 865 static void lsi_wait_reselect(LSIState *s)
 866 {
 867     int i;
 868     DPRINTF("Wait Reselect\n");
 869     if (s->current_dma_len)
 870         BADF("Reselect with pending DMA\n");
 871     for (i = 0; i < s->active_commands; i++) {
 872         if (s->queue[i].pending) {
 873             lsi_reselect(s, s->queue[i].tag);
 874             break;
 875         }
 876     }
 877     if (s->current_dma_len == 0) {
 878         s->waiting = 1;
 879     }
 880 }
 881
 882 static void lsi_execute_script(LSIState *s)
 883 {
 884     uint32_t insn;
 885     uint32_t addr, addr_high;
 886     int opcode;
 887     int insn_processed = 0;
 888
 889     s->istat1 |= LSI_ISTAT1_SRUN;
 890 again:
 891     insn_processed++;
 892     insn = read_dword(s, s->dsp);
 893     if (!insn) {
 894         /* If we receive an empty opcode increment the DSP by 4 bytes
 895            instead of 8 and execute the next opcode at that location */
 896         s->dsp += 4;
 897         goto again;
 898     }
 899     addr = read_dword(s, s->dsp + 4);
 900     addr_high = 0;
 901     DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
 902     s->dsps = addr;
 903     s->dcmd = insn >> 24;
 904     s->dsp += 8;
 905     switch (insn >> 30) {
 906     case 0: /* Block move.  */
 907         if (s->sist1 & LSI_SIST1_STO) {
 908             DPRINTF("Delayed select timeout\n");
 909             lsi_stop_script(s);
 910             break;
 911         }
 912         s->dbc = insn & 0xffffff;
 913         s->rbc = s->dbc;
 914         /* ??? Set ESA.  */
 915         s->ia = s->dsp - 8;
 916         if (insn & (1 << 29)) {
 917             /* Indirect addressing.  */
 918             addr = read_dword(s, addr);
 919         } else if (insn & (1 << 28)) {
 920             uint32_t buf[2];
 921             int32_t offset;
 922             /* Table indirect addressing.  */
 923
 924             /* 32-bit Table indirect */
 925             offset = sxt24(addr);
 926             cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
 927             /* byte count is stored in bits 0:23 only */
 928             s->dbc = cpu_to_le32(buf[0]) & 0xffffff;
 929             s->rbc = s->dbc;
 930             addr = cpu_to_le32(buf[1]);
 931
 932             /* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of
 933              * table, bits [31:24] */
 934             if (lsi_dma_40bit(s))
 935                 addr_high = cpu_to_le32(buf[0]) >> 24;
 936             else if (lsi_dma_ti64bit(s)) {
 937                 int selector = (cpu_to_le32(buf[0]) >> 24) & 0x1f;
 938                 switch (selector) {
 939                 case 0 ... 0x0f:
 940                     /* offset index into scratch registers since
 941                      * TI64 mode can use registers C to R */
 942                     addr_high = s->scratch[2 + selector];
 943                     break;
 944                 case 0x10:
 945                     addr_high = s->mmrs;
 946                     break;
 947                 case 0x11:
 948                     addr_high = s->mmws;
 949                     break;
 950                 case 0x12:
 951                     addr_high = s->sfs;
 952                     break;
 953                 case 0x13:
 954                     addr_high = s->drs;
 955                     break;
 956                 case 0x14:
 957                     addr_high = s->sbms;
 958                     break;
 959                 case 0x15:
 960                     addr_high = s->dbms;
 961                     break;
 962                 default:
 963                     BADF("Illegal selector specified (0x%x > 0x15)"
 964                          " for 64-bit DMA block move", selector);
 965                     break;
 966                 }
 967             }
 968         } else if (lsi_dma_64bit(s)) {
 969             /* fetch a 3rd dword if 64-bit direct move is enabled and
 970                only if we're not doing table indirect or indirect addressing */
 971             s->dbms = read_dword(s, s->dsp);
 972             s->dsp += 4;
 973             s->ia = s->dsp - 12;
 974         }
 975         if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
 976             DPRINTF("Wrong phase got %d expected %d\n",
 977                     s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
 978             lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 979             break;
 980         }
 981         s->dnad = addr;
 982         s->dnad64 = addr_high;
 983         switch (s->sstat1 & 0x7) {
 984         case PHASE_DO:
 985             s->waiting = 2;
 986             lsi_do_dma(s, 1);
 987             if (s->waiting)
 988                 s->waiting = 3;
 989             break;
 990         case PHASE_DI:
 991             s->waiting = 2;
 992             lsi_do_dma(s, 0);
 993             if (s->waiting)
 994                 s->waiting = 3;
 995             break;
 996         case PHASE_CMD:
 997             lsi_do_command(s);
 998             break;
 999         case PHASE_ST:
1000             lsi_do_status(s);
1001             break;
1002         case PHASE_MO:
1003             lsi_do_msgout(s);
1004             break;
1005         case PHASE_MI:
1006             lsi_do_msgin(s);
1007             break;
1008         default:
1009             BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
1010             exit(1);
1011         }
1012         s->dfifo = s->dbc & 0xff;
1013         s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
1014         s->sbc = s->dbc;
1015         s->rbc -= s->dbc;
1016         s->ua = addr + s->dbc;
1017         break;
1018
1019     case 1: /* IO or Read/Write instruction.  */
1020         opcode = (insn >> 27) & 7;
1021         if (opcode < 5) {
1022             uint32_t id;
1023
1024             if (insn & (1 << 25)) {
1025                 id = read_dword(s, s->dsa + sxt24(insn));
1026             } else {
1027                 id = addr;
1028             }
1029             id = (id >> 16) & 0xf;
1030             if (insn & (1 << 26)) {
1031                 addr = s->dsp + sxt24(addr);
1032             }
1033             s->dnad = addr;
1034             switch (opcode) {
1035             case 0: /* Select */
1036                 s->sdid = id;
1037                 if (s->current_dma_len && (s->ssid & 0xf) == id) {
1038                     DPRINTF("Already reselected by target %d\n", id);
1039                     break;
1040                 }
1041                 s->sstat0 |= LSI_SSTAT0_WOA;
1042                 s->scntl1 &= ~LSI_SCNTL1_IARB;
1043                 if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
1044                     DPRINTF("Selected absent target %d\n", id);
1045                     lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
1046                     lsi_disconnect(s);
1047                     break;
1048                 }
1049                 DPRINTF("Selected target %d%s\n",
1050                         id, insn & (1 << 3) ? " ATN" : "");
1051                 /* ??? Linux drivers compain when this is set.  Maybe
1052                    it only applies in low-level mode (unimplemented).
1053                 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
1054                 s->current_dev = s->scsi_dev[id];
1055                 s->current_tag = id << 8;
1056                 s->scntl1 |= LSI_SCNTL1_CON;
1057                 if (insn & (1 << 3)) {
1058                     s->socl |= LSI_SOCL_ATN;
1059                 }
1060                 lsi_set_phase(s, PHASE_MO);
1061                 break;
1062             case 1: /* Disconnect */
1063                 DPRINTF("Wait Disconect\n");
1064                 s->scntl1 &= ~LSI_SCNTL1_CON;
1065                 break;
1066             case 2: /* Wait Reselect */
1067                 lsi_wait_reselect(s);
1068                 break;
1069             case 3: /* Set */
1070                 DPRINTF("Set%s%s%s%s\n",
1071                         insn & (1 << 3) ? " ATN" : "",
1072                         insn & (1 << 6) ? " ACK" : "",
1073                         insn & (1 << 9) ? " TM" : "",
1074                         insn & (1 << 10) ? " CC" : "");
1075                 if (insn & (1 << 3)) {
1076                     s->socl |= LSI_SOCL_ATN;
1077                     lsi_set_phase(s, PHASE_MO);
1078                 }
1079                 if (insn & (1 << 9)) {
1080                     BADF("Target mode not implemented\n");
1081                     exit(1);
1082                 }
1083                 if (insn & (1 << 10))
1084                     s->carry = 1;
1085                 break;
1086             case 4: /* Clear */
1087                 DPRINTF("Clear%s%s%s%s\n",
1088                         insn & (1 << 3) ? " ATN" : "",
1089                         insn & (1 << 6) ? " ACK" : "",
1090                         insn & (1 << 9) ? " TM" : "",
1091                         insn & (1 << 10) ? " CC" : "");
1092                 if (insn & (1 << 3)) {
1093                     s->socl &= ~LSI_SOCL_ATN;
1094                 }
1095                 if (insn & (1 << 10))
1096                     s->carry = 0;
1097                 break;
1098             }
1099         } else {
1100             uint8_t op0;
1101             uint8_t op1;
1102             uint8_t data8;
1103             int reg;
1104             int operator;
1105 #ifdef DEBUG_LSI
1106             static const char *opcode_names[3] =
1107                 {"Write", "Read", "Read-Modify-Write"};
1108             static const char *operator_names[8] =
1109                 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1110 #endif
1111
1112             reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
1113             data8 = (insn >> 8) & 0xff;
1114             opcode = (insn >> 27) & 7;
1115             operator = (insn >> 24) & 7;
1116             DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1117                     opcode_names[opcode - 5], reg,
1118                     operator_names[operator], data8, s->sfbr,
1119                     (insn & (1 << 23)) ? " SFBR" : "");
1120             op0 = op1 = 0;
1121             switch (opcode) {
1122             case 5: /* From SFBR */
1123                 op0 = s->sfbr;
1124                 op1 = data8;
1125                 break;
1126             case 6: /* To SFBR */
1127                 if (operator)
1128                     op0 = lsi_reg_readb(s, reg);
1129                 op1 = data8;
1130                 break;
1131             case 7: /* Read-modify-write */
1132                 if (operator)
1133                     op0 = lsi_reg_readb(s, reg);
1134                 if (insn & (1 << 23)) {
1135                     op1 = s->sfbr;
1136                 } else {
1137                     op1 = data8;
1138                 }
1139                 break;
1140             }
1141
1142             switch (operator) {
1143             case 0: /* move */
1144                 op0 = op1;
1145                 break;
1146             case 1: /* Shift left */
1147                 op1 = op0 >> 7;
1148                 op0 = (op0 << 1) | s->carry;
1149                 s->carry = op1;
1150                 break;
1151             case 2: /* OR */
1152                 op0 |= op1;
1153                 break;
1154             case 3: /* XOR */
1155                 op0 ^= op1;
1156                 break;
1157             case 4: /* AND */
1158                 op0 &= op1;
1159                 break;
1160             case 5: /* SHR */
1161                 op1 = op0 & 1;
1162                 op0 = (op0 >> 1) | (s->carry << 7);
1163                 s->carry = op1;
1164                 break;
1165             case 6: /* ADD */
1166                 op0 += op1;
1167                 s->carry = op0 < op1;
1168                 break;
1169             case 7: /* ADC */
1170                 op0 += op1 + s->carry;
1171                 if (s->carry)
1172                     s->carry = op0 <= op1;
1173                 else
1174                     s->carry = op0 < op1;
1175                 break;
1176             }
1177
1178             switch (opcode) {
1179             case 5: /* From SFBR */
1180             case 7: /* Read-modify-write */
1181                 lsi_reg_writeb(s, reg, op0);
1182                 break;
1183             case 6: /* To SFBR */
1184                 s->sfbr = op0;
1185                 break;
1186             }
1187         }
1188         break;
1189
1190     case 2: /* Transfer Control.  */
1191         {
1192             int cond;
1193             int jmp;
1194
1195             if ((insn & 0x002e0000) == 0) {
1196                 DPRINTF("NOP\n");
1197                 break;
1198             }
1199             if (s->sist1 & LSI_SIST1_STO) {
1200                 DPRINTF("Delayed select timeout\n");
1201                 lsi_stop_script(s);
1202                 break;
1203             }
1204             cond = jmp = (insn & (1 << 19)) != 0;
1205             if (cond == jmp && (insn & (1 << 21))) {
1206                 DPRINTF("Compare carry %d\n", s->carry == jmp);
1207                 cond = s->carry != 0;
1208             }
1209             if (cond == jmp && (insn & (1 << 17))) {
1210                 DPRINTF("Compare phase %d %c= %d\n",
1211                         (s->sstat1 & PHASE_MASK),
1212                         jmp ? '=' : '!',
1213                         ((insn >> 24) & 7));
1214                 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
1215             }
1216             if (cond == jmp && (insn & (1 << 18))) {
1217                 uint8_t mask;
1218
1219                 mask = (~insn >> 8) & 0xff;
1220                 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1221                         s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1222                 cond = (s->sfbr & mask) == (insn & mask);
1223             }
1224             if (cond == jmp) {
1225                 if (insn & (1 << 23)) {
1226                     /* Relative address.  */
1227                     addr = s->dsp + sxt24(addr);
1228                 }
1229                 switch ((insn >> 27) & 7) {
1230                 case 0: /* Jump */
1231                     DPRINTF("Jump to 0x%08x\n", addr);
1232                     s->dsp = addr;
1233                     break;
1234                 case 1: /* Call */
1235                     DPRINTF("Call 0x%08x\n", addr);
1236                     s->temp = s->dsp;
1237                     s->dsp = addr;
1238                     break;
1239                 case 2: /* Return */
1240                     DPRINTF("Return to 0x%08x\n", s->temp);
1241                     s->dsp = s->temp;
1242                     break;
1243                 case 3: /* Interrupt */
1244                     DPRINTF("Interrupt 0x%08x\n", s->dsps);
1245                     if ((insn & (1 << 20)) != 0) {
1246                         s->istat0 |= LSI_ISTAT0_INTF;
1247                         lsi_update_irq(s);
1248                     } else {
1249                         lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1250                     }
1251                     break;
1252                 default:
1253                     DPRINTF("Illegal transfer control\n");
1254                     lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1255                     break;
1256                 }
1257             } else {
1258                 DPRINTF("Control condition failed\n");
1259             }
1260         }
1261         break;
1262
1263     case 3:
1264         if ((insn & (1 << 29)) == 0) {
1265             /* Memory move.  */
1266             uint32_t dest;
1267             /* ??? The docs imply the destination address is loaded into
1268                the TEMP register.  However the Linux drivers rely on
1269                the value being presrved.  */
1270             dest = read_dword(s, s->dsp);
1271             s->dsp += 4;
1272             lsi_memcpy(s, dest, addr, insn & 0xffffff);
1273         } else {
1274             uint8_t data[7];
1275             int reg;
1276             int n;
1277             int i;
1278
1279             if (insn & (1 << 28)) {
1280                 addr = s->dsa + sxt24(addr);
1281             }
1282             n = (insn & 7);
1283             reg = (insn >> 16) & 0xff;
1284             if (insn & (1 << 24)) {
1285                 cpu_physical_memory_read(addr, data, n);
1286                 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1287                         addr, *(int *)data);
1288                 for (i = 0; i < n; i++) {
1289                     lsi_reg_writeb(s, reg + i, data[i]);
1290                 }
1291             } else {
1292                 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1293                 for (i = 0; i < n; i++) {
1294                     data[i] = lsi_reg_readb(s, reg + i);
1295                 }
1296                 cpu_physical_memory_write(addr, data, n);
1297             }
1298         }
1299     }
1300     if (insn_processed > 10000 && !s->waiting) {
1301         /* Some windows drivers make the device spin waiting for a memory
1302            location to change.  If we have been executed a lot of code then
1303            assume this is the case and force an unexpected device disconnect.
1304            This is apparently sufficient to beat the drivers into submission.
1305          */
1306         if (!(s->sien0 & LSI_SIST0_UDC))
1307             fprintf(stderr, "inf. loop with UDC masked\n");
1308         lsi_script_scsi_interrupt(s, LSI_SIST0_UDC, 0);
1309         lsi_disconnect(s);
1310     } else if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
1311         if (s->dcntl & LSI_DCNTL_SSM) {
1312             lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1313         } else {
1314             goto again;
1315         }
1316     }
1317     DPRINTF("SCRIPTS execution stopped\n");
1318 }
1319
1320 static uint8_t lsi_reg_readb(LSIState *s, int offset)
1321 {
1322     uint8_t tmp;
1323 #define CASE_GET_REG24(name, addr) \
1324     case addr: return s->name & 0xff; \
1325     case addr + 1: return (s->name >> 8) & 0xff; \
1326     case addr + 2: return (s->name >> 16) & 0xff;
1327
1328 #define CASE_GET_REG32(name, addr) \
1329     case addr: return s->name & 0xff; \
1330     case addr + 1: return (s->name >> 8) & 0xff; \
1331     case addr + 2: return (s->name >> 16) & 0xff; \
1332     case addr + 3: return (s->name >> 24) & 0xff;
1333
1334 #ifdef DEBUG_LSI_REG
1335     DPRINTF("Read reg %x\n", offset);
1336 #endif
1337     switch (offset) {
1338     case 0x00: /* SCNTL0 */
1339         return s->scntl0;
1340     case 0x01: /* SCNTL1 */
1341         return s->scntl1;
1342     case 0x02: /* SCNTL2 */
1343         return s->scntl2;
1344     case 0x03: /* SCNTL3 */
1345         return s->scntl3;
1346     case 0x04: /* SCID */
1347         return s->scid;
1348     case 0x05: /* SXFER */
1349         return s->sxfer;
1350     case 0x06: /* SDID */
1351         return s->sdid;
1352     case 0x07: /* GPREG0 */
1353         return 0x7f;
1354     case 0x08: /* Revision ID */
1355         return 0x00;
1356     case 0xa: /* SSID */
1357         return s->ssid;
1358     case 0xb: /* SBCL */
1359         /* ??? This is not correct. However it's (hopefully) only
1360            used for diagnostics, so should be ok.  */
1361         return 0;
1362     case 0xc: /* DSTAT */
1363         tmp = s->dstat | 0x80;
1364         if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1365             s->dstat = 0;
1366         lsi_update_irq(s);
1367         return tmp;
1368     case 0x0d: /* SSTAT0 */
1369         return s->sstat0;
1370     case 0x0e: /* SSTAT1 */
1371         return s->sstat1;
1372     case 0x0f: /* SSTAT2 */
1373         return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1374     CASE_GET_REG32(dsa, 0x10)
1375     case 0x14: /* ISTAT0 */
1376         return s->istat0;
1377     case 0x15: /* ISTAT1 */
1378         return s->istat1;
1379     case 0x16: /* MBOX0 */
1380         return s->mbox0;
1381     case 0x17: /* MBOX1 */
1382         return s->mbox1;
1383     case 0x18: /* CTEST0 */
1384         return 0xff;
1385     case 0x19: /* CTEST1 */
1386         return 0;
1387     case 0x1a: /* CTEST2 */
1388         tmp = s->ctest2 | LSI_CTEST2_DACK | LSI_CTEST2_CM;
1389         if (s->istat0 & LSI_ISTAT0_SIGP) {
1390             s->istat0 &= ~LSI_ISTAT0_SIGP;
1391             tmp |= LSI_CTEST2_SIGP;
1392         }
1393         return tmp;
1394     case 0x1b: /* CTEST3 */
1395         return s->ctest3;
1396     CASE_GET_REG32(temp, 0x1c)
1397     case 0x20: /* DFIFO */
1398         return 0;
1399     case 0x21: /* CTEST4 */
1400         return s->ctest4;
1401     case 0x22: /* CTEST5 */
1402         return s->ctest5;
1403     case 0x23: /* CTEST6 */
1404          return 0;
1405     CASE_GET_REG24(dbc, 0x24)
1406     case 0x27: /* DCMD */
1407         return s->dcmd;
1408     CASE_GET_REG32(dnad, 0x28)
1409     CASE_GET_REG32(dsp, 0x2c)
1410     CASE_GET_REG32(dsps, 0x30)
1411     CASE_GET_REG32(scratch[0], 0x34)
1412     case 0x38: /* DMODE */
1413         return s->dmode;
1414     case 0x39: /* DIEN */
1415         return s->dien;
1416     case 0x3a: /* SBR */
1417         return s->sbr;
1418     case 0x3b: /* DCNTL */
1419         return s->dcntl;
1420     case 0x40: /* SIEN0 */
1421         return s->sien0;
1422     case 0x41: /* SIEN1 */
1423         return s->sien1;
1424     case 0x42: /* SIST0 */
1425         tmp = s->sist0;
1426         s->sist0 = 0;
1427         lsi_update_irq(s);
1428         return tmp;
1429     case 0x43: /* SIST1 */
1430         tmp = s->sist1;
1431         s->sist1 = 0;
1432         lsi_update_irq(s);
1433         return tmp;
1434     case 0x46: /* MACNTL */
1435         return 0x0f;
1436     case 0x47: /* GPCNTL0 */
1437         return 0x0f;
1438     case 0x48: /* STIME0 */
1439         return s->stime0;
1440     case 0x4a: /* RESPID0 */
1441         return s->respid0;
1442     case 0x4b: /* RESPID1 */
1443         return s->respid1;
1444     case 0x4d: /* STEST1 */
1445         return s->stest1;
1446     case 0x4e: /* STEST2 */
1447         return s->stest2;
1448     case 0x4f: /* STEST3 */
1449         return s->stest3;
1450     case 0x50: /* SIDL */
1451         /* This is needed by the linux drivers.  We currently only update it
1452            during the MSG IN phase.  */
1453         return s->sidl;
1454     case 0x52: /* STEST4 */
1455         return 0xe0;
1456     case 0x56: /* CCNTL0 */
1457         return s->ccntl0;
1458     case 0x57: /* CCNTL1 */
1459         return s->ccntl1;
1460     case 0x58: /* SBDL */
1461         /* Some drivers peek at the data bus during the MSG IN phase.  */
1462         if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1463             return s->msg[0];
1464         return 0;
1465     case 0x59: /* SBDL high */
1466         return 0;
1467     CASE_GET_REG32(mmrs, 0xa0)
1468     CASE_GET_REG32(mmws, 0xa4)
1469     CASE_GET_REG32(sfs, 0xa8)
1470     CASE_GET_REG32(drs, 0xac)
1471     CASE_GET_REG32(sbms, 0xb0)
1472     CASE_GET_REG32(dbms, 0xb4)
1473     CASE_GET_REG32(dnad64, 0xb8)
1474     CASE_GET_REG32(pmjad1, 0xc0)
1475     CASE_GET_REG32(pmjad2, 0xc4)
1476     CASE_GET_REG32(rbc, 0xc8)
1477     CASE_GET_REG32(ua, 0xcc)
1478     CASE_GET_REG32(ia, 0xd4)
1479     CASE_GET_REG32(sbc, 0xd8)
1480     CASE_GET_REG32(csbc, 0xdc)
1481     }
1482     if (offset >= 0x5c && offset < 0xa0) {
1483         int n;
1484         int shift;
1485         n = (offset - 0x58) >> 2;
1486         shift = (offset & 3) * 8;
1487         return (s->scratch[n] >> shift) & 0xff;
1488     }
1489     BADF("readb 0x%x\n", offset);
1490     exit(1);
1491 #undef CASE_GET_REG24
1492 #undef CASE_GET_REG32
1493 }
1494
1495 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1496 {
1497 #define CASE_SET_REG24(name, addr) \
1498     case addr    : s->name &= 0xffffff00; s->name |= val;       break; \
1499     case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8;  break; \
1500     case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break;
1501
1502 #define CASE_SET_REG32(name, addr) \
1503     case addr    : s->name &= 0xffffff00; s->name |= val;       break; \
1504     case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8;  break; \
1505     case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1506     case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1507
1508 #ifdef DEBUG_LSI_REG
1509     DPRINTF("Write reg %x = %02x\n", offset, val);
1510 #endif
1511     switch (offset) {
1512     case 0x00: /* SCNTL0 */
1513         s->scntl0 = val;
1514         if (val & LSI_SCNTL0_START) {
1515             BADF("Start sequence not implemented\n");
1516         }
1517         break;
1518     case 0x01: /* SCNTL1 */
1519         s->scntl1 = val & ~LSI_SCNTL1_SST;
1520         if (val & LSI_SCNTL1_IARB) {
1521             BADF("Immediate Arbritration not implemented\n");
1522         }
1523         if (val & LSI_SCNTL1_RST) {
1524             s->sstat0 |= LSI_SSTAT0_RST;
1525             lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1526         } else {
1527             s->sstat0 &= ~LSI_SSTAT0_RST;
1528         }
1529         break;
1530     case 0x02: /* SCNTL2 */
1531         val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1532         s->scntl2 = val;
1533         break;
1534     case 0x03: /* SCNTL3 */
1535         s->scntl3 = val;
1536         break;
1537     case 0x04: /* SCID */
1538         s->scid = val;
1539         break;
1540     case 0x05: /* SXFER */
1541         s->sxfer = val;
1542         break;
1543     case 0x06: /* SDID */
1544         if ((val & 0xf) != (s->ssid & 0xf))
1545             BADF("Destination ID does not match SSID\n");
1546         s->sdid = val & 0xf;
1547         break;
1548     case 0x07: /* GPREG0 */
1549         break;
1550     case 0x08: /* SFBR */
1551         /* The CPU is not allowed to write to this register.  However the
1552            SCRIPTS register move instructions are.  */
1553         s->sfbr = val;
1554         break;
1555     case 0x0a: case 0x0b:
1556         /* Openserver writes to these readonly registers on startup */
1557         return;
1558     case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1559         /* Linux writes to these readonly registers on startup.  */
1560         return;
1561     CASE_SET_REG32(dsa, 0x10)
1562     case 0x14: /* ISTAT0 */
1563         s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1564         if (val & LSI_ISTAT0_ABRT) {
1565             lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1566         }
1567         if (val & LSI_ISTAT0_INTF) {
1568             s->istat0 &= ~LSI_ISTAT0_INTF;
1569             lsi_update_irq(s);
1570         }
1571         if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1572             DPRINTF("Woken by SIGP\n");
1573             s->waiting = 0;
1574             s->dsp = s->dnad;
1575             lsi_execute_script(s);
1576         }
1577         if (val & LSI_ISTAT0_SRST) {
1578             lsi_soft_reset(s);
1579         }
1580         break;
1581     case 0x16: /* MBOX0 */
1582         s->mbox0 = val;
1583         break;
1584     case 0x17: /* MBOX1 */
1585         s->mbox1 = val;
1586         break;
1587     case 0x1a: /* CTEST2 */
1588         s->ctest2 = val & LSI_CTEST2_PCICIE;
1589         break;
1590     case 0x1b: /* CTEST3 */
1591         s->ctest3 = val & 0x0f;
1592         break;
1593     CASE_SET_REG32(temp, 0x1c)
1594     case 0x21: /* CTEST4 */
1595         if (val & 7) {
1596            BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1597         }
1598         s->ctest4 = val;
1599         break;
1600     case 0x22: /* CTEST5 */
1601         if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1602             BADF("CTEST5 DMA increment not implemented\n");
1603         }
1604         s->ctest5 = val;
1605         break;
1606     CASE_SET_REG24(dbc, 0x24)
1607     CASE_SET_REG32(dnad, 0x28)
1608     case 0x2c: /* DSP[0:7] */
1609         s->dsp &= 0xffffff00;
1610         s->dsp |= val;
1611         break;
1612     case 0x2d: /* DSP[8:15] */
1613         s->dsp &= 0xffff00ff;
1614         s->dsp |= val << 8;
1615         break;
1616     case 0x2e: /* DSP[16:23] */
1617         s->dsp &= 0xff00ffff;
1618         s->dsp |= val << 16;
1619         break;
1620     case 0x2f: /* DSP[24:31] */
1621         s->dsp &= 0x00ffffff;
1622         s->dsp |= val << 24;
1623         if ((s->dmode & LSI_DMODE_MAN) == 0
1624             && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1625             lsi_execute_script(s);
1626         break;
1627     CASE_SET_REG32(dsps, 0x30)
1628     CASE_SET_REG32(scratch[0], 0x34)
1629     case 0x38: /* DMODE */
1630         if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1631             BADF("IO mappings not implemented\n");
1632         }
1633         s->dmode = val;
1634         break;
1635     case 0x39: /* DIEN */
1636         s->dien = val;
1637         lsi_update_irq(s);
1638         break;
1639     case 0x3a: /* SBR */
1640         s->sbr = val;
1641         break;
1642     case 0x3b: /* DCNTL */
1643         s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1644         if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1645             lsi_execute_script(s);
1646         break;
1647     case 0x40: /* SIEN0 */
1648         s->sien0 = val;
1649         lsi_update_irq(s);
1650         break;
1651     case 0x41: /* SIEN1 */
1652         s->sien1 = val;
1653         lsi_update_irq(s);
1654         break;
1655     case 0x47: /* GPCNTL0 */
1656         break;
1657     case 0x48: /* STIME0 */
1658         s->stime0 = val;
1659         break;
1660     case 0x49: /* STIME1 */
1661         if (val & 0xf) {
1662             DPRINTF("General purpose timer not implemented\n");
1663             /* ??? Raising the interrupt immediately seems to be sufficient
1664                to keep the FreeBSD driver happy.  */
1665             lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1666         }
1667         break;
1668     case 0x4a: /* RESPID0 */
1669         s->respid0 = val;
1670         break;
1671     case 0x4b: /* RESPID1 */
1672         s->respid1 = val;
1673         break;
1674     case 0x4d: /* STEST1 */
1675         s->stest1 = val;
1676         break;
1677     case 0x4e: /* STEST2 */
1678         if (val & 1) {
1679             BADF("Low level mode not implemented\n");
1680         }
1681         s->stest2 = val;
1682         break;
1683     case 0x4f: /* STEST3 */
1684         if (val & 0x41) {
1685             BADF("SCSI FIFO test mode not implemented\n");
1686         }
1687         s->stest3 = val;
1688         break;
1689     case 0x56: /* CCNTL0 */
1690         s->ccntl0 = val;
1691         break;
1692     case 0x57: /* CCNTL1 */
1693         s->ccntl1 = val;
1694         break;
1695     CASE_SET_REG32(mmrs, 0xa0)
1696     CASE_SET_REG32(mmws, 0xa4)
1697     CASE_SET_REG32(sfs, 0xa8)
1698     CASE_SET_REG32(drs, 0xac)
1699     CASE_SET_REG32(sbms, 0xb0)
1700     CASE_SET_REG32(dbms, 0xb4)
1701     CASE_SET_REG32(dnad64, 0xb8)
1702     CASE_SET_REG32(pmjad1, 0xc0)
1703     CASE_SET_REG32(pmjad2, 0xc4)
1704     CASE_SET_REG32(rbc, 0xc8)
1705     CASE_SET_REG32(ua, 0xcc)
1706     CASE_SET_REG32(ia, 0xd4)
1707     CASE_SET_REG32(sbc, 0xd8)
1708     CASE_SET_REG32(csbc, 0xdc)
1709     default:
1710         if (offset >= 0x5c && offset < 0xa0) {
1711             int n;
1712             int shift;
1713             n = (offset - 0x58) >> 2;
1714             shift = (offset & 3) * 8;
1715             s->scratch[n] &= ~(0xff << shift);
1716             s->scratch[n] |= (val & 0xff) << shift;
1717         } else {
1718             BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1719         }
1720     }
1721 #undef CASE_SET_REG24
1722 #undef CASE_SET_REG32
1723 }
1724
1725 static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1726 {
1727     LSIState *s = (LSIState *)opaque;
1728
1729     lsi_reg_writeb(s, addr & 0xff, val);
1730 }
1731
1732 static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1733 {
1734     LSIState *s = (LSIState *)opaque;
1735
1736     addr &= 0xff;
1737     lsi_reg_writeb(s, addr, val & 0xff);
1738     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1739 }
1740
1741 static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1742 {
1743     LSIState *s = (LSIState *)opaque;
1744
1745     addr &= 0xff;
1746     lsi_reg_writeb(s, addr, val & 0xff);
1747     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1748     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1749     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1750 }
1751
1752 static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1753 {
1754     LSIState *s = (LSIState *)opaque;
1755
1756     return lsi_reg_readb(s, addr & 0xff);
1757 }
1758
1759 static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1760 {
1761     LSIState *s = (LSIState *)opaque;
1762     uint32_t val;
1763
1764     addr &= 0xff;
1765     val = lsi_reg_readb(s, addr);
1766     val |= lsi_reg_readb(s, addr + 1) << 8;
1767     return val;
1768 }
1769
1770 static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1771 {
1772     LSIState *s = (LSIState *)opaque;
1773     uint32_t val;
1774     addr &= 0xff;
1775     val = lsi_reg_readb(s, addr);
1776     val |= lsi_reg_readb(s, addr + 1) << 8;
1777     val |= lsi_reg_readb(s, addr + 2) << 16;
1778     val |= lsi_reg_readb(s, addr + 3) << 24;
1779     return val;
1780 }
1781
1782 static CPUReadMemoryFunc * const lsi_mmio_readfn[3] = {
1783     lsi_mmio_readb,
1784     lsi_mmio_readw,
1785     lsi_mmio_readl,
1786 };
1787
1788 static CPUWriteMemoryFunc * const lsi_mmio_writefn[3] = {
1789     lsi_mmio_writeb,
1790     lsi_mmio_writew,
1791     lsi_mmio_writel,
1792 };
1793
1794 static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1795 {
1796     LSIState *s = (LSIState *)opaque;
1797     uint32_t newval;
1798     int shift;
1799
1800     addr &= 0x1fff;
1801     newval = s->script_ram[addr >> 2];
1802     shift = (addr & 3) * 8;
1803     newval &= ~(0xff << shift);
1804     newval |= val << shift;
1805     s->script_ram[addr >> 2] = newval;
1806 }
1807
1808 static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1809 {
1810     LSIState *s = (LSIState *)opaque;
1811     uint32_t newval;
1812
1813     addr &= 0x1fff;
1814     newval = s->script_ram[addr >> 2];
1815     if (addr & 2) {
1816         newval = (newval & 0xffff) | (val << 16);
1817     } else {
1818         newval = (newval & 0xffff0000) | val;
1819     }
1820     s->script_ram[addr >> 2] = newval;
1821 }
1822
1823
1824 static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1825 {
1826     LSIState *s = (LSIState *)opaque;
1827
1828     addr &= 0x1fff;
1829     s->script_ram[addr >> 2] = val;
1830 }
1831
1832 static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1833 {
1834     LSIState *s = (LSIState *)opaque;
1835     uint32_t val;
1836
1837     addr &= 0x1fff;
1838     val = s->script_ram[addr >> 2];
1839     val >>= (addr & 3) * 8;
1840     return val & 0xff;
1841 }
1842
1843 static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1844 {
1845     LSIState *s = (LSIState *)opaque;
1846     uint32_t val;
1847
1848     addr &= 0x1fff;
1849     val = s->script_ram[addr >> 2];
1850     if (addr & 2)
1851         val >>= 16;
1852     return le16_to_cpu(val);
1853 }
1854
1855 static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1856 {
1857     LSIState *s = (LSIState *)opaque;
1858
1859     addr &= 0x1fff;
1860     return le32_to_cpu(s->script_ram[addr >> 2]);
1861 }
1862
1863 static CPUReadMemoryFunc * const lsi_ram_readfn[3] = {
1864     lsi_ram_readb,
1865     lsi_ram_readw,
1866     lsi_ram_readl,
1867 };
1868
1869 static CPUWriteMemoryFunc * const lsi_ram_writefn[3] = {
1870     lsi_ram_writeb,
1871     lsi_ram_writew,
1872     lsi_ram_writel,
1873 };
1874
1875 static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1876 {
1877     LSIState *s = (LSIState *)opaque;
1878     return lsi_reg_readb(s, addr & 0xff);
1879 }
1880
1881 static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1882 {
1883     LSIState *s = (LSIState *)opaque;
1884     uint32_t val;
1885     addr &= 0xff;
1886     val = lsi_reg_readb(s, addr);
1887     val |= lsi_reg_readb(s, addr + 1) << 8;
1888     return val;
1889 }
1890
1891 static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1892 {
1893     LSIState *s = (LSIState *)opaque;
1894     uint32_t val;
1895     addr &= 0xff;
1896     val = lsi_reg_readb(s, addr);
1897     val |= lsi_reg_readb(s, addr + 1) << 8;
1898     val |= lsi_reg_readb(s, addr + 2) << 16;
1899     val |= lsi_reg_readb(s, addr + 3) << 24;
1900     return val;
1901 }
1902
1903 static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1904 {
1905     LSIState *s = (LSIState *)opaque;
1906     lsi_reg_writeb(s, addr & 0xff, val);
1907 }
1908
1909 static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1910 {
1911     LSIState *s = (LSIState *)opaque;
1912     addr &= 0xff;
1913     lsi_reg_writeb(s, addr, val & 0xff);
1914     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1915 }
1916
1917 static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1918 {
1919     LSIState *s = (LSIState *)opaque;
1920     addr &= 0xff;
1921     lsi_reg_writeb(s, addr, val & 0xff);
1922     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1923     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1924     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1925 }
1926
1927 static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
1928                            uint32_t addr, uint32_t size, int type)
1929 {
1930     LSIState *s = (LSIState *)pci_dev;
1931
1932     DPRINTF("Mapping IO at %08x\n", addr);
1933
1934     register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1935     register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1936     register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1937     register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1938     register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1939     register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1940 }
1941
1942 static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
1943                             uint32_t addr, uint32_t size, int type)
1944 {
1945     LSIState *s = (LSIState *)pci_dev;
1946
1947     DPRINTF("Mapping ram at %08x\n", addr);
1948     s->script_ram_base = addr;
1949     cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1950 }
1951
1952 static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
1953                              uint32_t addr, uint32_t size, int type)
1954 {
1955     LSIState *s = (LSIState *)pci_dev;
1956
1957     DPRINTF("Mapping registers at %08x\n", addr);
1958     cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
1959 }
1960
1961 void lsi_scsi_attach(DeviceState *host, BlockDriverState *bd, int id)
1962 {
1963     LSIState *s = (LSIState *)host;
1964
1965     if (id < 0) {
1966         for (id = 0; id < LSI_MAX_DEVS; id++) {
1967             if (s->scsi_dev[id] == NULL)
1968                 break;
1969         }
1970     }
1971     if (id >= LSI_MAX_DEVS) {
1972         BADF("Bad Device ID %d\n", id);
1973         return;
1974     }
1975     if (s->scsi_dev[id]) {
1976         DPRINTF("Destroying device %d\n", id);
1977         s->scsi_dev[id]->destroy(s->scsi_dev[id]);
1978     }
1979     DPRINTF("Attaching block device %d\n", id);
1980     s->scsi_dev[id] = scsi_generic_init(bd, 1, lsi_command_complete, s);
1981     if (s->scsi_dev[id] == NULL)
1982         s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
1983     bd->private = &s->pci_dev;
1984 }
1985
1986 static void lsi_scsi_save(QEMUFile *f, void *opaque)
1987 {
1988     LSIState *s = opaque;
1989
1990     assert(s->dma_buf == NULL);
1991     assert(s->current_dma_len == 0);
1992     assert(s->active_commands == 0);
1993
1994     pci_device_save(&s->pci_dev, f);
1995
1996     qemu_put_sbe32s(f, &s->carry);
1997     qemu_put_sbe32s(f, &s->sense);
1998     qemu_put_sbe32s(f, &s->msg_action);
1999     qemu_put_sbe32s(f, &s->msg_len);
2000     qemu_put_buffer(f, s->msg, sizeof (s->msg));
2001     qemu_put_sbe32s(f, &s->waiting);
2002
2003     qemu_put_be32s(f, &s->dsa);
2004     qemu_put_be32s(f, &s->temp);
2005     qemu_put_be32s(f, &s->dnad);
2006     qemu_put_be32s(f, &s->dbc);
2007     qemu_put_8s(f, &s->istat0);
2008     qemu_put_8s(f, &s->istat1);
2009     qemu_put_8s(f, &s->dcmd);
2010     qemu_put_8s(f, &s->dstat);
2011     qemu_put_8s(f, &s->dien);
2012     qemu_put_8s(f, &s->sist0);
2013     qemu_put_8s(f, &s->sist1);
2014     qemu_put_8s(f, &s->sien0);
2015     qemu_put_8s(f, &s->sien1);
2016     qemu_put_8s(f, &s->mbox0);
2017     qemu_put_8s(f, &s->mbox1);
2018     qemu_put_8s(f, &s->dfifo);
2019     qemu_put_8s(f, &s->ctest2);
2020     qemu_put_8s(f, &s->ctest3);
2021     qemu_put_8s(f, &s->ctest4);
2022     qemu_put_8s(f, &s->ctest5);
2023     qemu_put_8s(f, &s->ccntl0);
2024     qemu_put_8s(f, &s->ccntl1);
2025     qemu_put_be32s(f, &s->dsp);
2026     qemu_put_be32s(f, &s->dsps);
2027     qemu_put_8s(f, &s->dmode);
2028     qemu_put_8s(f, &s->dcntl);
2029     qemu_put_8s(f, &s->scntl0);
2030     qemu_put_8s(f, &s->scntl1);
2031     qemu_put_8s(f, &s->scntl2);
2032     qemu_put_8s(f, &s->scntl3);
2033     qemu_put_8s(f, &s->sstat0);
2034     qemu_put_8s(f, &s->sstat1);
2035     qemu_put_8s(f, &s->scid);
2036     qemu_put_8s(f, &s->sxfer);
2037     qemu_put_8s(f, &s->socl);
2038     qemu_put_8s(f, &s->sdid);
2039     qemu_put_8s(f, &s->ssid);
2040     qemu_put_8s(f, &s->sfbr);
2041     qemu_put_8s(f, &s->stest1);
2042     qemu_put_8s(f, &s->stest2);
2043     qemu_put_8s(f, &s->stest3);
2044     qemu_put_8s(f, &s->sidl);
2045     qemu_put_8s(f, &s->stime0);
2046     qemu_put_8s(f, &s->respid0);
2047     qemu_put_8s(f, &s->respid1);
2048     qemu_put_be32s(f, &s->mmrs);
2049     qemu_put_be32s(f, &s->mmws);
2050     qemu_put_be32s(f, &s->sfs);
2051     qemu_put_be32s(f, &s->drs);
2052     qemu_put_be32s(f, &s->sbms);
2053     qemu_put_be32s(f, &s->dbms);
2054     qemu_put_be32s(f, &s->dnad64);
2055     qemu_put_be32s(f, &s->pmjad1);
2056     qemu_put_be32s(f, &s->pmjad2);
2057     qemu_put_be32s(f, &s->rbc);
2058     qemu_put_be32s(f, &s->ua);
2059     qemu_put_be32s(f, &s->ia);
2060     qemu_put_be32s(f, &s->sbc);
2061     qemu_put_be32s(f, &s->csbc);
2062     qemu_put_buffer(f, (uint8_t *)s->scratch, sizeof (s->scratch));
2063     qemu_put_8s(f, &s->sbr);
2064
2065     qemu_put_buffer(f, (uint8_t *)s->script_ram, sizeof (s->script_ram));
2066 }
2067
2068 static int lsi_scsi_load(QEMUFile *f, void *opaque, int version_id)
2069 {
2070     LSIState *s = opaque;
2071     int ret;
2072
2073     if (version_id > 0) {
2074         return -EINVAL;
2075     }
2076
2077     if ((ret = pci_device_load(&s->pci_dev, f)) < 0)
2078         return ret;
2079
2080     qemu_get_sbe32s(f, &s->carry);
2081     qemu_get_sbe32s(f, &s->sense);
2082     qemu_get_sbe32s(f, &s->msg_action);
2083     qemu_get_sbe32s(f, &s->msg_len);
2084     qemu_get_buffer(f, s->msg, sizeof (s->msg));
2085     qemu_get_sbe32s(f, &s->waiting);
2086
2087     qemu_get_be32s(f, &s->dsa);
2088     qemu_get_be32s(f, &s->temp);
2089     qemu_get_be32s(f, &s->dnad);
2090     qemu_get_be32s(f, &s->dbc);
2091     qemu_get_8s(f, &s->istat0);
2092     qemu_get_8s(f, &s->istat1);
2093     qemu_get_8s(f, &s->dcmd);
2094     qemu_get_8s(f, &s->dstat);
2095     qemu_get_8s(f, &s->dien);
2096     qemu_get_8s(f, &s->sist0);
2097     qemu_get_8s(f, &s->sist1);
2098     qemu_get_8s(f, &s->sien0);
2099     qemu_get_8s(f, &s->sien1);
2100     qemu_get_8s(f, &s->mbox0);
2101     qemu_get_8s(f, &s->mbox1);
2102     qemu_get_8s(f, &s->dfifo);
2103     qemu_get_8s(f, &s->ctest2);
2104     qemu_get_8s(f, &s->ctest3);
2105     qemu_get_8s(f, &s->ctest4);
2106     qemu_get_8s(f, &s->ctest5);
2107     qemu_get_8s(f, &s->ccntl0);
2108     qemu_get_8s(f, &s->ccntl1);
2109     qemu_get_be32s(f, &s->dsp);
2110     qemu_get_be32s(f, &s->dsps);
2111     qemu_get_8s(f, &s->dmode);
2112     qemu_get_8s(f, &s->dcntl);
2113     qemu_get_8s(f, &s->scntl0);
2114     qemu_get_8s(f, &s->scntl1);
2115     qemu_get_8s(f, &s->scntl2);
2116     qemu_get_8s(f, &s->scntl3);
2117     qemu_get_8s(f, &s->sstat0);
2118     qemu_get_8s(f, &s->sstat1);
2119     qemu_get_8s(f, &s->scid);
2120     qemu_get_8s(f, &s->sxfer);
2121     qemu_get_8s(f, &s->socl);
2122     qemu_get_8s(f, &s->sdid);
2123     qemu_get_8s(f, &s->ssid);
2124     qemu_get_8s(f, &s->sfbr);
2125     qemu_get_8s(f, &s->stest1);
2126     qemu_get_8s(f, &s->stest2);
2127     qemu_get_8s(f, &s->stest3);
2128     qemu_get_8s(f, &s->sidl);
2129     qemu_get_8s(f, &s->stime0);
2130     qemu_get_8s(f, &s->respid0);
2131     qemu_get_8s(f, &s->respid1);
2132     qemu_get_be32s(f, &s->mmrs);
2133     qemu_get_be32s(f, &s->mmws);
2134     qemu_get_be32s(f, &s->sfs);
2135     qemu_get_be32s(f, &s->drs);
2136     qemu_get_be32s(f, &s->sbms);
2137     qemu_get_be32s(f, &s->dbms);
2138     qemu_get_be32s(f, &s->dnad64);
2139     qemu_get_be32s(f, &s->pmjad1);
2140     qemu_get_be32s(f, &s->pmjad2);
2141     qemu_get_be32s(f, &s->rbc);
2142     qemu_get_be32s(f, &s->ua);
2143     qemu_get_be32s(f, &s->ia);
2144     qemu_get_be32s(f, &s->sbc);
2145     qemu_get_be32s(f, &s->csbc);
2146     qemu_get_buffer(f, (uint8_t *)s->scratch, sizeof (s->scratch));
2147     qemu_get_8s(f, &s->sbr);
2148
2149     qemu_get_buffer(f, (uint8_t *)s->script_ram, sizeof (s->script_ram));
2150
2151     return 0;
2152 }
2153
2154 static int lsi_scsi_uninit(PCIDevice *d)
2155 {
2156     LSIState *s = (LSIState *) d;
2157
2158     cpu_unregister_io_memory(s->mmio_io_addr);
2159     cpu_unregister_io_memory(s->ram_io_addr);
2160
2161     qemu_free(s->queue);
2162
2163     return 0;
2164 }
2165
2166 static void lsi_scsi_init(PCIDevice *dev)
2167 {
2168     LSIState *s = (LSIState *)dev;
2169     uint8_t *pci_conf;
2170
2171     pci_conf = s->pci_dev.config;
2172
2173     /* PCI Vendor ID (word) */
2174     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_LSI_LOGIC);
2175     /* PCI device ID (word) */
2176     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_LSI_53C895A);
2177     /* PCI base class code */
2178     pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_SCSI);
2179     /* PCI subsystem ID */
2180     pci_conf[0x2e] = 0x00;
2181     pci_conf[0x2f] = 0x10;
2182     /* PCI latency timer = 255 */
2183     pci_conf[0x0d] = 0xff;
2184     /* Interrupt pin 1 */
2185     pci_conf[0x3d] = 0x01;
2186
2187     s->mmio_io_addr = cpu_register_io_memory(lsi_mmio_readfn,
2188                                              lsi_mmio_writefn, s);
2189     s->ram_io_addr = cpu_register_io_memory(lsi_ram_readfn,
2190                                             lsi_ram_writefn, s);
2191
2192     pci_register_bar((struct PCIDevice *)s, 0, 256,
2193                            PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);
2194     pci_register_bar((struct PCIDevice *)s, 1, 0x400,
2195                            PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);
2196     pci_register_bar((struct PCIDevice *)s, 2, 0x2000,
2197                            PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);
2198     s->queue = qemu_malloc(sizeof(lsi_queue));
2199     s->queue_len = 1;
2200     s->active_commands = 0;
2201     s->pci_dev.unregister = lsi_scsi_uninit;
2202
2203     lsi_soft_reset(s);
2204
2205     scsi_bus_new(&dev->qdev, lsi_scsi_attach);
2206
2207     register_savevm("lsiscsi", -1, 0, lsi_scsi_save, lsi_scsi_load, s);
2208 }
2209
2210 static PCIDeviceInfo lsi_info = {
2211     .qdev.name = "lsi53c895a",
2212     .qdev.size = sizeof(LSIState),
2213     .init      = lsi_scsi_init,
2214 };
2215
2216 static void lsi53c895a_register_devices(void)
2217 {
2218     pci_qdev_register(&lsi_info);
2219 }
2220
2221 device_init(lsi53c895a_register_devices);