2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "tcg-be-null.h"
28 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
64 /* Define some temporary registers. T2 is used for constant generation. */
65 #define TCG_REG_T1 TCG_REG_G1
66 #define TCG_REG_T2 TCG_REG_O7
68 #ifdef CONFIG_USE_GUEST_BASE
69 # define TCG_GUEST_BASE_REG TCG_REG_I5
71 # define TCG_GUEST_BASE_REG TCG_REG_G0
74 static const int tcg_target_reg_alloc_order
[] = {
104 static const int tcg_target_call_iarg_regs
[6] = {
113 static const int tcg_target_call_oarg_regs
[] = {
120 #define INSN_OP(x) ((x) << 30)
121 #define INSN_OP2(x) ((x) << 22)
122 #define INSN_OP3(x) ((x) << 19)
123 #define INSN_OPF(x) ((x) << 5)
124 #define INSN_RD(x) ((x) << 25)
125 #define INSN_RS1(x) ((x) << 14)
126 #define INSN_RS2(x) (x)
127 #define INSN_ASI(x) ((x) << 5)
129 #define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff))
130 #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
131 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
132 #define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20))
133 #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
134 #define INSN_COND(x) ((x) << 25)
152 #define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2))
161 #define MOVCC_ICC (1 << 18)
162 #define MOVCC_XCC (1 << 18 | 1 << 12)
165 #define BPCC_XCC (2 << 20)
166 #define BPCC_PT (1 << 19)
168 #define BPCC_A (1 << 29)
170 #define BPR_PT BPCC_PT
172 #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
173 #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
174 #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
175 #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
176 #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
177 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
178 #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
179 #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
180 #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
181 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
182 #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x08))
183 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
184 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
185 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
186 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
187 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
188 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
189 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
190 #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
191 #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f))
193 #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
194 #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
195 #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
197 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
198 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
199 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
201 #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
202 #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
203 #define JMPL (INSN_OP(2) | INSN_OP3(0x38))
204 #define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
205 #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
206 #define SETHI (INSN_OP(0) | INSN_OP2(0x4))
207 #define CALL INSN_OP(1)
208 #define LDUB (INSN_OP(3) | INSN_OP3(0x01))
209 #define LDSB (INSN_OP(3) | INSN_OP3(0x09))
210 #define LDUH (INSN_OP(3) | INSN_OP3(0x02))
211 #define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
212 #define LDUW (INSN_OP(3) | INSN_OP3(0x00))
213 #define LDSW (INSN_OP(3) | INSN_OP3(0x08))
214 #define LDX (INSN_OP(3) | INSN_OP3(0x0b))
215 #define STB (INSN_OP(3) | INSN_OP3(0x05))
216 #define STH (INSN_OP(3) | INSN_OP3(0x06))
217 #define STW (INSN_OP(3) | INSN_OP3(0x04))
218 #define STX (INSN_OP(3) | INSN_OP3(0x0e))
219 #define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
220 #define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
221 #define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
222 #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
223 #define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
224 #define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
225 #define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
226 #define STBA (INSN_OP(3) | INSN_OP3(0x15))
227 #define STHA (INSN_OP(3) | INSN_OP3(0x16))
228 #define STWA (INSN_OP(3) | INSN_OP3(0x14))
229 #define STXA (INSN_OP(3) | INSN_OP3(0x1e))
231 #ifndef ASI_PRIMARY_LITTLE
232 #define ASI_PRIMARY_LITTLE 0x88
235 #define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE))
236 #define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE))
237 #define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE))
238 #define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE))
239 #define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE))
241 #define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE))
242 #define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
243 #define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
245 static inline int check_fit_tl(tcg_target_long val
, unsigned int bits
)
247 return (val
<< ((sizeof(tcg_target_long
) * 8 - bits
))
248 >> (sizeof(tcg_target_long
) * 8 - bits
)) == val
;
251 static inline int check_fit_i32(uint32_t val
, unsigned int bits
)
253 return ((val
<< (32 - bits
)) >> (32 - bits
)) == val
;
256 static void patch_reloc(uint8_t *code_ptr
, int type
,
257 intptr_t value
, intptr_t addend
)
263 if (value
!= (uint32_t)value
) {
266 *(uint32_t *)code_ptr
= value
;
268 case R_SPARC_WDISP16
:
269 value
-= (intptr_t)code_ptr
;
270 if (!check_fit_tl(value
>> 2, 16)) {
273 insn
= *(uint32_t *)code_ptr
;
274 insn
&= ~INSN_OFF16(-1);
275 insn
|= INSN_OFF16(value
);
276 *(uint32_t *)code_ptr
= insn
;
278 case R_SPARC_WDISP19
:
279 value
-= (intptr_t)code_ptr
;
280 if (!check_fit_tl(value
>> 2, 19)) {
283 insn
= *(uint32_t *)code_ptr
;
284 insn
&= ~INSN_OFF19(-1);
285 insn
|= INSN_OFF19(value
);
286 *(uint32_t *)code_ptr
= insn
;
293 /* parse target specific constraints */
294 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
301 ct
->ct
|= TCG_CT_REG
;
302 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
304 case 'L': /* qemu_ld/st constraint */
305 ct
->ct
|= TCG_CT_REG
;
306 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
308 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_O0
);
309 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_O1
);
310 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_O2
);
313 ct
->ct
|= TCG_CT_CONST_S11
;
316 ct
->ct
|= TCG_CT_CONST_S13
;
319 ct
->ct
|= TCG_CT_CONST_ZERO
;
329 /* test if a constant matches the constraint */
330 static inline int tcg_target_const_match(tcg_target_long val
,
331 const TCGArgConstraint
*arg_ct
)
335 if (ct
& TCG_CT_CONST
) {
337 } else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0) {
339 } else if ((ct
& TCG_CT_CONST_S11
) && check_fit_tl(val
, 11)) {
341 } else if ((ct
& TCG_CT_CONST_S13
) && check_fit_tl(val
, 13)) {
348 static inline void tcg_out_arith(TCGContext
*s
, int rd
, int rs1
, int rs2
,
351 tcg_out32(s
, op
| INSN_RD(rd
) | INSN_RS1(rs1
) |
355 static inline void tcg_out_arithi(TCGContext
*s
, int rd
, int rs1
,
356 uint32_t offset
, int op
)
358 tcg_out32(s
, op
| INSN_RD(rd
) | INSN_RS1(rs1
) |
362 static void tcg_out_arithc(TCGContext
*s
, int rd
, int rs1
,
363 int val2
, int val2const
, int op
)
365 tcg_out32(s
, op
| INSN_RD(rd
) | INSN_RS1(rs1
)
366 | (val2const
? INSN_IMM13(val2
) : INSN_RS2(val2
)));
369 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
,
370 TCGReg ret
, TCGReg arg
)
373 tcg_out_arith(s
, ret
, arg
, TCG_REG_G0
, ARITH_OR
);
377 static inline void tcg_out_sethi(TCGContext
*s
, int ret
, uint32_t arg
)
379 tcg_out32(s
, SETHI
| INSN_RD(ret
) | ((arg
& 0xfffffc00) >> 10));
382 static inline void tcg_out_movi_imm13(TCGContext
*s
, int ret
, uint32_t arg
)
384 tcg_out_arithi(s
, ret
, TCG_REG_G0
, arg
, ARITH_OR
);
387 static inline void tcg_out_movi_imm32(TCGContext
*s
, int ret
, uint32_t arg
)
389 if (check_fit_tl(arg
, 13))
390 tcg_out_movi_imm13(s
, ret
, arg
);
392 tcg_out_sethi(s
, ret
, arg
);
394 tcg_out_arithi(s
, ret
, ret
, arg
& 0x3ff, ARITH_OR
);
398 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
399 TCGReg ret
, tcg_target_long arg
)
401 /* All 32-bit constants, as well as 64-bit constants with
402 no high bits set go through movi_imm32. */
403 if (TCG_TARGET_REG_BITS
== 32
404 || type
== TCG_TYPE_I32
405 || (arg
& ~(tcg_target_long
)0xffffffff) == 0) {
406 tcg_out_movi_imm32(s
, ret
, arg
);
407 } else if (check_fit_tl(arg
, 13)) {
408 /* A 13-bit constant sign-extended to 64-bits. */
409 tcg_out_movi_imm13(s
, ret
, arg
);
410 } else if (check_fit_tl(arg
, 32)) {
411 /* A 32-bit constant sign-extended to 64-bits. */
412 tcg_out_sethi(s
, ret
, ~arg
);
413 tcg_out_arithi(s
, ret
, ret
, (arg
& 0x3ff) | -0x400, ARITH_XOR
);
415 tcg_out_movi_imm32(s
, ret
, arg
>> (TCG_TARGET_REG_BITS
/ 2));
416 tcg_out_arithi(s
, ret
, ret
, 32, SHIFT_SLLX
);
417 tcg_out_movi_imm32(s
, TCG_REG_T2
, arg
);
418 tcg_out_arith(s
, ret
, ret
, TCG_REG_T2
, ARITH_OR
);
422 static inline void tcg_out_ldst_rr(TCGContext
*s
, int data
, int a1
,
425 tcg_out32(s
, op
| INSN_RD(data
) | INSN_RS1(a1
) | INSN_RS2(a2
));
428 static inline void tcg_out_ldst(TCGContext
*s
, int ret
, int addr
,
431 if (check_fit_tl(offset
, 13)) {
432 tcg_out32(s
, op
| INSN_RD(ret
) | INSN_RS1(addr
) |
435 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_T1
, offset
);
436 tcg_out_ldst_rr(s
, ret
, addr
, TCG_REG_T1
, op
);
440 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
,
441 TCGReg arg1
, intptr_t arg2
)
443 tcg_out_ldst(s
, ret
, arg1
, arg2
, (type
== TCG_TYPE_I32
? LDUW
: LDX
));
446 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
447 TCGReg arg1
, intptr_t arg2
)
449 tcg_out_ldst(s
, arg
, arg1
, arg2
, (type
== TCG_TYPE_I32
? STW
: STX
));
452 static inline void tcg_out_ld_ptr(TCGContext
*s
, int ret
,
455 if (!check_fit_tl(arg
, 10)) {
456 tcg_out_movi(s
, TCG_TYPE_PTR
, ret
, arg
& ~0x3ff);
458 tcg_out_ld(s
, TCG_TYPE_PTR
, ret
, ret
, arg
& 0x3ff);
461 static inline void tcg_out_sety(TCGContext
*s
, int rs
)
463 tcg_out32(s
, WRY
| INSN_RS1(TCG_REG_G0
) | INSN_RS2(rs
));
466 static inline void tcg_out_rdy(TCGContext
*s
, int rd
)
468 tcg_out32(s
, RDY
| INSN_RD(rd
));
471 static inline void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
474 if (check_fit_tl(val
, 13))
475 tcg_out_arithi(s
, reg
, reg
, val
, ARITH_ADD
);
477 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_T1
, val
);
478 tcg_out_arith(s
, reg
, reg
, TCG_REG_T1
, ARITH_ADD
);
483 static inline void tcg_out_andi(TCGContext
*s
, int rd
, int rs
,
487 if (check_fit_tl(val
, 13))
488 tcg_out_arithi(s
, rd
, rs
, val
, ARITH_AND
);
490 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_T1
, val
);
491 tcg_out_arith(s
, rd
, rs
, TCG_REG_T1
, ARITH_AND
);
496 static void tcg_out_div32(TCGContext
*s
, int rd
, int rs1
,
497 int val2
, int val2const
, int uns
)
499 /* Load Y with the sign/zero extension of RS1 to 64-bits. */
501 tcg_out_sety(s
, TCG_REG_G0
);
503 tcg_out_arithi(s
, TCG_REG_T1
, rs1
, 31, SHIFT_SRA
);
504 tcg_out_sety(s
, TCG_REG_T1
);
507 tcg_out_arithc(s
, rd
, rs1
, val2
, val2const
,
508 uns
? ARITH_UDIV
: ARITH_SDIV
);
511 static inline void tcg_out_nop(TCGContext
*s
)
513 tcg_out_sethi(s
, TCG_REG_G0
, 0);
516 static const uint8_t tcg_cond_to_bcond
[] = {
517 [TCG_COND_EQ
] = COND_E
,
518 [TCG_COND_NE
] = COND_NE
,
519 [TCG_COND_LT
] = COND_L
,
520 [TCG_COND_GE
] = COND_GE
,
521 [TCG_COND_LE
] = COND_LE
,
522 [TCG_COND_GT
] = COND_G
,
523 [TCG_COND_LTU
] = COND_CS
,
524 [TCG_COND_GEU
] = COND_CC
,
525 [TCG_COND_LEU
] = COND_LEU
,
526 [TCG_COND_GTU
] = COND_GU
,
529 static const uint8_t tcg_cond_to_rcond
[] = {
530 [TCG_COND_EQ
] = RCOND_Z
,
531 [TCG_COND_NE
] = RCOND_NZ
,
532 [TCG_COND_LT
] = RCOND_LZ
,
533 [TCG_COND_GT
] = RCOND_GZ
,
534 [TCG_COND_LE
] = RCOND_LEZ
,
535 [TCG_COND_GE
] = RCOND_GEZ
538 static void tcg_out_bpcc0(TCGContext
*s
, int scond
, int flags
, int off19
)
540 tcg_out32(s
, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond
) | flags
| off19
);
543 static void tcg_out_bpcc(TCGContext
*s
, int scond
, int flags
, int label
)
545 TCGLabel
*l
= &s
->labels
[label
];
549 off19
= INSN_OFF19(l
->u
.value
- (unsigned long)s
->code_ptr
);
551 /* Make sure to preserve destinations during retranslation. */
552 off19
= *(uint32_t *)s
->code_ptr
& INSN_OFF19(-1);
553 tcg_out_reloc(s
, s
->code_ptr
, R_SPARC_WDISP19
, label
, 0);
555 tcg_out_bpcc0(s
, scond
, flags
, off19
);
558 static void tcg_out_cmp(TCGContext
*s
, TCGArg c1
, TCGArg c2
, int c2const
)
560 tcg_out_arithc(s
, TCG_REG_G0
, c1
, c2
, c2const
, ARITH_SUBCC
);
563 static void tcg_out_brcond_i32(TCGContext
*s
, TCGCond cond
, TCGArg arg1
,
564 TCGArg arg2
, int const_arg2
, int label
)
566 tcg_out_cmp(s
, arg1
, arg2
, const_arg2
);
567 tcg_out_bpcc(s
, tcg_cond_to_bcond
[cond
], BPCC_ICC
| BPCC_PT
, label
);
571 static void tcg_out_movcc(TCGContext
*s
, TCGCond cond
, int cc
, TCGArg ret
,
572 TCGArg v1
, int v1const
)
574 tcg_out32(s
, ARITH_MOVCC
| cc
| INSN_RD(ret
)
575 | INSN_RS1(tcg_cond_to_bcond
[cond
])
576 | (v1const
? INSN_IMM11(v1
) : INSN_RS2(v1
)));
579 static void tcg_out_movcond_i32(TCGContext
*s
, TCGCond cond
, TCGArg ret
,
580 TCGArg c1
, TCGArg c2
, int c2const
,
581 TCGArg v1
, int v1const
)
583 tcg_out_cmp(s
, c1
, c2
, c2const
);
584 tcg_out_movcc(s
, cond
, MOVCC_ICC
, ret
, v1
, v1const
);
587 #if TCG_TARGET_REG_BITS == 64
588 static void tcg_out_brcond_i64(TCGContext
*s
, TCGCond cond
, TCGArg arg1
,
589 TCGArg arg2
, int const_arg2
, int label
)
591 /* For 64-bit signed comparisons vs zero, we can avoid the compare. */
592 if (arg2
== 0 && !is_unsigned_cond(cond
)) {
593 TCGLabel
*l
= &s
->labels
[label
];
597 off16
= INSN_OFF16(l
->u
.value
- (unsigned long)s
->code_ptr
);
599 /* Make sure to preserve destinations during retranslation. */
600 off16
= *(uint32_t *)s
->code_ptr
& INSN_OFF16(-1);
601 tcg_out_reloc(s
, s
->code_ptr
, R_SPARC_WDISP16
, label
, 0);
603 tcg_out32(s
, INSN_OP(0) | INSN_OP2(3) | BPR_PT
| INSN_RS1(arg1
)
604 | INSN_COND(tcg_cond_to_rcond
[cond
]) | off16
);
606 tcg_out_cmp(s
, arg1
, arg2
, const_arg2
);
607 tcg_out_bpcc(s
, tcg_cond_to_bcond
[cond
], BPCC_XCC
| BPCC_PT
, label
);
612 static void tcg_out_movr(TCGContext
*s
, TCGCond cond
, TCGArg ret
, TCGArg c1
,
613 TCGArg v1
, int v1const
)
615 tcg_out32(s
, ARITH_MOVR
| INSN_RD(ret
) | INSN_RS1(c1
)
616 | (tcg_cond_to_rcond
[cond
] << 10)
617 | (v1const
? INSN_IMM10(v1
) : INSN_RS2(v1
)));
620 static void tcg_out_movcond_i64(TCGContext
*s
, TCGCond cond
, TCGArg ret
,
621 TCGArg c1
, TCGArg c2
, int c2const
,
622 TCGArg v1
, int v1const
)
624 /* For 64-bit signed comparisons vs zero, we can avoid the compare.
625 Note that the immediate range is one bit smaller, so we must check
627 if (c2
== 0 && !is_unsigned_cond(cond
)
628 && (!v1const
|| check_fit_tl(v1
, 10))) {
629 tcg_out_movr(s
, cond
, ret
, c1
, v1
, v1const
);
631 tcg_out_cmp(s
, c1
, c2
, c2const
);
632 tcg_out_movcc(s
, cond
, MOVCC_XCC
, ret
, v1
, v1const
);
636 static void tcg_out_brcond2_i32(TCGContext
*s
, TCGCond cond
,
637 TCGArg al
, TCGArg ah
,
638 TCGArg bl
, int blconst
,
639 TCGArg bh
, int bhconst
, int label_dest
)
641 int scond
, label_next
= gen_new_label();
643 tcg_out_cmp(s
, ah
, bh
, bhconst
);
645 /* Note that we fill one of the delay slots with the second compare. */
648 tcg_out_bpcc(s
, COND_NE
, BPCC_ICC
| BPCC_PT
, label_next
);
649 tcg_out_cmp(s
, al
, bl
, blconst
);
650 tcg_out_bpcc(s
, COND_E
, BPCC_ICC
| BPCC_PT
, label_dest
);
654 tcg_out_bpcc(s
, COND_NE
, BPCC_ICC
| BPCC_PT
, label_dest
);
655 tcg_out_cmp(s
, al
, bl
, blconst
);
656 tcg_out_bpcc(s
, COND_NE
, BPCC_ICC
| BPCC_PT
, label_dest
);
660 scond
= tcg_cond_to_bcond
[tcg_high_cond(cond
)];
661 tcg_out_bpcc(s
, scond
, BPCC_ICC
| BPCC_PT
, label_dest
);
663 tcg_out_bpcc(s
, COND_NE
, BPCC_ICC
| BPCC_PT
, label_next
);
664 tcg_out_cmp(s
, al
, bl
, blconst
);
665 scond
= tcg_cond_to_bcond
[tcg_unsigned_cond(cond
)];
666 tcg_out_bpcc(s
, scond
, BPCC_ICC
| BPCC_PT
, label_dest
);
671 tcg_out_label(s
, label_next
, s
->code_ptr
);
675 static void tcg_out_setcond_i32(TCGContext
*s
, TCGCond cond
, TCGArg ret
,
676 TCGArg c1
, TCGArg c2
, int c2const
)
678 /* For 32-bit comparisons, we can play games with ADDX/SUBX. */
682 /* The result of the comparison is in the carry bit. */
687 /* For equality, we can transform to inequality vs zero. */
689 tcg_out_arithc(s
, ret
, c1
, c2
, c2const
, ARITH_XOR
);
691 c1
= TCG_REG_G0
, c2
= ret
, c2const
= 0;
692 cond
= (cond
== TCG_COND_EQ
? TCG_COND_GEU
: TCG_COND_LTU
);
697 /* If we don't need to load a constant into a register, we can
698 swap the operands on GTU/LEU. There's no benefit to loading
699 the constant into a temporary register. */
700 if (!c2const
|| c2
== 0) {
705 cond
= tcg_swap_cond(cond
);
711 tcg_out_cmp(s
, c1
, c2
, c2const
);
712 tcg_out_movi_imm13(s
, ret
, 0);
713 tcg_out_movcc(s
, cond
, MOVCC_ICC
, ret
, 1, 1);
717 tcg_out_cmp(s
, c1
, c2
, c2const
);
718 if (cond
== TCG_COND_LTU
) {
719 tcg_out_arithi(s
, ret
, TCG_REG_G0
, 0, ARITH_ADDX
);
721 tcg_out_arithi(s
, ret
, TCG_REG_G0
, -1, ARITH_SUBX
);
725 #if TCG_TARGET_REG_BITS == 64
726 static void tcg_out_setcond_i64(TCGContext
*s
, TCGCond cond
, TCGArg ret
,
727 TCGArg c1
, TCGArg c2
, int c2const
)
729 /* For 64-bit signed comparisons vs zero, we can avoid the compare
730 if the input does not overlap the output. */
731 if (c2
== 0 && !is_unsigned_cond(cond
) && c1
!= ret
) {
732 tcg_out_movi_imm13(s
, ret
, 0);
733 tcg_out_movr(s
, cond
, ret
, c1
, 1, 1);
735 tcg_out_cmp(s
, c1
, c2
, c2const
);
736 tcg_out_movi_imm13(s
, ret
, 0);
737 tcg_out_movcc(s
, cond
, MOVCC_XCC
, ret
, 1, 1);
741 static void tcg_out_setcond2_i32(TCGContext
*s
, TCGCond cond
, TCGArg ret
,
742 TCGArg al
, TCGArg ah
,
743 TCGArg bl
, int blconst
,
744 TCGArg bh
, int bhconst
)
746 int tmp
= TCG_REG_T1
;
748 /* Note that the low parts are fully consumed before tmp is set. */
749 if (ret
!= ah
&& (bhconst
|| ret
!= bh
)) {
756 if (bl
== 0 && bh
== 0) {
757 if (cond
== TCG_COND_EQ
) {
758 tcg_out_arith(s
, TCG_REG_G0
, al
, ah
, ARITH_ORCC
);
759 tcg_out_movi(s
, TCG_TYPE_I32
, ret
, 1);
761 tcg_out_arith(s
, ret
, al
, ah
, ARITH_ORCC
);
764 tcg_out_setcond_i32(s
, cond
, tmp
, al
, bl
, blconst
);
765 tcg_out_cmp(s
, ah
, bh
, bhconst
);
766 tcg_out_mov(s
, TCG_TYPE_I32
, ret
, tmp
);
768 tcg_out_movcc(s
, TCG_COND_NE
, MOVCC_ICC
, ret
, cond
== TCG_COND_NE
, 1);
772 /* <= : ah < bh | (ah == bh && al <= bl) */
773 tcg_out_setcond_i32(s
, tcg_unsigned_cond(cond
), tmp
, al
, bl
, blconst
);
774 tcg_out_cmp(s
, ah
, bh
, bhconst
);
775 tcg_out_mov(s
, TCG_TYPE_I32
, ret
, tmp
);
776 tcg_out_movcc(s
, TCG_COND_NE
, MOVCC_ICC
, ret
, 0, 1);
777 tcg_out_movcc(s
, tcg_high_cond(cond
), MOVCC_ICC
, ret
, 1, 1);
783 static void tcg_out_addsub2(TCGContext
*s
, TCGArg rl
, TCGArg rh
,
784 TCGArg al
, TCGArg ah
, TCGArg bl
, int blconst
,
785 TCGArg bh
, int bhconst
, int opl
, int oph
)
787 TCGArg tmp
= TCG_REG_T1
;
789 /* Note that the low parts are fully consumed before tmp is set. */
790 if (rl
!= ah
&& (bhconst
|| rl
!= bh
)) {
794 tcg_out_arithc(s
, tmp
, al
, bl
, blconst
, opl
);
795 tcg_out_arithc(s
, rh
, ah
, bh
, bhconst
, oph
);
796 tcg_out_mov(s
, TCG_TYPE_I32
, rl
, tmp
);
799 /* Generate global QEMU prologue and epilogue code */
800 static void tcg_target_qemu_prologue(TCGContext
*s
)
802 int tmp_buf_size
, frame_size
;
804 /* The TCG temp buffer is at the top of the frame, immediately
805 below the frame pointer. */
806 tmp_buf_size
= CPU_TEMP_BUF_NLONGS
* (int)sizeof(long);
807 tcg_set_frame(s
, TCG_REG_I6
, TCG_TARGET_STACK_BIAS
- tmp_buf_size
,
810 /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is
811 otherwise the minimal frame usable by callees. */
812 frame_size
= TCG_TARGET_CALL_STACK_OFFSET
- TCG_TARGET_STACK_BIAS
;
813 frame_size
+= TCG_STATIC_CALL_ARGS_SIZE
+ tmp_buf_size
;
814 frame_size
+= TCG_TARGET_STACK_ALIGN
- 1;
815 frame_size
&= -TCG_TARGET_STACK_ALIGN
;
816 tcg_out32(s
, SAVE
| INSN_RD(TCG_REG_O6
) | INSN_RS1(TCG_REG_O6
) |
817 INSN_IMM13(-frame_size
));
819 #ifdef CONFIG_USE_GUEST_BASE
820 if (GUEST_BASE
!= 0) {
821 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_GUEST_BASE_REG
, GUEST_BASE
);
822 tcg_regset_set_reg(s
->reserved_regs
, TCG_GUEST_BASE_REG
);
826 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I1
) |
827 INSN_RS2(TCG_REG_G0
));
831 /* No epilogue required. We issue ret + restore directly in the TB. */
834 #if defined(CONFIG_SOFTMMU)
836 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
838 static const void * const qemu_ld_helpers
[4] = {
845 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
846 uintxx_t val, int mmu_idx) */
847 static const void * const qemu_st_helpers
[4] = {
854 /* Perform the TLB load and compare.
857 ADDRLO_IDX contains the index into ARGS of the low part of the
858 address; the high part of the address is at ADDR_LOW_IDX+1.
860 MEM_INDEX and S_BITS are the memory context and log2 size of the load.
862 WHICH is the offset into the CPUTLBEntry structure of the slot to read.
863 This should be offsetof addr_read or addr_write.
865 The result of the TLB comparison is in %[ix]cc. The sanitized address
866 is in the returned register, maybe %o0. The TLB addend is in %o1. */
868 static int tcg_out_tlb_load(TCGContext
*s
, int addrlo_idx
, int mem_index
,
869 int s_bits
, const TCGArg
*args
, int which
)
871 const int addrlo
= args
[addrlo_idx
];
872 const int r0
= TCG_REG_O0
;
873 const int r1
= TCG_REG_O1
;
874 const int r2
= TCG_REG_O2
;
878 if (TCG_TARGET_REG_BITS
== 32 && TARGET_LONG_BITS
== 64) {
879 /* Assemble the 64-bit address in R0. */
880 tcg_out_arithi(s
, r0
, addrlo
, 0, SHIFT_SRL
);
881 tcg_out_arithi(s
, r1
, args
[addrlo_idx
+ 1], 32, SHIFT_SLLX
);
882 tcg_out_arith(s
, r0
, r0
, r1
, ARITH_OR
);
885 /* Shift the page number down to tlb-entry. */
886 tcg_out_arithi(s
, r1
, addrlo
,
887 TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
, SHIFT_SRL
);
889 /* Mask out the page offset, except for the required alignment. */
890 tcg_out_andi(s
, r0
, addr
, TARGET_PAGE_MASK
| ((1 << s_bits
) - 1));
892 /* Compute tlb index, modulo tlb size. */
893 tcg_out_andi(s
, r1
, r1
, (CPU_TLB_SIZE
- 1) << CPU_TLB_ENTRY_BITS
);
895 /* Relative to the current ENV. */
896 tcg_out_arith(s
, r1
, TCG_AREG0
, r1
, ARITH_ADD
);
898 /* Find a base address that can load both tlb comparator and addend. */
899 tlb_ofs
= offsetof(CPUArchState
, tlb_table
[mem_index
][0]);
900 if (!check_fit_tl(tlb_ofs
+ sizeof(CPUTLBEntry
), 13)) {
901 tcg_out_addi(s
, r1
, tlb_ofs
);
905 /* Load the tlb comparator and the addend. */
906 tcg_out_ld(s
, TCG_TYPE_TL
, r2
, r1
, tlb_ofs
+ which
);
907 tcg_out_ld(s
, TCG_TYPE_PTR
, r1
, r1
, tlb_ofs
+offsetof(CPUTLBEntry
, addend
));
909 /* subcc arg0, arg2, %g0 */
910 tcg_out_cmp(s
, r0
, r2
, 0);
912 /* If the guest address must be zero-extended, do so now. */
913 if (TCG_TARGET_REG_BITS
== 64 && TARGET_LONG_BITS
== 32) {
914 tcg_out_arithi(s
, r0
, addrlo
, 0, SHIFT_SRL
);
919 #endif /* CONFIG_SOFTMMU */
921 static const int qemu_ld_opc
[8] = {
922 #ifdef TARGET_WORDS_BIGENDIAN
923 LDUB
, LDUH
, LDUW
, LDX
, LDSB
, LDSH
, LDSW
, LDX
925 LDUB
, LDUH_LE
, LDUW_LE
, LDX_LE
, LDSB
, LDSH_LE
, LDSW_LE
, LDX_LE
929 static const int qemu_st_opc
[4] = {
930 #ifdef TARGET_WORDS_BIGENDIAN
933 STB
, STH_LE
, STW_LE
, STX_LE
937 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, int sizeop
)
939 int addrlo_idx
= 1, datalo
, datahi
, addr_reg
;
940 #if defined(CONFIG_SOFTMMU)
941 int memi_idx
, memi
, s_bits
, n
;
942 uint32_t *label_ptr
[2];
945 datahi
= datalo
= args
[0];
946 if (TCG_TARGET_REG_BITS
== 32 && sizeop
== 3) {
951 #if defined(CONFIG_SOFTMMU)
952 memi_idx
= addrlo_idx
+ 1 + (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
);
953 memi
= args
[memi_idx
];
956 addr_reg
= tcg_out_tlb_load(s
, addrlo_idx
, memi
, s_bits
, args
,
957 offsetof(CPUTLBEntry
, addr_read
));
959 if (TCG_TARGET_REG_BITS
== 32 && sizeop
== 3) {
962 /* bne,pn %[xi]cc, label0 */
963 label_ptr
[0] = (uint32_t *)s
->code_ptr
;
964 tcg_out_bpcc0(s
, COND_NE
, BPCC_PN
965 | (TARGET_LONG_BITS
== 64 ? BPCC_XCC
: BPCC_ICC
), 0);
968 /* Load all 64-bits into an O/G register. */
969 reg64
= (datalo
< 16 ? datalo
: TCG_REG_O0
);
970 tcg_out_ldst_rr(s
, reg64
, addr_reg
, TCG_REG_O1
, qemu_ld_opc
[sizeop
]);
972 /* Move the two 32-bit pieces into the destination registers. */
973 tcg_out_arithi(s
, datahi
, reg64
, 32, SHIFT_SRLX
);
974 if (reg64
!= datalo
) {
975 tcg_out_mov(s
, TCG_TYPE_I32
, datalo
, reg64
);
979 label_ptr
[1] = (uint32_t *)s
->code_ptr
;
980 tcg_out_bpcc0(s
, COND_A
, BPCC_A
| BPCC_PT
, 0);
982 /* The fast path is exactly one insn. Thus we can perform the
983 entire TLB Hit in the (annulled) delay slot of the branch
984 over the TLB Miss case. */
986 /* beq,a,pt %[xi]cc, label0 */
988 label_ptr
[1] = (uint32_t *)s
->code_ptr
;
989 tcg_out_bpcc0(s
, COND_E
, BPCC_A
| BPCC_PT
990 | (TARGET_LONG_BITS
== 64 ? BPCC_XCC
: BPCC_ICC
), 0);
992 tcg_out_ldst_rr(s
, datalo
, addr_reg
, TCG_REG_O1
, qemu_ld_opc
[sizeop
]);
998 *label_ptr
[0] |= INSN_OFF19((unsigned long)s
->code_ptr
-
999 (unsigned long)label_ptr
[0]);
1002 tcg_out_mov(s
, TCG_TYPE_PTR
, tcg_target_call_iarg_regs
[n
++], TCG_AREG0
);
1003 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
1004 tcg_out_mov(s
, TCG_TYPE_REG
, tcg_target_call_iarg_regs
[n
++],
1005 args
[addrlo_idx
+ 1]);
1007 tcg_out_mov(s
, TCG_TYPE_REG
, tcg_target_call_iarg_regs
[n
++],
1010 /* qemu_ld_helper[s_bits](arg0, arg1) */
1011 tcg_out32(s
, CALL
| ((((tcg_target_ulong
)qemu_ld_helpers
[s_bits
]
1012 - (tcg_target_ulong
)s
->code_ptr
) >> 2)
1015 tcg_out_movi(s
, TCG_TYPE_I32
, tcg_target_call_iarg_regs
[n
], memi
);
1017 n
= tcg_target_call_oarg_regs
[0];
1018 /* datalo = sign_extend(arg0) */
1021 /* Recall that SRA sign extends from bit 31 through bit 63. */
1022 tcg_out_arithi(s
, datalo
, n
, 24, SHIFT_SLL
);
1023 tcg_out_arithi(s
, datalo
, datalo
, 24, SHIFT_SRA
);
1026 tcg_out_arithi(s
, datalo
, n
, 16, SHIFT_SLL
);
1027 tcg_out_arithi(s
, datalo
, datalo
, 16, SHIFT_SRA
);
1030 tcg_out_arithi(s
, datalo
, n
, 0, SHIFT_SRA
);
1033 if (TCG_TARGET_REG_BITS
== 32) {
1034 tcg_out_mov(s
, TCG_TYPE_REG
, datahi
, n
);
1035 tcg_out_mov(s
, TCG_TYPE_REG
, datalo
, n
+ 1);
1044 tcg_out_mov(s
, TCG_TYPE_REG
, datalo
, n
);
1048 *label_ptr
[1] |= INSN_OFF19((unsigned long)s
->code_ptr
-
1049 (unsigned long)label_ptr
[1]);
1051 addr_reg
= args
[addrlo_idx
];
1052 if (TCG_TARGET_REG_BITS
== 64 && TARGET_LONG_BITS
== 32) {
1053 tcg_out_arithi(s
, TCG_REG_T1
, addr_reg
, 0, SHIFT_SRL
);
1054 addr_reg
= TCG_REG_T1
;
1056 if (TCG_TARGET_REG_BITS
== 32 && sizeop
== 3) {
1057 int reg64
= (datalo
< 16 ? datalo
: TCG_REG_O0
);
1059 tcg_out_ldst_rr(s
, reg64
, addr_reg
,
1060 (GUEST_BASE
? TCG_GUEST_BASE_REG
: TCG_REG_G0
),
1061 qemu_ld_opc
[sizeop
]);
1063 tcg_out_arithi(s
, datahi
, reg64
, 32, SHIFT_SRLX
);
1064 if (reg64
!= datalo
) {
1065 tcg_out_mov(s
, TCG_TYPE_I32
, datalo
, reg64
);
1068 tcg_out_ldst_rr(s
, datalo
, addr_reg
,
1069 (GUEST_BASE
? TCG_GUEST_BASE_REG
: TCG_REG_G0
),
1070 qemu_ld_opc
[sizeop
]);
1072 #endif /* CONFIG_SOFTMMU */
1075 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, int sizeop
)
1077 int addrlo_idx
= 1, datalo
, datahi
, addr_reg
;
1078 #if defined(CONFIG_SOFTMMU)
1079 int memi_idx
, memi
, n
, datafull
;
1080 uint32_t *label_ptr
;
1083 datahi
= datalo
= args
[0];
1084 if (TCG_TARGET_REG_BITS
== 32 && sizeop
== 3) {
1089 #if defined(CONFIG_SOFTMMU)
1090 memi_idx
= addrlo_idx
+ 1 + (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
);
1091 memi
= args
[memi_idx
];
1093 addr_reg
= tcg_out_tlb_load(s
, addrlo_idx
, memi
, sizeop
, args
,
1094 offsetof(CPUTLBEntry
, addr_write
));
1097 if (TCG_TARGET_REG_BITS
== 32 && sizeop
== 3) {
1098 /* Reconstruct the full 64-bit value. */
1099 tcg_out_arithi(s
, TCG_REG_T1
, datalo
, 0, SHIFT_SRL
);
1100 tcg_out_arithi(s
, TCG_REG_O2
, datahi
, 32, SHIFT_SLLX
);
1101 tcg_out_arith(s
, TCG_REG_O2
, TCG_REG_T1
, TCG_REG_O2
, ARITH_OR
);
1102 datafull
= TCG_REG_O2
;
1105 /* The fast path is exactly one insn. Thus we can perform the entire
1106 TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */
1107 /* beq,a,pt %[xi]cc, label0 */
1108 label_ptr
= (uint32_t *)s
->code_ptr
;
1109 tcg_out_bpcc0(s
, COND_E
, BPCC_A
| BPCC_PT
1110 | (TARGET_LONG_BITS
== 64 ? BPCC_XCC
: BPCC_ICC
), 0);
1112 tcg_out_ldst_rr(s
, datafull
, addr_reg
, TCG_REG_O1
, qemu_st_opc
[sizeop
]);
1117 tcg_out_mov(s
, TCG_TYPE_PTR
, tcg_target_call_iarg_regs
[n
++], TCG_AREG0
);
1118 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
1119 tcg_out_mov(s
, TCG_TYPE_REG
, tcg_target_call_iarg_regs
[n
++],
1120 args
[addrlo_idx
+ 1]);
1122 tcg_out_mov(s
, TCG_TYPE_REG
, tcg_target_call_iarg_regs
[n
++],
1124 if (TCG_TARGET_REG_BITS
== 32 && sizeop
== 3) {
1125 tcg_out_mov(s
, TCG_TYPE_REG
, tcg_target_call_iarg_regs
[n
++], datahi
);
1127 tcg_out_mov(s
, TCG_TYPE_REG
, tcg_target_call_iarg_regs
[n
++], datalo
);
1129 /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
1130 tcg_out32(s
, CALL
| ((((tcg_target_ulong
)qemu_st_helpers
[sizeop
]
1131 - (tcg_target_ulong
)s
->code_ptr
) >> 2)
1134 tcg_out_movi(s
, TCG_TYPE_REG
, tcg_target_call_iarg_regs
[n
], memi
);
1136 *label_ptr
|= INSN_OFF19((unsigned long)s
->code_ptr
-
1137 (unsigned long)label_ptr
);
1139 addr_reg
= args
[addrlo_idx
];
1140 if (TCG_TARGET_REG_BITS
== 64 && TARGET_LONG_BITS
== 32) {
1141 tcg_out_arithi(s
, TCG_REG_T1
, addr_reg
, 0, SHIFT_SRL
);
1142 addr_reg
= TCG_REG_T1
;
1144 if (TCG_TARGET_REG_BITS
== 32 && sizeop
== 3) {
1145 tcg_out_arithi(s
, TCG_REG_T1
, datalo
, 0, SHIFT_SRL
);
1146 tcg_out_arithi(s
, TCG_REG_O2
, datahi
, 32, SHIFT_SLLX
);
1147 tcg_out_arith(s
, TCG_REG_O2
, TCG_REG_T1
, TCG_REG_O2
, ARITH_OR
);
1148 datalo
= TCG_REG_O2
;
1150 tcg_out_ldst_rr(s
, datalo
, addr_reg
,
1151 (GUEST_BASE
? TCG_GUEST_BASE_REG
: TCG_REG_G0
),
1152 qemu_st_opc
[sizeop
]);
1153 #endif /* CONFIG_SOFTMMU */
1156 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
1157 const int *const_args
)
1162 case INDEX_op_exit_tb
:
1163 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_I0
, args
[0]);
1164 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_I7
) |
1166 tcg_out32(s
, RESTORE
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_G0
) |
1167 INSN_RS2(TCG_REG_G0
));
1169 case INDEX_op_goto_tb
:
1170 if (s
->tb_jmp_offset
) {
1171 /* direct jump method */
1172 uint32_t old_insn
= *(uint32_t *)s
->code_ptr
;
1173 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1174 /* Make sure to preserve links during retranslation. */
1175 tcg_out32(s
, CALL
| (old_insn
& ~INSN_OP(-1)));
1177 /* indirect jump method */
1178 tcg_out_ld_ptr(s
, TCG_REG_T1
,
1179 (tcg_target_long
)(s
->tb_next
+ args
[0]));
1180 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_G0
) | INSN_RS1(TCG_REG_T1
) |
1181 INSN_RS2(TCG_REG_G0
));
1184 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1187 if (const_args
[0]) {
1188 tcg_out32(s
, CALL
| ((((tcg_target_ulong
)args
[0]
1189 - (tcg_target_ulong
)s
->code_ptr
) >> 2)
1192 tcg_out_ld_ptr(s
, TCG_REG_T1
,
1193 (tcg_target_long
)(s
->tb_next
+ args
[0]));
1194 tcg_out32(s
, JMPL
| INSN_RD(TCG_REG_O7
) | INSN_RS1(TCG_REG_T1
) |
1195 INSN_RS2(TCG_REG_G0
));
1201 tcg_out_bpcc(s
, COND_A
, BPCC_PT
, args
[0]);
1204 case INDEX_op_movi_i32
:
1205 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], (uint32_t)args
[1]);
1208 #if TCG_TARGET_REG_BITS == 64
1209 #define OP_32_64(x) \
1210 glue(glue(case INDEX_op_, x), _i32): \
1211 glue(glue(case INDEX_op_, x), _i64)
1213 #define OP_32_64(x) \
1214 glue(glue(case INDEX_op_, x), _i32)
1217 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUB
);
1220 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSB
);
1223 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUH
);
1226 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSH
);
1228 case INDEX_op_ld_i32
:
1229 #if TCG_TARGET_REG_BITS == 64
1230 case INDEX_op_ld32u_i64
:
1232 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDUW
);
1235 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STB
);
1238 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STH
);
1240 case INDEX_op_st_i32
:
1241 #if TCG_TARGET_REG_BITS == 64
1242 case INDEX_op_st32_i64
:
1244 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STW
);
1267 case INDEX_op_shl_i32
:
1270 /* Limit immediate shift count lest we create an illegal insn. */
1271 tcg_out_arithc(s
, args
[0], args
[1], args
[2] & 31, const_args
[2], c
);
1273 case INDEX_op_shr_i32
:
1276 case INDEX_op_sar_i32
:
1279 case INDEX_op_mul_i32
:
1290 case INDEX_op_div_i32
:
1291 tcg_out_div32(s
, args
[0], args
[1], args
[2], const_args
[2], 0);
1293 case INDEX_op_divu_i32
:
1294 tcg_out_div32(s
, args
[0], args
[1], args
[2], const_args
[2], 1);
1297 case INDEX_op_rem_i32
:
1298 case INDEX_op_remu_i32
:
1299 tcg_out_div32(s
, TCG_REG_T1
, args
[1], args
[2], const_args
[2],
1300 opc
== INDEX_op_remu_i32
);
1301 tcg_out_arithc(s
, TCG_REG_T1
, TCG_REG_T1
, args
[2], const_args
[2],
1303 tcg_out_arith(s
, args
[0], args
[1], TCG_REG_T1
, ARITH_SUB
);
1306 case INDEX_op_brcond_i32
:
1307 tcg_out_brcond_i32(s
, args
[2], args
[0], args
[1], const_args
[1],
1310 case INDEX_op_setcond_i32
:
1311 tcg_out_setcond_i32(s
, args
[3], args
[0], args
[1],
1312 args
[2], const_args
[2]);
1314 case INDEX_op_movcond_i32
:
1315 tcg_out_movcond_i32(s
, args
[5], args
[0], args
[1],
1316 args
[2], const_args
[2], args
[3], const_args
[3]);
1319 #if TCG_TARGET_REG_BITS == 32
1320 case INDEX_op_brcond2_i32
:
1321 tcg_out_brcond2_i32(s
, args
[4], args
[0], args
[1],
1322 args
[2], const_args
[2],
1323 args
[3], const_args
[3], args
[5]);
1325 case INDEX_op_setcond2_i32
:
1326 tcg_out_setcond2_i32(s
, args
[5], args
[0], args
[1], args
[2],
1327 args
[3], const_args
[3],
1328 args
[4], const_args
[4]);
1332 case INDEX_op_add2_i32
:
1333 tcg_out_addsub2(s
, args
[0], args
[1], args
[2], args
[3],
1334 args
[4], const_args
[4], args
[5], const_args
[5],
1335 ARITH_ADDCC
, ARITH_ADDX
);
1337 case INDEX_op_sub2_i32
:
1338 tcg_out_addsub2(s
, args
[0], args
[1], args
[2], args
[3],
1339 args
[4], const_args
[4], args
[5], const_args
[5],
1340 ARITH_SUBCC
, ARITH_SUBX
);
1342 case INDEX_op_mulu2_i32
:
1343 tcg_out_arithc(s
, args
[0], args
[2], args
[3], const_args
[3],
1345 tcg_out_rdy(s
, args
[1]);
1348 case INDEX_op_qemu_ld8u
:
1349 tcg_out_qemu_ld(s
, args
, 0);
1351 case INDEX_op_qemu_ld8s
:
1352 tcg_out_qemu_ld(s
, args
, 0 | 4);
1354 case INDEX_op_qemu_ld16u
:
1355 tcg_out_qemu_ld(s
, args
, 1);
1357 case INDEX_op_qemu_ld16s
:
1358 tcg_out_qemu_ld(s
, args
, 1 | 4);
1360 case INDEX_op_qemu_ld32
:
1361 #if TCG_TARGET_REG_BITS == 64
1362 case INDEX_op_qemu_ld32u
:
1364 tcg_out_qemu_ld(s
, args
, 2);
1366 #if TCG_TARGET_REG_BITS == 64
1367 case INDEX_op_qemu_ld32s
:
1368 tcg_out_qemu_ld(s
, args
, 2 | 4);
1371 case INDEX_op_qemu_ld64
:
1372 tcg_out_qemu_ld(s
, args
, 3);
1374 case INDEX_op_qemu_st8
:
1375 tcg_out_qemu_st(s
, args
, 0);
1377 case INDEX_op_qemu_st16
:
1378 tcg_out_qemu_st(s
, args
, 1);
1380 case INDEX_op_qemu_st32
:
1381 tcg_out_qemu_st(s
, args
, 2);
1383 case INDEX_op_qemu_st64
:
1384 tcg_out_qemu_st(s
, args
, 3);
1387 #if TCG_TARGET_REG_BITS == 64
1388 case INDEX_op_movi_i64
:
1389 tcg_out_movi(s
, TCG_TYPE_I64
, args
[0], args
[1]);
1391 case INDEX_op_ld32s_i64
:
1392 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDSW
);
1394 case INDEX_op_ld_i64
:
1395 tcg_out_ldst(s
, args
[0], args
[1], args
[2], LDX
);
1397 case INDEX_op_st_i64
:
1398 tcg_out_ldst(s
, args
[0], args
[1], args
[2], STX
);
1400 case INDEX_op_shl_i64
:
1403 /* Limit immediate shift count lest we create an illegal insn. */
1404 tcg_out_arithc(s
, args
[0], args
[1], args
[2] & 63, const_args
[2], c
);
1406 case INDEX_op_shr_i64
:
1409 case INDEX_op_sar_i64
:
1412 case INDEX_op_mul_i64
:
1415 case INDEX_op_div_i64
:
1418 case INDEX_op_divu_i64
:
1421 case INDEX_op_rem_i64
:
1422 case INDEX_op_remu_i64
:
1423 tcg_out_arithc(s
, TCG_REG_T1
, args
[1], args
[2], const_args
[2],
1424 opc
== INDEX_op_rem_i64
? ARITH_SDIVX
: ARITH_UDIVX
);
1425 tcg_out_arithc(s
, TCG_REG_T1
, TCG_REG_T1
, args
[2], const_args
[2],
1427 tcg_out_arith(s
, args
[0], args
[1], TCG_REG_T1
, ARITH_SUB
);
1429 case INDEX_op_ext32s_i64
:
1430 if (const_args
[1]) {
1431 tcg_out_movi(s
, TCG_TYPE_I64
, args
[0], (int32_t)args
[1]);
1433 tcg_out_arithi(s
, args
[0], args
[1], 0, SHIFT_SRA
);
1436 case INDEX_op_ext32u_i64
:
1437 if (const_args
[1]) {
1438 tcg_out_movi_imm32(s
, args
[0], args
[1]);
1440 tcg_out_arithi(s
, args
[0], args
[1], 0, SHIFT_SRL
);
1444 case INDEX_op_brcond_i64
:
1445 tcg_out_brcond_i64(s
, args
[2], args
[0], args
[1], const_args
[1],
1448 case INDEX_op_setcond_i64
:
1449 tcg_out_setcond_i64(s
, args
[3], args
[0], args
[1],
1450 args
[2], const_args
[2]);
1452 case INDEX_op_movcond_i64
:
1453 tcg_out_movcond_i64(s
, args
[5], args
[0], args
[1],
1454 args
[2], const_args
[2], args
[3], const_args
[3]);
1458 tcg_out_arithc(s
, args
[0], args
[1], args
[2], const_args
[2], c
);
1462 tcg_out_arithc(s
, args
[0], TCG_REG_G0
, args
[1], const_args
[1], c
);
1466 fprintf(stderr
, "unknown opcode 0x%x\n", opc
);
1471 static const TCGTargetOpDef sparc_op_defs
[] = {
1472 { INDEX_op_exit_tb
, { } },
1473 { INDEX_op_goto_tb
, { } },
1474 { INDEX_op_call
, { "ri" } },
1475 { INDEX_op_br
, { } },
1477 { INDEX_op_mov_i32
, { "r", "r" } },
1478 { INDEX_op_movi_i32
, { "r" } },
1479 { INDEX_op_ld8u_i32
, { "r", "r" } },
1480 { INDEX_op_ld8s_i32
, { "r", "r" } },
1481 { INDEX_op_ld16u_i32
, { "r", "r" } },
1482 { INDEX_op_ld16s_i32
, { "r", "r" } },
1483 { INDEX_op_ld_i32
, { "r", "r" } },
1484 { INDEX_op_st8_i32
, { "rZ", "r" } },
1485 { INDEX_op_st16_i32
, { "rZ", "r" } },
1486 { INDEX_op_st_i32
, { "rZ", "r" } },
1488 { INDEX_op_add_i32
, { "r", "rZ", "rJ" } },
1489 { INDEX_op_mul_i32
, { "r", "rZ", "rJ" } },
1490 { INDEX_op_div_i32
, { "r", "rZ", "rJ" } },
1491 { INDEX_op_divu_i32
, { "r", "rZ", "rJ" } },
1492 { INDEX_op_rem_i32
, { "r", "rZ", "rJ" } },
1493 { INDEX_op_remu_i32
, { "r", "rZ", "rJ" } },
1494 { INDEX_op_sub_i32
, { "r", "rZ", "rJ" } },
1495 { INDEX_op_and_i32
, { "r", "rZ", "rJ" } },
1496 { INDEX_op_andc_i32
, { "r", "rZ", "rJ" } },
1497 { INDEX_op_or_i32
, { "r", "rZ", "rJ" } },
1498 { INDEX_op_orc_i32
, { "r", "rZ", "rJ" } },
1499 { INDEX_op_xor_i32
, { "r", "rZ", "rJ" } },
1501 { INDEX_op_shl_i32
, { "r", "rZ", "rJ" } },
1502 { INDEX_op_shr_i32
, { "r", "rZ", "rJ" } },
1503 { INDEX_op_sar_i32
, { "r", "rZ", "rJ" } },
1505 { INDEX_op_neg_i32
, { "r", "rJ" } },
1506 { INDEX_op_not_i32
, { "r", "rJ" } },
1508 { INDEX_op_brcond_i32
, { "rZ", "rJ" } },
1509 { INDEX_op_setcond_i32
, { "r", "rZ", "rJ" } },
1510 { INDEX_op_movcond_i32
, { "r", "rZ", "rJ", "rI", "0" } },
1512 #if TCG_TARGET_REG_BITS == 32
1513 { INDEX_op_brcond2_i32
, { "rZ", "rZ", "rJ", "rJ" } },
1514 { INDEX_op_setcond2_i32
, { "r", "rZ", "rZ", "rJ", "rJ" } },
1517 { INDEX_op_add2_i32
, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
1518 { INDEX_op_sub2_i32
, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
1519 { INDEX_op_mulu2_i32
, { "r", "r", "rZ", "rJ" } },
1521 #if TCG_TARGET_REG_BITS == 64
1522 { INDEX_op_mov_i64
, { "r", "r" } },
1523 { INDEX_op_movi_i64
, { "r" } },
1524 { INDEX_op_ld8u_i64
, { "r", "r" } },
1525 { INDEX_op_ld8s_i64
, { "r", "r" } },
1526 { INDEX_op_ld16u_i64
, { "r", "r" } },
1527 { INDEX_op_ld16s_i64
, { "r", "r" } },
1528 { INDEX_op_ld32u_i64
, { "r", "r" } },
1529 { INDEX_op_ld32s_i64
, { "r", "r" } },
1530 { INDEX_op_ld_i64
, { "r", "r" } },
1531 { INDEX_op_st8_i64
, { "rZ", "r" } },
1532 { INDEX_op_st16_i64
, { "rZ", "r" } },
1533 { INDEX_op_st32_i64
, { "rZ", "r" } },
1534 { INDEX_op_st_i64
, { "rZ", "r" } },
1536 { INDEX_op_add_i64
, { "r", "rZ", "rJ" } },
1537 { INDEX_op_mul_i64
, { "r", "rZ", "rJ" } },
1538 { INDEX_op_div_i64
, { "r", "rZ", "rJ" } },
1539 { INDEX_op_divu_i64
, { "r", "rZ", "rJ" } },
1540 { INDEX_op_rem_i64
, { "r", "rZ", "rJ" } },
1541 { INDEX_op_remu_i64
, { "r", "rZ", "rJ" } },
1542 { INDEX_op_sub_i64
, { "r", "rZ", "rJ" } },
1543 { INDEX_op_and_i64
, { "r", "rZ", "rJ" } },
1544 { INDEX_op_andc_i64
, { "r", "rZ", "rJ" } },
1545 { INDEX_op_or_i64
, { "r", "rZ", "rJ" } },
1546 { INDEX_op_orc_i64
, { "r", "rZ", "rJ" } },
1547 { INDEX_op_xor_i64
, { "r", "rZ", "rJ" } },
1549 { INDEX_op_shl_i64
, { "r", "rZ", "rJ" } },
1550 { INDEX_op_shr_i64
, { "r", "rZ", "rJ" } },
1551 { INDEX_op_sar_i64
, { "r", "rZ", "rJ" } },
1553 { INDEX_op_neg_i64
, { "r", "rJ" } },
1554 { INDEX_op_not_i64
, { "r", "rJ" } },
1556 { INDEX_op_ext32s_i64
, { "r", "ri" } },
1557 { INDEX_op_ext32u_i64
, { "r", "ri" } },
1559 { INDEX_op_brcond_i64
, { "rZ", "rJ" } },
1560 { INDEX_op_setcond_i64
, { "r", "rZ", "rJ" } },
1561 { INDEX_op_movcond_i64
, { "r", "rZ", "rJ", "rI", "0" } },
1564 #if TCG_TARGET_REG_BITS == 64
1565 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1566 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1567 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1568 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1569 { INDEX_op_qemu_ld32
, { "r", "L" } },
1570 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1571 { INDEX_op_qemu_ld32s
, { "r", "L" } },
1572 { INDEX_op_qemu_ld64
, { "r", "L" } },
1574 { INDEX_op_qemu_st8
, { "L", "L" } },
1575 { INDEX_op_qemu_st16
, { "L", "L" } },
1576 { INDEX_op_qemu_st32
, { "L", "L" } },
1577 { INDEX_op_qemu_st64
, { "L", "L" } },
1578 #elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
1579 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1580 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1581 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1582 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1583 { INDEX_op_qemu_ld32
, { "r", "L" } },
1584 { INDEX_op_qemu_ld64
, { "r", "r", "L" } },
1586 { INDEX_op_qemu_st8
, { "L", "L" } },
1587 { INDEX_op_qemu_st16
, { "L", "L" } },
1588 { INDEX_op_qemu_st32
, { "L", "L" } },
1589 { INDEX_op_qemu_st64
, { "L", "L", "L" } },
1591 { INDEX_op_qemu_ld8u
, { "r", "L", "L" } },
1592 { INDEX_op_qemu_ld8s
, { "r", "L", "L" } },
1593 { INDEX_op_qemu_ld16u
, { "r", "L", "L" } },
1594 { INDEX_op_qemu_ld16s
, { "r", "L", "L" } },
1595 { INDEX_op_qemu_ld32
, { "r", "L", "L" } },
1596 { INDEX_op_qemu_ld64
, { "L", "L", "L", "L" } },
1598 { INDEX_op_qemu_st8
, { "L", "L", "L" } },
1599 { INDEX_op_qemu_st16
, { "L", "L", "L" } },
1600 { INDEX_op_qemu_st32
, { "L", "L", "L" } },
1601 { INDEX_op_qemu_st64
, { "L", "L", "L", "L" } },
1607 static void tcg_target_init(TCGContext
*s
)
1609 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
1610 #if TCG_TARGET_REG_BITS == 64
1611 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffffffff);
1613 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1629 tcg_regset_clear(s
->reserved_regs
);
1630 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_G0
); /* zero */
1631 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_G6
); /* reserved for os */
1632 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_G7
); /* thread pointer */
1633 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I6
); /* frame pointer */
1634 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_I7
); /* return address */
1635 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_O6
); /* stack pointer */
1636 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_T1
); /* for internal use */
1637 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_T2
); /* for internal use */
1639 tcg_add_target_add_op_defs(sparc_op_defs
);
1642 #if TCG_TARGET_REG_BITS == 64
1643 # define ELF_HOST_MACHINE EM_SPARCV9
1645 # define ELF_HOST_MACHINE EM_SPARC32PLUS
1646 # define ELF_HOST_FLAGS EF_SPARC_32PLUS
1651 DebugFrameFDEHeader fde
;
1652 uint8_t fde_def_cfa
[TCG_TARGET_REG_BITS
== 64 ? 4 : 2];
1653 uint8_t fde_win_save
;
1654 uint8_t fde_ret_save
[3];
1657 static DebugFrame debug_frame
= {
1658 .cie
.len
= sizeof(DebugFrameCIE
)-4, /* length after .len member */
1661 .cie
.code_align
= 1,
1662 .cie
.data_align
= -sizeof(void *) & 0x7f,
1663 .cie
.return_column
= 15, /* o7 */
1665 /* Total FDE size does not include the "len" member. */
1666 .fde
.len
= sizeof(DebugFrame
) - offsetof(DebugFrame
, fde
.cie_offset
),
1669 #if TCG_TARGET_REG_BITS == 64
1670 12, 30, /* DW_CFA_def_cfa i6, 2047 */
1671 (2047 & 0x7f) | 0x80, (2047 >> 7)
1673 13, 30 /* DW_CFA_def_cfa_register i6 */
1676 .fde_win_save
= 0x2d, /* DW_CFA_GNU_window_save */
1677 .fde_ret_save
= { 9, 15, 31 }, /* DW_CFA_register o7, i7 */
1680 void tcg_register_jit(void *buf
, size_t buf_size
)
1682 debug_frame
.fde
.func_start
= (tcg_target_long
) buf
;
1683 debug_frame
.fde
.func_len
= buf_size
;
1685 tcg_register_jit_int(buf
, buf_size
, &debug_frame
, sizeof(debug_frame
));
1688 void tb_set_jmp_target1(uintptr_t jmp_addr
, uintptr_t addr
)
1690 uint32_t *ptr
= (uint32_t *)jmp_addr
;
1691 tcg_target_long disp
= (tcg_target_long
)(addr
- jmp_addr
) >> 2;
1693 /* We can reach the entire address space for 32-bit. For 64-bit
1694 the code_gen_buffer can't be larger than 2GB. */
1695 if (TCG_TARGET_REG_BITS
== 64 && !check_fit_tl(disp
, 30)) {
1699 *ptr
= CALL
| (disp
& 0x3fffffff);
1700 flush_icache_range(jmp_addr
, jmp_addr
+ 4);