2 * QEMU SPAPR PCI BUS definitions
4 * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #if !defined(__HW_SPAPR_H__)
20 #error Please include spapr.h before this file!
23 #if !defined(__HW_SPAPR_PCI_H__)
24 #define __HW_SPAPR_PCI_H__
26 #include "hw/pci/pci.h"
27 #include "hw/pci/pci_host.h"
28 #include "hw/ppc/xics.h"
30 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
32 #define SPAPR_PCI_HOST_BRIDGE(obj) \
33 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
35 typedef struct sPAPRPHBState sPAPRPHBState
;
37 typedef struct spapr_pci_msi
{
42 typedef struct spapr_pci_msi_mig
{
47 struct sPAPRPHBState
{
48 PCIHostState parent_obj
;
55 MemoryRegion memspace
, iospace
;
56 hwaddr mem_win_addr
, mem_win_size
, io_win_addr
, io_win_size
;
57 MemoryRegion memwindow
, iowindow
, msiwindow
;
60 hwaddr dma_win_addr
, dma_win_size
;
61 AddressSpace iommu_as
;
62 MemoryRegion iommu_root
;
64 struct spapr_pci_lsi
{
66 } lsi_table
[PCI_NUM_PINS
];
69 /* Temporary cache for migration purposes */
71 spapr_pci_msi_mig
*msi_devs
;
73 QLIST_ENTRY(sPAPRPHBState
) list
;
76 #define SPAPR_PCI_MAX_INDEX 255
78 #define SPAPR_PCI_BASE_BUID 0x800000020000000ULL
80 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
82 #define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL
83 #define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL
84 #define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000
85 #define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \
86 SPAPR_PCI_MEM_WIN_BUS_OFFSET)
87 #define SPAPR_PCI_IO_WIN_OFF 0x80000000
88 #define SPAPR_PCI_IO_WIN_SIZE 0x10000
90 #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
92 static inline qemu_irq
spapr_phb_lsi_qirq(struct sPAPRPHBState
*phb
, int pin
)
94 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
96 return xics_get_qirq(spapr
->icp
, phb
->lsi_table
[pin
].irq
);
99 PCIHostState
*spapr_create_phb(sPAPRMachineState
*spapr
, int index
);
101 int spapr_populate_pci_dt(sPAPRPHBState
*phb
,
102 uint32_t xics_phandle
,
105 void spapr_pci_msi_init(sPAPRMachineState
*spapr
, hwaddr addr
);
107 void spapr_pci_rtas_init(void);
109 sPAPRPHBState
*spapr_pci_find_phb(sPAPRMachineState
*spapr
, uint64_t buid
);
110 PCIDevice
*spapr_pci_find_dev(sPAPRMachineState
*spapr
, uint64_t buid
,
111 uint32_t config_addr
);
115 bool spapr_phb_eeh_available(sPAPRPHBState
*sphb
);
116 int spapr_phb_vfio_eeh_set_option(sPAPRPHBState
*sphb
,
117 unsigned int addr
, int option
);
118 int spapr_phb_vfio_eeh_get_state(sPAPRPHBState
*sphb
, int *state
);
119 int spapr_phb_vfio_eeh_reset(sPAPRPHBState
*sphb
, int option
);
120 int spapr_phb_vfio_eeh_configure(sPAPRPHBState
*sphb
);
121 void spapr_phb_vfio_reset(DeviceState
*qdev
);
123 static inline bool spapr_phb_eeh_available(sPAPRPHBState
*sphb
)
127 static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState
*sphb
,
128 unsigned int addr
, int option
)
130 return RTAS_OUT_HW_ERROR
;
132 static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState
*sphb
,
135 return RTAS_OUT_HW_ERROR
;
137 static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState
*sphb
, int option
)
139 return RTAS_OUT_HW_ERROR
;
141 static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState
*sphb
)
143 return RTAS_OUT_HW_ERROR
;
145 static inline void spapr_phb_vfio_reset(DeviceState
*qdev
)
150 void spapr_phb_dma_reset(sPAPRPHBState
*sphb
);
152 #endif /* __HW_SPAPR_PCI_H__ */