target-arm/translate-a64.c

   1 /*
   2  *  AArch64 translation
   3  *
   4  *  Copyright (c) 2013 Alexander Graf <agraf@suse.de>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24
  25 #include "cpu.h"
  26 #include "tcg-op.h"
  27 #include "qemu/log.h"
  28 #include "translate.h"
  29 #include "qemu/host-utils.h"
  30
  31 #include "exec/gen-icount.h"
  32
  33 #include "helper.h"
  34 #define GEN_HELPER 1
  35 #include "helper.h"
  36
  37 static TCGv_i64 cpu_X[32];
  38 static TCGv_i64 cpu_pc;
  39 static TCGv_i32 pstate;
  40
  41 static const char *regnames[] = {
  42     "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
  43     "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
  44     "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
  45     "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
  46 };
  47
  48 /* initialize TCG globals.  */
  49 void a64_translate_init(void)
  50 {
  51     int i;
  52
  53     cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
  54                                     offsetof(CPUARMState, pc),
  55                                     "pc");
  56     for (i = 0; i < 32; i++) {
  57         cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
  58                                           offsetof(CPUARMState, xregs[i]),
  59                                           regnames[i]);
  60     }
  61
  62     pstate = tcg_global_mem_new_i32(TCG_AREG0,
  63                                     offsetof(CPUARMState, pstate),
  64                                     "pstate");
  65 }
  66
  67 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
  68                             fprintf_function cpu_fprintf, int flags)
  69 {
  70     ARMCPU *cpu = ARM_CPU(cs);
  71     CPUARMState *env = &cpu->env;
  72     uint32_t psr = pstate_read(env);
  73     int i;
  74
  75     cpu_fprintf(f, "PC=%016"PRIx64"  SP=%016"PRIx64"\n",
  76             env->pc, env->xregs[31]);
  77     for (i = 0; i < 31; i++) {
  78         cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
  79         if ((i % 4) == 3) {
  80             cpu_fprintf(f, "\n");
  81         } else {
  82             cpu_fprintf(f, " ");
  83         }
  84     }
  85     cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
  86                 psr,
  87                 psr & PSTATE_N ? 'N' : '-',
  88                 psr & PSTATE_Z ? 'Z' : '-',
  89                 psr & PSTATE_C ? 'C' : '-',
  90                 psr & PSTATE_V ? 'V' : '-');
  91     cpu_fprintf(f, "\n");
  92 }
  93
  94 void gen_a64_set_pc_im(uint64_t val)
  95 {
  96     tcg_gen_movi_i64(cpu_pc, val);
  97 }
  98
  99 static void gen_exception(int excp)
 100 {
 101     TCGv_i32 tmp = tcg_temp_new_i32();
 102     tcg_gen_movi_i32(tmp, excp);
 103     gen_helper_exception(cpu_env, tmp);
 104     tcg_temp_free_i32(tmp);
 105 }
 106
 107 static void gen_exception_insn(DisasContext *s, int offset, int excp)
 108 {
 109     gen_a64_set_pc_im(s->pc - offset);
 110     gen_exception(excp);
 111     s->is_jmp = DISAS_EXC;
 112 }
 113
 114 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
 115 {
 116     /* No direct tb linking with singlestep or deterministic io */
 117     if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
 118         return false;
 119     }
 120
 121     /* Only link tbs from inside the same guest page */
 122     if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
 123         return false;
 124     }
 125
 126     return true;
 127 }
 128
 129 static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
 130 {
 131     TranslationBlock *tb;
 132
 133     tb = s->tb;
 134     if (use_goto_tb(s, n, dest)) {
 135         tcg_gen_goto_tb(n);
 136         gen_a64_set_pc_im(dest);
 137         tcg_gen_exit_tb((tcg_target_long)tb + n);
 138         s->is_jmp = DISAS_TB_JUMP;
 139     } else {
 140         gen_a64_set_pc_im(dest);
 141         if (s->singlestep_enabled) {
 142             gen_exception(EXCP_DEBUG);
 143         }
 144         tcg_gen_exit_tb(0);
 145         s->is_jmp = DISAS_JUMP;
 146     }
 147 }
 148
 149 static void unallocated_encoding(DisasContext *s)
 150 {
 151     gen_exception_insn(s, 4, EXCP_UDEF);
 152 }
 153
 154 #define unsupported_encoding(s, insn)                                    \
 155     do {                                                                 \
 156         qemu_log_mask(LOG_UNIMP,                                         \
 157                       "%s:%d: unsupported instruction encoding 0x%08x "  \
 158                       "at pc=%016" PRIx64 "\n",                          \
 159                       __FILE__, __LINE__, insn, s->pc - 4);              \
 160         unallocated_encoding(s);                                         \
 161     } while (0);
 162
 163 static void init_tmp_a64_array(DisasContext *s)
 164 {
 165 #ifdef CONFIG_DEBUG_TCG
 166     int i;
 167     for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
 168         TCGV_UNUSED_I64(s->tmp_a64[i]);
 169     }
 170 #endif
 171     s->tmp_a64_count = 0;
 172 }
 173
 174 static void free_tmp_a64(DisasContext *s)
 175 {
 176     int i;
 177     for (i = 0; i < s->tmp_a64_count; i++) {
 178         tcg_temp_free_i64(s->tmp_a64[i]);
 179     }
 180     init_tmp_a64_array(s);
 181 }
 182
 183 static TCGv_i64 new_tmp_a64(DisasContext *s)
 184 {
 185     assert(s->tmp_a64_count < TMP_A64_MAX);
 186     return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
 187 }
 188
 189 static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
 190 {
 191     TCGv_i64 t = new_tmp_a64(s);
 192     tcg_gen_movi_i64(t, 0);
 193     return t;
 194 }
 195
 196 static TCGv_i64 cpu_reg(DisasContext *s, int reg)
 197 {
 198     if (reg == 31) {
 199         return new_tmp_a64_zero(s);
 200     } else {
 201         return cpu_X[reg];
 202     }
 203 }
 204
 205 /*
 206  * the instruction disassembly implemented here matches
 207  * the instruction encoding classifications in chapter 3 (C3)
 208  * of the ARM Architecture Reference Manual (DDI0487A_a)
 209  */
 210
 211 /* C3.2.7 Unconditional branch (immediate)
 212  *   31  30       26 25                                  0
 213  * +----+-----------+-------------------------------------+
 214  * | op | 0 0 1 0 1 |                 imm26               |
 215  * +----+-----------+-------------------------------------+
 216  */
 217 static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
 218 {
 219     uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
 220
 221     if (insn & (1 << 31)) {
 222         /* C5.6.26 BL Branch with link */
 223         tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
 224     }
 225
 226     /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
 227     gen_goto_tb(s, 0, addr);
 228 }
 229
 230 /* Compare & branch (immediate) */
 231 static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
 232 {
 233     unsupported_encoding(s, insn);
 234 }
 235
 236 /* Test & branch (immediate) */
 237 static void disas_test_b_imm(DisasContext *s, uint32_t insn)
 238 {
 239     unsupported_encoding(s, insn);
 240 }
 241
 242 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
 243  *  31           25  24  23                  5   4  3    0
 244  * +---------------+----+---------------------+----+------+
 245  * | 0 1 0 1 0 1 0 | o1 |         imm19       | o0 | cond |
 246  * +---------------+----+---------------------+----+------+
 247  */
 248 static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
 249 {
 250     unsigned int cond;
 251     uint64_t addr;
 252
 253     if ((insn & (1 << 4)) || (insn & (1 << 24))) {
 254         unallocated_encoding(s);
 255         return;
 256     }
 257     addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
 258     cond = extract32(insn, 0, 4);
 259
 260     if (cond < 0x0e) {
 261         /* genuinely conditional branches */
 262         int label_match = gen_new_label();
 263         arm_gen_test_cc(cond, label_match);
 264         gen_goto_tb(s, 0, s->pc);
 265         gen_set_label(label_match);
 266         gen_goto_tb(s, 1, addr);
 267     } else {
 268         /* 0xe and 0xf are both "always" conditions */
 269         gen_goto_tb(s, 0, addr);
 270     }
 271 }
 272
 273 /* C5.6.68 HINT */
 274 static void handle_hint(DisasContext *s, uint32_t insn,
 275                         unsigned int op1, unsigned int op2, unsigned int crm)
 276 {
 277     unsigned int selector = crm << 3 | op2;
 278
 279     if (op1 != 3) {
 280         unallocated_encoding(s);
 281         return;
 282     }
 283
 284     switch (selector) {
 285     case 0: /* NOP */
 286         return;
 287     case 1: /* YIELD */
 288     case 2: /* WFE */
 289     case 3: /* WFI */
 290     case 4: /* SEV */
 291     case 5: /* SEVL */
 292         /* we treat all as NOP at least for now */
 293         return;
 294     default:
 295         /* default specified as NOP equivalent */
 296         return;
 297     }
 298 }
 299
 300 /* CLREX, DSB, DMB, ISB */
 301 static void handle_sync(DisasContext *s, uint32_t insn,
 302                         unsigned int op1, unsigned int op2, unsigned int crm)
 303 {
 304     if (op1 != 3) {
 305         unallocated_encoding(s);
 306         return;
 307     }
 308
 309     switch (op2) {
 310     case 2: /* CLREX */
 311         unsupported_encoding(s, insn);
 312         return;
 313     case 4: /* DSB */
 314     case 5: /* DMB */
 315     case 6: /* ISB */
 316         /* We don't emulate caches so barriers are no-ops */
 317         return;
 318     default:
 319         unallocated_encoding(s);
 320         return;
 321     }
 322 }
 323
 324 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
 325 static void handle_msr_i(DisasContext *s, uint32_t insn,
 326                          unsigned int op1, unsigned int op2, unsigned int crm)
 327 {
 328     unsupported_encoding(s, insn);
 329 }
 330
 331 /* C5.6.204 SYS */
 332 static void handle_sys(DisasContext *s, uint32_t insn, unsigned int l,
 333                        unsigned int op1, unsigned int op2,
 334                        unsigned int crn, unsigned int crm, unsigned int rt)
 335 {
 336     unsupported_encoding(s, insn);
 337 }
 338
 339 /* C5.6.129 MRS - move from system register */
 340 static void handle_mrs(DisasContext *s, uint32_t insn, unsigned int op0,
 341                        unsigned int op1, unsigned int op2,
 342                        unsigned int crn, unsigned int crm, unsigned int rt)
 343 {
 344     unsupported_encoding(s, insn);
 345 }
 346
 347 /* C5.6.131 MSR (register) - move to system register */
 348 static void handle_msr(DisasContext *s, uint32_t insn, unsigned int op0,
 349                        unsigned int op1, unsigned int op2,
 350                        unsigned int crn, unsigned int crm, unsigned int rt)
 351 {
 352     unsupported_encoding(s, insn);
 353 }
 354
 355 /* C3.2.4 System
 356  *  31                 22 21  20 19 18 16 15   12 11    8 7   5 4    0
 357  * +---------------------+---+-----+-----+-------+-------+-----+------+
 358  * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 |  CRn  |  CRm  | op2 |  Rt  |
 359  * +---------------------+---+-----+-----+-------+-------+-----+------+
 360  */
 361 static void disas_system(DisasContext *s, uint32_t insn)
 362 {
 363     unsigned int l, op0, op1, crn, crm, op2, rt;
 364     l = extract32(insn, 21, 1);
 365     op0 = extract32(insn, 19, 2);
 366     op1 = extract32(insn, 16, 3);
 367     crn = extract32(insn, 12, 4);
 368     crm = extract32(insn, 8, 4);
 369     op2 = extract32(insn, 5, 3);
 370     rt = extract32(insn, 0, 5);
 371
 372     if (op0 == 0) {
 373         if (l || rt != 31) {
 374             unallocated_encoding(s);
 375             return;
 376         }
 377         switch (crn) {
 378         case 2: /* C5.6.68 HINT */
 379             handle_hint(s, insn, op1, op2, crm);
 380             break;
 381         case 3: /* CLREX, DSB, DMB, ISB */
 382             handle_sync(s, insn, op1, op2, crm);
 383             break;
 384         case 4: /* C5.6.130 MSR (immediate) */
 385             handle_msr_i(s, insn, op1, op2, crm);
 386             break;
 387         default:
 388             unallocated_encoding(s);
 389             break;
 390         }
 391         return;
 392     }
 393
 394     if (op0 == 1) {
 395         /* C5.6.204 SYS */
 396         handle_sys(s, insn, l, op1, op2, crn, crm, rt);
 397     } else if (l) { /* op0 > 1 */
 398         /* C5.6.129 MRS - move from system register */
 399         handle_mrs(s, insn, op0, op1, op2, crn, crm, rt);
 400     } else {
 401         /* C5.6.131 MSR (register) - move to system register */
 402         handle_msr(s, insn, op0, op1, op2, crn, crm, rt);
 403     }
 404 }
 405
 406 /* Exception generation */
 407 static void disas_exc(DisasContext *s, uint32_t insn)
 408 {
 409     unsupported_encoding(s, insn);
 410 }
 411
 412 /* C3.2.7 Unconditional branch (register)
 413  *  31           25 24   21 20   16 15   10 9    5 4     0
 414  * +---------------+-------+-------+-------+------+-------+
 415  * | 1 1 0 1 0 1 1 |  opc  |  op2  |  op3  |  Rn  |  op4  |
 416  * +---------------+-------+-------+-------+------+-------+
 417  */
 418 static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
 419 {
 420     unsigned int opc, op2, op3, rn, op4;
 421
 422     opc = extract32(insn, 21, 4);
 423     op2 = extract32(insn, 16, 5);
 424     op3 = extract32(insn, 10, 6);
 425     rn = extract32(insn, 5, 5);
 426     op4 = extract32(insn, 0, 5);
 427
 428     if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
 429         unallocated_encoding(s);
 430         return;
 431     }
 432
 433     switch (opc) {
 434     case 0: /* BR */
 435     case 2: /* RET */
 436         break;
 437     case 1: /* BLR */
 438         tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
 439         break;
 440     case 4: /* ERET */
 441     case 5: /* DRPS */
 442         if (rn != 0x1f) {
 443             unallocated_encoding(s);
 444         } else {
 445             unsupported_encoding(s, insn);
 446         }
 447         return;
 448     default:
 449         unallocated_encoding(s);
 450         return;
 451     }
 452
 453     tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
 454     s->is_jmp = DISAS_JUMP;
 455 }
 456
 457 /* C3.2 Branches, exception generating and system instructions */
 458 static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
 459 {
 460     switch (extract32(insn, 25, 7)) {
 461     case 0x0a: case 0x0b:
 462     case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
 463         disas_uncond_b_imm(s, insn);
 464         break;
 465     case 0x1a: case 0x5a: /* Compare & branch (immediate) */
 466         disas_comp_b_imm(s, insn);
 467         break;
 468     case 0x1b: case 0x5b: /* Test & branch (immediate) */
 469         disas_test_b_imm(s, insn);
 470         break;
 471     case 0x2a: /* Conditional branch (immediate) */
 472         disas_cond_b_imm(s, insn);
 473         break;
 474     case 0x6a: /* Exception generation / System */
 475         if (insn & (1 << 24)) {
 476             disas_system(s, insn);
 477         } else {
 478             disas_exc(s, insn);
 479         }
 480         break;
 481     case 0x6b: /* Unconditional branch (register) */
 482         disas_uncond_b_reg(s, insn);
 483         break;
 484     default:
 485         unallocated_encoding(s);
 486         break;
 487     }
 488 }
 489
 490 /* Load/store exclusive */
 491 static void disas_ldst_excl(DisasContext *s, uint32_t insn)
 492 {
 493     unsupported_encoding(s, insn);
 494 }
 495
 496 /* Load register (literal) */
 497 static void disas_ld_lit(DisasContext *s, uint32_t insn)
 498 {
 499     unsupported_encoding(s, insn);
 500 }
 501
 502 /* Load/store pair (all forms) */
 503 static void disas_ldst_pair(DisasContext *s, uint32_t insn)
 504 {
 505     unsupported_encoding(s, insn);
 506 }
 507
 508 /* Load/store register (all forms) */
 509 static void disas_ldst_reg(DisasContext *s, uint32_t insn)
 510 {
 511     unsupported_encoding(s, insn);
 512 }
 513
 514 /* AdvSIMD load/store multiple structures */
 515 static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
 516 {
 517     unsupported_encoding(s, insn);
 518 }
 519
 520 /* AdvSIMD load/store single structure */
 521 static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
 522 {
 523     unsupported_encoding(s, insn);
 524 }
 525
 526 /* C3.3 Loads and stores */
 527 static void disas_ldst(DisasContext *s, uint32_t insn)
 528 {
 529     switch (extract32(insn, 24, 6)) {
 530     case 0x08: /* Load/store exclusive */
 531         disas_ldst_excl(s, insn);
 532         break;
 533     case 0x18: case 0x1c: /* Load register (literal) */
 534         disas_ld_lit(s, insn);
 535         break;
 536     case 0x28: case 0x29:
 537     case 0x2c: case 0x2d: /* Load/store pair (all forms) */
 538         disas_ldst_pair(s, insn);
 539         break;
 540     case 0x38: case 0x39:
 541     case 0x3c: case 0x3d: /* Load/store register (all forms) */
 542         disas_ldst_reg(s, insn);
 543         break;
 544     case 0x0c: /* AdvSIMD load/store multiple structures */
 545         disas_ldst_multiple_struct(s, insn);
 546         break;
 547     case 0x0d: /* AdvSIMD load/store single structure */
 548         disas_ldst_single_struct(s, insn);
 549         break;
 550     default:
 551         unallocated_encoding(s);
 552         break;
 553     }
 554 }
 555
 556 /* PC-rel. addressing */
 557 static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
 558 {
 559     unsupported_encoding(s, insn);
 560 }
 561
 562 /* Add/subtract (immediate) */
 563 static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
 564 {
 565     unsupported_encoding(s, insn);
 566 }
 567
 568 /* Logical (immediate) */
 569 static void disas_logic_imm(DisasContext *s, uint32_t insn)
 570 {
 571     unsupported_encoding(s, insn);
 572 }
 573
 574 /* Move wide (immediate) */
 575 static void disas_movw_imm(DisasContext *s, uint32_t insn)
 576 {
 577     unsupported_encoding(s, insn);
 578 }
 579
 580 /* Bitfield */
 581 static void disas_bitfield(DisasContext *s, uint32_t insn)
 582 {
 583     unsupported_encoding(s, insn);
 584 }
 585
 586 /* Extract */
 587 static void disas_extract(DisasContext *s, uint32_t insn)
 588 {
 589     unsupported_encoding(s, insn);
 590 }
 591
 592 /* C3.4 Data processing - immediate */
 593 static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
 594 {
 595     switch (extract32(insn, 23, 6)) {
 596     case 0x20: case 0x21: /* PC-rel. addressing */
 597         disas_pc_rel_adr(s, insn);
 598         break;
 599     case 0x22: case 0x23: /* Add/subtract (immediate) */
 600         disas_add_sub_imm(s, insn);
 601         break;
 602     case 0x24: /* Logical (immediate) */
 603         disas_logic_imm(s, insn);
 604         break;
 605     case 0x25: /* Move wide (immediate) */
 606         disas_movw_imm(s, insn);
 607         break;
 608     case 0x26: /* Bitfield */
 609         disas_bitfield(s, insn);
 610         break;
 611     case 0x27: /* Extract */
 612         disas_extract(s, insn);
 613         break;
 614     default:
 615         unallocated_encoding(s);
 616         break;
 617     }
 618 }
 619
 620 /* Logical (shifted register) */
 621 static void disas_logic_reg(DisasContext *s, uint32_t insn)
 622 {
 623     unsupported_encoding(s, insn);
 624 }
 625
 626 /* Add/subtract (extended register) */
 627 static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
 628 {
 629     unsupported_encoding(s, insn);
 630 }
 631
 632 /* Add/subtract (shifted register) */
 633 static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
 634 {
 635     unsupported_encoding(s, insn);
 636 }
 637
 638 /* Data-processing (3 source) */
 639 static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
 640 {
 641     unsupported_encoding(s, insn);
 642 }
 643
 644 /* Add/subtract (with carry) */
 645 static void disas_adc_sbc(DisasContext *s, uint32_t insn)
 646 {
 647     unsupported_encoding(s, insn);
 648 }
 649
 650 /* Conditional compare (immediate) */
 651 static void disas_cc_imm(DisasContext *s, uint32_t insn)
 652 {
 653     unsupported_encoding(s, insn);
 654 }
 655
 656 /* Conditional compare (register) */
 657 static void disas_cc_reg(DisasContext *s, uint32_t insn)
 658 {
 659     unsupported_encoding(s, insn);
 660 }
 661
 662 /* Conditional select */
 663 static void disas_cond_select(DisasContext *s, uint32_t insn)
 664 {
 665     unsupported_encoding(s, insn);
 666 }
 667
 668 /* Data-processing (1 source) */
 669 static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
 670 {
 671     unsupported_encoding(s, insn);
 672 }
 673
 674 /* Data-processing (2 source) */
 675 static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
 676 {
 677     unsupported_encoding(s, insn);
 678 }
 679
 680 /* C3.5 Data processing - register */
 681 static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
 682 {
 683     switch (extract32(insn, 24, 5)) {
 684     case 0x0a: /* Logical (shifted register) */
 685         disas_logic_reg(s, insn);
 686         break;
 687     case 0x0b: /* Add/subtract */
 688         if (insn & (1 << 21)) { /* (extended register) */
 689             disas_add_sub_ext_reg(s, insn);
 690         } else {
 691             disas_add_sub_reg(s, insn);
 692         }
 693         break;
 694     case 0x1b: /* Data-processing (3 source) */
 695         disas_data_proc_3src(s, insn);
 696         break;
 697     case 0x1a:
 698         switch (extract32(insn, 21, 3)) {
 699         case 0x0: /* Add/subtract (with carry) */
 700             disas_adc_sbc(s, insn);
 701             break;
 702         case 0x2: /* Conditional compare */
 703             if (insn & (1 << 11)) { /* (immediate) */
 704                 disas_cc_imm(s, insn);
 705             } else {            /* (register) */
 706                 disas_cc_reg(s, insn);
 707             }
 708             break;
 709         case 0x4: /* Conditional select */
 710             disas_cond_select(s, insn);
 711             break;
 712         case 0x6: /* Data-processing */
 713             if (insn & (1 << 30)) { /* (1 source) */
 714                 disas_data_proc_1src(s, insn);
 715             } else {            /* (2 source) */
 716                 disas_data_proc_2src(s, insn);
 717             }
 718             break;
 719         default:
 720             unallocated_encoding(s);
 721             break;
 722         }
 723         break;
 724     default:
 725         unallocated_encoding(s);
 726         break;
 727     }
 728 }
 729
 730 /* C3.6 Data processing - SIMD and floating point */
 731 static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
 732 {
 733     unsupported_encoding(s, insn);
 734 }
 735
 736 /* C3.1 A64 instruction index by encoding */
 737 static void disas_a64_insn(CPUARMState *env, DisasContext *s)
 738 {
 739     uint32_t insn;
 740
 741     insn = arm_ldl_code(env, s->pc, s->bswap_code);
 742     s->insn = insn;
 743     s->pc += 4;
 744
 745     switch (extract32(insn, 25, 4)) {
 746     case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
 747         unallocated_encoding(s);
 748         break;
 749     case 0x8: case 0x9: /* Data processing - immediate */
 750         disas_data_proc_imm(s, insn);
 751         break;
 752     case 0xa: case 0xb: /* Branch, exception generation and system insns */
 753         disas_b_exc_sys(s, insn);
 754         break;
 755     case 0x4:
 756     case 0x6:
 757     case 0xc:
 758     case 0xe:      /* Loads and stores */
 759         disas_ldst(s, insn);
 760         break;
 761     case 0x5:
 762     case 0xd:      /* Data processing - register */
 763         disas_data_proc_reg(s, insn);
 764         break;
 765     case 0x7:
 766     case 0xf:      /* Data processing - SIMD and floating point */
 767         disas_data_proc_simd_fp(s, insn);
 768         break;
 769     default:
 770         assert(FALSE); /* all 15 cases should be handled above */
 771         break;
 772     }
 773
 774     /* if we allocated any temporaries, free them here */
 775     free_tmp_a64(s);
 776 }
 777
 778 void gen_intermediate_code_internal_a64(ARMCPU *cpu,
 779                                         TranslationBlock *tb,
 780                                         bool search_pc)
 781 {
 782     CPUState *cs = CPU(cpu);
 783     CPUARMState *env = &cpu->env;
 784     DisasContext dc1, *dc = &dc1;
 785     CPUBreakpoint *bp;
 786     uint16_t *gen_opc_end;
 787     int j, lj;
 788     target_ulong pc_start;
 789     target_ulong next_page_start;
 790     int num_insns;
 791     int max_insns;
 792
 793     pc_start = tb->pc;
 794
 795     dc->tb = tb;
 796
 797     gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
 798
 799     dc->is_jmp = DISAS_NEXT;
 800     dc->pc = pc_start;
 801     dc->singlestep_enabled = cs->singlestep_enabled;
 802     dc->condjmp = 0;
 803
 804     dc->aarch64 = 1;
 805     dc->thumb = 0;
 806     dc->bswap_code = 0;
 807     dc->condexec_mask = 0;
 808     dc->condexec_cond = 0;
 809 #if !defined(CONFIG_USER_ONLY)
 810     dc->user = 0;
 811 #endif
 812     dc->vfp_enabled = 0;
 813     dc->vec_len = 0;
 814     dc->vec_stride = 0;
 815
 816     init_tmp_a64_array(dc);
 817
 818     next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
 819     lj = -1;
 820     num_insns = 0;
 821     max_insns = tb->cflags & CF_COUNT_MASK;
 822     if (max_insns == 0) {
 823         max_insns = CF_COUNT_MASK;
 824     }
 825
 826     gen_tb_start();
 827
 828     tcg_clear_temp_count();
 829
 830     do {
 831         if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
 832             QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
 833                 if (bp->pc == dc->pc) {
 834                     gen_exception_insn(dc, 0, EXCP_DEBUG);
 835                     /* Advance PC so that clearing the breakpoint will
 836                        invalidate this TB.  */
 837                     dc->pc += 2;
 838                     goto done_generating;
 839                 }
 840             }
 841         }
 842
 843         if (search_pc) {
 844             j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
 845             if (lj < j) {
 846                 lj++;
 847                 while (lj < j) {
 848                     tcg_ctx.gen_opc_instr_start[lj++] = 0;
 849                 }
 850             }
 851             tcg_ctx.gen_opc_pc[lj] = dc->pc;
 852             tcg_ctx.gen_opc_instr_start[lj] = 1;
 853             tcg_ctx.gen_opc_icount[lj] = num_insns;
 854         }
 855
 856         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
 857             gen_io_start();
 858         }
 859
 860         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
 861             tcg_gen_debug_insn_start(dc->pc);
 862         }
 863
 864         disas_a64_insn(env, dc);
 865
 866         if (tcg_check_temp_count()) {
 867             fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
 868                     dc->pc);
 869         }
 870
 871         /* Translation stops when a conditional branch is encountered.
 872          * Otherwise the subsequent code could get translated several times.
 873          * Also stop translation when a page boundary is reached.  This
 874          * ensures prefetch aborts occur at the right place.
 875          */
 876         num_insns++;
 877     } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
 878              !cs->singlestep_enabled &&
 879              !singlestep &&
 880              dc->pc < next_page_start &&
 881              num_insns < max_insns);
 882
 883     if (tb->cflags & CF_LAST_IO) {
 884         gen_io_end();
 885     }
 886
 887     if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) {
 888         /* Note that this means single stepping WFI doesn't halt the CPU.
 889          * For conditional branch insns this is harmless unreachable code as
 890          * gen_goto_tb() has already handled emitting the debug exception
 891          * (and thus a tb-jump is not possible when singlestepping).
 892          */
 893         assert(dc->is_jmp != DISAS_TB_JUMP);
 894         if (dc->is_jmp != DISAS_JUMP) {
 895             gen_a64_set_pc_im(dc->pc);
 896         }
 897         gen_exception(EXCP_DEBUG);
 898     } else {
 899         switch (dc->is_jmp) {
 900         case DISAS_NEXT:
 901             gen_goto_tb(dc, 1, dc->pc);
 902             break;
 903         default:
 904         case DISAS_JUMP:
 905         case DISAS_UPDATE:
 906             /* indicate that the hash table must be used to find the next TB */
 907             tcg_gen_exit_tb(0);
 908             break;
 909         case DISAS_TB_JUMP:
 910         case DISAS_EXC:
 911         case DISAS_SWI:
 912             break;
 913         case DISAS_WFI:
 914             /* This is a special case because we don't want to just halt the CPU
 915              * if trying to debug across a WFI.
 916              */
 917             gen_helper_wfi(cpu_env);
 918             break;
 919         }
 920     }
 921
 922 done_generating:
 923     gen_tb_end(tb, num_insns);
 924     *tcg_ctx.gen_opc_ptr = INDEX_op_end;
 925
 926 #ifdef DEBUG_DISAS
 927     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
 928         qemu_log("----------------\n");
 929         qemu_log("IN: %s\n", lookup_symbol(pc_start));
 930         log_target_disas(env, pc_start, dc->pc - pc_start,
 931                          dc->thumb | (dc->bswap_code << 1));
 932         qemu_log("\n");
 933     }
 934 #endif
 935     if (search_pc) {
 936         j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
 937         lj++;
 938         while (lj <= j) {
 939             tcg_ctx.gen_opc_instr_start[lj++] = 0;
 940         }
 941     } else {
 942         tb->size = dc->pc - pc_start;
 943         tb->icount = num_insns;
 944     }
 945 }