2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 int gen_new_label(void);
28 static inline void tcg_gen_op0(TCGOpcode opc
)
30 *tcg_ctx
.gen_opc_ptr
++ = opc
;
33 static inline void tcg_gen_op1_i32(TCGOpcode opc
, TCGv_i32 arg1
)
35 *tcg_ctx
.gen_opc_ptr
++ = opc
;
36 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
39 static inline void tcg_gen_op1_i64(TCGOpcode opc
, TCGv_i64 arg1
)
41 *tcg_ctx
.gen_opc_ptr
++ = opc
;
42 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
45 static inline void tcg_gen_op1i(TCGOpcode opc
, TCGArg arg1
)
47 *tcg_ctx
.gen_opc_ptr
++ = opc
;
48 *tcg_ctx
.gen_opparam_ptr
++ = arg1
;
51 static inline void tcg_gen_op2_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
)
53 *tcg_ctx
.gen_opc_ptr
++ = opc
;
54 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
55 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
58 static inline void tcg_gen_op2_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
)
60 *tcg_ctx
.gen_opc_ptr
++ = opc
;
61 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
62 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
65 static inline void tcg_gen_op2i_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGArg arg2
)
67 *tcg_ctx
.gen_opc_ptr
++ = opc
;
68 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
69 *tcg_ctx
.gen_opparam_ptr
++ = arg2
;
72 static inline void tcg_gen_op2i_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGArg arg2
)
74 *tcg_ctx
.gen_opc_ptr
++ = opc
;
75 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
76 *tcg_ctx
.gen_opparam_ptr
++ = arg2
;
79 static inline void tcg_gen_op2ii(TCGOpcode opc
, TCGArg arg1
, TCGArg arg2
)
81 *tcg_ctx
.gen_opc_ptr
++ = opc
;
82 *tcg_ctx
.gen_opparam_ptr
++ = arg1
;
83 *tcg_ctx
.gen_opparam_ptr
++ = arg2
;
86 static inline void tcg_gen_op3_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
89 *tcg_ctx
.gen_opc_ptr
++ = opc
;
90 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
91 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
92 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
95 static inline void tcg_gen_op3_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
98 *tcg_ctx
.gen_opc_ptr
++ = opc
;
99 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
100 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
101 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
104 static inline void tcg_gen_op3i_i32(TCGOpcode opc
, TCGv_i32 arg1
,
105 TCGv_i32 arg2
, TCGArg arg3
)
107 *tcg_ctx
.gen_opc_ptr
++ = opc
;
108 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
109 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
110 *tcg_ctx
.gen_opparam_ptr
++ = arg3
;
113 static inline void tcg_gen_op3i_i64(TCGOpcode opc
, TCGv_i64 arg1
,
114 TCGv_i64 arg2
, TCGArg arg3
)
116 *tcg_ctx
.gen_opc_ptr
++ = opc
;
117 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
118 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
119 *tcg_ctx
.gen_opparam_ptr
++ = arg3
;
122 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc
, TCGv_i32 val
,
123 TCGv_ptr base
, TCGArg offset
)
125 *tcg_ctx
.gen_opc_ptr
++ = opc
;
126 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(val
);
127 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_PTR(base
);
128 *tcg_ctx
.gen_opparam_ptr
++ = offset
;
131 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc
, TCGv_i64 val
,
132 TCGv_ptr base
, TCGArg offset
)
134 *tcg_ctx
.gen_opc_ptr
++ = opc
;
135 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(val
);
136 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_PTR(base
);
137 *tcg_ctx
.gen_opparam_ptr
++ = offset
;
140 static inline void tcg_gen_op4_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
141 TCGv_i32 arg3
, TCGv_i32 arg4
)
143 *tcg_ctx
.gen_opc_ptr
++ = opc
;
144 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
145 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
146 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
147 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
150 static inline void tcg_gen_op4_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
151 TCGv_i64 arg3
, TCGv_i64 arg4
)
153 *tcg_ctx
.gen_opc_ptr
++ = opc
;
154 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
155 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
156 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
157 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
160 static inline void tcg_gen_op4i_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
161 TCGv_i32 arg3
, TCGArg arg4
)
163 *tcg_ctx
.gen_opc_ptr
++ = opc
;
164 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
165 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
166 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
167 *tcg_ctx
.gen_opparam_ptr
++ = arg4
;
170 static inline void tcg_gen_op4i_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
171 TCGv_i64 arg3
, TCGArg arg4
)
173 *tcg_ctx
.gen_opc_ptr
++ = opc
;
174 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
175 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
176 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
177 *tcg_ctx
.gen_opparam_ptr
++ = arg4
;
180 static inline void tcg_gen_op4ii_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
181 TCGArg arg3
, TCGArg arg4
)
183 *tcg_ctx
.gen_opc_ptr
++ = opc
;
184 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
185 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
186 *tcg_ctx
.gen_opparam_ptr
++ = arg3
;
187 *tcg_ctx
.gen_opparam_ptr
++ = arg4
;
190 static inline void tcg_gen_op4ii_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
191 TCGArg arg3
, TCGArg arg4
)
193 *tcg_ctx
.gen_opc_ptr
++ = opc
;
194 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
195 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
196 *tcg_ctx
.gen_opparam_ptr
++ = arg3
;
197 *tcg_ctx
.gen_opparam_ptr
++ = arg4
;
200 static inline void tcg_gen_op5_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
201 TCGv_i32 arg3
, TCGv_i32 arg4
, TCGv_i32 arg5
)
203 *tcg_ctx
.gen_opc_ptr
++ = opc
;
204 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
205 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
206 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
207 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
208 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg5
);
211 static inline void tcg_gen_op5_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
212 TCGv_i64 arg3
, TCGv_i64 arg4
, TCGv_i64 arg5
)
214 *tcg_ctx
.gen_opc_ptr
++ = opc
;
215 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
216 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
217 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
218 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
219 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg5
);
222 static inline void tcg_gen_op5i_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
223 TCGv_i32 arg3
, TCGv_i32 arg4
, TCGArg arg5
)
225 *tcg_ctx
.gen_opc_ptr
++ = opc
;
226 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
227 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
228 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
229 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
230 *tcg_ctx
.gen_opparam_ptr
++ = arg5
;
233 static inline void tcg_gen_op5i_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
234 TCGv_i64 arg3
, TCGv_i64 arg4
, TCGArg arg5
)
236 *tcg_ctx
.gen_opc_ptr
++ = opc
;
237 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
238 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
239 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
240 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
241 *tcg_ctx
.gen_opparam_ptr
++ = arg5
;
244 static inline void tcg_gen_op5ii_i32(TCGOpcode opc
, TCGv_i32 arg1
,
245 TCGv_i32 arg2
, TCGv_i32 arg3
,
246 TCGArg arg4
, TCGArg arg5
)
248 *tcg_ctx
.gen_opc_ptr
++ = opc
;
249 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
250 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
251 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
252 *tcg_ctx
.gen_opparam_ptr
++ = arg4
;
253 *tcg_ctx
.gen_opparam_ptr
++ = arg5
;
256 static inline void tcg_gen_op5ii_i64(TCGOpcode opc
, TCGv_i64 arg1
,
257 TCGv_i64 arg2
, TCGv_i64 arg3
,
258 TCGArg arg4
, TCGArg arg5
)
260 *tcg_ctx
.gen_opc_ptr
++ = opc
;
261 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
262 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
263 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
264 *tcg_ctx
.gen_opparam_ptr
++ = arg4
;
265 *tcg_ctx
.gen_opparam_ptr
++ = arg5
;
268 static inline void tcg_gen_op6_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
269 TCGv_i32 arg3
, TCGv_i32 arg4
, TCGv_i32 arg5
,
272 *tcg_ctx
.gen_opc_ptr
++ = opc
;
273 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
274 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
275 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
276 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
277 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg5
);
278 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg6
);
281 static inline void tcg_gen_op6_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
282 TCGv_i64 arg3
, TCGv_i64 arg4
, TCGv_i64 arg5
,
285 *tcg_ctx
.gen_opc_ptr
++ = opc
;
286 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
287 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
288 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
289 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
290 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg5
);
291 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg6
);
294 static inline void tcg_gen_op6i_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
295 TCGv_i32 arg3
, TCGv_i32 arg4
,
296 TCGv_i32 arg5
, TCGArg arg6
)
298 *tcg_ctx
.gen_opc_ptr
++ = opc
;
299 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
300 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
301 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
302 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
303 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg5
);
304 *tcg_ctx
.gen_opparam_ptr
++ = arg6
;
307 static inline void tcg_gen_op6i_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
308 TCGv_i64 arg3
, TCGv_i64 arg4
,
309 TCGv_i64 arg5
, TCGArg arg6
)
311 *tcg_ctx
.gen_opc_ptr
++ = opc
;
312 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
313 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
314 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
315 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
316 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg5
);
317 *tcg_ctx
.gen_opparam_ptr
++ = arg6
;
320 static inline void tcg_gen_op6ii_i32(TCGOpcode opc
, TCGv_i32 arg1
,
321 TCGv_i32 arg2
, TCGv_i32 arg3
,
322 TCGv_i32 arg4
, TCGArg arg5
, TCGArg arg6
)
324 *tcg_ctx
.gen_opc_ptr
++ = opc
;
325 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
326 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
327 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
328 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
329 *tcg_ctx
.gen_opparam_ptr
++ = arg5
;
330 *tcg_ctx
.gen_opparam_ptr
++ = arg6
;
333 static inline void tcg_gen_op6ii_i64(TCGOpcode opc
, TCGv_i64 arg1
,
334 TCGv_i64 arg2
, TCGv_i64 arg3
,
335 TCGv_i64 arg4
, TCGArg arg5
, TCGArg arg6
)
337 *tcg_ctx
.gen_opc_ptr
++ = opc
;
338 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
339 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
340 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
341 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
342 *tcg_ctx
.gen_opparam_ptr
++ = arg5
;
343 *tcg_ctx
.gen_opparam_ptr
++ = arg6
;
346 static inline void tcg_add_param_i32(TCGv_i32 val
)
348 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(val
);
351 static inline void tcg_add_param_i64(TCGv_i64 val
)
353 #if TCG_TARGET_REG_BITS == 32
354 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(TCGV_LOW(val
));
355 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I32(TCGV_HIGH(val
));
357 *tcg_ctx
.gen_opparam_ptr
++ = GET_TCGV_I64(val
);
361 static inline void gen_set_label(int n
)
363 tcg_gen_op1i(INDEX_op_set_label
, n
);
366 static inline void tcg_gen_br(int label
)
368 tcg_gen_op1i(INDEX_op_br
, label
);
371 static inline void tcg_gen_mov_i32(TCGv_i32 ret
, TCGv_i32 arg
)
373 if (!TCGV_EQUAL_I32(ret
, arg
))
374 tcg_gen_op2_i32(INDEX_op_mov_i32
, ret
, arg
);
377 static inline void tcg_gen_movi_i32(TCGv_i32 ret
, int32_t arg
)
379 tcg_gen_op2i_i32(INDEX_op_movi_i32
, ret
, arg
);
382 /* A version of dh_sizemask from def-helper.h that doesn't rely on
383 preprocessor magic. */
384 static inline int tcg_gen_sizemask(int n
, int is_64bit
, int is_signed
)
386 return (is_64bit
<< n
*2) | (is_signed
<< (n
*2 + 1));
390 static inline void tcg_gen_helperN(void *func
, int flags
, int sizemask
,
391 TCGArg ret
, int nargs
, TCGArg
*args
)
393 tcg_gen_callN(&tcg_ctx
, func
, flags
, sizemask
, ret
, nargs
, args
);
396 /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
397 reserved for helpers in tcg-runtime.c. These helpers all do not read
398 globals and do not have side effects, hence the call to tcg_gen_callN()
399 with TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_SIDE_EFFECTS. This may need
400 to be adjusted if these functions start to be used with other helpers. */
401 static inline void tcg_gen_helper32(void *func
, int sizemask
, TCGv_i32 ret
,
402 TCGv_i32 a
, TCGv_i32 b
)
405 args
[0] = GET_TCGV_I32(a
);
406 args
[1] = GET_TCGV_I32(b
);
407 tcg_gen_callN(&tcg_ctx
, func
,
408 TCG_CALL_NO_READ_GLOBALS
| TCG_CALL_NO_SIDE_EFFECTS
,
409 sizemask
, GET_TCGV_I32(ret
), 2, args
);
412 static inline void tcg_gen_helper64(void *func
, int sizemask
, TCGv_i64 ret
,
413 TCGv_i64 a
, TCGv_i64 b
)
416 args
[0] = GET_TCGV_I64(a
);
417 args
[1] = GET_TCGV_I64(b
);
418 tcg_gen_callN(&tcg_ctx
, func
,
419 TCG_CALL_NO_READ_GLOBALS
| TCG_CALL_NO_SIDE_EFFECTS
,
420 sizemask
, GET_TCGV_I64(ret
), 2, args
);
425 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
427 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32
, ret
, arg2
, offset
);
430 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
432 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32
, ret
, arg2
, offset
);
435 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
437 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32
, ret
, arg2
, offset
);
440 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
442 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32
, ret
, arg2
, offset
);
445 static inline void tcg_gen_ld_i32(TCGv_i32 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
447 tcg_gen_ldst_op_i32(INDEX_op_ld_i32
, ret
, arg2
, offset
);
450 static inline void tcg_gen_st8_i32(TCGv_i32 arg1
, TCGv_ptr arg2
, tcg_target_long offset
)
452 tcg_gen_ldst_op_i32(INDEX_op_st8_i32
, arg1
, arg2
, offset
);
455 static inline void tcg_gen_st16_i32(TCGv_i32 arg1
, TCGv_ptr arg2
, tcg_target_long offset
)
457 tcg_gen_ldst_op_i32(INDEX_op_st16_i32
, arg1
, arg2
, offset
);
460 static inline void tcg_gen_st_i32(TCGv_i32 arg1
, TCGv_ptr arg2
, tcg_target_long offset
)
462 tcg_gen_ldst_op_i32(INDEX_op_st_i32
, arg1
, arg2
, offset
);
465 static inline void tcg_gen_add_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
467 tcg_gen_op3_i32(INDEX_op_add_i32
, ret
, arg1
, arg2
);
470 static inline void tcg_gen_addi_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
472 /* some cases can be optimized here */
474 tcg_gen_mov_i32(ret
, arg1
);
476 TCGv_i32 t0
= tcg_const_i32(arg2
);
477 tcg_gen_add_i32(ret
, arg1
, t0
);
478 tcg_temp_free_i32(t0
);
482 static inline void tcg_gen_sub_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
484 tcg_gen_op3_i32(INDEX_op_sub_i32
, ret
, arg1
, arg2
);
487 static inline void tcg_gen_subfi_i32(TCGv_i32 ret
, int32_t arg1
, TCGv_i32 arg2
)
489 TCGv_i32 t0
= tcg_const_i32(arg1
);
490 tcg_gen_sub_i32(ret
, t0
, arg2
);
491 tcg_temp_free_i32(t0
);
494 static inline void tcg_gen_subi_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
496 /* some cases can be optimized here */
498 tcg_gen_mov_i32(ret
, arg1
);
500 TCGv_i32 t0
= tcg_const_i32(arg2
);
501 tcg_gen_sub_i32(ret
, arg1
, t0
);
502 tcg_temp_free_i32(t0
);
506 static inline void tcg_gen_and_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
508 if (TCGV_EQUAL_I32(arg1
, arg2
)) {
509 tcg_gen_mov_i32(ret
, arg1
);
511 tcg_gen_op3_i32(INDEX_op_and_i32
, ret
, arg1
, arg2
);
515 static inline void tcg_gen_andi_i32(TCGv_i32 ret
, TCGv_i32 arg1
, uint32_t arg2
)
518 /* Some cases can be optimized here. */
521 tcg_gen_movi_i32(ret
, 0);
524 tcg_gen_mov_i32(ret
, arg1
);
527 /* Don't recurse with tcg_gen_ext8u_i32. */
528 if (TCG_TARGET_HAS_ext8u_i32
) {
529 tcg_gen_op2_i32(INDEX_op_ext8u_i32
, ret
, arg1
);
534 if (TCG_TARGET_HAS_ext16u_i32
) {
535 tcg_gen_op2_i32(INDEX_op_ext16u_i32
, ret
, arg1
);
540 t0
= tcg_const_i32(arg2
);
541 tcg_gen_and_i32(ret
, arg1
, t0
);
542 tcg_temp_free_i32(t0
);
545 static inline void tcg_gen_or_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
547 if (TCGV_EQUAL_I32(arg1
, arg2
)) {
548 tcg_gen_mov_i32(ret
, arg1
);
550 tcg_gen_op3_i32(INDEX_op_or_i32
, ret
, arg1
, arg2
);
554 static inline void tcg_gen_ori_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
556 /* Some cases can be optimized here. */
558 tcg_gen_movi_i32(ret
, -1);
559 } else if (arg2
== 0) {
560 tcg_gen_mov_i32(ret
, arg1
);
562 TCGv_i32 t0
= tcg_const_i32(arg2
);
563 tcg_gen_or_i32(ret
, arg1
, t0
);
564 tcg_temp_free_i32(t0
);
568 static inline void tcg_gen_xor_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
570 if (TCGV_EQUAL_I32(arg1
, arg2
)) {
571 tcg_gen_movi_i32(ret
, 0);
573 tcg_gen_op3_i32(INDEX_op_xor_i32
, ret
, arg1
, arg2
);
577 static inline void tcg_gen_xori_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
579 /* Some cases can be optimized here. */
581 tcg_gen_mov_i32(ret
, arg1
);
582 } else if (arg2
== -1 && TCG_TARGET_HAS_not_i32
) {
583 /* Don't recurse with tcg_gen_not_i32. */
584 tcg_gen_op2_i32(INDEX_op_not_i32
, ret
, arg1
);
586 TCGv_i32 t0
= tcg_const_i32(arg2
);
587 tcg_gen_xor_i32(ret
, arg1
, t0
);
588 tcg_temp_free_i32(t0
);
592 static inline void tcg_gen_shl_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
594 tcg_gen_op3_i32(INDEX_op_shl_i32
, ret
, arg1
, arg2
);
597 static inline void tcg_gen_shli_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
600 tcg_gen_mov_i32(ret
, arg1
);
602 TCGv_i32 t0
= tcg_const_i32(arg2
);
603 tcg_gen_shl_i32(ret
, arg1
, t0
);
604 tcg_temp_free_i32(t0
);
608 static inline void tcg_gen_shr_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
610 tcg_gen_op3_i32(INDEX_op_shr_i32
, ret
, arg1
, arg2
);
613 static inline void tcg_gen_shri_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
616 tcg_gen_mov_i32(ret
, arg1
);
618 TCGv_i32 t0
= tcg_const_i32(arg2
);
619 tcg_gen_shr_i32(ret
, arg1
, t0
);
620 tcg_temp_free_i32(t0
);
624 static inline void tcg_gen_sar_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
626 tcg_gen_op3_i32(INDEX_op_sar_i32
, ret
, arg1
, arg2
);
629 static inline void tcg_gen_sari_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
632 tcg_gen_mov_i32(ret
, arg1
);
634 TCGv_i32 t0
= tcg_const_i32(arg2
);
635 tcg_gen_sar_i32(ret
, arg1
, t0
);
636 tcg_temp_free_i32(t0
);
640 static inline void tcg_gen_brcond_i32(TCGCond cond
, TCGv_i32 arg1
,
641 TCGv_i32 arg2
, int label_index
)
643 if (cond
== TCG_COND_ALWAYS
) {
644 tcg_gen_br(label_index
);
645 } else if (cond
!= TCG_COND_NEVER
) {
646 tcg_gen_op4ii_i32(INDEX_op_brcond_i32
, arg1
, arg2
, cond
, label_index
);
650 static inline void tcg_gen_brcondi_i32(TCGCond cond
, TCGv_i32 arg1
,
651 int32_t arg2
, int label_index
)
653 if (cond
== TCG_COND_ALWAYS
) {
654 tcg_gen_br(label_index
);
655 } else if (cond
!= TCG_COND_NEVER
) {
656 TCGv_i32 t0
= tcg_const_i32(arg2
);
657 tcg_gen_brcond_i32(cond
, arg1
, t0
, label_index
);
658 tcg_temp_free_i32(t0
);
662 static inline void tcg_gen_setcond_i32(TCGCond cond
, TCGv_i32 ret
,
663 TCGv_i32 arg1
, TCGv_i32 arg2
)
665 if (cond
== TCG_COND_ALWAYS
) {
666 tcg_gen_movi_i32(ret
, 1);
667 } else if (cond
== TCG_COND_NEVER
) {
668 tcg_gen_movi_i32(ret
, 0);
670 tcg_gen_op4i_i32(INDEX_op_setcond_i32
, ret
, arg1
, arg2
, cond
);
674 static inline void tcg_gen_setcondi_i32(TCGCond cond
, TCGv_i32 ret
,
675 TCGv_i32 arg1
, int32_t arg2
)
677 if (cond
== TCG_COND_ALWAYS
) {
678 tcg_gen_movi_i32(ret
, 1);
679 } else if (cond
== TCG_COND_NEVER
) {
680 tcg_gen_movi_i32(ret
, 0);
682 TCGv_i32 t0
= tcg_const_i32(arg2
);
683 tcg_gen_setcond_i32(cond
, ret
, arg1
, t0
);
684 tcg_temp_free_i32(t0
);
688 static inline void tcg_gen_mul_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
690 tcg_gen_op3_i32(INDEX_op_mul_i32
, ret
, arg1
, arg2
);
693 static inline void tcg_gen_muli_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
695 TCGv_i32 t0
= tcg_const_i32(arg2
);
696 tcg_gen_mul_i32(ret
, arg1
, t0
);
697 tcg_temp_free_i32(t0
);
700 static inline void tcg_gen_div_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
702 if (TCG_TARGET_HAS_div_i32
) {
703 tcg_gen_op3_i32(INDEX_op_div_i32
, ret
, arg1
, arg2
);
704 } else if (TCG_TARGET_HAS_div2_i32
) {
705 TCGv_i32 t0
= tcg_temp_new_i32();
706 tcg_gen_sari_i32(t0
, arg1
, 31);
707 tcg_gen_op5_i32(INDEX_op_div2_i32
, ret
, t0
, arg1
, t0
, arg2
);
708 tcg_temp_free_i32(t0
);
711 /* Return value and both arguments are 32-bit and signed. */
712 sizemask
|= tcg_gen_sizemask(0, 0, 1);
713 sizemask
|= tcg_gen_sizemask(1, 0, 1);
714 sizemask
|= tcg_gen_sizemask(2, 0, 1);
715 tcg_gen_helper32(tcg_helper_div_i32
, sizemask
, ret
, arg1
, arg2
);
719 static inline void tcg_gen_rem_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
721 if (TCG_TARGET_HAS_rem_i32
) {
722 tcg_gen_op3_i32(INDEX_op_rem_i32
, ret
, arg1
, arg2
);
723 } else if (TCG_TARGET_HAS_div_i32
) {
724 TCGv_i32 t0
= tcg_temp_new_i32();
725 tcg_gen_op3_i32(INDEX_op_div_i32
, t0
, arg1
, arg2
);
726 tcg_gen_mul_i32(t0
, t0
, arg2
);
727 tcg_gen_sub_i32(ret
, arg1
, t0
);
728 tcg_temp_free_i32(t0
);
729 } else if (TCG_TARGET_HAS_div2_i32
) {
730 TCGv_i32 t0
= tcg_temp_new_i32();
731 tcg_gen_sari_i32(t0
, arg1
, 31);
732 tcg_gen_op5_i32(INDEX_op_div2_i32
, t0
, ret
, arg1
, t0
, arg2
);
733 tcg_temp_free_i32(t0
);
736 /* Return value and both arguments are 32-bit and signed. */
737 sizemask
|= tcg_gen_sizemask(0, 0, 1);
738 sizemask
|= tcg_gen_sizemask(1, 0, 1);
739 sizemask
|= tcg_gen_sizemask(2, 0, 1);
740 tcg_gen_helper32(tcg_helper_rem_i32
, sizemask
, ret
, arg1
, arg2
);
744 static inline void tcg_gen_divu_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
746 if (TCG_TARGET_HAS_div_i32
) {
747 tcg_gen_op3_i32(INDEX_op_divu_i32
, ret
, arg1
, arg2
);
748 } else if (TCG_TARGET_HAS_div2_i32
) {
749 TCGv_i32 t0
= tcg_temp_new_i32();
750 tcg_gen_movi_i32(t0
, 0);
751 tcg_gen_op5_i32(INDEX_op_divu2_i32
, ret
, t0
, arg1
, t0
, arg2
);
752 tcg_temp_free_i32(t0
);
755 /* Return value and both arguments are 32-bit and unsigned. */
756 sizemask
|= tcg_gen_sizemask(0, 0, 0);
757 sizemask
|= tcg_gen_sizemask(1, 0, 0);
758 sizemask
|= tcg_gen_sizemask(2, 0, 0);
759 tcg_gen_helper32(tcg_helper_divu_i32
, sizemask
, ret
, arg1
, arg2
);
763 static inline void tcg_gen_remu_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
765 if (TCG_TARGET_HAS_rem_i32
) {
766 tcg_gen_op3_i32(INDEX_op_remu_i32
, ret
, arg1
, arg2
);
767 } else if (TCG_TARGET_HAS_div_i32
) {
768 TCGv_i32 t0
= tcg_temp_new_i32();
769 tcg_gen_op3_i32(INDEX_op_divu_i32
, t0
, arg1
, arg2
);
770 tcg_gen_mul_i32(t0
, t0
, arg2
);
771 tcg_gen_sub_i32(ret
, arg1
, t0
);
772 tcg_temp_free_i32(t0
);
773 } else if (TCG_TARGET_HAS_div2_i32
) {
774 TCGv_i32 t0
= tcg_temp_new_i32();
775 tcg_gen_movi_i32(t0
, 0);
776 tcg_gen_op5_i32(INDEX_op_divu2_i32
, t0
, ret
, arg1
, t0
, arg2
);
777 tcg_temp_free_i32(t0
);
780 /* Return value and both arguments are 32-bit and unsigned. */
781 sizemask
|= tcg_gen_sizemask(0, 0, 0);
782 sizemask
|= tcg_gen_sizemask(1, 0, 0);
783 sizemask
|= tcg_gen_sizemask(2, 0, 0);
784 tcg_gen_helper32(tcg_helper_remu_i32
, sizemask
, ret
, arg1
, arg2
);
788 #if TCG_TARGET_REG_BITS == 32
790 static inline void tcg_gen_mov_i64(TCGv_i64 ret
, TCGv_i64 arg
)
792 if (!TCGV_EQUAL_I64(ret
, arg
)) {
793 tcg_gen_mov_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
794 tcg_gen_mov_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg
));
798 static inline void tcg_gen_movi_i64(TCGv_i64 ret
, int64_t arg
)
800 tcg_gen_movi_i32(TCGV_LOW(ret
), arg
);
801 tcg_gen_movi_i32(TCGV_HIGH(ret
), arg
>> 32);
804 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
805 tcg_target_long offset
)
807 tcg_gen_ld8u_i32(TCGV_LOW(ret
), arg2
, offset
);
808 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
811 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
812 tcg_target_long offset
)
814 tcg_gen_ld8s_i32(TCGV_LOW(ret
), arg2
, offset
);
815 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_HIGH(ret
), 31);
818 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
819 tcg_target_long offset
)
821 tcg_gen_ld16u_i32(TCGV_LOW(ret
), arg2
, offset
);
822 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
825 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
826 tcg_target_long offset
)
828 tcg_gen_ld16s_i32(TCGV_LOW(ret
), arg2
, offset
);
829 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
832 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
833 tcg_target_long offset
)
835 tcg_gen_ld_i32(TCGV_LOW(ret
), arg2
, offset
);
836 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
839 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
840 tcg_target_long offset
)
842 tcg_gen_ld_i32(TCGV_LOW(ret
), arg2
, offset
);
843 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
846 static inline void tcg_gen_ld_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
847 tcg_target_long offset
)
849 /* since arg2 and ret have different types, they cannot be the
851 #ifdef HOST_WORDS_BIGENDIAN
852 tcg_gen_ld_i32(TCGV_HIGH(ret
), arg2
, offset
);
853 tcg_gen_ld_i32(TCGV_LOW(ret
), arg2
, offset
+ 4);
855 tcg_gen_ld_i32(TCGV_LOW(ret
), arg2
, offset
);
856 tcg_gen_ld_i32(TCGV_HIGH(ret
), arg2
, offset
+ 4);
860 static inline void tcg_gen_st8_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
861 tcg_target_long offset
)
863 tcg_gen_st8_i32(TCGV_LOW(arg1
), arg2
, offset
);
866 static inline void tcg_gen_st16_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
867 tcg_target_long offset
)
869 tcg_gen_st16_i32(TCGV_LOW(arg1
), arg2
, offset
);
872 static inline void tcg_gen_st32_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
873 tcg_target_long offset
)
875 tcg_gen_st_i32(TCGV_LOW(arg1
), arg2
, offset
);
878 static inline void tcg_gen_st_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
879 tcg_target_long offset
)
881 #ifdef HOST_WORDS_BIGENDIAN
882 tcg_gen_st_i32(TCGV_HIGH(arg1
), arg2
, offset
);
883 tcg_gen_st_i32(TCGV_LOW(arg1
), arg2
, offset
+ 4);
885 tcg_gen_st_i32(TCGV_LOW(arg1
), arg2
, offset
);
886 tcg_gen_st_i32(TCGV_HIGH(arg1
), arg2
, offset
+ 4);
890 static inline void tcg_gen_add_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
892 tcg_gen_op6_i32(INDEX_op_add2_i32
, TCGV_LOW(ret
), TCGV_HIGH(ret
),
893 TCGV_LOW(arg1
), TCGV_HIGH(arg1
), TCGV_LOW(arg2
),
895 /* Allow the optimizer room to replace add2 with two moves. */
896 tcg_gen_op0(INDEX_op_nop
);
899 static inline void tcg_gen_sub_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
901 tcg_gen_op6_i32(INDEX_op_sub2_i32
, TCGV_LOW(ret
), TCGV_HIGH(ret
),
902 TCGV_LOW(arg1
), TCGV_HIGH(arg1
), TCGV_LOW(arg2
),
904 /* Allow the optimizer room to replace sub2 with two moves. */
905 tcg_gen_op0(INDEX_op_nop
);
908 static inline void tcg_gen_and_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
910 tcg_gen_and_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
911 tcg_gen_and_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
914 static inline void tcg_gen_andi_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
916 tcg_gen_andi_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), arg2
);
917 tcg_gen_andi_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), arg2
>> 32);
920 static inline void tcg_gen_or_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
922 tcg_gen_or_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
923 tcg_gen_or_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
926 static inline void tcg_gen_ori_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
928 tcg_gen_ori_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), arg2
);
929 tcg_gen_ori_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), arg2
>> 32);
932 static inline void tcg_gen_xor_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
934 tcg_gen_xor_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
935 tcg_gen_xor_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
938 static inline void tcg_gen_xori_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
940 tcg_gen_xori_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), arg2
);
941 tcg_gen_xori_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), arg2
>> 32);
944 /* XXX: use generic code when basic block handling is OK or CPU
945 specific code (x86) */
946 static inline void tcg_gen_shl_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
949 /* Return value and both arguments are 64-bit and signed. */
950 sizemask
|= tcg_gen_sizemask(0, 1, 1);
951 sizemask
|= tcg_gen_sizemask(1, 1, 1);
952 sizemask
|= tcg_gen_sizemask(2, 1, 1);
954 tcg_gen_helper64(tcg_helper_shl_i64
, sizemask
, ret
, arg1
, arg2
);
957 static inline void tcg_gen_shli_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
959 tcg_gen_shifti_i64(ret
, arg1
, arg2
, 0, 0);
962 static inline void tcg_gen_shr_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
965 /* Return value and both arguments are 64-bit and signed. */
966 sizemask
|= tcg_gen_sizemask(0, 1, 1);
967 sizemask
|= tcg_gen_sizemask(1, 1, 1);
968 sizemask
|= tcg_gen_sizemask(2, 1, 1);
970 tcg_gen_helper64(tcg_helper_shr_i64
, sizemask
, ret
, arg1
, arg2
);
973 static inline void tcg_gen_shri_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
975 tcg_gen_shifti_i64(ret
, arg1
, arg2
, 1, 0);
978 static inline void tcg_gen_sar_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
981 /* Return value and both arguments are 64-bit and signed. */
982 sizemask
|= tcg_gen_sizemask(0, 1, 1);
983 sizemask
|= tcg_gen_sizemask(1, 1, 1);
984 sizemask
|= tcg_gen_sizemask(2, 1, 1);
986 tcg_gen_helper64(tcg_helper_sar_i64
, sizemask
, ret
, arg1
, arg2
);
989 static inline void tcg_gen_sari_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
991 tcg_gen_shifti_i64(ret
, arg1
, arg2
, 1, 1);
994 static inline void tcg_gen_brcond_i64(TCGCond cond
, TCGv_i64 arg1
,
995 TCGv_i64 arg2
, int label_index
)
997 if (cond
== TCG_COND_ALWAYS
) {
998 tcg_gen_br(label_index
);
999 } else if (cond
!= TCG_COND_NEVER
) {
1000 tcg_gen_op6ii_i32(INDEX_op_brcond2_i32
,
1001 TCGV_LOW(arg1
), TCGV_HIGH(arg1
), TCGV_LOW(arg2
),
1002 TCGV_HIGH(arg2
), cond
, label_index
);
1006 static inline void tcg_gen_setcond_i64(TCGCond cond
, TCGv_i64 ret
,
1007 TCGv_i64 arg1
, TCGv_i64 arg2
)
1009 if (cond
== TCG_COND_ALWAYS
) {
1010 tcg_gen_movi_i32(TCGV_LOW(ret
), 1);
1011 } else if (cond
== TCG_COND_NEVER
) {
1012 tcg_gen_movi_i32(TCGV_LOW(ret
), 0);
1014 tcg_gen_op6i_i32(INDEX_op_setcond2_i32
, TCGV_LOW(ret
),
1015 TCGV_LOW(arg1
), TCGV_HIGH(arg1
),
1016 TCGV_LOW(arg2
), TCGV_HIGH(arg2
), cond
);
1018 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
1021 static inline void tcg_gen_mul_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1026 t0
= tcg_temp_new_i64();
1027 t1
= tcg_temp_new_i32();
1029 if (TCG_TARGET_HAS_mulu2_i32
) {
1030 tcg_gen_op4_i32(INDEX_op_mulu2_i32
, TCGV_LOW(t0
), TCGV_HIGH(t0
),
1031 TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1032 /* Allow the optimizer room to replace mulu2 with two moves. */
1033 tcg_gen_op0(INDEX_op_nop
);
1035 tcg_debug_assert(TCG_TARGET_HAS_muluh_i32
);
1036 tcg_gen_op3_i32(INDEX_op_mul_i32
, TCGV_LOW(t0
),
1037 TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1038 tcg_gen_op3_i32(INDEX_op_muluh_i32
, TCGV_HIGH(t0
),
1039 TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1042 tcg_gen_mul_i32(t1
, TCGV_LOW(arg1
), TCGV_HIGH(arg2
));
1043 tcg_gen_add_i32(TCGV_HIGH(t0
), TCGV_HIGH(t0
), t1
);
1044 tcg_gen_mul_i32(t1
, TCGV_HIGH(arg1
), TCGV_LOW(arg2
));
1045 tcg_gen_add_i32(TCGV_HIGH(t0
), TCGV_HIGH(t0
), t1
);
1047 tcg_gen_mov_i64(ret
, t0
);
1048 tcg_temp_free_i64(t0
);
1049 tcg_temp_free_i32(t1
);
1052 static inline void tcg_gen_div_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1055 /* Return value and both arguments are 64-bit and signed. */
1056 sizemask
|= tcg_gen_sizemask(0, 1, 1);
1057 sizemask
|= tcg_gen_sizemask(1, 1, 1);
1058 sizemask
|= tcg_gen_sizemask(2, 1, 1);
1060 tcg_gen_helper64(tcg_helper_div_i64
, sizemask
, ret
, arg1
, arg2
);
1063 static inline void tcg_gen_rem_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1066 /* Return value and both arguments are 64-bit and signed. */
1067 sizemask
|= tcg_gen_sizemask(0, 1, 1);
1068 sizemask
|= tcg_gen_sizemask(1, 1, 1);
1069 sizemask
|= tcg_gen_sizemask(2, 1, 1);
1071 tcg_gen_helper64(tcg_helper_rem_i64
, sizemask
, ret
, arg1
, arg2
);
1074 static inline void tcg_gen_divu_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1077 /* Return value and both arguments are 64-bit and unsigned. */
1078 sizemask
|= tcg_gen_sizemask(0, 1, 0);
1079 sizemask
|= tcg_gen_sizemask(1, 1, 0);
1080 sizemask
|= tcg_gen_sizemask(2, 1, 0);
1082 tcg_gen_helper64(tcg_helper_divu_i64
, sizemask
, ret
, arg1
, arg2
);
1085 static inline void tcg_gen_remu_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1088 /* Return value and both arguments are 64-bit and unsigned. */
1089 sizemask
|= tcg_gen_sizemask(0, 1, 0);
1090 sizemask
|= tcg_gen_sizemask(1, 1, 0);
1091 sizemask
|= tcg_gen_sizemask(2, 1, 0);
1093 tcg_gen_helper64(tcg_helper_remu_i64
, sizemask
, ret
, arg1
, arg2
);
1098 static inline void tcg_gen_mov_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1100 if (!TCGV_EQUAL_I64(ret
, arg
))
1101 tcg_gen_op2_i64(INDEX_op_mov_i64
, ret
, arg
);
1104 static inline void tcg_gen_movi_i64(TCGv_i64 ret
, int64_t arg
)
1106 tcg_gen_op2i_i64(INDEX_op_movi_i64
, ret
, arg
);
1109 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1110 tcg_target_long offset
)
1112 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64
, ret
, arg2
, offset
);
1115 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1116 tcg_target_long offset
)
1118 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64
, ret
, arg2
, offset
);
1121 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1122 tcg_target_long offset
)
1124 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64
, ret
, arg2
, offset
);
1127 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1128 tcg_target_long offset
)
1130 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64
, ret
, arg2
, offset
);
1133 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1134 tcg_target_long offset
)
1136 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64
, ret
, arg2
, offset
);
1139 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1140 tcg_target_long offset
)
1142 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64
, ret
, arg2
, offset
);
1145 static inline void tcg_gen_ld_i64(TCGv_i64 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
1147 tcg_gen_ldst_op_i64(INDEX_op_ld_i64
, ret
, arg2
, offset
);
1150 static inline void tcg_gen_st8_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
1151 tcg_target_long offset
)
1153 tcg_gen_ldst_op_i64(INDEX_op_st8_i64
, arg1
, arg2
, offset
);
1156 static inline void tcg_gen_st16_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
1157 tcg_target_long offset
)
1159 tcg_gen_ldst_op_i64(INDEX_op_st16_i64
, arg1
, arg2
, offset
);
1162 static inline void tcg_gen_st32_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
1163 tcg_target_long offset
)
1165 tcg_gen_ldst_op_i64(INDEX_op_st32_i64
, arg1
, arg2
, offset
);
1168 static inline void tcg_gen_st_i64(TCGv_i64 arg1
, TCGv_ptr arg2
, tcg_target_long offset
)
1170 tcg_gen_ldst_op_i64(INDEX_op_st_i64
, arg1
, arg2
, offset
);
1173 static inline void tcg_gen_add_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1175 tcg_gen_op3_i64(INDEX_op_add_i64
, ret
, arg1
, arg2
);
1178 static inline void tcg_gen_sub_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1180 tcg_gen_op3_i64(INDEX_op_sub_i64
, ret
, arg1
, arg2
);
1183 static inline void tcg_gen_and_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1185 if (TCGV_EQUAL_I64(arg1
, arg2
)) {
1186 tcg_gen_mov_i64(ret
, arg1
);
1188 tcg_gen_op3_i64(INDEX_op_and_i64
, ret
, arg1
, arg2
);
1192 static inline void tcg_gen_andi_i64(TCGv_i64 ret
, TCGv_i64 arg1
, uint64_t arg2
)
1195 /* Some cases can be optimized here. */
1198 tcg_gen_movi_i64(ret
, 0);
1200 case 0xffffffffffffffffull
:
1201 tcg_gen_mov_i64(ret
, arg1
);
1204 /* Don't recurse with tcg_gen_ext8u_i32. */
1205 if (TCG_TARGET_HAS_ext8u_i64
) {
1206 tcg_gen_op2_i64(INDEX_op_ext8u_i64
, ret
, arg1
);
1211 if (TCG_TARGET_HAS_ext16u_i64
) {
1212 tcg_gen_op2_i64(INDEX_op_ext16u_i64
, ret
, arg1
);
1217 if (TCG_TARGET_HAS_ext32u_i64
) {
1218 tcg_gen_op2_i64(INDEX_op_ext32u_i64
, ret
, arg1
);
1223 t0
= tcg_const_i64(arg2
);
1224 tcg_gen_and_i64(ret
, arg1
, t0
);
1225 tcg_temp_free_i64(t0
);
1228 static inline void tcg_gen_or_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1230 if (TCGV_EQUAL_I64(arg1
, arg2
)) {
1231 tcg_gen_mov_i64(ret
, arg1
);
1233 tcg_gen_op3_i64(INDEX_op_or_i64
, ret
, arg1
, arg2
);
1237 static inline void tcg_gen_ori_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1239 /* Some cases can be optimized here. */
1241 tcg_gen_movi_i64(ret
, -1);
1242 } else if (arg2
== 0) {
1243 tcg_gen_mov_i64(ret
, arg1
);
1245 TCGv_i64 t0
= tcg_const_i64(arg2
);
1246 tcg_gen_or_i64(ret
, arg1
, t0
);
1247 tcg_temp_free_i64(t0
);
1251 static inline void tcg_gen_xor_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1253 if (TCGV_EQUAL_I64(arg1
, arg2
)) {
1254 tcg_gen_movi_i64(ret
, 0);
1256 tcg_gen_op3_i64(INDEX_op_xor_i64
, ret
, arg1
, arg2
);
1260 static inline void tcg_gen_xori_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1262 /* Some cases can be optimized here. */
1264 tcg_gen_mov_i64(ret
, arg1
);
1265 } else if (arg2
== -1 && TCG_TARGET_HAS_not_i64
) {
1266 /* Don't recurse with tcg_gen_not_i64. */
1267 tcg_gen_op2_i64(INDEX_op_not_i64
, ret
, arg1
);
1269 TCGv_i64 t0
= tcg_const_i64(arg2
);
1270 tcg_gen_xor_i64(ret
, arg1
, t0
);
1271 tcg_temp_free_i64(t0
);
1275 static inline void tcg_gen_shl_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1277 tcg_gen_op3_i64(INDEX_op_shl_i64
, ret
, arg1
, arg2
);
1280 static inline void tcg_gen_shli_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1283 tcg_gen_mov_i64(ret
, arg1
);
1285 TCGv_i64 t0
= tcg_const_i64(arg2
);
1286 tcg_gen_shl_i64(ret
, arg1
, t0
);
1287 tcg_temp_free_i64(t0
);
1291 static inline void tcg_gen_shr_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1293 tcg_gen_op3_i64(INDEX_op_shr_i64
, ret
, arg1
, arg2
);
1296 static inline void tcg_gen_shri_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1299 tcg_gen_mov_i64(ret
, arg1
);
1301 TCGv_i64 t0
= tcg_const_i64(arg2
);
1302 tcg_gen_shr_i64(ret
, arg1
, t0
);
1303 tcg_temp_free_i64(t0
);
1307 static inline void tcg_gen_sar_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1309 tcg_gen_op3_i64(INDEX_op_sar_i64
, ret
, arg1
, arg2
);
1312 static inline void tcg_gen_sari_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1315 tcg_gen_mov_i64(ret
, arg1
);
1317 TCGv_i64 t0
= tcg_const_i64(arg2
);
1318 tcg_gen_sar_i64(ret
, arg1
, t0
);
1319 tcg_temp_free_i64(t0
);
1323 static inline void tcg_gen_brcond_i64(TCGCond cond
, TCGv_i64 arg1
,
1324 TCGv_i64 arg2
, int label_index
)
1326 if (cond
== TCG_COND_ALWAYS
) {
1327 tcg_gen_br(label_index
);
1328 } else if (cond
!= TCG_COND_NEVER
) {
1329 tcg_gen_op4ii_i64(INDEX_op_brcond_i64
, arg1
, arg2
, cond
, label_index
);
1333 static inline void tcg_gen_setcond_i64(TCGCond cond
, TCGv_i64 ret
,
1334 TCGv_i64 arg1
, TCGv_i64 arg2
)
1336 if (cond
== TCG_COND_ALWAYS
) {
1337 tcg_gen_movi_i64(ret
, 1);
1338 } else if (cond
== TCG_COND_NEVER
) {
1339 tcg_gen_movi_i64(ret
, 0);
1341 tcg_gen_op4i_i64(INDEX_op_setcond_i64
, ret
, arg1
, arg2
, cond
);
1345 static inline void tcg_gen_mul_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1347 tcg_gen_op3_i64(INDEX_op_mul_i64
, ret
, arg1
, arg2
);
1350 static inline void tcg_gen_div_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1352 if (TCG_TARGET_HAS_div_i64
) {
1353 tcg_gen_op3_i64(INDEX_op_div_i64
, ret
, arg1
, arg2
);
1354 } else if (TCG_TARGET_HAS_div2_i64
) {
1355 TCGv_i64 t0
= tcg_temp_new_i64();
1356 tcg_gen_sari_i64(t0
, arg1
, 63);
1357 tcg_gen_op5_i64(INDEX_op_div2_i64
, ret
, t0
, arg1
, t0
, arg2
);
1358 tcg_temp_free_i64(t0
);
1361 /* Return value and both arguments are 64-bit and signed. */
1362 sizemask
|= tcg_gen_sizemask(0, 1, 1);
1363 sizemask
|= tcg_gen_sizemask(1, 1, 1);
1364 sizemask
|= tcg_gen_sizemask(2, 1, 1);
1365 tcg_gen_helper64(tcg_helper_div_i64
, sizemask
, ret
, arg1
, arg2
);
1369 static inline void tcg_gen_rem_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1371 if (TCG_TARGET_HAS_rem_i64
) {
1372 tcg_gen_op3_i64(INDEX_op_rem_i64
, ret
, arg1
, arg2
);
1373 } else if (TCG_TARGET_HAS_div_i64
) {
1374 TCGv_i64 t0
= tcg_temp_new_i64();
1375 tcg_gen_op3_i64(INDEX_op_div_i64
, t0
, arg1
, arg2
);
1376 tcg_gen_mul_i64(t0
, t0
, arg2
);
1377 tcg_gen_sub_i64(ret
, arg1
, t0
);
1378 tcg_temp_free_i64(t0
);
1379 } else if (TCG_TARGET_HAS_div2_i64
) {
1380 TCGv_i64 t0
= tcg_temp_new_i64();
1381 tcg_gen_sari_i64(t0
, arg1
, 63);
1382 tcg_gen_op5_i64(INDEX_op_div2_i64
, t0
, ret
, arg1
, t0
, arg2
);
1383 tcg_temp_free_i64(t0
);
1386 /* Return value and both arguments are 64-bit and signed. */
1387 sizemask
|= tcg_gen_sizemask(0, 1, 1);
1388 sizemask
|= tcg_gen_sizemask(1, 1, 1);
1389 sizemask
|= tcg_gen_sizemask(2, 1, 1);
1390 tcg_gen_helper64(tcg_helper_rem_i64
, sizemask
, ret
, arg1
, arg2
);
1394 static inline void tcg_gen_divu_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1396 if (TCG_TARGET_HAS_div_i64
) {
1397 tcg_gen_op3_i64(INDEX_op_divu_i64
, ret
, arg1
, arg2
);
1398 } else if (TCG_TARGET_HAS_div2_i64
) {
1399 TCGv_i64 t0
= tcg_temp_new_i64();
1400 tcg_gen_movi_i64(t0
, 0);
1401 tcg_gen_op5_i64(INDEX_op_divu2_i64
, ret
, t0
, arg1
, t0
, arg2
);
1402 tcg_temp_free_i64(t0
);
1405 /* Return value and both arguments are 64-bit and unsigned. */
1406 sizemask
|= tcg_gen_sizemask(0, 1, 0);
1407 sizemask
|= tcg_gen_sizemask(1, 1, 0);
1408 sizemask
|= tcg_gen_sizemask(2, 1, 0);
1409 tcg_gen_helper64(tcg_helper_divu_i64
, sizemask
, ret
, arg1
, arg2
);
1413 static inline void tcg_gen_remu_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1415 if (TCG_TARGET_HAS_rem_i64
) {
1416 tcg_gen_op3_i64(INDEX_op_remu_i64
, ret
, arg1
, arg2
);
1417 } else if (TCG_TARGET_HAS_div_i64
) {
1418 TCGv_i64 t0
= tcg_temp_new_i64();
1419 tcg_gen_op3_i64(INDEX_op_divu_i64
, t0
, arg1
, arg2
);
1420 tcg_gen_mul_i64(t0
, t0
, arg2
);
1421 tcg_gen_sub_i64(ret
, arg1
, t0
);
1422 tcg_temp_free_i64(t0
);
1423 } else if (TCG_TARGET_HAS_div2_i64
) {
1424 TCGv_i64 t0
= tcg_temp_new_i64();
1425 tcg_gen_movi_i64(t0
, 0);
1426 tcg_gen_op5_i64(INDEX_op_divu2_i64
, t0
, ret
, arg1
, t0
, arg2
);
1427 tcg_temp_free_i64(t0
);
1430 /* Return value and both arguments are 64-bit and unsigned. */
1431 sizemask
|= tcg_gen_sizemask(0, 1, 0);
1432 sizemask
|= tcg_gen_sizemask(1, 1, 0);
1433 sizemask
|= tcg_gen_sizemask(2, 1, 0);
1434 tcg_gen_helper64(tcg_helper_remu_i64
, sizemask
, ret
, arg1
, arg2
);
1437 #endif /* TCG_TARGET_REG_BITS == 32 */
1439 static inline void tcg_gen_addi_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1441 /* some cases can be optimized here */
1443 tcg_gen_mov_i64(ret
, arg1
);
1445 TCGv_i64 t0
= tcg_const_i64(arg2
);
1446 tcg_gen_add_i64(ret
, arg1
, t0
);
1447 tcg_temp_free_i64(t0
);
1451 static inline void tcg_gen_subfi_i64(TCGv_i64 ret
, int64_t arg1
, TCGv_i64 arg2
)
1453 TCGv_i64 t0
= tcg_const_i64(arg1
);
1454 tcg_gen_sub_i64(ret
, t0
, arg2
);
1455 tcg_temp_free_i64(t0
);
1458 static inline void tcg_gen_subi_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1460 /* some cases can be optimized here */
1462 tcg_gen_mov_i64(ret
, arg1
);
1464 TCGv_i64 t0
= tcg_const_i64(arg2
);
1465 tcg_gen_sub_i64(ret
, arg1
, t0
);
1466 tcg_temp_free_i64(t0
);
1469 static inline void tcg_gen_brcondi_i64(TCGCond cond
, TCGv_i64 arg1
,
1470 int64_t arg2
, int label_index
)
1472 if (cond
== TCG_COND_ALWAYS
) {
1473 tcg_gen_br(label_index
);
1474 } else if (cond
!= TCG_COND_NEVER
) {
1475 TCGv_i64 t0
= tcg_const_i64(arg2
);
1476 tcg_gen_brcond_i64(cond
, arg1
, t0
, label_index
);
1477 tcg_temp_free_i64(t0
);
1481 static inline void tcg_gen_setcondi_i64(TCGCond cond
, TCGv_i64 ret
,
1482 TCGv_i64 arg1
, int64_t arg2
)
1484 TCGv_i64 t0
= tcg_const_i64(arg2
);
1485 tcg_gen_setcond_i64(cond
, ret
, arg1
, t0
);
1486 tcg_temp_free_i64(t0
);
1489 static inline void tcg_gen_muli_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1491 TCGv_i64 t0
= tcg_const_i64(arg2
);
1492 tcg_gen_mul_i64(ret
, arg1
, t0
);
1493 tcg_temp_free_i64(t0
);
1497 /***************************************/
1498 /* optional operations */
1500 static inline void tcg_gen_ext8s_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1502 if (TCG_TARGET_HAS_ext8s_i32
) {
1503 tcg_gen_op2_i32(INDEX_op_ext8s_i32
, ret
, arg
);
1505 tcg_gen_shli_i32(ret
, arg
, 24);
1506 tcg_gen_sari_i32(ret
, ret
, 24);
1510 static inline void tcg_gen_ext16s_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1512 if (TCG_TARGET_HAS_ext16s_i32
) {
1513 tcg_gen_op2_i32(INDEX_op_ext16s_i32
, ret
, arg
);
1515 tcg_gen_shli_i32(ret
, arg
, 16);
1516 tcg_gen_sari_i32(ret
, ret
, 16);
1520 static inline void tcg_gen_ext8u_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1522 if (TCG_TARGET_HAS_ext8u_i32
) {
1523 tcg_gen_op2_i32(INDEX_op_ext8u_i32
, ret
, arg
);
1525 tcg_gen_andi_i32(ret
, arg
, 0xffu
);
1529 static inline void tcg_gen_ext16u_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1531 if (TCG_TARGET_HAS_ext16u_i32
) {
1532 tcg_gen_op2_i32(INDEX_op_ext16u_i32
, ret
, arg
);
1534 tcg_gen_andi_i32(ret
, arg
, 0xffffu
);
1538 /* Note: we assume the two high bytes are set to zero */
1539 static inline void tcg_gen_bswap16_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1541 if (TCG_TARGET_HAS_bswap16_i32
) {
1542 tcg_gen_op2_i32(INDEX_op_bswap16_i32
, ret
, arg
);
1544 TCGv_i32 t0
= tcg_temp_new_i32();
1546 tcg_gen_ext8u_i32(t0
, arg
);
1547 tcg_gen_shli_i32(t0
, t0
, 8);
1548 tcg_gen_shri_i32(ret
, arg
, 8);
1549 tcg_gen_or_i32(ret
, ret
, t0
);
1550 tcg_temp_free_i32(t0
);
1554 static inline void tcg_gen_bswap32_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1556 if (TCG_TARGET_HAS_bswap32_i32
) {
1557 tcg_gen_op2_i32(INDEX_op_bswap32_i32
, ret
, arg
);
1560 t0
= tcg_temp_new_i32();
1561 t1
= tcg_temp_new_i32();
1563 tcg_gen_shli_i32(t0
, arg
, 24);
1565 tcg_gen_andi_i32(t1
, arg
, 0x0000ff00);
1566 tcg_gen_shli_i32(t1
, t1
, 8);
1567 tcg_gen_or_i32(t0
, t0
, t1
);
1569 tcg_gen_shri_i32(t1
, arg
, 8);
1570 tcg_gen_andi_i32(t1
, t1
, 0x0000ff00);
1571 tcg_gen_or_i32(t0
, t0
, t1
);
1573 tcg_gen_shri_i32(t1
, arg
, 24);
1574 tcg_gen_or_i32(ret
, t0
, t1
);
1575 tcg_temp_free_i32(t0
);
1576 tcg_temp_free_i32(t1
);
1580 #if TCG_TARGET_REG_BITS == 32
1581 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1583 tcg_gen_ext8s_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1584 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
1587 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1589 tcg_gen_ext16s_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1590 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
1593 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1595 tcg_gen_mov_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1596 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
1599 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1601 tcg_gen_ext8u_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1602 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
1605 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1607 tcg_gen_ext16u_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1608 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
1611 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1613 tcg_gen_mov_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1614 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
1617 static inline void tcg_gen_trunc_shr_i64_i32(TCGv_i32 ret
, TCGv_i64 arg
,
1620 tcg_debug_assert(count
< 64);
1622 tcg_gen_shri_i32(ret
, TCGV_HIGH(arg
), count
- 32);
1623 } else if (count
== 0) {
1624 tcg_gen_mov_i32(ret
, TCGV_LOW(arg
));
1626 TCGv_i64 t
= tcg_temp_new_i64();
1627 tcg_gen_shri_i64(t
, arg
, count
);
1628 tcg_gen_mov_i32(ret
, TCGV_LOW(t
));
1629 tcg_temp_free_i64(t
);
1633 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret
, TCGv_i32 arg
)
1635 tcg_gen_mov_i32(TCGV_LOW(ret
), arg
);
1636 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
1639 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret
, TCGv_i32 arg
)
1641 tcg_gen_mov_i32(TCGV_LOW(ret
), arg
);
1642 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
1645 /* Note: we assume the six high bytes are set to zero */
1646 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1648 tcg_gen_mov_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg
));
1649 tcg_gen_bswap16_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1652 /* Note: we assume the four high bytes are set to zero */
1653 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1655 tcg_gen_mov_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg
));
1656 tcg_gen_bswap32_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1659 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1662 t0
= tcg_temp_new_i32();
1663 t1
= tcg_temp_new_i32();
1665 tcg_gen_bswap32_i32(t0
, TCGV_LOW(arg
));
1666 tcg_gen_bswap32_i32(t1
, TCGV_HIGH(arg
));
1667 tcg_gen_mov_i32(TCGV_LOW(ret
), t1
);
1668 tcg_gen_mov_i32(TCGV_HIGH(ret
), t0
);
1669 tcg_temp_free_i32(t0
);
1670 tcg_temp_free_i32(t1
);
1674 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1676 if (TCG_TARGET_HAS_ext8s_i64
) {
1677 tcg_gen_op2_i64(INDEX_op_ext8s_i64
, ret
, arg
);
1679 tcg_gen_shli_i64(ret
, arg
, 56);
1680 tcg_gen_sari_i64(ret
, ret
, 56);
1684 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1686 if (TCG_TARGET_HAS_ext16s_i64
) {
1687 tcg_gen_op2_i64(INDEX_op_ext16s_i64
, ret
, arg
);
1689 tcg_gen_shli_i64(ret
, arg
, 48);
1690 tcg_gen_sari_i64(ret
, ret
, 48);
1694 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1696 if (TCG_TARGET_HAS_ext32s_i64
) {
1697 tcg_gen_op2_i64(INDEX_op_ext32s_i64
, ret
, arg
);
1699 tcg_gen_shli_i64(ret
, arg
, 32);
1700 tcg_gen_sari_i64(ret
, ret
, 32);
1704 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1706 if (TCG_TARGET_HAS_ext8u_i64
) {
1707 tcg_gen_op2_i64(INDEX_op_ext8u_i64
, ret
, arg
);
1709 tcg_gen_andi_i64(ret
, arg
, 0xffu
);
1713 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1715 if (TCG_TARGET_HAS_ext16u_i64
) {
1716 tcg_gen_op2_i64(INDEX_op_ext16u_i64
, ret
, arg
);
1718 tcg_gen_andi_i64(ret
, arg
, 0xffffu
);
1722 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1724 if (TCG_TARGET_HAS_ext32u_i64
) {
1725 tcg_gen_op2_i64(INDEX_op_ext32u_i64
, ret
, arg
);
1727 tcg_gen_andi_i64(ret
, arg
, 0xffffffffu
);
1731 static inline void tcg_gen_trunc_shr_i64_i32(TCGv_i32 ret
, TCGv_i64 arg
,
1734 tcg_debug_assert(count
< 64);
1735 if (TCG_TARGET_HAS_trunc_shr_i32
) {
1736 tcg_gen_op3i_i32(INDEX_op_trunc_shr_i32
, ret
,
1737 MAKE_TCGV_I32(GET_TCGV_I64(arg
)), count
);
1738 } else if (count
== 0) {
1739 tcg_gen_mov_i32(ret
, MAKE_TCGV_I32(GET_TCGV_I64(arg
)));
1741 TCGv_i64 t
= tcg_temp_new_i64();
1742 tcg_gen_shri_i64(t
, arg
, count
);
1743 tcg_gen_mov_i32(ret
, MAKE_TCGV_I32(GET_TCGV_I64(t
)));
1744 tcg_temp_free_i64(t
);
1748 /* Note: we assume the target supports move between 32 and 64 bit
1750 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret
, TCGv_i32 arg
)
1752 tcg_gen_ext32u_i64(ret
, MAKE_TCGV_I64(GET_TCGV_I32(arg
)));
1755 /* Note: we assume the target supports move between 32 and 64 bit
1757 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret
, TCGv_i32 arg
)
1759 tcg_gen_ext32s_i64(ret
, MAKE_TCGV_I64(GET_TCGV_I32(arg
)));
1762 /* Note: we assume the six high bytes are set to zero */
1763 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1765 if (TCG_TARGET_HAS_bswap16_i64
) {
1766 tcg_gen_op2_i64(INDEX_op_bswap16_i64
, ret
, arg
);
1768 TCGv_i64 t0
= tcg_temp_new_i64();
1770 tcg_gen_ext8u_i64(t0
, arg
);
1771 tcg_gen_shli_i64(t0
, t0
, 8);
1772 tcg_gen_shri_i64(ret
, arg
, 8);
1773 tcg_gen_or_i64(ret
, ret
, t0
);
1774 tcg_temp_free_i64(t0
);
1778 /* Note: we assume the four high bytes are set to zero */
1779 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1781 if (TCG_TARGET_HAS_bswap32_i64
) {
1782 tcg_gen_op2_i64(INDEX_op_bswap32_i64
, ret
, arg
);
1785 t0
= tcg_temp_new_i64();
1786 t1
= tcg_temp_new_i64();
1788 tcg_gen_shli_i64(t0
, arg
, 24);
1789 tcg_gen_ext32u_i64(t0
, t0
);
1791 tcg_gen_andi_i64(t1
, arg
, 0x0000ff00);
1792 tcg_gen_shli_i64(t1
, t1
, 8);
1793 tcg_gen_or_i64(t0
, t0
, t1
);
1795 tcg_gen_shri_i64(t1
, arg
, 8);
1796 tcg_gen_andi_i64(t1
, t1
, 0x0000ff00);
1797 tcg_gen_or_i64(t0
, t0
, t1
);
1799 tcg_gen_shri_i64(t1
, arg
, 24);
1800 tcg_gen_or_i64(ret
, t0
, t1
);
1801 tcg_temp_free_i64(t0
);
1802 tcg_temp_free_i64(t1
);
1806 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1808 if (TCG_TARGET_HAS_bswap64_i64
) {
1809 tcg_gen_op2_i64(INDEX_op_bswap64_i64
, ret
, arg
);
1811 TCGv_i64 t0
= tcg_temp_new_i64();
1812 TCGv_i64 t1
= tcg_temp_new_i64();
1814 tcg_gen_shli_i64(t0
, arg
, 56);
1816 tcg_gen_andi_i64(t1
, arg
, 0x0000ff00);
1817 tcg_gen_shli_i64(t1
, t1
, 40);
1818 tcg_gen_or_i64(t0
, t0
, t1
);
1820 tcg_gen_andi_i64(t1
, arg
, 0x00ff0000);
1821 tcg_gen_shli_i64(t1
, t1
, 24);
1822 tcg_gen_or_i64(t0
, t0
, t1
);
1824 tcg_gen_andi_i64(t1
, arg
, 0xff000000);
1825 tcg_gen_shli_i64(t1
, t1
, 8);
1826 tcg_gen_or_i64(t0
, t0
, t1
);
1828 tcg_gen_shri_i64(t1
, arg
, 8);
1829 tcg_gen_andi_i64(t1
, t1
, 0xff000000);
1830 tcg_gen_or_i64(t0
, t0
, t1
);
1832 tcg_gen_shri_i64(t1
, arg
, 24);
1833 tcg_gen_andi_i64(t1
, t1
, 0x00ff0000);
1834 tcg_gen_or_i64(t0
, t0
, t1
);
1836 tcg_gen_shri_i64(t1
, arg
, 40);
1837 tcg_gen_andi_i64(t1
, t1
, 0x0000ff00);
1838 tcg_gen_or_i64(t0
, t0
, t1
);
1840 tcg_gen_shri_i64(t1
, arg
, 56);
1841 tcg_gen_or_i64(ret
, t0
, t1
);
1842 tcg_temp_free_i64(t0
);
1843 tcg_temp_free_i64(t1
);
1849 static inline void tcg_gen_neg_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1851 if (TCG_TARGET_HAS_neg_i32
) {
1852 tcg_gen_op2_i32(INDEX_op_neg_i32
, ret
, arg
);
1854 TCGv_i32 t0
= tcg_const_i32(0);
1855 tcg_gen_sub_i32(ret
, t0
, arg
);
1856 tcg_temp_free_i32(t0
);
1860 static inline void tcg_gen_neg_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1862 if (TCG_TARGET_HAS_neg_i64
) {
1863 tcg_gen_op2_i64(INDEX_op_neg_i64
, ret
, arg
);
1865 TCGv_i64 t0
= tcg_const_i64(0);
1866 tcg_gen_sub_i64(ret
, t0
, arg
);
1867 tcg_temp_free_i64(t0
);
1871 static inline void tcg_gen_not_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1873 if (TCG_TARGET_HAS_not_i32
) {
1874 tcg_gen_op2_i32(INDEX_op_not_i32
, ret
, arg
);
1876 tcg_gen_xori_i32(ret
, arg
, -1);
1880 static inline void tcg_gen_not_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1882 #if TCG_TARGET_REG_BITS == 64
1883 if (TCG_TARGET_HAS_not_i64
) {
1884 tcg_gen_op2_i64(INDEX_op_not_i64
, ret
, arg
);
1886 tcg_gen_xori_i64(ret
, arg
, -1);
1889 tcg_gen_not_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1890 tcg_gen_not_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg
));
1894 static inline void tcg_gen_discard_i32(TCGv_i32 arg
)
1896 tcg_gen_op1_i32(INDEX_op_discard
, arg
);
1899 static inline void tcg_gen_discard_i64(TCGv_i64 arg
)
1901 #if TCG_TARGET_REG_BITS == 32
1902 tcg_gen_discard_i32(TCGV_LOW(arg
));
1903 tcg_gen_discard_i32(TCGV_HIGH(arg
));
1905 tcg_gen_op1_i64(INDEX_op_discard
, arg
);
1909 static inline void tcg_gen_andc_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
1911 if (TCG_TARGET_HAS_andc_i32
) {
1912 tcg_gen_op3_i32(INDEX_op_andc_i32
, ret
, arg1
, arg2
);
1914 TCGv_i32 t0
= tcg_temp_new_i32();
1915 tcg_gen_not_i32(t0
, arg2
);
1916 tcg_gen_and_i32(ret
, arg1
, t0
);
1917 tcg_temp_free_i32(t0
);
1921 static inline void tcg_gen_andc_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1923 #if TCG_TARGET_REG_BITS == 64
1924 if (TCG_TARGET_HAS_andc_i64
) {
1925 tcg_gen_op3_i64(INDEX_op_andc_i64
, ret
, arg1
, arg2
);
1927 TCGv_i64 t0
= tcg_temp_new_i64();
1928 tcg_gen_not_i64(t0
, arg2
);
1929 tcg_gen_and_i64(ret
, arg1
, t0
);
1930 tcg_temp_free_i64(t0
);
1933 tcg_gen_andc_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1934 tcg_gen_andc_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
1938 static inline void tcg_gen_eqv_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
1940 if (TCG_TARGET_HAS_eqv_i32
) {
1941 tcg_gen_op3_i32(INDEX_op_eqv_i32
, ret
, arg1
, arg2
);
1943 tcg_gen_xor_i32(ret
, arg1
, arg2
);
1944 tcg_gen_not_i32(ret
, ret
);
1948 static inline void tcg_gen_eqv_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1950 #if TCG_TARGET_REG_BITS == 64
1951 if (TCG_TARGET_HAS_eqv_i64
) {
1952 tcg_gen_op3_i64(INDEX_op_eqv_i64
, ret
, arg1
, arg2
);
1954 tcg_gen_xor_i64(ret
, arg1
, arg2
);
1955 tcg_gen_not_i64(ret
, ret
);
1958 tcg_gen_eqv_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1959 tcg_gen_eqv_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
1963 static inline void tcg_gen_nand_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
1965 if (TCG_TARGET_HAS_nand_i32
) {
1966 tcg_gen_op3_i32(INDEX_op_nand_i32
, ret
, arg1
, arg2
);
1968 tcg_gen_and_i32(ret
, arg1
, arg2
);
1969 tcg_gen_not_i32(ret
, ret
);
1973 static inline void tcg_gen_nand_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1975 #if TCG_TARGET_REG_BITS == 64
1976 if (TCG_TARGET_HAS_nand_i64
) {
1977 tcg_gen_op3_i64(INDEX_op_nand_i64
, ret
, arg1
, arg2
);
1979 tcg_gen_and_i64(ret
, arg1
, arg2
);
1980 tcg_gen_not_i64(ret
, ret
);
1983 tcg_gen_nand_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1984 tcg_gen_nand_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
1988 static inline void tcg_gen_nor_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
1990 if (TCG_TARGET_HAS_nor_i32
) {
1991 tcg_gen_op3_i32(INDEX_op_nor_i32
, ret
, arg1
, arg2
);
1993 tcg_gen_or_i32(ret
, arg1
, arg2
);
1994 tcg_gen_not_i32(ret
, ret
);
1998 static inline void tcg_gen_nor_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
2000 #if TCG_TARGET_REG_BITS == 64
2001 if (TCG_TARGET_HAS_nor_i64
) {
2002 tcg_gen_op3_i64(INDEX_op_nor_i64
, ret
, arg1
, arg2
);
2004 tcg_gen_or_i64(ret
, arg1
, arg2
);
2005 tcg_gen_not_i64(ret
, ret
);
2008 tcg_gen_nor_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
2009 tcg_gen_nor_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
2013 static inline void tcg_gen_orc_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
2015 if (TCG_TARGET_HAS_orc_i32
) {
2016 tcg_gen_op3_i32(INDEX_op_orc_i32
, ret
, arg1
, arg2
);
2018 TCGv_i32 t0
= tcg_temp_new_i32();
2019 tcg_gen_not_i32(t0
, arg2
);
2020 tcg_gen_or_i32(ret
, arg1
, t0
);
2021 tcg_temp_free_i32(t0
);
2025 static inline void tcg_gen_orc_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
2027 #if TCG_TARGET_REG_BITS == 64
2028 if (TCG_TARGET_HAS_orc_i64
) {
2029 tcg_gen_op3_i64(INDEX_op_orc_i64
, ret
, arg1
, arg2
);
2031 TCGv_i64 t0
= tcg_temp_new_i64();
2032 tcg_gen_not_i64(t0
, arg2
);
2033 tcg_gen_or_i64(ret
, arg1
, t0
);
2034 tcg_temp_free_i64(t0
);
2037 tcg_gen_orc_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
2038 tcg_gen_orc_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
2042 static inline void tcg_gen_rotl_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
2044 if (TCG_TARGET_HAS_rot_i32
) {
2045 tcg_gen_op3_i32(INDEX_op_rotl_i32
, ret
, arg1
, arg2
);
2049 t0
= tcg_temp_new_i32();
2050 t1
= tcg_temp_new_i32();
2051 tcg_gen_shl_i32(t0
, arg1
, arg2
);
2052 tcg_gen_subfi_i32(t1
, 32, arg2
);
2053 tcg_gen_shr_i32(t1
, arg1
, t1
);
2054 tcg_gen_or_i32(ret
, t0
, t1
);
2055 tcg_temp_free_i32(t0
);
2056 tcg_temp_free_i32(t1
);
2060 static inline void tcg_gen_rotl_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
2062 if (TCG_TARGET_HAS_rot_i64
) {
2063 tcg_gen_op3_i64(INDEX_op_rotl_i64
, ret
, arg1
, arg2
);
2066 t0
= tcg_temp_new_i64();
2067 t1
= tcg_temp_new_i64();
2068 tcg_gen_shl_i64(t0
, arg1
, arg2
);
2069 tcg_gen_subfi_i64(t1
, 64, arg2
);
2070 tcg_gen_shr_i64(t1
, arg1
, t1
);
2071 tcg_gen_or_i64(ret
, t0
, t1
);
2072 tcg_temp_free_i64(t0
);
2073 tcg_temp_free_i64(t1
);
2077 static inline void tcg_gen_rotli_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
2079 /* some cases can be optimized here */
2081 tcg_gen_mov_i32(ret
, arg1
);
2082 } else if (TCG_TARGET_HAS_rot_i32
) {
2083 TCGv_i32 t0
= tcg_const_i32(arg2
);
2084 tcg_gen_rotl_i32(ret
, arg1
, t0
);
2085 tcg_temp_free_i32(t0
);
2088 t0
= tcg_temp_new_i32();
2089 t1
= tcg_temp_new_i32();
2090 tcg_gen_shli_i32(t0
, arg1
, arg2
);
2091 tcg_gen_shri_i32(t1
, arg1
, 32 - arg2
);
2092 tcg_gen_or_i32(ret
, t0
, t1
);
2093 tcg_temp_free_i32(t0
);
2094 tcg_temp_free_i32(t1
);
2098 static inline void tcg_gen_rotli_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
2100 /* some cases can be optimized here */
2102 tcg_gen_mov_i64(ret
, arg1
);
2103 } else if (TCG_TARGET_HAS_rot_i64
) {
2104 TCGv_i64 t0
= tcg_const_i64(arg2
);
2105 tcg_gen_rotl_i64(ret
, arg1
, t0
);
2106 tcg_temp_free_i64(t0
);
2109 t0
= tcg_temp_new_i64();
2110 t1
= tcg_temp_new_i64();
2111 tcg_gen_shli_i64(t0
, arg1
, arg2
);
2112 tcg_gen_shri_i64(t1
, arg1
, 64 - arg2
);
2113 tcg_gen_or_i64(ret
, t0
, t1
);
2114 tcg_temp_free_i64(t0
);
2115 tcg_temp_free_i64(t1
);
2119 static inline void tcg_gen_rotr_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
2121 if (TCG_TARGET_HAS_rot_i32
) {
2122 tcg_gen_op3_i32(INDEX_op_rotr_i32
, ret
, arg1
, arg2
);
2126 t0
= tcg_temp_new_i32();
2127 t1
= tcg_temp_new_i32();
2128 tcg_gen_shr_i32(t0
, arg1
, arg2
);
2129 tcg_gen_subfi_i32(t1
, 32, arg2
);
2130 tcg_gen_shl_i32(t1
, arg1
, t1
);
2131 tcg_gen_or_i32(ret
, t0
, t1
);
2132 tcg_temp_free_i32(t0
);
2133 tcg_temp_free_i32(t1
);
2137 static inline void tcg_gen_rotr_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
2139 if (TCG_TARGET_HAS_rot_i64
) {
2140 tcg_gen_op3_i64(INDEX_op_rotr_i64
, ret
, arg1
, arg2
);
2143 t0
= tcg_temp_new_i64();
2144 t1
= tcg_temp_new_i64();
2145 tcg_gen_shr_i64(t0
, arg1
, arg2
);
2146 tcg_gen_subfi_i64(t1
, 64, arg2
);
2147 tcg_gen_shl_i64(t1
, arg1
, t1
);
2148 tcg_gen_or_i64(ret
, t0
, t1
);
2149 tcg_temp_free_i64(t0
);
2150 tcg_temp_free_i64(t1
);
2154 static inline void tcg_gen_rotri_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
2156 /* some cases can be optimized here */
2158 tcg_gen_mov_i32(ret
, arg1
);
2160 tcg_gen_rotli_i32(ret
, arg1
, 32 - arg2
);
2164 static inline void tcg_gen_rotri_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
2166 /* some cases can be optimized here */
2168 tcg_gen_mov_i64(ret
, arg1
);
2170 tcg_gen_rotli_i64(ret
, arg1
, 64 - arg2
);
2174 static inline void tcg_gen_deposit_i32(TCGv_i32 ret
, TCGv_i32 arg1
,
2175 TCGv_i32 arg2
, unsigned int ofs
,
2181 tcg_debug_assert(ofs
< 32);
2182 tcg_debug_assert(len
<= 32);
2183 tcg_debug_assert(ofs
+ len
<= 32);
2185 if (ofs
== 0 && len
== 32) {
2186 tcg_gen_mov_i32(ret
, arg2
);
2189 if (TCG_TARGET_HAS_deposit_i32
&& TCG_TARGET_deposit_i32_valid(ofs
, len
)) {
2190 tcg_gen_op5ii_i32(INDEX_op_deposit_i32
, ret
, arg1
, arg2
, ofs
, len
);
2194 mask
= (1u << len
) - 1;
2195 t1
= tcg_temp_new_i32();
2197 if (ofs
+ len
< 32) {
2198 tcg_gen_andi_i32(t1
, arg2
, mask
);
2199 tcg_gen_shli_i32(t1
, t1
, ofs
);
2201 tcg_gen_shli_i32(t1
, arg2
, ofs
);
2203 tcg_gen_andi_i32(ret
, arg1
, ~(mask
<< ofs
));
2204 tcg_gen_or_i32(ret
, ret
, t1
);
2206 tcg_temp_free_i32(t1
);
2209 static inline void tcg_gen_deposit_i64(TCGv_i64 ret
, TCGv_i64 arg1
,
2210 TCGv_i64 arg2
, unsigned int ofs
,
2216 tcg_debug_assert(ofs
< 64);
2217 tcg_debug_assert(len
<= 64);
2218 tcg_debug_assert(ofs
+ len
<= 64);
2220 if (ofs
== 0 && len
== 64) {
2221 tcg_gen_mov_i64(ret
, arg2
);
2224 if (TCG_TARGET_HAS_deposit_i64
&& TCG_TARGET_deposit_i64_valid(ofs
, len
)) {
2225 tcg_gen_op5ii_i64(INDEX_op_deposit_i64
, ret
, arg1
, arg2
, ofs
, len
);
2229 #if TCG_TARGET_REG_BITS == 32
2231 tcg_gen_deposit_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
),
2232 TCGV_LOW(arg2
), ofs
- 32, len
);
2233 tcg_gen_mov_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
));
2236 if (ofs
+ len
<= 32) {
2237 tcg_gen_deposit_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
),
2238 TCGV_LOW(arg2
), ofs
, len
);
2239 tcg_gen_mov_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
));
2244 mask
= (1ull << len
) - 1;
2245 t1
= tcg_temp_new_i64();
2247 if (ofs
+ len
< 64) {
2248 tcg_gen_andi_i64(t1
, arg2
, mask
);
2249 tcg_gen_shli_i64(t1
, t1
, ofs
);
2251 tcg_gen_shli_i64(t1
, arg2
, ofs
);
2253 tcg_gen_andi_i64(ret
, arg1
, ~(mask
<< ofs
));
2254 tcg_gen_or_i64(ret
, ret
, t1
);
2256 tcg_temp_free_i64(t1
);
2259 static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest
, TCGv_i32 low
,
2262 #if TCG_TARGET_REG_BITS == 32
2263 tcg_gen_mov_i32(TCGV_LOW(dest
), low
);
2264 tcg_gen_mov_i32(TCGV_HIGH(dest
), high
);
2266 TCGv_i64 tmp
= tcg_temp_new_i64();
2267 /* These extensions are only needed for type correctness.
2268 We may be able to do better given target specific information. */
2269 tcg_gen_extu_i32_i64(tmp
, high
);
2270 tcg_gen_extu_i32_i64(dest
, low
);
2271 /* If deposit is available, use it. Otherwise use the extra
2272 knowledge that we have of the zero-extensions above. */
2273 if (TCG_TARGET_HAS_deposit_i64
&& TCG_TARGET_deposit_i64_valid(32, 32)) {
2274 tcg_gen_deposit_i64(dest
, dest
, tmp
, 32, 32);
2276 tcg_gen_shli_i64(tmp
, tmp
, 32);
2277 tcg_gen_or_i64(dest
, dest
, tmp
);
2279 tcg_temp_free_i64(tmp
);
2283 static inline void tcg_gen_concat32_i64(TCGv_i64 dest
, TCGv_i64 low
,
2286 tcg_gen_deposit_i64(dest
, low
, high
, 32, 32);
2289 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret
, TCGv_i64 arg
)
2291 tcg_gen_trunc_shr_i64_i32(ret
, arg
, 0);
2294 static inline void tcg_gen_extr_i64_i32(TCGv_i32 lo
, TCGv_i32 hi
, TCGv_i64 arg
)
2296 tcg_gen_trunc_shr_i64_i32(lo
, arg
, 0);
2297 tcg_gen_trunc_shr_i64_i32(hi
, arg
, 32);
2300 static inline void tcg_gen_extr32_i64(TCGv_i64 lo
, TCGv_i64 hi
, TCGv_i64 arg
)
2302 tcg_gen_ext32u_i64(lo
, arg
);
2303 tcg_gen_shri_i64(hi
, arg
, 32);
2306 static inline void tcg_gen_movcond_i32(TCGCond cond
, TCGv_i32 ret
,
2307 TCGv_i32 c1
, TCGv_i32 c2
,
2308 TCGv_i32 v1
, TCGv_i32 v2
)
2310 if (TCG_TARGET_HAS_movcond_i32
) {
2311 tcg_gen_op6i_i32(INDEX_op_movcond_i32
, ret
, c1
, c2
, v1
, v2
, cond
);
2313 TCGv_i32 t0
= tcg_temp_new_i32();
2314 TCGv_i32 t1
= tcg_temp_new_i32();
2315 tcg_gen_setcond_i32(cond
, t0
, c1
, c2
);
2316 tcg_gen_neg_i32(t0
, t0
);
2317 tcg_gen_and_i32(t1
, v1
, t0
);
2318 tcg_gen_andc_i32(ret
, v2
, t0
);
2319 tcg_gen_or_i32(ret
, ret
, t1
);
2320 tcg_temp_free_i32(t0
);
2321 tcg_temp_free_i32(t1
);
2325 static inline void tcg_gen_movcond_i64(TCGCond cond
, TCGv_i64 ret
,
2326 TCGv_i64 c1
, TCGv_i64 c2
,
2327 TCGv_i64 v1
, TCGv_i64 v2
)
2329 #if TCG_TARGET_REG_BITS == 32
2330 TCGv_i32 t0
= tcg_temp_new_i32();
2331 TCGv_i32 t1
= tcg_temp_new_i32();
2332 tcg_gen_op6i_i32(INDEX_op_setcond2_i32
, t0
,
2333 TCGV_LOW(c1
), TCGV_HIGH(c1
),
2334 TCGV_LOW(c2
), TCGV_HIGH(c2
), cond
);
2336 if (TCG_TARGET_HAS_movcond_i32
) {
2337 tcg_gen_movi_i32(t1
, 0);
2338 tcg_gen_movcond_i32(TCG_COND_NE
, TCGV_LOW(ret
), t0
, t1
,
2339 TCGV_LOW(v1
), TCGV_LOW(v2
));
2340 tcg_gen_movcond_i32(TCG_COND_NE
, TCGV_HIGH(ret
), t0
, t1
,
2341 TCGV_HIGH(v1
), TCGV_HIGH(v2
));
2343 tcg_gen_neg_i32(t0
, t0
);
2345 tcg_gen_and_i32(t1
, TCGV_LOW(v1
), t0
);
2346 tcg_gen_andc_i32(TCGV_LOW(ret
), TCGV_LOW(v2
), t0
);
2347 tcg_gen_or_i32(TCGV_LOW(ret
), TCGV_LOW(ret
), t1
);
2349 tcg_gen_and_i32(t1
, TCGV_HIGH(v1
), t0
);
2350 tcg_gen_andc_i32(TCGV_HIGH(ret
), TCGV_HIGH(v2
), t0
);
2351 tcg_gen_or_i32(TCGV_HIGH(ret
), TCGV_HIGH(ret
), t1
);
2353 tcg_temp_free_i32(t0
);
2354 tcg_temp_free_i32(t1
);
2356 if (TCG_TARGET_HAS_movcond_i64
) {
2357 tcg_gen_op6i_i64(INDEX_op_movcond_i64
, ret
, c1
, c2
, v1
, v2
, cond
);
2359 TCGv_i64 t0
= tcg_temp_new_i64();
2360 TCGv_i64 t1
= tcg_temp_new_i64();
2361 tcg_gen_setcond_i64(cond
, t0
, c1
, c2
);
2362 tcg_gen_neg_i64(t0
, t0
);
2363 tcg_gen_and_i64(t1
, v1
, t0
);
2364 tcg_gen_andc_i64(ret
, v2
, t0
);
2365 tcg_gen_or_i64(ret
, ret
, t1
);
2366 tcg_temp_free_i64(t0
);
2367 tcg_temp_free_i64(t1
);
2372 static inline void tcg_gen_add2_i32(TCGv_i32 rl
, TCGv_i32 rh
, TCGv_i32 al
,
2373 TCGv_i32 ah
, TCGv_i32 bl
, TCGv_i32 bh
)
2375 if (TCG_TARGET_HAS_add2_i32
) {
2376 tcg_gen_op6_i32(INDEX_op_add2_i32
, rl
, rh
, al
, ah
, bl
, bh
);
2377 /* Allow the optimizer room to replace add2 with two moves. */
2378 tcg_gen_op0(INDEX_op_nop
);
2380 TCGv_i64 t0
= tcg_temp_new_i64();
2381 TCGv_i64 t1
= tcg_temp_new_i64();
2382 tcg_gen_concat_i32_i64(t0
, al
, ah
);
2383 tcg_gen_concat_i32_i64(t1
, bl
, bh
);
2384 tcg_gen_add_i64(t0
, t0
, t1
);
2385 tcg_gen_extr_i64_i32(rl
, rh
, t0
);
2386 tcg_temp_free_i64(t0
);
2387 tcg_temp_free_i64(t1
);
2391 static inline void tcg_gen_sub2_i32(TCGv_i32 rl
, TCGv_i32 rh
, TCGv_i32 al
,
2392 TCGv_i32 ah
, TCGv_i32 bl
, TCGv_i32 bh
)
2394 if (TCG_TARGET_HAS_sub2_i32
) {
2395 tcg_gen_op6_i32(INDEX_op_sub2_i32
, rl
, rh
, al
, ah
, bl
, bh
);
2396 /* Allow the optimizer room to replace sub2 with two moves. */
2397 tcg_gen_op0(INDEX_op_nop
);
2399 TCGv_i64 t0
= tcg_temp_new_i64();
2400 TCGv_i64 t1
= tcg_temp_new_i64();
2401 tcg_gen_concat_i32_i64(t0
, al
, ah
);
2402 tcg_gen_concat_i32_i64(t1
, bl
, bh
);
2403 tcg_gen_sub_i64(t0
, t0
, t1
);
2404 tcg_gen_extr_i64_i32(rl
, rh
, t0
);
2405 tcg_temp_free_i64(t0
);
2406 tcg_temp_free_i64(t1
);
2410 static inline void tcg_gen_mulu2_i32(TCGv_i32 rl
, TCGv_i32 rh
,
2411 TCGv_i32 arg1
, TCGv_i32 arg2
)
2413 if (TCG_TARGET_HAS_mulu2_i32
) {
2414 tcg_gen_op4_i32(INDEX_op_mulu2_i32
, rl
, rh
, arg1
, arg2
);
2415 /* Allow the optimizer room to replace mulu2 with two moves. */
2416 tcg_gen_op0(INDEX_op_nop
);
2417 } else if (TCG_TARGET_HAS_muluh_i32
) {
2418 TCGv_i32 t
= tcg_temp_new_i32();
2419 tcg_gen_op3_i32(INDEX_op_mul_i32
, t
, arg1
, arg2
);
2420 tcg_gen_op3_i32(INDEX_op_muluh_i32
, rh
, arg1
, arg2
);
2421 tcg_gen_mov_i32(rl
, t
);
2422 tcg_temp_free_i32(t
);
2424 TCGv_i64 t0
= tcg_temp_new_i64();
2425 TCGv_i64 t1
= tcg_temp_new_i64();
2426 tcg_gen_extu_i32_i64(t0
, arg1
);
2427 tcg_gen_extu_i32_i64(t1
, arg2
);
2428 tcg_gen_mul_i64(t0
, t0
, t1
);
2429 tcg_gen_extr_i64_i32(rl
, rh
, t0
);
2430 tcg_temp_free_i64(t0
);
2431 tcg_temp_free_i64(t1
);
2435 static inline void tcg_gen_muls2_i32(TCGv_i32 rl
, TCGv_i32 rh
,
2436 TCGv_i32 arg1
, TCGv_i32 arg2
)
2438 if (TCG_TARGET_HAS_muls2_i32
) {
2439 tcg_gen_op4_i32(INDEX_op_muls2_i32
, rl
, rh
, arg1
, arg2
);
2440 /* Allow the optimizer room to replace muls2 with two moves. */
2441 tcg_gen_op0(INDEX_op_nop
);
2442 } else if (TCG_TARGET_HAS_mulsh_i32
) {
2443 TCGv_i32 t
= tcg_temp_new_i32();
2444 tcg_gen_op3_i32(INDEX_op_mul_i32
, t
, arg1
, arg2
);
2445 tcg_gen_op3_i32(INDEX_op_mulsh_i32
, rh
, arg1
, arg2
);
2446 tcg_gen_mov_i32(rl
, t
);
2447 tcg_temp_free_i32(t
);
2448 } else if (TCG_TARGET_REG_BITS
== 32) {
2449 TCGv_i32 t0
= tcg_temp_new_i32();
2450 TCGv_i32 t1
= tcg_temp_new_i32();
2451 TCGv_i32 t2
= tcg_temp_new_i32();
2452 TCGv_i32 t3
= tcg_temp_new_i32();
2453 tcg_gen_mulu2_i32(t0
, t1
, arg1
, arg2
);
2454 /* Adjust for negative inputs. */
2455 tcg_gen_sari_i32(t2
, arg1
, 31);
2456 tcg_gen_sari_i32(t3
, arg2
, 31);
2457 tcg_gen_and_i32(t2
, t2
, arg2
);
2458 tcg_gen_and_i32(t3
, t3
, arg1
);
2459 tcg_gen_sub_i32(rh
, t1
, t2
);
2460 tcg_gen_sub_i32(rh
, rh
, t3
);
2461 tcg_gen_mov_i32(rl
, t0
);
2462 tcg_temp_free_i32(t0
);
2463 tcg_temp_free_i32(t1
);
2464 tcg_temp_free_i32(t2
);
2465 tcg_temp_free_i32(t3
);
2467 TCGv_i64 t0
= tcg_temp_new_i64();
2468 TCGv_i64 t1
= tcg_temp_new_i64();
2469 tcg_gen_ext_i32_i64(t0
, arg1
);
2470 tcg_gen_ext_i32_i64(t1
, arg2
);
2471 tcg_gen_mul_i64(t0
, t0
, t1
);
2472 tcg_gen_extr_i64_i32(rl
, rh
, t0
);
2473 tcg_temp_free_i64(t0
);
2474 tcg_temp_free_i64(t1
);
2478 static inline void tcg_gen_add2_i64(TCGv_i64 rl
, TCGv_i64 rh
, TCGv_i64 al
,
2479 TCGv_i64 ah
, TCGv_i64 bl
, TCGv_i64 bh
)
2481 if (TCG_TARGET_HAS_add2_i64
) {
2482 tcg_gen_op6_i64(INDEX_op_add2_i64
, rl
, rh
, al
, ah
, bl
, bh
);
2483 /* Allow the optimizer room to replace add2 with two moves. */
2484 tcg_gen_op0(INDEX_op_nop
);
2486 TCGv_i64 t0
= tcg_temp_new_i64();
2487 TCGv_i64 t1
= tcg_temp_new_i64();
2488 tcg_gen_add_i64(t0
, al
, bl
);
2489 tcg_gen_setcond_i64(TCG_COND_LTU
, t1
, t0
, al
);
2490 tcg_gen_add_i64(rh
, ah
, bh
);
2491 tcg_gen_add_i64(rh
, rh
, t1
);
2492 tcg_gen_mov_i64(rl
, t0
);
2493 tcg_temp_free_i64(t0
);
2494 tcg_temp_free_i64(t1
);
2498 static inline void tcg_gen_sub2_i64(TCGv_i64 rl
, TCGv_i64 rh
, TCGv_i64 al
,
2499 TCGv_i64 ah
, TCGv_i64 bl
, TCGv_i64 bh
)
2501 if (TCG_TARGET_HAS_sub2_i64
) {
2502 tcg_gen_op6_i64(INDEX_op_sub2_i64
, rl
, rh
, al
, ah
, bl
, bh
);
2503 /* Allow the optimizer room to replace sub2 with two moves. */
2504 tcg_gen_op0(INDEX_op_nop
);
2506 TCGv_i64 t0
= tcg_temp_new_i64();
2507 TCGv_i64 t1
= tcg_temp_new_i64();
2508 tcg_gen_sub_i64(t0
, al
, bl
);
2509 tcg_gen_setcond_i64(TCG_COND_LTU
, t1
, al
, bl
);
2510 tcg_gen_sub_i64(rh
, ah
, bh
);
2511 tcg_gen_sub_i64(rh
, rh
, t1
);
2512 tcg_gen_mov_i64(rl
, t0
);
2513 tcg_temp_free_i64(t0
);
2514 tcg_temp_free_i64(t1
);
2518 static inline void tcg_gen_mulu2_i64(TCGv_i64 rl
, TCGv_i64 rh
,
2519 TCGv_i64 arg1
, TCGv_i64 arg2
)
2521 if (TCG_TARGET_HAS_mulu2_i64
) {
2522 tcg_gen_op4_i64(INDEX_op_mulu2_i64
, rl
, rh
, arg1
, arg2
);
2523 /* Allow the optimizer room to replace mulu2 with two moves. */
2524 tcg_gen_op0(INDEX_op_nop
);
2525 } else if (TCG_TARGET_HAS_muluh_i64
) {
2526 TCGv_i64 t
= tcg_temp_new_i64();
2527 tcg_gen_op3_i64(INDEX_op_mul_i64
, t
, arg1
, arg2
);
2528 tcg_gen_op3_i64(INDEX_op_muluh_i64
, rh
, arg1
, arg2
);
2529 tcg_gen_mov_i64(rl
, t
);
2530 tcg_temp_free_i64(t
);
2532 TCGv_i64 t0
= tcg_temp_new_i64();
2534 /* Return value and both arguments are 64-bit and unsigned. */
2535 sizemask
|= tcg_gen_sizemask(0, 1, 0);
2536 sizemask
|= tcg_gen_sizemask(1, 1, 0);
2537 sizemask
|= tcg_gen_sizemask(2, 1, 0);
2538 tcg_gen_mul_i64(t0
, arg1
, arg2
);
2539 tcg_gen_helper64(tcg_helper_muluh_i64
, sizemask
, rh
, arg1
, arg2
);
2540 tcg_gen_mov_i64(rl
, t0
);
2541 tcg_temp_free_i64(t0
);
2545 static inline void tcg_gen_muls2_i64(TCGv_i64 rl
, TCGv_i64 rh
,
2546 TCGv_i64 arg1
, TCGv_i64 arg2
)
2548 if (TCG_TARGET_HAS_muls2_i64
) {
2549 tcg_gen_op4_i64(INDEX_op_muls2_i64
, rl
, rh
, arg1
, arg2
);
2550 /* Allow the optimizer room to replace muls2 with two moves. */
2551 tcg_gen_op0(INDEX_op_nop
);
2552 } else if (TCG_TARGET_HAS_mulsh_i64
) {
2553 TCGv_i64 t
= tcg_temp_new_i64();
2554 tcg_gen_op3_i64(INDEX_op_mul_i64
, t
, arg1
, arg2
);
2555 tcg_gen_op3_i64(INDEX_op_mulsh_i64
, rh
, arg1
, arg2
);
2556 tcg_gen_mov_i64(rl
, t
);
2557 tcg_temp_free_i64(t
);
2558 } else if (TCG_TARGET_HAS_mulu2_i64
|| TCG_TARGET_HAS_muluh_i64
) {
2559 TCGv_i64 t0
= tcg_temp_new_i64();
2560 TCGv_i64 t1
= tcg_temp_new_i64();
2561 TCGv_i64 t2
= tcg_temp_new_i64();
2562 TCGv_i64 t3
= tcg_temp_new_i64();
2563 tcg_gen_mulu2_i64(t0
, t1
, arg1
, arg2
);
2564 /* Adjust for negative inputs. */
2565 tcg_gen_sari_i64(t2
, arg1
, 63);
2566 tcg_gen_sari_i64(t3
, arg2
, 63);
2567 tcg_gen_and_i64(t2
, t2
, arg2
);
2568 tcg_gen_and_i64(t3
, t3
, arg1
);
2569 tcg_gen_sub_i64(rh
, t1
, t2
);
2570 tcg_gen_sub_i64(rh
, rh
, t3
);
2571 tcg_gen_mov_i64(rl
, t0
);
2572 tcg_temp_free_i64(t0
);
2573 tcg_temp_free_i64(t1
);
2574 tcg_temp_free_i64(t2
);
2575 tcg_temp_free_i64(t3
);
2577 TCGv_i64 t0
= tcg_temp_new_i64();
2579 /* Return value and both arguments are 64-bit and signed. */
2580 sizemask
|= tcg_gen_sizemask(0, 1, 1);
2581 sizemask
|= tcg_gen_sizemask(1, 1, 1);
2582 sizemask
|= tcg_gen_sizemask(2, 1, 1);
2583 tcg_gen_mul_i64(t0
, arg1
, arg2
);
2584 tcg_gen_helper64(tcg_helper_mulsh_i64
, sizemask
, rh
, arg1
, arg2
);
2585 tcg_gen_mov_i64(rl
, t0
);
2586 tcg_temp_free_i64(t0
);
2590 /***************************************/
2591 /* QEMU specific operations. Their type depend on the QEMU CPU
2593 #ifndef TARGET_LONG_BITS
2594 #error must include QEMU headers
2597 #if TARGET_LONG_BITS == 32
2598 #define TCGv TCGv_i32
2599 #define tcg_temp_new() tcg_temp_new_i32()
2600 #define tcg_global_reg_new tcg_global_reg_new_i32
2601 #define tcg_global_mem_new tcg_global_mem_new_i32
2602 #define tcg_temp_local_new() tcg_temp_local_new_i32()
2603 #define tcg_temp_free tcg_temp_free_i32
2604 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
2605 #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)
2606 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
2607 #define tcg_add_param_tl tcg_add_param_i32
2608 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
2609 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
2611 #define TCGv TCGv_i64
2612 #define tcg_temp_new() tcg_temp_new_i64()
2613 #define tcg_global_reg_new tcg_global_reg_new_i64
2614 #define tcg_global_mem_new tcg_global_mem_new_i64
2615 #define tcg_temp_local_new() tcg_temp_local_new_i64()
2616 #define tcg_temp_free tcg_temp_free_i64
2617 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
2618 #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)
2619 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
2620 #define tcg_add_param_tl tcg_add_param_i64
2621 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
2622 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
2625 /* debug info: write the PC of the corresponding QEMU CPU instruction */
2626 static inline void tcg_gen_debug_insn_start(uint64_t pc
)
2628 /* XXX: must really use a 32 bit size for TCGArg in all cases */
2629 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2630 tcg_gen_op2ii(INDEX_op_debug_insn_start
,
2631 (uint32_t)(pc
), (uint32_t)(pc
>> 32));
2633 tcg_gen_op1i(INDEX_op_debug_insn_start
, pc
);
2637 static inline void tcg_gen_exit_tb(uintptr_t val
)
2639 tcg_gen_op1i(INDEX_op_exit_tb
, val
);
2642 static inline void tcg_gen_goto_tb(unsigned idx
)
2644 /* We only support two chained exits. */
2645 tcg_debug_assert(idx
<= 1);
2646 #ifdef CONFIG_DEBUG_TCG
2647 /* Verify that we havn't seen this numbered exit before. */
2648 tcg_debug_assert((tcg_ctx
.goto_tb_issue_mask
& (1 << idx
)) == 0);
2649 tcg_ctx
.goto_tb_issue_mask
|= 1 << idx
;
2651 tcg_gen_op1i(INDEX_op_goto_tb
, idx
);
2655 void tcg_gen_qemu_ld_i32(TCGv_i32
, TCGv
, TCGArg
, TCGMemOp
);
2656 void tcg_gen_qemu_st_i32(TCGv_i32
, TCGv
, TCGArg
, TCGMemOp
);
2657 void tcg_gen_qemu_ld_i64(TCGv_i64
, TCGv
, TCGArg
, TCGMemOp
);
2658 void tcg_gen_qemu_st_i64(TCGv_i64
, TCGv
, TCGArg
, TCGMemOp
);
2660 static inline void tcg_gen_qemu_ld8u(TCGv ret
, TCGv addr
, int mem_index
)
2662 tcg_gen_qemu_ld_tl(ret
, addr
, mem_index
, MO_UB
);
2665 static inline void tcg_gen_qemu_ld8s(TCGv ret
, TCGv addr
, int mem_index
)
2667 tcg_gen_qemu_ld_tl(ret
, addr
, mem_index
, MO_SB
);
2670 static inline void tcg_gen_qemu_ld16u(TCGv ret
, TCGv addr
, int mem_index
)
2672 tcg_gen_qemu_ld_tl(ret
, addr
, mem_index
, MO_TEUW
);
2675 static inline void tcg_gen_qemu_ld16s(TCGv ret
, TCGv addr
, int mem_index
)
2677 tcg_gen_qemu_ld_tl(ret
, addr
, mem_index
, MO_TESW
);
2680 static inline void tcg_gen_qemu_ld32u(TCGv ret
, TCGv addr
, int mem_index
)
2682 tcg_gen_qemu_ld_tl(ret
, addr
, mem_index
, MO_TEUL
);
2685 static inline void tcg_gen_qemu_ld32s(TCGv ret
, TCGv addr
, int mem_index
)
2687 tcg_gen_qemu_ld_tl(ret
, addr
, mem_index
, MO_TESL
);
2690 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret
, TCGv addr
, int mem_index
)
2692 tcg_gen_qemu_ld_i64(ret
, addr
, mem_index
, MO_TEQ
);
2695 static inline void tcg_gen_qemu_st8(TCGv arg
, TCGv addr
, int mem_index
)
2697 tcg_gen_qemu_st_tl(arg
, addr
, mem_index
, MO_UB
);
2700 static inline void tcg_gen_qemu_st16(TCGv arg
, TCGv addr
, int mem_index
)
2702 tcg_gen_qemu_st_tl(arg
, addr
, mem_index
, MO_TEUW
);
2705 static inline void tcg_gen_qemu_st32(TCGv arg
, TCGv addr
, int mem_index
)
2707 tcg_gen_qemu_st_tl(arg
, addr
, mem_index
, MO_TEUL
);
2710 static inline void tcg_gen_qemu_st64(TCGv_i64 arg
, TCGv addr
, int mem_index
)
2712 tcg_gen_qemu_st_i64(arg
, addr
, mem_index
, MO_TEQ
);
2715 #if TARGET_LONG_BITS == 64
2716 #define tcg_gen_movi_tl tcg_gen_movi_i64
2717 #define tcg_gen_mov_tl tcg_gen_mov_i64
2718 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2719 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2720 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2721 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2722 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2723 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2724 #define tcg_gen_ld_tl tcg_gen_ld_i64
2725 #define tcg_gen_st8_tl tcg_gen_st8_i64
2726 #define tcg_gen_st16_tl tcg_gen_st16_i64
2727 #define tcg_gen_st32_tl tcg_gen_st32_i64
2728 #define tcg_gen_st_tl tcg_gen_st_i64
2729 #define tcg_gen_add_tl tcg_gen_add_i64
2730 #define tcg_gen_addi_tl tcg_gen_addi_i64
2731 #define tcg_gen_sub_tl tcg_gen_sub_i64
2732 #define tcg_gen_neg_tl tcg_gen_neg_i64
2733 #define tcg_gen_subfi_tl tcg_gen_subfi_i64
2734 #define tcg_gen_subi_tl tcg_gen_subi_i64
2735 #define tcg_gen_and_tl tcg_gen_and_i64
2736 #define tcg_gen_andi_tl tcg_gen_andi_i64
2737 #define tcg_gen_or_tl tcg_gen_or_i64
2738 #define tcg_gen_ori_tl tcg_gen_ori_i64
2739 #define tcg_gen_xor_tl tcg_gen_xor_i64
2740 #define tcg_gen_xori_tl tcg_gen_xori_i64
2741 #define tcg_gen_not_tl tcg_gen_not_i64
2742 #define tcg_gen_shl_tl tcg_gen_shl_i64
2743 #define tcg_gen_shli_tl tcg_gen_shli_i64
2744 #define tcg_gen_shr_tl tcg_gen_shr_i64
2745 #define tcg_gen_shri_tl tcg_gen_shri_i64
2746 #define tcg_gen_sar_tl tcg_gen_sar_i64
2747 #define tcg_gen_sari_tl tcg_gen_sari_i64
2748 #define tcg_gen_brcond_tl tcg_gen_brcond_i64
2749 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2750 #define tcg_gen_setcond_tl tcg_gen_setcond_i64
2751 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
2752 #define tcg_gen_mul_tl tcg_gen_mul_i64
2753 #define tcg_gen_muli_tl tcg_gen_muli_i64
2754 #define tcg_gen_div_tl tcg_gen_div_i64
2755 #define tcg_gen_rem_tl tcg_gen_rem_i64
2756 #define tcg_gen_divu_tl tcg_gen_divu_i64
2757 #define tcg_gen_remu_tl tcg_gen_remu_i64
2758 #define tcg_gen_discard_tl tcg_gen_discard_i64
2759 #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2760 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2761 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2762 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2763 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2764 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2765 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2766 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2767 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2768 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2769 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2770 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2771 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2772 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2773 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2774 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2775 #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
2776 #define tcg_gen_andc_tl tcg_gen_andc_i64
2777 #define tcg_gen_eqv_tl tcg_gen_eqv_i64
2778 #define tcg_gen_nand_tl tcg_gen_nand_i64
2779 #define tcg_gen_nor_tl tcg_gen_nor_i64
2780 #define tcg_gen_orc_tl tcg_gen_orc_i64
2781 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
2782 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
2783 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
2784 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
2785 #define tcg_gen_deposit_tl tcg_gen_deposit_i64
2786 #define tcg_const_tl tcg_const_i64
2787 #define tcg_const_local_tl tcg_const_local_i64
2788 #define tcg_gen_movcond_tl tcg_gen_movcond_i64
2789 #define tcg_gen_add2_tl tcg_gen_add2_i64
2790 #define tcg_gen_sub2_tl tcg_gen_sub2_i64
2791 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
2792 #define tcg_gen_muls2_tl tcg_gen_muls2_i64
2794 #define tcg_gen_movi_tl tcg_gen_movi_i32
2795 #define tcg_gen_mov_tl tcg_gen_mov_i32
2796 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2797 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2798 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2799 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2800 #define tcg_gen_ld32u_tl tcg_gen_ld_i32
2801 #define tcg_gen_ld32s_tl tcg_gen_ld_i32
2802 #define tcg_gen_ld_tl tcg_gen_ld_i32
2803 #define tcg_gen_st8_tl tcg_gen_st8_i32
2804 #define tcg_gen_st16_tl tcg_gen_st16_i32
2805 #define tcg_gen_st32_tl tcg_gen_st_i32
2806 #define tcg_gen_st_tl tcg_gen_st_i32
2807 #define tcg_gen_add_tl tcg_gen_add_i32
2808 #define tcg_gen_addi_tl tcg_gen_addi_i32
2809 #define tcg_gen_sub_tl tcg_gen_sub_i32
2810 #define tcg_gen_neg_tl tcg_gen_neg_i32
2811 #define tcg_gen_subfi_tl tcg_gen_subfi_i32
2812 #define tcg_gen_subi_tl tcg_gen_subi_i32
2813 #define tcg_gen_and_tl tcg_gen_and_i32
2814 #define tcg_gen_andi_tl tcg_gen_andi_i32
2815 #define tcg_gen_or_tl tcg_gen_or_i32
2816 #define tcg_gen_ori_tl tcg_gen_ori_i32
2817 #define tcg_gen_xor_tl tcg_gen_xor_i32
2818 #define tcg_gen_xori_tl tcg_gen_xori_i32
2819 #define tcg_gen_not_tl tcg_gen_not_i32
2820 #define tcg_gen_shl_tl tcg_gen_shl_i32
2821 #define tcg_gen_shli_tl tcg_gen_shli_i32
2822 #define tcg_gen_shr_tl tcg_gen_shr_i32
2823 #define tcg_gen_shri_tl tcg_gen_shri_i32
2824 #define tcg_gen_sar_tl tcg_gen_sar_i32
2825 #define tcg_gen_sari_tl tcg_gen_sari_i32
2826 #define tcg_gen_brcond_tl tcg_gen_brcond_i32
2827 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2828 #define tcg_gen_setcond_tl tcg_gen_setcond_i32
2829 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
2830 #define tcg_gen_mul_tl tcg_gen_mul_i32
2831 #define tcg_gen_muli_tl tcg_gen_muli_i32
2832 #define tcg_gen_div_tl tcg_gen_div_i32
2833 #define tcg_gen_rem_tl tcg_gen_rem_i32
2834 #define tcg_gen_divu_tl tcg_gen_divu_i32
2835 #define tcg_gen_remu_tl tcg_gen_remu_i32
2836 #define tcg_gen_discard_tl tcg_gen_discard_i32
2837 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2838 #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2839 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2840 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2841 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2842 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2843 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2844 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2845 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2846 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2847 #define tcg_gen_ext32u_tl tcg_gen_mov_i32
2848 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
2849 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2850 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2851 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2852 #define tcg_gen_extr_tl_i64 tcg_gen_extr_i32_i64
2853 #define tcg_gen_andc_tl tcg_gen_andc_i32
2854 #define tcg_gen_eqv_tl tcg_gen_eqv_i32
2855 #define tcg_gen_nand_tl tcg_gen_nand_i32
2856 #define tcg_gen_nor_tl tcg_gen_nor_i32
2857 #define tcg_gen_orc_tl tcg_gen_orc_i32
2858 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
2859 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
2860 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
2861 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
2862 #define tcg_gen_deposit_tl tcg_gen_deposit_i32
2863 #define tcg_const_tl tcg_const_i32
2864 #define tcg_const_local_tl tcg_const_local_i32
2865 #define tcg_gen_movcond_tl tcg_gen_movcond_i32
2866 #define tcg_gen_add2_tl tcg_gen_add2_i32
2867 #define tcg_gen_sub2_tl tcg_gen_sub2_i32
2868 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
2869 #define tcg_gen_muls2_tl tcg_gen_muls2_i32
2872 #if UINTPTR_MAX == UINT32_MAX
2873 # define tcg_gen_ld_ptr(R, A, O) \
2874 tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
2875 # define tcg_gen_discard_ptr(A) \
2876 tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
2877 # define tcg_gen_add_ptr(R, A, B) \
2878 tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
2879 # define tcg_gen_addi_ptr(R, A, B) \
2880 tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
2881 # define tcg_gen_ext_i32_ptr(R, A) \
2882 tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
2884 # define tcg_gen_ld_ptr(R, A, O) \
2885 tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
2886 # define tcg_gen_discard_ptr(A) \
2887 tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
2888 # define tcg_gen_add_ptr(R, A, B) \
2889 tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
2890 # define tcg_gen_addi_ptr(R, A, B) \
2891 tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
2892 # define tcg_gen_ext_i32_ptr(R, A) \
2893 tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
2894 #endif /* UINTPTR_MAX == UINT32_MAX */