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ahci: fix DPRINTF format strings
[qemu/cris-port.git] / hw / pci.c
blobe8cc1b046ffabff719f4e2054295e06deddabeca
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "qemu-objects.h"
33 #include "range.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static char *pcibus_get_fw_dev_path(DeviceState *dev);
45 static int pcibus_reset(BusState *qbus);
46
47 struct BusInfo pci_bus_info = {
48 .name = "PCI",
49 .size = sizeof(PCIBus),
50 .print_dev = pcibus_dev_print,
51 .get_dev_path = pcibus_get_dev_path,
52 .get_fw_dev_path = pcibus_get_fw_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
61 QEMU_PCI_CAP_SERR_BITNR, true),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
130 {
131 assert(irq_num >= 0);
132 assert(irq_num < bus->nirq);
133 return !!bus->irq_count[irq_num];
134 }
135
136 /* Update interrupt status bit in config space on interrupt
137 * state change. */
138 static void pci_update_irq_status(PCIDevice *dev)
139 {
140 if (dev->irq_state) {
141 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
142 } else {
143 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
144 }
145 }
146
147 void pci_device_deassert_intx(PCIDevice *dev)
148 {
149 int i;
150 for (i = 0; i < PCI_NUM_PINS; ++i) {
151 qemu_set_irq(dev->irq[i], 0);
152 }
153 }
154
155 /*
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
158 */
159 void pci_device_reset(PCIDevice *dev)
160 {
161 int r;
162 /* TODO: call the below unconditionally once all pci devices
163 * are qdevified */
164 if (dev->qdev.info) {
165 qdev_reset_all(&dev->qdev);
166 }
167
168 dev->irq_state = 0;
169 pci_update_irq_status(dev);
170 pci_device_deassert_intx(dev);
171 /* Clear all writable bits */
172 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
173 pci_get_word(dev->wmask + PCI_COMMAND) |
174 pci_get_word(dev->w1cmask + PCI_COMMAND));
175 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
176 pci_get_word(dev->wmask + PCI_STATUS) |
177 pci_get_word(dev->w1cmask + PCI_STATUS));
178 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
179 dev->config[PCI_INTERRUPT_LINE] = 0x0;
180 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
181 PCIIORegion *region = &dev->io_regions[r];
182 if (!region->size) {
183 continue;
184 }
185
186 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
187 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
188 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
189 } else {
190 pci_set_long(dev->config + pci_bar(dev, r), region->type);
191 }
192 }
193 pci_update_mappings(dev);
194 }
195
196 /*
197 * Trigger pci bus reset under a given bus.
198 * To be called on RST# assert.
199 */
200 void pci_bus_reset(PCIBus *bus)
201 {
202 int i;
203
204 for (i = 0; i < bus->nirq; i++) {
205 bus->irq_count[i] = 0;
206 }
207 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
208 if (bus->devices[i]) {
209 pci_device_reset(bus->devices[i]);
210 }
211 }
212 }
213
214 static int pcibus_reset(BusState *qbus)
215 {
216 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
217
218 /* topology traverse is done by pci_bus_reset().
219 Tell qbus/qdev walker not to traverse the tree */
220 return 1;
221 }
222
223 static void pci_host_bus_register(int domain, PCIBus *bus)
224 {
225 struct PCIHostBus *host;
226 host = g_malloc0(sizeof(*host));
227 host->domain = domain;
228 host->bus = bus;
229 QLIST_INSERT_HEAD(&host_buses, host, next);
230 }
231
232 PCIBus *pci_find_root_bus(int domain)
233 {
234 struct PCIHostBus *host;
235
236 QLIST_FOREACH(host, &host_buses, next) {
237 if (host->domain == domain) {
238 return host->bus;
239 }
240 }
241
242 return NULL;
243 }
244
245 int pci_find_domain(const PCIBus *bus)
246 {
247 PCIDevice *d;
248 struct PCIHostBus *host;
249
250 /* obtain root bus */
251 while ((d = bus->parent_dev) != NULL) {
252 bus = d->bus;
253 }
254
255 QLIST_FOREACH(host, &host_buses, next) {
256 if (host->bus == bus) {
257 return host->domain;
258 }
259 }
260
261 abort(); /* should not be reached */
262 return -1;
263 }
264
265 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
266 const char *name,
267 MemoryRegion *address_space_mem,
268 MemoryRegion *address_space_io,
269 uint8_t devfn_min)
270 {
271 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
272 assert(PCI_FUNC(devfn_min) == 0);
273 bus->devfn_min = devfn_min;
274 bus->address_space_mem = address_space_mem;
275 bus->address_space_io = address_space_io;
276
277 /* host bridge */
278 QLIST_INIT(&bus->child);
279 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
280
281 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
282 }
283
284 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
285 MemoryRegion *address_space_mem,
286 MemoryRegion *address_space_io,
287 uint8_t devfn_min)
288 {
289 PCIBus *bus;
290
291 bus = g_malloc0(sizeof(*bus));
292 bus->qbus.qdev_allocated = 1;
293 pci_bus_new_inplace(bus, parent, name, address_space_mem,
294 address_space_io, devfn_min);
295 return bus;
296 }
297
298 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
299 void *irq_opaque, int nirq)
300 {
301 bus->set_irq = set_irq;
302 bus->map_irq = map_irq;
303 bus->irq_opaque = irq_opaque;
304 bus->nirq = nirq;
305 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
306 }
307
308 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
309 {
310 bus->qbus.allow_hotplug = 1;
311 bus->hotplug = hotplug;
312 bus->hotplug_qdev = qdev;
313 }
314
315 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
316 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
317 void *irq_opaque,
318 MemoryRegion *address_space_mem,
319 MemoryRegion *address_space_io,
320 uint8_t devfn_min, int nirq)
321 {
322 PCIBus *bus;
323
324 bus = pci_bus_new(parent, name, address_space_mem,
325 address_space_io, devfn_min);
326 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
327 return bus;
328 }
329
330 int pci_bus_num(PCIBus *s)
331 {
332 if (!s->parent_dev)
333 return 0; /* pci host bridge */
334 return s->parent_dev->config[PCI_SECONDARY_BUS];
335 }
336
337 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
338 {
339 PCIDevice *s = container_of(pv, PCIDevice, config);
340 uint8_t *config;
341 int i;
342
343 assert(size == pci_config_size(s));
344 config = g_malloc(size);
345
346 qemu_get_buffer(f, config, size);
347 for (i = 0; i < size; ++i) {
348 if ((config[i] ^ s->config[i]) &
349 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
350 g_free(config);
351 return -EINVAL;
352 }
353 }
354 memcpy(s->config, config, size);
355
356 pci_update_mappings(s);
357
358 g_free(config);
359 return 0;
360 }
361
362 /* just put buffer */
363 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
364 {
365 const uint8_t **v = pv;
366 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
367 qemu_put_buffer(f, *v, size);
368 }
369
370 static VMStateInfo vmstate_info_pci_config = {
371 .name = "pci config",
372 .get = get_pci_config_device,
373 .put = put_pci_config_device,
374 };
375
376 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
377 {
378 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
379 uint32_t irq_state[PCI_NUM_PINS];
380 int i;
381 for (i = 0; i < PCI_NUM_PINS; ++i) {
382 irq_state[i] = qemu_get_be32(f);
383 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
384 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
385 irq_state[i]);
386 return -EINVAL;
387 }
388 }
389
390 for (i = 0; i < PCI_NUM_PINS; ++i) {
391 pci_set_irq_state(s, i, irq_state[i]);
392 }
393
394 return 0;
395 }
396
397 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
398 {
399 int i;
400 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
401
402 for (i = 0; i < PCI_NUM_PINS; ++i) {
403 qemu_put_be32(f, pci_irq_state(s, i));
404 }
405 }
406
407 static VMStateInfo vmstate_info_pci_irq_state = {
408 .name = "pci irq state",
409 .get = get_pci_irq_state,
410 .put = put_pci_irq_state,
411 };
412
413 const VMStateDescription vmstate_pci_device = {
414 .name = "PCIDevice",
415 .version_id = 2,
416 .minimum_version_id = 1,
417 .minimum_version_id_old = 1,
418 .fields = (VMStateField []) {
419 VMSTATE_INT32_LE(version_id, PCIDevice),
420 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
421 vmstate_info_pci_config,
422 PCI_CONFIG_SPACE_SIZE),
423 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
424 vmstate_info_pci_irq_state,
425 PCI_NUM_PINS * sizeof(int32_t)),
426 VMSTATE_END_OF_LIST()
427 }
428 };
429
430 const VMStateDescription vmstate_pcie_device = {
431 .name = "PCIDevice",
432 .version_id = 2,
433 .minimum_version_id = 1,
434 .minimum_version_id_old = 1,
435 .fields = (VMStateField []) {
436 VMSTATE_INT32_LE(version_id, PCIDevice),
437 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
438 vmstate_info_pci_config,
439 PCIE_CONFIG_SPACE_SIZE),
440 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
441 vmstate_info_pci_irq_state,
442 PCI_NUM_PINS * sizeof(int32_t)),
443 VMSTATE_END_OF_LIST()
444 }
445 };
446
447 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
448 {
449 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
450 }
451
452 void pci_device_save(PCIDevice *s, QEMUFile *f)
453 {
454 /* Clear interrupt status bit: it is implicit
455 * in irq_state which we are saving.
456 * This makes us compatible with old devices
457 * which never set or clear this bit. */
458 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
459 vmstate_save_state(f, pci_get_vmstate(s), s);
460 /* Restore the interrupt status bit. */
461 pci_update_irq_status(s);
462 }
463
464 int pci_device_load(PCIDevice *s, QEMUFile *f)
465 {
466 int ret;
467 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
468 /* Restore the interrupt status bit. */
469 pci_update_irq_status(s);
470 return ret;
471 }
472
473 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
474 {
475 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
476 pci_default_sub_vendor_id);
477 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
478 pci_default_sub_device_id);
479 }
480
481 /*
482 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
483 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
484 */
485 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
486 unsigned int *slotp, unsigned int *funcp)
487 {
488 const char *p;
489 char *e;
490 unsigned long val;
491 unsigned long dom = 0, bus = 0;
492 unsigned int slot = 0;
493 unsigned int func = 0;
494
495 p = addr;
496 val = strtoul(p, &e, 16);
497 if (e == p)
498 return -1;
499 if (*e == ':') {
500 bus = val;
501 p = e + 1;
502 val = strtoul(p, &e, 16);
503 if (e == p)
504 return -1;
505 if (*e == ':') {
506 dom = bus;
507 bus = val;
508 p = e + 1;
509 val = strtoul(p, &e, 16);
510 if (e == p)
511 return -1;
512 }
513 }
514
515 slot = val;
516
517 if (funcp != NULL) {
518 if (*e != '.')
519 return -1;
520
521 p = e + 1;
522 val = strtoul(p, &e, 16);
523 if (e == p)
524 return -1;
525
526 func = val;
527 }
528
529 /* if funcp == NULL func is 0 */
530 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
531 return -1;
532
533 if (*e)
534 return -1;
535
536 /* Note: QEMU doesn't implement domains other than 0 */
537 if (!pci_find_bus(pci_find_root_bus(dom), bus))
538 return -1;
539
540 *domp = dom;
541 *busp = bus;
542 *slotp = slot;
543 if (funcp != NULL)
544 *funcp = func;
545 return 0;
546 }
547
548 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
549 unsigned *slotp)
550 {
551 /* strip legacy tag */
552 if (!strncmp(addr, "pci_addr=", 9)) {
553 addr += 9;
554 }
555 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
556 monitor_printf(mon, "Invalid pci address\n");
557 return -1;
558 }
559 return 0;
560 }
561
562 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
563 {
564 int dom, bus;
565 unsigned slot;
566
567 if (!devaddr) {
568 *devfnp = -1;
569 return pci_find_bus(pci_find_root_bus(0), 0);
570 }
571
572 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
573 return NULL;
574 }
575
576 *devfnp = PCI_DEVFN(slot, 0);
577 return pci_find_bus(pci_find_root_bus(dom), bus);
578 }
579
580 static void pci_init_cmask(PCIDevice *dev)
581 {
582 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
583 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
584 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
585 dev->cmask[PCI_REVISION_ID] = 0xff;
586 dev->cmask[PCI_CLASS_PROG] = 0xff;
587 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
588 dev->cmask[PCI_HEADER_TYPE] = 0xff;
589 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
590 }
591
592 static void pci_init_wmask(PCIDevice *dev)
593 {
594 int config_size = pci_config_size(dev);
595
596 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
597 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
598 pci_set_word(dev->wmask + PCI_COMMAND,
599 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
600 PCI_COMMAND_INTX_DISABLE);
601 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
602 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
603 }
604
605 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
606 config_size - PCI_CONFIG_HEADER_SIZE);
607 }
608
609 static void pci_init_w1cmask(PCIDevice *dev)
610 {
611 /*
612 * Note: It's okay to set w1cmask even for readonly bits as
613 * long as their value is hardwired to 0.
614 */
615 pci_set_word(dev->w1cmask + PCI_STATUS,
616 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
617 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
618 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
619 }
620
621 static void pci_init_wmask_bridge(PCIDevice *d)
622 {
623 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
624 PCI_SEC_LETENCY_TIMER */
625 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
626
627 /* base and limit */
628 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
629 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
630 pci_set_word(d->wmask + PCI_MEMORY_BASE,
631 PCI_MEMORY_RANGE_MASK & 0xffff);
632 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
633 PCI_MEMORY_RANGE_MASK & 0xffff);
634 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
635 PCI_PREF_RANGE_MASK & 0xffff);
636 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
637 PCI_PREF_RANGE_MASK & 0xffff);
638
639 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
640 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
641
642 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
643 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
644 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
645 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
646 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
647 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
648 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
649 PCI_BRIDGE_CTL_PARITY |
650 PCI_BRIDGE_CTL_SERR |
651 PCI_BRIDGE_CTL_ISA |
652 PCI_BRIDGE_CTL_VGA |
653 PCI_BRIDGE_CTL_VGA_16BIT |
654 PCI_BRIDGE_CTL_MASTER_ABORT |
655 PCI_BRIDGE_CTL_BUS_RESET |
656 PCI_BRIDGE_CTL_FAST_BACK |
657 PCI_BRIDGE_CTL_DISCARD |
658 PCI_BRIDGE_CTL_SEC_DISCARD |
659 PCI_BRIDGE_CTL_DISCARD_SERR);
660 /* Below does not do anything as we never set this bit, put here for
661 * completeness. */
662 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
663 PCI_BRIDGE_CTL_DISCARD_STATUS);
664 }
665
666 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
667 {
668 uint8_t slot = PCI_SLOT(dev->devfn);
669 uint8_t func;
670
671 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
672 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
673 }
674
675 /*
676 * multifunction bit is interpreted in two ways as follows.
677 * - all functions must set the bit to 1.
678 * Example: Intel X53
679 * - function 0 must set the bit, but the rest function (> 0)
680 * is allowed to leave the bit to 0.
681 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
682 *
683 * So OS (at least Linux) checks the bit of only function 0,
684 * and doesn't see the bit of function > 0.
685 *
686 * The below check allows both interpretation.
687 */
688 if (PCI_FUNC(dev->devfn)) {
689 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
690 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
691 /* function 0 should set multifunction bit */
692 error_report("PCI: single function device can't be populated "
693 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
694 return -1;
695 }
696 return 0;
697 }
698
699 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
700 return 0;
701 }
702 /* function 0 indicates single function, so function > 0 must be NULL */
703 for (func = 1; func < PCI_FUNC_MAX; ++func) {
704 if (bus->devices[PCI_DEVFN(slot, func)]) {
705 error_report("PCI: %x.0 indicates single function, "
706 "but %x.%x is already populated.",
707 slot, slot, func);
708 return -1;
709 }
710 }
711 return 0;
712 }
713
714 static void pci_config_alloc(PCIDevice *pci_dev)
715 {
716 int config_size = pci_config_size(pci_dev);
717
718 pci_dev->config = g_malloc0(config_size);
719 pci_dev->cmask = g_malloc0(config_size);
720 pci_dev->wmask = g_malloc0(config_size);
721 pci_dev->w1cmask = g_malloc0(config_size);
722 pci_dev->used = g_malloc0(config_size);
723 }
724
725 static void pci_config_free(PCIDevice *pci_dev)
726 {
727 g_free(pci_dev->config);
728 g_free(pci_dev->cmask);
729 g_free(pci_dev->wmask);
730 g_free(pci_dev->w1cmask);
731 g_free(pci_dev->used);
732 }
733
734 /* -1 for devfn means auto assign */
735 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
736 const char *name, int devfn,
737 const PCIDeviceInfo *info)
738 {
739 PCIConfigReadFunc *config_read = info->config_read;
740 PCIConfigWriteFunc *config_write = info->config_write;
741
742 if (devfn < 0) {
743 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
744 devfn += PCI_FUNC_MAX) {
745 if (!bus->devices[devfn])
746 goto found;
747 }
748 error_report("PCI: no slot/function available for %s, all in use", name);
749 return NULL;
750 found: ;
751 } else if (bus->devices[devfn]) {
752 error_report("PCI: slot %d function %d not available for %s, in use by %s",
753 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
754 return NULL;
755 }
756 pci_dev->bus = bus;
757 pci_dev->devfn = devfn;
758 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
759 pci_dev->irq_state = 0;
760 pci_config_alloc(pci_dev);
761
762 pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
763 pci_config_set_device_id(pci_dev->config, info->device_id);
764 pci_config_set_revision(pci_dev->config, info->revision);
765 pci_config_set_class(pci_dev->config, info->class_id);
766
767 if (!info->is_bridge) {
768 if (info->subsystem_vendor_id || info->subsystem_id) {
769 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
770 info->subsystem_vendor_id);
771 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
772 info->subsystem_id);
773 } else {
774 pci_set_default_subsystem_id(pci_dev);
775 }
776 } else {
777 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
778 assert(!info->subsystem_vendor_id);
779 assert(!info->subsystem_id);
780 }
781 pci_init_cmask(pci_dev);
782 pci_init_wmask(pci_dev);
783 pci_init_w1cmask(pci_dev);
784 if (info->is_bridge) {
785 pci_init_wmask_bridge(pci_dev);
786 }
787 if (pci_init_multifunction(bus, pci_dev)) {
788 pci_config_free(pci_dev);
789 return NULL;
790 }
791
792 if (!config_read)
793 config_read = pci_default_read_config;
794 if (!config_write)
795 config_write = pci_default_write_config;
796 pci_dev->config_read = config_read;
797 pci_dev->config_write = config_write;
798 bus->devices[devfn] = pci_dev;
799 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
800 pci_dev->version_id = 2; /* Current pci device vmstate version */
801 return pci_dev;
802 }
803
804 static void do_pci_unregister_device(PCIDevice *pci_dev)
805 {
806 qemu_free_irqs(pci_dev->irq);
807 pci_dev->bus->devices[pci_dev->devfn] = NULL;
808 pci_config_free(pci_dev);
809 }
810
811 /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
812 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
813 int instance_size, int devfn,
814 PCIConfigReadFunc *config_read,
815 PCIConfigWriteFunc *config_write)
816 {
817 PCIDevice *pci_dev;
818 PCIDeviceInfo info = {
819 .config_read = config_read,
820 .config_write = config_write,
821 };
822
823 pci_dev = g_malloc0(instance_size);
824 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info);
825 if (pci_dev == NULL) {
826 hw_error("PCI: can't register device\n");
827 }
828 return pci_dev;
829 }
830
831 static void pci_unregister_io_regions(PCIDevice *pci_dev)
832 {
833 PCIIORegion *r;
834 int i;
835
836 for(i = 0; i < PCI_NUM_REGIONS; i++) {
837 r = &pci_dev->io_regions[i];
838 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
839 continue;
840 memory_region_del_subregion(r->address_space, r->memory);
841 }
842 }
843
844 static int pci_unregister_device(DeviceState *dev)
845 {
846 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
847 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
848 int ret = 0;
849
850 if (info->exit)
851 ret = info->exit(pci_dev);
852 if (ret)
853 return ret;
854
855 pci_unregister_io_regions(pci_dev);
856 pci_del_option_rom(pci_dev);
857 g_free(pci_dev->romfile);
858 do_pci_unregister_device(pci_dev);
859 return 0;
860 }
861
862 void pci_register_bar(PCIDevice *pci_dev, int region_num,
863 uint8_t type, MemoryRegion *memory)
864 {
865 PCIIORegion *r;
866 uint32_t addr;
867 uint64_t wmask;
868 pcibus_t size = memory_region_size(memory);
869
870 assert(region_num >= 0);
871 assert(region_num < PCI_NUM_REGIONS);
872 if (size & (size-1)) {
873 fprintf(stderr, "ERROR: PCI region size must be pow2 "
874 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
875 exit(1);
876 }
877
878 r = &pci_dev->io_regions[region_num];
879 r->addr = PCI_BAR_UNMAPPED;
880 r->size = size;
881 r->type = type;
882 r->memory = NULL;
883
884 wmask = ~(size - 1);
885 addr = pci_bar(pci_dev, region_num);
886 if (region_num == PCI_ROM_SLOT) {
887 /* ROM enable bit is writable */
888 wmask |= PCI_ROM_ADDRESS_ENABLE;
889 }
890 pci_set_long(pci_dev->config + addr, type);
891 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
892 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
893 pci_set_quad(pci_dev->wmask + addr, wmask);
894 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
895 } else {
896 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
897 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
898 }
899 pci_dev->io_regions[region_num].memory = memory;
900 pci_dev->io_regions[region_num].address_space
901 = type & PCI_BASE_ADDRESS_SPACE_IO
902 ? pci_dev->bus->address_space_io
903 : pci_dev->bus->address_space_mem;
904 }
905
906 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
907 {
908 return pci_dev->io_regions[region_num].addr;
909 }
910
911 static pcibus_t pci_bar_address(PCIDevice *d,
912 int reg, uint8_t type, pcibus_t size)
913 {
914 pcibus_t new_addr, last_addr;
915 int bar = pci_bar(d, reg);
916 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
917
918 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
919 if (!(cmd & PCI_COMMAND_IO)) {
920 return PCI_BAR_UNMAPPED;
921 }
922 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
923 last_addr = new_addr + size - 1;
924 /* NOTE: we have only 64K ioports on PC */
925 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
926 return PCI_BAR_UNMAPPED;
927 }
928 return new_addr;
929 }
930
931 if (!(cmd & PCI_COMMAND_MEMORY)) {
932 return PCI_BAR_UNMAPPED;
933 }
934 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
935 new_addr = pci_get_quad(d->config + bar);
936 } else {
937 new_addr = pci_get_long(d->config + bar);
938 }
939 /* the ROM slot has a specific enable bit */
940 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
941 return PCI_BAR_UNMAPPED;
942 }
943 new_addr &= ~(size - 1);
944 last_addr = new_addr + size - 1;
945 /* NOTE: we do not support wrapping */
946 /* XXX: as we cannot support really dynamic
947 mappings, we handle specific values as invalid
948 mappings. */
949 if (last_addr <= new_addr || new_addr == 0 ||
950 last_addr == PCI_BAR_UNMAPPED) {
951 return PCI_BAR_UNMAPPED;
952 }
953
954 /* Now pcibus_t is 64bit.
955 * Check if 32 bit BAR wraps around explicitly.
956 * Without this, PC ide doesn't work well.
957 * TODO: remove this work around.
958 */
959 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
960 return PCI_BAR_UNMAPPED;
961 }
962
963 /*
964 * OS is allowed to set BAR beyond its addressable
965 * bits. For example, 32 bit OS can set 64bit bar
966 * to >4G. Check it. TODO: we might need to support
967 * it in the future for e.g. PAE.
968 */
969 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
970 return PCI_BAR_UNMAPPED;
971 }
972
973 return new_addr;
974 }
975
976 static void pci_update_mappings(PCIDevice *d)
977 {
978 PCIIORegion *r;
979 int i;
980 pcibus_t new_addr;
981
982 for(i = 0; i < PCI_NUM_REGIONS; i++) {
983 r = &d->io_regions[i];
984
985 /* this region isn't registered */
986 if (!r->size)
987 continue;
988
989 new_addr = pci_bar_address(d, i, r->type, r->size);
990
991 /* This bar isn't changed */
992 if (new_addr == r->addr)
993 continue;
994
995 /* now do the real mapping */
996 if (r->addr != PCI_BAR_UNMAPPED) {
997 memory_region_del_subregion(r->address_space, r->memory);
998 }
999 r->addr = new_addr;
1000 if (r->addr != PCI_BAR_UNMAPPED) {
1001 memory_region_add_subregion_overlap(r->address_space,
1002 r->addr, r->memory, 1);
1003 }
1004 }
1005 }
1006
1007 static inline int pci_irq_disabled(PCIDevice *d)
1008 {
1009 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1010 }
1011
1012 /* Called after interrupt disabled field update in config space,
1013 * assert/deassert interrupts if necessary.
1014 * Gets original interrupt disable bit value (before update). */
1015 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1016 {
1017 int i, disabled = pci_irq_disabled(d);
1018 if (disabled == was_irq_disabled)
1019 return;
1020 for (i = 0; i < PCI_NUM_PINS; ++i) {
1021 int state = pci_irq_state(d, i);
1022 pci_change_irq_level(d, i, disabled ? -state : state);
1023 }
1024 }
1025
1026 uint32_t pci_default_read_config(PCIDevice *d,
1027 uint32_t address, int len)
1028 {
1029 uint32_t val = 0;
1030
1031 memcpy(&val, d->config + address, len);
1032 return le32_to_cpu(val);
1033 }
1034
1035 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1036 {
1037 int i, was_irq_disabled = pci_irq_disabled(d);
1038
1039 for (i = 0; i < l; val >>= 8, ++i) {
1040 uint8_t wmask = d->wmask[addr + i];
1041 uint8_t w1cmask = d->w1cmask[addr + i];
1042 assert(!(wmask & w1cmask));
1043 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1044 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1045 }
1046 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1047 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1048 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1049 range_covers_byte(addr, l, PCI_COMMAND))
1050 pci_update_mappings(d);
1051
1052 if (range_covers_byte(addr, l, PCI_COMMAND))
1053 pci_update_irq_disabled(d, was_irq_disabled);
1054 }
1055
1056 /***********************************************************/
1057 /* generic PCI irq support */
1058
1059 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1060 static void pci_set_irq(void *opaque, int irq_num, int level)
1061 {
1062 PCIDevice *pci_dev = opaque;
1063 int change;
1064
1065 change = level - pci_irq_state(pci_dev, irq_num);
1066 if (!change)
1067 return;
1068
1069 pci_set_irq_state(pci_dev, irq_num, level);
1070 pci_update_irq_status(pci_dev);
1071 if (pci_irq_disabled(pci_dev))
1072 return;
1073 pci_change_irq_level(pci_dev, irq_num, change);
1074 }
1075
1076 /***********************************************************/
1077 /* monitor info on PCI */
1078
1079 typedef struct {
1080 uint16_t class;
1081 const char *desc;
1082 const char *fw_name;
1083 uint16_t fw_ign_bits;
1084 } pci_class_desc;
1085
1086 static const pci_class_desc pci_class_descriptions[] =
1087 {
1088 { 0x0001, "VGA controller", "display"},
1089 { 0x0100, "SCSI controller", "scsi"},
1090 { 0x0101, "IDE controller", "ide"},
1091 { 0x0102, "Floppy controller", "fdc"},
1092 { 0x0103, "IPI controller", "ipi"},
1093 { 0x0104, "RAID controller", "raid"},
1094 { 0x0106, "SATA controller"},
1095 { 0x0107, "SAS controller"},
1096 { 0x0180, "Storage controller"},
1097 { 0x0200, "Ethernet controller", "ethernet"},
1098 { 0x0201, "Token Ring controller", "token-ring"},
1099 { 0x0202, "FDDI controller", "fddi"},
1100 { 0x0203, "ATM controller", "atm"},
1101 { 0x0280, "Network controller"},
1102 { 0x0300, "VGA controller", "display", 0x00ff},
1103 { 0x0301, "XGA controller"},
1104 { 0x0302, "3D controller"},
1105 { 0x0380, "Display controller"},
1106 { 0x0400, "Video controller", "video"},
1107 { 0x0401, "Audio controller", "sound"},
1108 { 0x0402, "Phone"},
1109 { 0x0403, "Audio controller", "sound"},
1110 { 0x0480, "Multimedia controller"},
1111 { 0x0500, "RAM controller", "memory"},
1112 { 0x0501, "Flash controller", "flash"},
1113 { 0x0580, "Memory controller"},
1114 { 0x0600, "Host bridge", "host"},
1115 { 0x0601, "ISA bridge", "isa"},
1116 { 0x0602, "EISA bridge", "eisa"},
1117 { 0x0603, "MC bridge", "mca"},
1118 { 0x0604, "PCI bridge", "pci"},
1119 { 0x0605, "PCMCIA bridge", "pcmcia"},
1120 { 0x0606, "NUBUS bridge", "nubus"},
1121 { 0x0607, "CARDBUS bridge", "cardbus"},
1122 { 0x0608, "RACEWAY bridge"},
1123 { 0x0680, "Bridge"},
1124 { 0x0700, "Serial port", "serial"},
1125 { 0x0701, "Parallel port", "parallel"},
1126 { 0x0800, "Interrupt controller", "interrupt-controller"},
1127 { 0x0801, "DMA controller", "dma-controller"},
1128 { 0x0802, "Timer", "timer"},
1129 { 0x0803, "RTC", "rtc"},
1130 { 0x0900, "Keyboard", "keyboard"},
1131 { 0x0901, "Pen", "pen"},
1132 { 0x0902, "Mouse", "mouse"},
1133 { 0x0A00, "Dock station", "dock", 0x00ff},
1134 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1135 { 0x0c00, "Fireware contorller", "fireware"},
1136 { 0x0c01, "Access bus controller", "access-bus"},
1137 { 0x0c02, "SSA controller", "ssa"},
1138 { 0x0c03, "USB controller", "usb"},
1139 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1140 { 0, NULL}
1141 };
1142
1143 static void pci_for_each_device_under_bus(PCIBus *bus,
1144 void (*fn)(PCIBus *b, PCIDevice *d))
1145 {
1146 PCIDevice *d;
1147 int devfn;
1148
1149 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1150 d = bus->devices[devfn];
1151 if (d) {
1152 fn(bus, d);
1153 }
1154 }
1155 }
1156
1157 void pci_for_each_device(PCIBus *bus, int bus_num,
1158 void (*fn)(PCIBus *b, PCIDevice *d))
1159 {
1160 bus = pci_find_bus(bus, bus_num);
1161
1162 if (bus) {
1163 pci_for_each_device_under_bus(bus, fn);
1164 }
1165 }
1166
1167 static void pci_device_print(Monitor *mon, QDict *device)
1168 {
1169 QDict *qdict;
1170 QListEntry *entry;
1171 uint64_t addr, size;
1172
1173 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1174 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1175 qdict_get_int(device, "slot"),
1176 qdict_get_int(device, "function"));
1177 monitor_printf(mon, " ");
1178
1179 qdict = qdict_get_qdict(device, "class_info");
1180 if (qdict_haskey(qdict, "desc")) {
1181 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1182 } else {
1183 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1184 }
1185
1186 qdict = qdict_get_qdict(device, "id");
1187 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1188 qdict_get_int(qdict, "device"),
1189 qdict_get_int(qdict, "vendor"));
1190
1191 if (qdict_haskey(device, "irq")) {
1192 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1193 qdict_get_int(device, "irq"));
1194 }
1195
1196 if (qdict_haskey(device, "pci_bridge")) {
1197 QDict *info;
1198
1199 qdict = qdict_get_qdict(device, "pci_bridge");
1200
1201 info = qdict_get_qdict(qdict, "bus");
1202 monitor_printf(mon, " BUS %" PRId64 ".\n",
1203 qdict_get_int(info, "number"));
1204 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1205 qdict_get_int(info, "secondary"));
1206 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1207 qdict_get_int(info, "subordinate"));
1208
1209 info = qdict_get_qdict(qdict, "io_range");
1210 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1211 qdict_get_int(info, "base"),
1212 qdict_get_int(info, "limit"));
1213
1214 info = qdict_get_qdict(qdict, "memory_range");
1215 monitor_printf(mon,
1216 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1217 qdict_get_int(info, "base"),
1218 qdict_get_int(info, "limit"));
1219
1220 info = qdict_get_qdict(qdict, "prefetchable_range");
1221 monitor_printf(mon, " prefetchable memory range "
1222 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1223 qdict_get_int(info, "base"),
1224 qdict_get_int(info, "limit"));
1225 }
1226
1227 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1228 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1229 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1230
1231 addr = qdict_get_int(qdict, "address");
1232 size = qdict_get_int(qdict, "size");
1233
1234 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1235 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1236 " [0x%04"FMT_PCIBUS"].\n",
1237 addr, addr + size - 1);
1238 } else {
1239 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1240 " [0x%08"FMT_PCIBUS"].\n",
1241 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1242 qdict_get_bool(qdict, "prefetch") ?
1243 " prefetchable" : "", addr, addr + size - 1);
1244 }
1245 }
1246
1247 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1248
1249 if (qdict_haskey(device, "pci_bridge")) {
1250 qdict = qdict_get_qdict(device, "pci_bridge");
1251 if (qdict_haskey(qdict, "devices")) {
1252 QListEntry *dev;
1253 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1254 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1255 }
1256 }
1257 }
1258 }
1259
1260 void do_pci_info_print(Monitor *mon, const QObject *data)
1261 {
1262 QListEntry *bus, *dev;
1263
1264 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1265 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1266 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1267 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1268 }
1269 }
1270 }
1271
1272 static QObject *pci_get_dev_class(const PCIDevice *dev)
1273 {
1274 int class;
1275 const pci_class_desc *desc;
1276
1277 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1278 desc = pci_class_descriptions;
1279 while (desc->desc && class != desc->class)
1280 desc++;
1281
1282 if (desc->desc) {
1283 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1284 desc->desc, class);
1285 } else {
1286 return qobject_from_jsonf("{ 'class': %d }", class);
1287 }
1288 }
1289
1290 static QObject *pci_get_dev_id(const PCIDevice *dev)
1291 {
1292 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1293 pci_get_word(dev->config + PCI_VENDOR_ID),
1294 pci_get_word(dev->config + PCI_DEVICE_ID));
1295 }
1296
1297 static QObject *pci_get_regions_list(const PCIDevice *dev)
1298 {
1299 int i;
1300 QList *regions_list;
1301
1302 regions_list = qlist_new();
1303
1304 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1305 QObject *obj;
1306 const PCIIORegion *r = &dev->io_regions[i];
1307
1308 if (!r->size) {
1309 continue;
1310 }
1311
1312 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1313 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1314 "'address': %" PRId64 ", "
1315 "'size': %" PRId64 " }",
1316 i, r->addr, r->size);
1317 } else {
1318 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1319
1320 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1321 "'mem_type_64': %i, 'prefetch': %i, "
1322 "'address': %" PRId64 ", "
1323 "'size': %" PRId64 " }",
1324 i, mem_type_64,
1325 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1326 r->addr, r->size);
1327 }
1328
1329 qlist_append_obj(regions_list, obj);
1330 }
1331
1332 return QOBJECT(regions_list);
1333 }
1334
1335 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1336
1337 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1338 {
1339 uint8_t type;
1340 QObject *obj;
1341
1342 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1343 " 'qdev_id': %s }",
1344 bus_num,
1345 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1346 pci_get_dev_class(dev), pci_get_dev_id(dev),
1347 pci_get_regions_list(dev),
1348 dev->qdev.id ? dev->qdev.id : "");
1349
1350 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1351 QDict *qdict = qobject_to_qdict(obj);
1352 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1353 }
1354
1355 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1356 if (type == PCI_HEADER_TYPE_BRIDGE) {
1357 QDict *qdict;
1358 QObject *pci_bridge;
1359
1360 pci_bridge = qobject_from_jsonf("{ 'bus': "
1361 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1362 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1363 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1364 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1365 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1366 dev->config[PCI_SUBORDINATE_BUS],
1367 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1368 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1369 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1370 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1371 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1372 PCI_BASE_ADDRESS_MEM_PREFETCH),
1373 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1374 PCI_BASE_ADDRESS_MEM_PREFETCH));
1375
1376 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1377 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1378
1379 if (child_bus) {
1380 qdict = qobject_to_qdict(pci_bridge);
1381 qdict_put_obj(qdict, "devices",
1382 pci_get_devices_list(child_bus,
1383 dev->config[PCI_SECONDARY_BUS]));
1384 }
1385 }
1386 qdict = qobject_to_qdict(obj);
1387 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1388 }
1389
1390 return obj;
1391 }
1392
1393 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1394 {
1395 int devfn;
1396 PCIDevice *dev;
1397 QList *dev_list;
1398
1399 dev_list = qlist_new();
1400
1401 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1402 dev = bus->devices[devfn];
1403 if (dev) {
1404 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1405 }
1406 }
1407
1408 return QOBJECT(dev_list);
1409 }
1410
1411 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1412 {
1413 bus = pci_find_bus(bus, bus_num);
1414 if (bus) {
1415 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1416 bus_num, pci_get_devices_list(bus, bus_num));
1417 }
1418
1419 return NULL;
1420 }
1421
1422 void do_pci_info(Monitor *mon, QObject **ret_data)
1423 {
1424 QList *bus_list;
1425 struct PCIHostBus *host;
1426
1427 bus_list = qlist_new();
1428
1429 QLIST_FOREACH(host, &host_buses, next) {
1430 QObject *obj = pci_get_bus_dict(host->bus, 0);
1431 if (obj) {
1432 qlist_append_obj(bus_list, obj);
1433 }
1434 }
1435
1436 *ret_data = QOBJECT(bus_list);
1437 }
1438
1439 static const char * const pci_nic_models[] = {
1440 "ne2k_pci",
1441 "i82551",
1442 "i82557b",
1443 "i82559er",
1444 "rtl8139",
1445 "e1000",
1446 "pcnet",
1447 "virtio",
1448 NULL
1449 };
1450
1451 static const char * const pci_nic_names[] = {
1452 "ne2k_pci",
1453 "i82551",
1454 "i82557b",
1455 "i82559er",
1456 "rtl8139",
1457 "e1000",
1458 "pcnet",
1459 "virtio-net-pci",
1460 NULL
1461 };
1462
1463 /* Initialize a PCI NIC. */
1464 /* FIXME callers should check for failure, but don't */
1465 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1466 const char *default_devaddr)
1467 {
1468 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1469 PCIBus *bus;
1470 int devfn;
1471 PCIDevice *pci_dev;
1472 DeviceState *dev;
1473 int i;
1474
1475 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1476 if (i < 0)
1477 return NULL;
1478
1479 bus = pci_get_bus_devfn(&devfn, devaddr);
1480 if (!bus) {
1481 error_report("Invalid PCI device address %s for device %s",
1482 devaddr, pci_nic_names[i]);
1483 return NULL;
1484 }
1485
1486 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1487 dev = &pci_dev->qdev;
1488 qdev_set_nic_properties(dev, nd);
1489 if (qdev_init(dev) < 0)
1490 return NULL;
1491 return pci_dev;
1492 }
1493
1494 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1495 const char *default_devaddr)
1496 {
1497 PCIDevice *res;
1498
1499 if (qemu_show_nic_models(nd->model, pci_nic_models))
1500 exit(0);
1501
1502 res = pci_nic_init(nd, default_model, default_devaddr);
1503 if (!res)
1504 exit(1);
1505 return res;
1506 }
1507
1508 /* Whether a given bus number is in range of the secondary
1509 * bus of the given bridge device. */
1510 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1511 {
1512 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1513 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1514 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1515 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1516 }
1517
1518 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1519 {
1520 PCIBus *sec;
1521
1522 if (!bus) {
1523 return NULL;
1524 }
1525
1526 if (pci_bus_num(bus) == bus_num) {
1527 return bus;
1528 }
1529
1530 /* Consider all bus numbers in range for the host pci bridge. */
1531 if (bus->parent_dev &&
1532 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1533 return NULL;
1534 }
1535
1536 /* try child bus */
1537 for (; bus; bus = sec) {
1538 QLIST_FOREACH(sec, &bus->child, sibling) {
1539 assert(sec->parent_dev);
1540 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1541 return sec;
1542 }
1543 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1544 break;
1545 }
1546 }
1547 }
1548
1549 return NULL;
1550 }
1551
1552 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1553 {
1554 bus = pci_find_bus(bus, bus_num);
1555
1556 if (!bus)
1557 return NULL;
1558
1559 return bus->devices[devfn];
1560 }
1561
1562 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1563 {
1564 PCIDevice *pci_dev = (PCIDevice *)qdev;
1565 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1566 PCIBus *bus;
1567 int rc;
1568 bool is_default_rom;
1569
1570 /* initialize cap_present for pci_is_express() and pci_config_size() */
1571 if (info->is_express) {
1572 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1573 }
1574
1575 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1576 pci_dev = do_pci_register_device(pci_dev, bus, base->name,
1577 pci_dev->devfn, info);
1578 if (pci_dev == NULL)
1579 return -1;
1580 if (qdev->hotplugged && info->no_hotplug) {
1581 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1582 do_pci_unregister_device(pci_dev);
1583 return -1;
1584 }
1585 if (info->init) {
1586 rc = info->init(pci_dev);
1587 if (rc != 0) {
1588 do_pci_unregister_device(pci_dev);
1589 return rc;
1590 }
1591 }
1592
1593 /* rom loading */
1594 is_default_rom = false;
1595 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1596 pci_dev->romfile = g_strdup(info->romfile);
1597 is_default_rom = true;
1598 }
1599 pci_add_option_rom(pci_dev, is_default_rom);
1600
1601 if (bus->hotplug) {
1602 /* Let buses differentiate between hotplug and when device is
1603 * enabled during qemu machine creation. */
1604 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1605 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1606 PCI_COLDPLUG_ENABLED);
1607 if (rc != 0) {
1608 int r = pci_unregister_device(&pci_dev->qdev);
1609 assert(!r);
1610 return rc;
1611 }
1612 }
1613 return 0;
1614 }
1615
1616 static int pci_unplug_device(DeviceState *qdev)
1617 {
1618 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1619 PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
1620
1621 if (info->no_hotplug) {
1622 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1623 return -1;
1624 }
1625 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1626 PCI_HOTPLUG_DISABLED);
1627 }
1628
1629 void pci_qdev_register(PCIDeviceInfo *info)
1630 {
1631 info->qdev.init = pci_qdev_init;
1632 info->qdev.unplug = pci_unplug_device;
1633 info->qdev.exit = pci_unregister_device;
1634 info->qdev.bus_info = &pci_bus_info;
1635 qdev_register(&info->qdev);
1636 }
1637
1638 void pci_qdev_register_many(PCIDeviceInfo *info)
1639 {
1640 while (info->qdev.name) {
1641 pci_qdev_register(info);
1642 info++;
1643 }
1644 }
1645
1646 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1647 const char *name)
1648 {
1649 DeviceState *dev;
1650
1651 dev = qdev_create(&bus->qbus, name);
1652 qdev_prop_set_uint32(dev, "addr", devfn);
1653 qdev_prop_set_bit(dev, "multifunction", multifunction);
1654 return DO_UPCAST(PCIDevice, qdev, dev);
1655 }
1656
1657 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
1658 bool multifunction,
1659 const char *name)
1660 {
1661 DeviceState *dev;
1662
1663 dev = qdev_try_create(&bus->qbus, name);
1664 if (!dev) {
1665 return NULL;
1666 }
1667 qdev_prop_set_uint32(dev, "addr", devfn);
1668 qdev_prop_set_bit(dev, "multifunction", multifunction);
1669 return DO_UPCAST(PCIDevice, qdev, dev);
1670 }
1671
1672 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1673 bool multifunction,
1674 const char *name)
1675 {
1676 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1677 qdev_init_nofail(&dev->qdev);
1678 return dev;
1679 }
1680
1681 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1682 {
1683 return pci_create_multifunction(bus, devfn, false, name);
1684 }
1685
1686 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1687 {
1688 return pci_create_simple_multifunction(bus, devfn, false, name);
1689 }
1690
1691 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name)
1692 {
1693 return pci_try_create_multifunction(bus, devfn, false, name);
1694 }
1695
1696 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1697 {
1698 int config_size = pci_config_size(pdev);
1699 int offset = PCI_CONFIG_HEADER_SIZE;
1700 int i;
1701 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1702 if (pdev->used[i])
1703 offset = i + 1;
1704 else if (i - offset + 1 == size)
1705 return offset;
1706 return 0;
1707 }
1708
1709 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1710 uint8_t *prev_p)
1711 {
1712 uint8_t next, prev;
1713
1714 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1715 return 0;
1716
1717 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1718 prev = next + PCI_CAP_LIST_NEXT)
1719 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1720 break;
1721
1722 if (prev_p)
1723 *prev_p = prev;
1724 return next;
1725 }
1726
1727 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1728 {
1729 uint8_t next, prev, found = 0;
1730
1731 if (!(pdev->used[offset])) {
1732 return 0;
1733 }
1734
1735 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1736
1737 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1738 prev = next + PCI_CAP_LIST_NEXT) {
1739 if (next <= offset && next > found) {
1740 found = next;
1741 }
1742 }
1743 return found;
1744 }
1745
1746 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1747 This is needed for an option rom which is used for more than one device. */
1748 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1749 {
1750 uint16_t vendor_id;
1751 uint16_t device_id;
1752 uint16_t rom_vendor_id;
1753 uint16_t rom_device_id;
1754 uint16_t rom_magic;
1755 uint16_t pcir_offset;
1756 uint8_t checksum;
1757
1758 /* Words in rom data are little endian (like in PCI configuration),
1759 so they can be read / written with pci_get_word / pci_set_word. */
1760
1761 /* Only a valid rom will be patched. */
1762 rom_magic = pci_get_word(ptr);
1763 if (rom_magic != 0xaa55) {
1764 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1765 return;
1766 }
1767 pcir_offset = pci_get_word(ptr + 0x18);
1768 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1769 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1770 return;
1771 }
1772
1773 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1774 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1775 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1776 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1777
1778 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1779 vendor_id, device_id, rom_vendor_id, rom_device_id);
1780
1781 checksum = ptr[6];
1782
1783 if (vendor_id != rom_vendor_id) {
1784 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1785 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1786 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1787 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1788 ptr[6] = checksum;
1789 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1790 }
1791
1792 if (device_id != rom_device_id) {
1793 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1794 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1795 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1796 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1797 ptr[6] = checksum;
1798 pci_set_word(ptr + pcir_offset + 6, device_id);
1799 }
1800 }
1801
1802 /* Add an option rom for the device */
1803 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1804 {
1805 int size;
1806 char *path;
1807 void *ptr;
1808 char name[32];
1809
1810 if (!pdev->romfile)
1811 return 0;
1812 if (strlen(pdev->romfile) == 0)
1813 return 0;
1814
1815 if (!pdev->rom_bar) {
1816 /*
1817 * Load rom via fw_cfg instead of creating a rom bar,
1818 * for 0.11 compatibility.
1819 */
1820 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1821 if (class == 0x0300) {
1822 rom_add_vga(pdev->romfile);
1823 } else {
1824 rom_add_option(pdev->romfile, -1);
1825 }
1826 return 0;
1827 }
1828
1829 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1830 if (path == NULL) {
1831 path = g_strdup(pdev->romfile);
1832 }
1833
1834 size = get_image_size(path);
1835 if (size < 0) {
1836 error_report("%s: failed to find romfile \"%s\"",
1837 __FUNCTION__, pdev->romfile);
1838 g_free(path);
1839 return -1;
1840 }
1841 if (size & (size - 1)) {
1842 size = 1 << qemu_fls(size);
1843 }
1844
1845 if (pdev->qdev.info->vmsd)
1846 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1847 else
1848 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1849 pdev->has_rom = true;
1850 memory_region_init_ram(&pdev->rom, &pdev->qdev, name, size);
1851 ptr = memory_region_get_ram_ptr(&pdev->rom);
1852 load_image(path, ptr);
1853 g_free(path);
1854
1855 if (is_default_rom) {
1856 /* Only the default rom images will be patched (if needed). */
1857 pci_patch_ids(pdev, ptr, size);
1858 }
1859
1860 qemu_put_ram_ptr(ptr);
1861
1862 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1863
1864 return 0;
1865 }
1866
1867 static void pci_del_option_rom(PCIDevice *pdev)
1868 {
1869 if (!pdev->has_rom)
1870 return;
1871
1872 memory_region_destroy(&pdev->rom);
1873 pdev->has_rom = false;
1874 }
1875
1876 /*
1877 * if !offset
1878 * Reserve space and add capability to the linked list in pci config space
1879 *
1880 * if offset = 0,
1881 * Find and reserve space and add capability to the linked list
1882 * in pci config space */
1883 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1884 uint8_t offset, uint8_t size)
1885 {
1886 uint8_t *config;
1887 int i, overlapping_cap;
1888
1889 if (!offset) {
1890 offset = pci_find_space(pdev, size);
1891 if (!offset) {
1892 return -ENOSPC;
1893 }
1894 } else {
1895 /* Verify that capabilities don't overlap. Note: device assignment
1896 * depends on this check to verify that the device is not broken.
1897 * Should never trigger for emulated devices, but it's helpful
1898 * for debugging these. */
1899 for (i = offset; i < offset + size; i++) {
1900 overlapping_cap = pci_find_capability_at_offset(pdev, i);
1901 if (overlapping_cap) {
1902 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x "
1903 "Attempt to add PCI capability %x at offset "
1904 "%x overlaps existing capability %x at offset %x\n",
1905 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus),
1906 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1907 cap_id, offset, overlapping_cap, i);
1908 return -EINVAL;
1909 }
1910 }
1911 }
1912
1913 config = pdev->config + offset;
1914 config[PCI_CAP_LIST_ID] = cap_id;
1915 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1916 pdev->config[PCI_CAPABILITY_LIST] = offset;
1917 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1918 memset(pdev->used + offset, 0xFF, size);
1919 /* Make capability read-only by default */
1920 memset(pdev->wmask + offset, 0, size);
1921 /* Check capability by default */
1922 memset(pdev->cmask + offset, 0xFF, size);
1923 return offset;
1924 }
1925
1926 /* Unlink capability from the pci config space. */
1927 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1928 {
1929 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1930 if (!offset)
1931 return;
1932 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1933 /* Make capability writable again */
1934 memset(pdev->wmask + offset, 0xff, size);
1935 memset(pdev->w1cmask + offset, 0, size);
1936 /* Clear cmask as device-specific registers can't be checked */
1937 memset(pdev->cmask + offset, 0, size);
1938 memset(pdev->used + offset, 0, size);
1939
1940 if (!pdev->config[PCI_CAPABILITY_LIST])
1941 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1942 }
1943
1944 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1945 {
1946 return pci_find_capability_list(pdev, cap_id, NULL);
1947 }
1948
1949 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1950 {
1951 PCIDevice *d = (PCIDevice *)dev;
1952 const pci_class_desc *desc;
1953 char ctxt[64];
1954 PCIIORegion *r;
1955 int i, class;
1956
1957 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1958 desc = pci_class_descriptions;
1959 while (desc->desc && class != desc->class)
1960 desc++;
1961 if (desc->desc) {
1962 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1963 } else {
1964 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1965 }
1966
1967 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1968 "pci id %04x:%04x (sub %04x:%04x)\n",
1969 indent, "", ctxt, pci_bus_num(d->bus),
1970 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1971 pci_get_word(d->config + PCI_VENDOR_ID),
1972 pci_get_word(d->config + PCI_DEVICE_ID),
1973 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1974 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1975 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1976 r = &d->io_regions[i];
1977 if (!r->size)
1978 continue;
1979 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1980 " [0x%"FMT_PCIBUS"]\n",
1981 indent, "",
1982 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1983 r->addr, r->addr + r->size - 1);
1984 }
1985 }
1986
1987 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
1988 {
1989 PCIDevice *d = (PCIDevice *)dev;
1990 const char *name = NULL;
1991 const pci_class_desc *desc = pci_class_descriptions;
1992 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1993
1994 while (desc->desc &&
1995 (class & ~desc->fw_ign_bits) !=
1996 (desc->class & ~desc->fw_ign_bits)) {
1997 desc++;
1998 }
1999
2000 if (desc->desc) {
2001 name = desc->fw_name;
2002 }
2003
2004 if (name) {
2005 pstrcpy(buf, len, name);
2006 } else {
2007 snprintf(buf, len, "pci%04x,%04x",
2008 pci_get_word(d->config + PCI_VENDOR_ID),
2009 pci_get_word(d->config + PCI_DEVICE_ID));
2010 }
2011
2012 return buf;
2013 }
2014
2015 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2016 {
2017 PCIDevice *d = (PCIDevice *)dev;
2018 char path[50], name[33];
2019 int off;
2020
2021 off = snprintf(path, sizeof(path), "%s@%x",
2022 pci_dev_fw_name(dev, name, sizeof name),
2023 PCI_SLOT(d->devfn));
2024 if (PCI_FUNC(d->devfn))
2025 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2026 return strdup(path);
2027 }
2028
2029 static char *pcibus_get_dev_path(DeviceState *dev)
2030 {
2031 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2032 PCIDevice *t;
2033 int slot_depth;
2034 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2035 * 00 is added here to make this format compatible with
2036 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2037 * Slot.Function list specifies the slot and function numbers for all
2038 * devices on the path from root to the specific device. */
2039 char domain[] = "DDDD:00";
2040 char slot[] = ":SS.F";
2041 int domain_len = sizeof domain - 1 /* For '\0' */;
2042 int slot_len = sizeof slot - 1 /* For '\0' */;
2043 int path_len;
2044 char *path, *p;
2045 int s;
2046
2047 /* Calculate # of slots on path between device and root. */;
2048 slot_depth = 0;
2049 for (t = d; t; t = t->bus->parent_dev) {
2050 ++slot_depth;
2051 }
2052
2053 path_len = domain_len + slot_len * slot_depth;
2054
2055 /* Allocate memory, fill in the terminating null byte. */
2056 path = g_malloc(path_len + 1 /* For '\0' */);
2057 path[path_len] = '\0';
2058
2059 /* First field is the domain. */
2060 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
2061 assert(s == domain_len);
2062 memcpy(path, domain, domain_len);
2063
2064 /* Fill in slot numbers. We walk up from device to root, so need to print
2065 * them in the reverse order, last to first. */
2066 p = path + path_len;
2067 for (t = d; t; t = t->bus->parent_dev) {
2068 p -= slot_len;
2069 s = snprintf(slot, sizeof slot, ":%02x.%x",
2070 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2071 assert(s == slot_len);
2072 memcpy(p, slot, slot_len);
2073 }
2074
2075 return path;
2076 }
2077
2078 static int pci_qdev_find_recursive(PCIBus *bus,
2079 const char *id, PCIDevice **pdev)
2080 {
2081 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2082 if (!qdev) {
2083 return -ENODEV;
2084 }
2085
2086 /* roughly check if given qdev is pci device */
2087 if (qdev->info->init == &pci_qdev_init &&
2088 qdev->parent_bus->info == &pci_bus_info) {
2089 *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
2090 return 0;
2091 }
2092 return -EINVAL;
2093 }
2094
2095 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2096 {
2097 struct PCIHostBus *host;
2098 int rc = -ENODEV;
2099
2100 QLIST_FOREACH(host, &host_buses, next) {
2101 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2102 if (!tmp) {
2103 rc = 0;
2104 break;
2105 }
2106 if (tmp != -ENODEV) {
2107 rc = tmp;
2108 }
2109 }
2110
2111 return rc;
2112 }
2113
2114 MemoryRegion *pci_address_space(PCIDevice *dev)
2115 {
2116 return dev->bus->address_space_mem;
2117 }
2118
2119 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2120 {
2121 return dev->bus->address_space_io;
2122 }
CRIS target port of Qemu