target-i386/bpt_helper.c

   1 /*
   2  *  i386 breakpoint helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22
  23
  24 #ifndef CONFIG_USER_ONLY
  25 static void hw_breakpoint_insert(CPUX86State *env, int index)
  26 {
  27     CPUState *cs = CPU(x86_env_get_cpu(env));
  28     int type = 0, err = 0;
  29
  30     switch (hw_breakpoint_type(env->dr[7], index)) {
  31     case DR7_TYPE_BP_INST:
  32         if (hw_breakpoint_enabled(env->dr[7], index)) {
  33             err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU,
  34                                         &env->cpu_breakpoint[index]);
  35         }
  36         break;
  37     case DR7_TYPE_DATA_WR:
  38         type = BP_CPU | BP_MEM_WRITE;
  39         break;
  40     case DR7_TYPE_IO_RW:
  41         /* No support for I/O watchpoints yet */
  42         break;
  43     case DR7_TYPE_DATA_RW:
  44         type = BP_CPU | BP_MEM_ACCESS;
  45         break;
  46     }
  47
  48     if (type != 0) {
  49         err = cpu_watchpoint_insert(cs, env->dr[index],
  50                                     hw_breakpoint_len(env->dr[7], index),
  51                                     type, &env->cpu_watchpoint[index]);
  52     }
  53
  54     if (err) {
  55         env->cpu_breakpoint[index] = NULL;
  56     }
  57 }
  58
  59 static void hw_breakpoint_remove(CPUX86State *env, int index)
  60 {
  61     CPUState *cs;
  62
  63     if (!env->cpu_breakpoint[index]) {
  64         return;
  65     }
  66     cs = CPU(x86_env_get_cpu(env));
  67     switch (hw_breakpoint_type(env->dr[7], index)) {
  68     case DR7_TYPE_BP_INST:
  69         if (hw_breakpoint_enabled(env->dr[7], index)) {
  70             cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
  71         }
  72         break;
  73     case DR7_TYPE_DATA_WR:
  74     case DR7_TYPE_DATA_RW:
  75         cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
  76         break;
  77     case DR7_TYPE_IO_RW:
  78         /* No support for I/O watchpoints yet */
  79         break;
  80     }
  81 }
  82
  83 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
  84 {
  85     target_ulong old_dr7 = env->dr[7];
  86     int i;
  87
  88     /* If nothing is changing except the global/local enable bits,
  89        then we can make the change more efficient.  */
  90     if (((old_dr7 ^ new_dr7) & ~0xff) == 0) {
  91         /* Fold the global and local enable bits together into the
  92            global fields, then xor to show which registers have
  93            changed collective enable state.  */
  94         int mod = ((old_dr7 | old_dr7 * 2) ^ (new_dr7 | new_dr7 * 2)) & 0xff;
  95
  96         for (i = 0; i < DR7_MAX_BP; i++) {
  97             if ((mod & (2 << i * 2)) && !hw_breakpoint_enabled(new_dr7, i)) {
  98                 hw_breakpoint_remove(env, i);
  99             }
 100         }
 101         env->dr[7] = new_dr7;
 102         for (i = 0; i < DR7_MAX_BP; i++) {
 103             if (mod & (2 << i * 2) && hw_breakpoint_enabled(new_dr7, i)) {
 104                 hw_breakpoint_insert(env, i);
 105             }
 106         }
 107     } else {
 108         for (i = 0; i < DR7_MAX_BP; i++) {
 109             hw_breakpoint_remove(env, i);
 110         }
 111         env->dr[7] = new_dr7;
 112         for (i = 0; i < DR7_MAX_BP; i++) {
 113             hw_breakpoint_insert(env, i);
 114         }
 115     }
 116 }
 117 #endif
 118
 119 static bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
 120 {
 121     target_ulong dr6;
 122     int reg;
 123     bool hit_enabled = false;
 124
 125     dr6 = env->dr[6] & ~0xf;
 126     for (reg = 0; reg < DR7_MAX_BP; reg++) {
 127         bool bp_match = false;
 128         bool wp_match = false;
 129
 130         switch (hw_breakpoint_type(env->dr[7], reg)) {
 131         case DR7_TYPE_BP_INST:
 132             if (env->dr[reg] == env->eip) {
 133                 bp_match = true;
 134             }
 135             break;
 136         case DR7_TYPE_DATA_WR:
 137         case DR7_TYPE_DATA_RW:
 138             if (env->cpu_watchpoint[reg] &&
 139                 env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT) {
 140                 wp_match = true;
 141             }
 142             break;
 143         case DR7_TYPE_IO_RW:
 144             break;
 145         }
 146         if (bp_match || wp_match) {
 147             dr6 |= 1 << reg;
 148             if (hw_breakpoint_enabled(env->dr[7], reg)) {
 149                 hit_enabled = true;
 150             }
 151         }
 152     }
 153
 154     if (hit_enabled || force_dr6_update) {
 155         env->dr[6] = dr6;
 156     }
 157
 158     return hit_enabled;
 159 }
 160
 161 void breakpoint_handler(CPUState *cs)
 162 {
 163     X86CPU *cpu = X86_CPU(cs);
 164     CPUX86State *env = &cpu->env;
 165     CPUBreakpoint *bp;
 166
 167     if (cs->watchpoint_hit) {
 168         if (cs->watchpoint_hit->flags & BP_CPU) {
 169             cs->watchpoint_hit = NULL;
 170             if (check_hw_breakpoints(env, false)) {
 171                 raise_exception(env, EXCP01_DB);
 172             } else {
 173                 cpu_resume_from_signal(cs, NULL);
 174             }
 175         }
 176     } else {
 177         QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
 178             if (bp->pc == env->eip) {
 179                 if (bp->flags & BP_CPU) {
 180                     check_hw_breakpoints(env, true);
 181                     raise_exception(env, EXCP01_DB);
 182                 }
 183                 break;
 184             }
 185         }
 186     }
 187 }
 188
 189 void helper_single_step(CPUX86State *env)
 190 {
 191 #ifndef CONFIG_USER_ONLY
 192     check_hw_breakpoints(env, true);
 193     env->dr[6] |= DR6_BS;
 194 #endif
 195     raise_exception(env, EXCP01_DB);
 196 }
 197
 198 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
 199 {
 200 #ifndef CONFIG_USER_ONLY
 201     if (reg < 4) {
 202         hw_breakpoint_remove(env, reg);
 203         env->dr[reg] = t0;
 204         hw_breakpoint_insert(env, reg);
 205     } else if (reg == 7) {
 206         cpu_x86_update_dr7(env, t0);
 207     } else {
 208         env->dr[reg] = t0;
 209     }
 210 #endif
 211 }