target-ppc/mem_helper.c

   1 /*
   2  *  PowerPC memory access emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23
  24 #include "helper_regs.h"
  25 #include "exec/cpu_ldst.h"
  26
  27 //#define DEBUG_OP
  28
  29 static inline bool needs_byteswap(const CPUPPCState *env)
  30 {
  31 #if defined(TARGET_WORDS_BIGENDIAN)
  32   return msr_le;
  33 #else
  34   return !msr_le;
  35 #endif
  36 }
  37
  38 /*****************************************************************************/
  39 /* Memory load and stores */
  40
  41 static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
  42                                     target_long arg)
  43 {
  44 #if defined(TARGET_PPC64)
  45     if (!msr_is_64bit(env, env->msr)) {
  46         return (uint32_t)(addr + arg);
  47     } else
  48 #endif
  49     {
  50         return addr + arg;
  51     }
  52 }
  53
  54 void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
  55 {
  56     for (; reg < 32; reg++) {
  57         if (needs_byteswap(env)) {
  58             env->gpr[reg] = bswap32(cpu_ldl_data(env, addr));
  59         } else {
  60             env->gpr[reg] = cpu_ldl_data(env, addr);
  61         }
  62         addr = addr_add(env, addr, 4);
  63     }
  64 }
  65
  66 void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
  67 {
  68     for (; reg < 32; reg++) {
  69         if (needs_byteswap(env)) {
  70             cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg]));
  71         } else {
  72             cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]);
  73         }
  74         addr = addr_add(env, addr, 4);
  75     }
  76 }
  77
  78 void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
  79 {
  80     int sh;
  81
  82     for (; nb > 3; nb -= 4) {
  83         env->gpr[reg] = cpu_ldl_data(env, addr);
  84         reg = (reg + 1) % 32;
  85         addr = addr_add(env, addr, 4);
  86     }
  87     if (unlikely(nb > 0)) {
  88         env->gpr[reg] = 0;
  89         for (sh = 24; nb > 0; nb--, sh -= 8) {
  90             env->gpr[reg] |= cpu_ldub_data(env, addr) << sh;
  91             addr = addr_add(env, addr, 1);
  92         }
  93     }
  94 }
  95 /* PPC32 specification says we must generate an exception if
  96  * rA is in the range of registers to be loaded.
  97  * In an other hand, IBM says this is valid, but rA won't be loaded.
  98  * For now, I'll follow the spec...
  99  */
 100 void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
 101                  uint32_t ra, uint32_t rb)
 102 {
 103     if (likely(xer_bc != 0)) {
 104         int num_used_regs = (xer_bc + 3) / 4;
 105         if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) ||
 106                      lsw_reg_in_range(reg, num_used_regs, rb))) {
 107             env->nip += 4;     /* Compensate the "nip - 4" from gen_lswx() */
 108             helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 109                                        POWERPC_EXCP_INVAL |
 110                                        POWERPC_EXCP_INVAL_LSWX);
 111         } else {
 112             helper_lsw(env, addr, xer_bc, reg);
 113         }
 114     }
 115 }
 116
 117 void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
 118                  uint32_t reg)
 119 {
 120     int sh;
 121
 122     for (; nb > 3; nb -= 4) {
 123         cpu_stl_data(env, addr, env->gpr[reg]);
 124         reg = (reg + 1) % 32;
 125         addr = addr_add(env, addr, 4);
 126     }
 127     if (unlikely(nb > 0)) {
 128         for (sh = 24; nb > 0; nb--, sh -= 8) {
 129             cpu_stb_data(env, addr, (env->gpr[reg] >> sh) & 0xFF);
 130             addr = addr_add(env, addr, 1);
 131         }
 132     }
 133 }
 134
 135 static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size)
 136 {
 137     int i;
 138
 139     addr &= ~(dcache_line_size - 1);
 140     for (i = 0; i < dcache_line_size; i += 4) {
 141         cpu_stl_data(env, addr + i, 0);
 142     }
 143     if (env->reserve_addr == addr) {
 144         env->reserve_addr = (target_ulong)-1ULL;
 145     }
 146 }
 147
 148 void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl)
 149 {
 150     int dcbz_size = env->dcache_line_size;
 151
 152 #if defined(TARGET_PPC64)
 153     if (!is_dcbzl &&
 154         (env->excp_model == POWERPC_EXCP_970) &&
 155         ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
 156         dcbz_size = 32;
 157     }
 158 #endif
 159
 160     /* XXX add e500mc support */
 161
 162     do_dcbz(env, addr, dcbz_size);
 163 }
 164
 165 void helper_icbi(CPUPPCState *env, target_ulong addr)
 166 {
 167     addr &= ~(env->dcache_line_size - 1);
 168     /* Invalidate one cache line :
 169      * PowerPC specification says this is to be treated like a load
 170      * (not a fetch) by the MMU. To be sure it will be so,
 171      * do the load "by hand".
 172      */
 173     cpu_ldl_data(env, addr);
 174 }
 175
 176 /* XXX: to be tested */
 177 target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
 178                           uint32_t ra, uint32_t rb)
 179 {
 180     int i, c, d;
 181
 182     d = 24;
 183     for (i = 0; i < xer_bc; i++) {
 184         c = cpu_ldub_data(env, addr);
 185         addr = addr_add(env, addr, 1);
 186         /* ra (if not 0) and rb are never modified */
 187         if (likely(reg != rb && (ra == 0 || reg != ra))) {
 188             env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
 189         }
 190         if (unlikely(c == xer_cmp)) {
 191             break;
 192         }
 193         if (likely(d != 0)) {
 194             d -= 8;
 195         } else {
 196             d = 24;
 197             reg++;
 198             reg = reg & 0x1F;
 199         }
 200     }
 201     return i;
 202 }
 203
 204 /*****************************************************************************/
 205 /* Altivec extension helpers */
 206 #if defined(HOST_WORDS_BIGENDIAN)
 207 #define HI_IDX 0
 208 #define LO_IDX 1
 209 #else
 210 #define HI_IDX 1
 211 #define LO_IDX 0
 212 #endif
 213
 214 /* We use msr_le to determine index ordering in a vector.  However,
 215    byteswapping is not simply controlled by msr_le.  We also need to take
 216    into account endianness of the target.  This is done for the little-endian
 217    PPC64 user-mode target. */
 218
 219 #define LVE(name, access, swap, element)                        \
 220     void helper_##name(CPUPPCState *env, ppc_avr_t *r,          \
 221                        target_ulong addr)                       \
 222     {                                                           \
 223         size_t n_elems = ARRAY_SIZE(r->element);                \
 224         int adjust = HI_IDX*(n_elems - 1);                      \
 225         int sh = sizeof(r->element[0]) >> 1;                    \
 226         int index = (addr & 0xf) >> sh;                         \
 227         if (msr_le) {                                           \
 228             index = n_elems - index - 1;                        \
 229         }                                                       \
 230                                                                 \
 231         if (needs_byteswap(env)) {                              \
 232             r->element[LO_IDX ? index : (adjust - index)] =     \
 233                 swap(access(env, addr));                        \
 234         } else {                                                \
 235             r->element[LO_IDX ? index : (adjust - index)] =     \
 236                 access(env, addr);                              \
 237         }                                                       \
 238     }
 239 #define I(x) (x)
 240 LVE(lvebx, cpu_ldub_data, I, u8)
 241 LVE(lvehx, cpu_lduw_data, bswap16, u16)
 242 LVE(lvewx, cpu_ldl_data, bswap32, u32)
 243 #undef I
 244 #undef LVE
 245
 246 #define STVE(name, access, swap, element)                               \
 247     void helper_##name(CPUPPCState *env, ppc_avr_t *r,                  \
 248                        target_ulong addr)                               \
 249     {                                                                   \
 250         size_t n_elems = ARRAY_SIZE(r->element);                        \
 251         int adjust = HI_IDX * (n_elems - 1);                            \
 252         int sh = sizeof(r->element[0]) >> 1;                            \
 253         int index = (addr & 0xf) >> sh;                                 \
 254         if (msr_le) {                                                   \
 255             index = n_elems - index - 1;                                \
 256         }                                                               \
 257                                                                         \
 258         if (needs_byteswap(env)) {                                      \
 259             access(env, addr, swap(r->element[LO_IDX ? index :          \
 260                                               (adjust - index)]));      \
 261         } else {                                                        \
 262             access(env, addr, r->element[LO_IDX ? index :               \
 263                                          (adjust - index)]);            \
 264         }                                                               \
 265     }
 266 #define I(x) (x)
 267 STVE(stvebx, cpu_stb_data, I, u8)
 268 STVE(stvehx, cpu_stw_data, bswap16, u16)
 269 STVE(stvewx, cpu_stl_data, bswap32, u32)
 270 #undef I
 271 #undef LVE
 272
 273 #undef HI_IDX
 274 #undef LO_IDX
 275
 276 void helper_tbegin(CPUPPCState *env)
 277 {
 278     /* As a degenerate implementation, always fail tbegin.  The reason
 279      * given is "Nesting overflow".  The "persistent" bit is set,
 280      * providing a hint to the error handler to not retry.  The TFIAR
 281      * captures the address of the failure, which is this tbegin
 282      * instruction.  Instruction execution will continue with the
 283      * next instruction in memory, which is precisely what we want.
 284      */
 285
 286     env->spr[SPR_TEXASR] =
 287         (1ULL << TEXASR_FAILURE_PERSISTENT) |
 288         (1ULL << TEXASR_NESTING_OVERFLOW) |
 289         (msr_hv << TEXASR_PRIVILEGE_HV) |
 290         (msr_pr << TEXASR_PRIVILEGE_PR) |
 291         (1ULL << TEXASR_FAILURE_SUMMARY) |
 292         (1ULL << TEXASR_TFIAR_EXACT);
 293     env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
 294     env->spr[SPR_TFHAR] = env->nip + 4;
 295     env->crf[0] = 0xB; /* 0b1010 = transaction failure */
 296 }