target-ppc/machine.c

   1 #include "qemu/osdep.h"
   2 #include "hw/hw.h"
   3 #include "hw/boards.h"
   4 #include "sysemu/kvm.h"
   5 #include "helper_regs.h"
   6 #include "mmu-hash64.h"
   7 #include "migration/cpu.h"
   8
   9 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
  10 {
  11     PowerPCCPU *cpu = opaque;
  12     CPUPPCState *env = &cpu->env;
  13     unsigned int i, j;
  14     target_ulong sdr1;
  15     uint32_t fpscr;
  16     target_ulong xer;
  17
  18     for (i = 0; i < 32; i++)
  19         qemu_get_betls(f, &env->gpr[i]);
  20 #if !defined(TARGET_PPC64)
  21     for (i = 0; i < 32; i++)
  22         qemu_get_betls(f, &env->gprh[i]);
  23 #endif
  24     qemu_get_betls(f, &env->lr);
  25     qemu_get_betls(f, &env->ctr);
  26     for (i = 0; i < 8; i++)
  27         qemu_get_be32s(f, &env->crf[i]);
  28     qemu_get_betls(f, &xer);
  29     cpu_write_xer(env, xer);
  30     qemu_get_betls(f, &env->reserve_addr);
  31     qemu_get_betls(f, &env->msr);
  32     for (i = 0; i < 4; i++)
  33         qemu_get_betls(f, &env->tgpr[i]);
  34     for (i = 0; i < 32; i++) {
  35         union {
  36             float64 d;
  37             uint64_t l;
  38         } u;
  39         u.l = qemu_get_be64(f);
  40         env->fpr[i] = u.d;
  41     }
  42     qemu_get_be32s(f, &fpscr);
  43     env->fpscr = fpscr;
  44     qemu_get_sbe32s(f, &env->access_type);
  45 #if defined(TARGET_PPC64)
  46     qemu_get_betls(f, &env->spr[SPR_ASR]);
  47     qemu_get_sbe32s(f, &env->slb_nr);
  48 #endif
  49     qemu_get_betls(f, &sdr1);
  50     for (i = 0; i < 32; i++)
  51         qemu_get_betls(f, &env->sr[i]);
  52     for (i = 0; i < 2; i++)
  53         for (j = 0; j < 8; j++)
  54             qemu_get_betls(f, &env->DBAT[i][j]);
  55     for (i = 0; i < 2; i++)
  56         for (j = 0; j < 8; j++)
  57             qemu_get_betls(f, &env->IBAT[i][j]);
  58     qemu_get_sbe32s(f, &env->nb_tlb);
  59     qemu_get_sbe32s(f, &env->tlb_per_way);
  60     qemu_get_sbe32s(f, &env->nb_ways);
  61     qemu_get_sbe32s(f, &env->last_way);
  62     qemu_get_sbe32s(f, &env->id_tlbs);
  63     qemu_get_sbe32s(f, &env->nb_pids);
  64     if (env->tlb.tlb6) {
  65         // XXX assumes 6xx
  66         for (i = 0; i < env->nb_tlb; i++) {
  67             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
  68             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
  69             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
  70         }
  71     }
  72     for (i = 0; i < 4; i++)
  73         qemu_get_betls(f, &env->pb[i]);
  74     for (i = 0; i < 1024; i++)
  75         qemu_get_betls(f, &env->spr[i]);
  76     if (!env->external_htab) {
  77         ppc_store_sdr1(env, sdr1);
  78     }
  79     qemu_get_be32s(f, &env->vscr);
  80     qemu_get_be64s(f, &env->spe_acc);
  81     qemu_get_be32s(f, &env->spe_fscr);
  82     qemu_get_betls(f, &env->msr_mask);
  83     qemu_get_be32s(f, &env->flags);
  84     qemu_get_sbe32s(f, &env->error_code);
  85     qemu_get_be32s(f, &env->pending_interrupts);
  86     qemu_get_be32s(f, &env->irq_input_state);
  87     for (i = 0; i < POWERPC_EXCP_NB; i++)
  88         qemu_get_betls(f, &env->excp_vectors[i]);
  89     qemu_get_betls(f, &env->excp_prefix);
  90     qemu_get_betls(f, &env->ivor_mask);
  91     qemu_get_betls(f, &env->ivpr_mask);
  92     qemu_get_betls(f, &env->hreset_vector);
  93     qemu_get_betls(f, &env->nip);
  94     qemu_get_betls(f, &env->hflags);
  95     qemu_get_betls(f, &env->hflags_nmsr);
  96     qemu_get_sbe32s(f, &env->mmu_idx);
  97     qemu_get_sbe32(f); /* Discard unused power_mode */
  98
  99     return 0;
 100 }
 101
 102 static int get_avr(QEMUFile *f, void *pv, size_t size)
 103 {
 104     ppc_avr_t *v = pv;
 105
 106     v->u64[0] = qemu_get_be64(f);
 107     v->u64[1] = qemu_get_be64(f);
 108
 109     return 0;
 110 }
 111
 112 static void put_avr(QEMUFile *f, void *pv, size_t size)
 113 {
 114     ppc_avr_t *v = pv;
 115
 116     qemu_put_be64(f, v->u64[0]);
 117     qemu_put_be64(f, v->u64[1]);
 118 }
 119
 120 static const VMStateInfo vmstate_info_avr = {
 121     .name = "avr",
 122     .get  = get_avr,
 123     .put  = put_avr,
 124 };
 125
 126 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
 127     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
 128
 129 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
 130     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
 131
 132 static void cpu_pre_save(void *opaque)
 133 {
 134     PowerPCCPU *cpu = opaque;
 135     CPUPPCState *env = &cpu->env;
 136     int i;
 137
 138     env->spr[SPR_LR] = env->lr;
 139     env->spr[SPR_CTR] = env->ctr;
 140     env->spr[SPR_XER] = cpu_read_xer(env);
 141 #if defined(TARGET_PPC64)
 142     env->spr[SPR_CFAR] = env->cfar;
 143 #endif
 144     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 145
 146     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 147         env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
 148         env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
 149         env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
 150         env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
 151     }
 152     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 153         env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
 154         env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
 155         env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
 156         env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
 157     }
 158 }
 159
 160 static int cpu_post_load(void *opaque, int version_id)
 161 {
 162     PowerPCCPU *cpu = opaque;
 163     CPUPPCState *env = &cpu->env;
 164     int i;
 165     target_ulong msr;
 166
 167     /*
 168      * We always ignore the source PVR. The user or management
 169      * software has to take care of running QEMU in a compatible mode.
 170      */
 171     env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 172     env->lr = env->spr[SPR_LR];
 173     env->ctr = env->spr[SPR_CTR];
 174     cpu_write_xer(env, env->spr[SPR_XER]);
 175 #if defined(TARGET_PPC64)
 176     env->cfar = env->spr[SPR_CFAR];
 177 #endif
 178     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 179
 180     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 181         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
 182         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
 183         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
 184         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
 185     }
 186     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 187         env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
 188         env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
 189         env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
 190         env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
 191     }
 192
 193     if (!env->external_htab) {
 194         /* Restore htab_base and htab_mask variables */
 195         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 196     }
 197
 198     /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
 199     msr = env->msr;
 200     env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
 201     ppc_store_msr(env, msr);
 202
 203     hreg_compute_mem_idx(env);
 204
 205     return 0;
 206 }
 207
 208 static bool fpu_needed(void *opaque)
 209 {
 210     PowerPCCPU *cpu = opaque;
 211
 212     return (cpu->env.insns_flags & PPC_FLOAT);
 213 }
 214
 215 static const VMStateDescription vmstate_fpu = {
 216     .name = "cpu/fpu",
 217     .version_id = 1,
 218     .minimum_version_id = 1,
 219     .needed = fpu_needed,
 220     .fields = (VMStateField[]) {
 221         VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
 222         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 223         VMSTATE_END_OF_LIST()
 224     },
 225 };
 226
 227 static bool altivec_needed(void *opaque)
 228 {
 229     PowerPCCPU *cpu = opaque;
 230
 231     return (cpu->env.insns_flags & PPC_ALTIVEC);
 232 }
 233
 234 static const VMStateDescription vmstate_altivec = {
 235     .name = "cpu/altivec",
 236     .version_id = 1,
 237     .minimum_version_id = 1,
 238     .needed = altivec_needed,
 239     .fields = (VMStateField[]) {
 240         VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
 241         VMSTATE_UINT32(env.vscr, PowerPCCPU),
 242         VMSTATE_END_OF_LIST()
 243     },
 244 };
 245
 246 static bool vsx_needed(void *opaque)
 247 {
 248     PowerPCCPU *cpu = opaque;
 249
 250     return (cpu->env.insns_flags2 & PPC2_VSX);
 251 }
 252
 253 static const VMStateDescription vmstate_vsx = {
 254     .name = "cpu/vsx",
 255     .version_id = 1,
 256     .minimum_version_id = 1,
 257     .needed = vsx_needed,
 258     .fields = (VMStateField[]) {
 259         VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
 260         VMSTATE_END_OF_LIST()
 261     },
 262 };
 263
 264 #ifdef TARGET_PPC64
 265 /* Transactional memory state */
 266 static bool tm_needed(void *opaque)
 267 {
 268     PowerPCCPU *cpu = opaque;
 269     CPUPPCState *env = &cpu->env;
 270     return msr_ts;
 271 }
 272
 273 static const VMStateDescription vmstate_tm = {
 274     .name = "cpu/tm",
 275     .version_id = 1,
 276     .minimum_version_id = 1,
 277     .minimum_version_id_old = 1,
 278     .needed = tm_needed,
 279     .fields      = (VMStateField []) {
 280         VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
 281         VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
 282         VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
 283         VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
 284         VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
 285         VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
 286         VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
 287         VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
 288         VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
 289         VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
 290         VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
 291         VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
 292         VMSTATE_END_OF_LIST()
 293     },
 294 };
 295 #endif
 296
 297 static bool sr_needed(void *opaque)
 298 {
 299 #ifdef TARGET_PPC64
 300     PowerPCCPU *cpu = opaque;
 301
 302     return !(cpu->env.mmu_model & POWERPC_MMU_64);
 303 #else
 304     return true;
 305 #endif
 306 }
 307
 308 static const VMStateDescription vmstate_sr = {
 309     .name = "cpu/sr",
 310     .version_id = 1,
 311     .minimum_version_id = 1,
 312     .needed = sr_needed,
 313     .fields = (VMStateField[]) {
 314         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 315         VMSTATE_END_OF_LIST()
 316     },
 317 };
 318
 319 #ifdef TARGET_PPC64
 320 static int get_slbe(QEMUFile *f, void *pv, size_t size)
 321 {
 322     ppc_slb_t *v = pv;
 323
 324     v->esid = qemu_get_be64(f);
 325     v->vsid = qemu_get_be64(f);
 326
 327     return 0;
 328 }
 329
 330 static void put_slbe(QEMUFile *f, void *pv, size_t size)
 331 {
 332     ppc_slb_t *v = pv;
 333
 334     qemu_put_be64(f, v->esid);
 335     qemu_put_be64(f, v->vsid);
 336 }
 337
 338 static const VMStateInfo vmstate_info_slbe = {
 339     .name = "slbe",
 340     .get  = get_slbe,
 341     .put  = put_slbe,
 342 };
 343
 344 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 345     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 346
 347 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 348     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 349
 350 static bool slb_needed(void *opaque)
 351 {
 352     PowerPCCPU *cpu = opaque;
 353
 354     /* We don't support any of the old segment table based 64-bit CPUs */
 355     return (cpu->env.mmu_model & POWERPC_MMU_64);
 356 }
 357
 358 static int slb_post_load(void *opaque, int version_id)
 359 {
 360     PowerPCCPU *cpu = opaque;
 361     CPUPPCState *env = &cpu->env;
 362     int i;
 363
 364     /* We've pulled in the raw esid and vsid values from the migration
 365      * stream, but we need to recompute the page size pointers */
 366     for (i = 0; i < env->slb_nr; i++) {
 367         if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
 368             /* Migration source had bad values in its SLB */
 369             return -1;
 370         }
 371     }
 372
 373     return 0;
 374 }
 375
 376 static const VMStateDescription vmstate_slb = {
 377     .name = "cpu/slb",
 378     .version_id = 1,
 379     .minimum_version_id = 1,
 380     .needed = slb_needed,
 381     .post_load = slb_post_load,
 382     .fields = (VMStateField[]) {
 383         VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
 384         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 385         VMSTATE_END_OF_LIST()
 386     }
 387 };
 388 #endif /* TARGET_PPC64 */
 389
 390 static const VMStateDescription vmstate_tlb6xx_entry = {
 391     .name = "cpu/tlb6xx_entry",
 392     .version_id = 1,
 393     .minimum_version_id = 1,
 394     .fields = (VMStateField[]) {
 395         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 396         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 397         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 398         VMSTATE_END_OF_LIST()
 399     },
 400 };
 401
 402 static bool tlb6xx_needed(void *opaque)
 403 {
 404     PowerPCCPU *cpu = opaque;
 405     CPUPPCState *env = &cpu->env;
 406
 407     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 408 }
 409
 410 static const VMStateDescription vmstate_tlb6xx = {
 411     .name = "cpu/tlb6xx",
 412     .version_id = 1,
 413     .minimum_version_id = 1,
 414     .needed = tlb6xx_needed,
 415     .fields = (VMStateField[]) {
 416         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 417         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 418                                             env.nb_tlb,
 419                                             vmstate_tlb6xx_entry,
 420                                             ppc6xx_tlb_t),
 421         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 422         VMSTATE_END_OF_LIST()
 423     }
 424 };
 425
 426 static const VMStateDescription vmstate_tlbemb_entry = {
 427     .name = "cpu/tlbemb_entry",
 428     .version_id = 1,
 429     .minimum_version_id = 1,
 430     .fields = (VMStateField[]) {
 431         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 432         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 433         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 434         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 435         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 436         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 437         VMSTATE_END_OF_LIST()
 438     },
 439 };
 440
 441 static bool tlbemb_needed(void *opaque)
 442 {
 443     PowerPCCPU *cpu = opaque;
 444     CPUPPCState *env = &cpu->env;
 445
 446     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 447 }
 448
 449 static bool pbr403_needed(void *opaque)
 450 {
 451     PowerPCCPU *cpu = opaque;
 452     uint32_t pvr = cpu->env.spr[SPR_PVR];
 453
 454     return (pvr & 0xffff0000) == 0x00200000;
 455 }
 456
 457 static const VMStateDescription vmstate_pbr403 = {
 458     .name = "cpu/pbr403",
 459     .version_id = 1,
 460     .minimum_version_id = 1,
 461     .needed = pbr403_needed,
 462     .fields = (VMStateField[]) {
 463         VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
 464         VMSTATE_END_OF_LIST()
 465     },
 466 };
 467
 468 static const VMStateDescription vmstate_tlbemb = {
 469     .name = "cpu/tlb6xx",
 470     .version_id = 1,
 471     .minimum_version_id = 1,
 472     .needed = tlbemb_needed,
 473     .fields = (VMStateField[]) {
 474         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 475         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 476                                             env.nb_tlb,
 477                                             vmstate_tlbemb_entry,
 478                                             ppcemb_tlb_t),
 479         /* 403 protection registers */
 480         VMSTATE_END_OF_LIST()
 481     },
 482     .subsections = (const VMStateDescription*[]) {
 483         &vmstate_pbr403,
 484         NULL
 485     }
 486 };
 487
 488 static const VMStateDescription vmstate_tlbmas_entry = {
 489     .name = "cpu/tlbmas_entry",
 490     .version_id = 1,
 491     .minimum_version_id = 1,
 492     .fields = (VMStateField[]) {
 493         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 494         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 495         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 496         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 497         VMSTATE_END_OF_LIST()
 498     },
 499 };
 500
 501 static bool tlbmas_needed(void *opaque)
 502 {
 503     PowerPCCPU *cpu = opaque;
 504     CPUPPCState *env = &cpu->env;
 505
 506     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 507 }
 508
 509 static const VMStateDescription vmstate_tlbmas = {
 510     .name = "cpu/tlbmas",
 511     .version_id = 1,
 512     .minimum_version_id = 1,
 513     .needed = tlbmas_needed,
 514     .fields = (VMStateField[]) {
 515         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 516         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 517                                             env.nb_tlb,
 518                                             vmstate_tlbmas_entry,
 519                                             ppcmas_tlb_t),
 520         VMSTATE_END_OF_LIST()
 521     }
 522 };
 523
 524 const VMStateDescription vmstate_ppc_cpu = {
 525     .name = "cpu",
 526     .version_id = 5,
 527     .minimum_version_id = 5,
 528     .minimum_version_id_old = 4,
 529     .load_state_old = cpu_load_old,
 530     .pre_save = cpu_pre_save,
 531     .post_load = cpu_post_load,
 532     .fields = (VMStateField[]) {
 533         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 534
 535         /* User mode architected state */
 536         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 537 #if !defined(TARGET_PPC64)
 538         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 539 #endif
 540         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 541         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 542
 543         /* SPRs */
 544         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 545         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 546
 547         /* Reservation */
 548         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 549
 550         /* Supervisor mode architected state */
 551         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 552
 553         /* Internal state */
 554         VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
 555         /* FIXME: access_type? */
 556
 557         /* Sanity checking */
 558         VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
 559         VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
 560         VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
 561         VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
 562         VMSTATE_END_OF_LIST()
 563     },
 564     .subsections = (const VMStateDescription*[]) {
 565         &vmstate_fpu,
 566         &vmstate_altivec,
 567         &vmstate_vsx,
 568         &vmstate_sr,
 569 #ifdef TARGET_PPC64
 570         &vmstate_tm,
 571         &vmstate_slb,
 572 #endif /* TARGET_PPC64 */
 573         &vmstate_tlb6xx,
 574         &vmstate_tlbemb,
 575         &vmstate_tlbmas,
 576         NULL
 577     }
 578 };