2 * LatticeMico32 virtual CPU header.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #define TARGET_LONG_BITS 32
25 #define CPUArchState struct CPULM32State
27 #include "qemu-common.h"
29 #include "exec/cpu-defs.h"
31 typedef struct CPULM32State CPULM32State
;
33 #define NB_MMU_MODES 1
34 #define TARGET_PAGE_BITS 12
35 static inline int cpu_mmu_index(CPULM32State
*env
, bool ifetch
)
40 #define TARGET_PHYS_ADDR_SPACE_BITS 32
41 #define TARGET_VIRT_ADDR_SPACE_BITS 32
43 /* Exceptions indices */
57 R_R0
= 0, R_R1
, R_R2
, R_R3
, R_R4
, R_R5
, R_R6
, R_R7
, R_R8
, R_R9
, R_R10
,
58 R_R11
, R_R12
, R_R13
, R_R14
, R_R15
, R_R16
, R_R17
, R_R18
, R_R19
, R_R20
,
59 R_R21
, R_R22
, R_R23
, R_R24
, R_R25
, R_R26
, R_R27
, R_R28
, R_R29
, R_R30
,
63 /* Register aliases */
135 LM32_FEATURE_MULTIPLY
= 1,
136 LM32_FEATURE_DIVIDE
= 2,
137 LM32_FEATURE_SHIFT
= 4,
138 LM32_FEATURE_SIGN_EXTEND
= 8,
139 LM32_FEATURE_I_CACHE
= 16,
140 LM32_FEATURE_D_CACHE
= 32,
141 LM32_FEATURE_CYCLE_COUNT
= 64,
145 LM32_FLAG_IGNORE_MSB
= 1,
148 struct CPULM32State
{
149 /* general registers */
152 /* special registers */
153 uint32_t pc
; /* program counter */
154 uint32_t ie
; /* interrupt enable */
155 uint32_t icc
; /* instruction cache control */
156 uint32_t dcc
; /* data cache control */
157 uint32_t cc
; /* cycle counter */
158 uint32_t cfg
; /* configuration */
160 /* debug registers */
161 uint32_t dc
; /* debug control */
162 uint32_t bp
[4]; /* breakpoints */
163 uint32_t wp
[4]; /* watchpoints */
165 struct CPUBreakpoint
*cpu_breakpoint
[4];
166 struct CPUWatchpoint
*cpu_watchpoint
[4];
170 /* Fields from here on are preserved across CPU reset. */
171 uint32_t eba
; /* exception base address */
172 uint32_t deba
; /* debug exception base address */
174 /* interrupt controller handle for callbacks */
175 DeviceState
*pic_state
;
176 /* JTAG UART handle for callbacks */
177 DeviceState
*juart_state
;
179 /* processor core features */
186 * @env: #CPULM32State
188 * A LatticeMico32 CPU.
198 uint8_t num_interrupts
;
199 uint8_t num_breakpoints
;
200 uint8_t num_watchpoints
;
204 static inline LM32CPU
*lm32_env_get_cpu(CPULM32State
*env
)
206 return container_of(env
, LM32CPU
, env
);
209 #define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e))
211 #define ENV_OFFSET offsetof(LM32CPU, env)
213 #ifndef CONFIG_USER_ONLY
214 extern const struct VMStateDescription vmstate_lm32_cpu
;
217 void lm32_cpu_do_interrupt(CPUState
*cpu
);
218 bool lm32_cpu_exec_interrupt(CPUState
*cs
, int int_req
);
219 void lm32_cpu_dump_state(CPUState
*cpu
, FILE *f
, fprintf_function cpu_fprintf
,
221 hwaddr
lm32_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
222 int lm32_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
223 int lm32_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
226 LM32_WP_DISABLED
= 0,
232 static inline lm32_wp_t
lm32_wp_type(uint32_t dc
, int idx
)
235 return (dc
>> (idx
+1)*2) & 0x3;
238 LM32CPU
*cpu_lm32_init(const char *cpu_model
);
239 int cpu_lm32_exec(CPUState
*cpu
);
240 /* you can call this signal handler from your SIGBUS and SIGSEGV
241 signal handlers to inform the virtual CPU of exceptions. non zero
242 is returned if the signal was handled by the virtual CPU. */
243 int cpu_lm32_signal_handler(int host_signum
, void *pinfo
,
245 void lm32_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
246 void lm32_translate_init(void);
247 void cpu_lm32_set_phys_msb_ignore(CPULM32State
*env
, int value
);
248 void QEMU_NORETURN
raise_exception(CPULM32State
*env
, int index
);
249 void lm32_debug_excp_handler(CPUState
*cs
);
250 void lm32_breakpoint_insert(CPULM32State
*env
, int index
, target_ulong address
);
251 void lm32_breakpoint_remove(CPULM32State
*env
, int index
);
252 void lm32_watchpoint_insert(CPULM32State
*env
, int index
, target_ulong address
,
254 void lm32_watchpoint_remove(CPULM32State
*env
, int index
);
255 bool lm32_cpu_do_semihosting(CPUState
*cs
);
257 #define cpu_init(cpu_model) CPU(cpu_lm32_init(cpu_model))
259 #define cpu_list lm32_cpu_list
260 #define cpu_exec cpu_lm32_exec
261 #define cpu_signal_handler cpu_lm32_signal_handler
263 int lm32_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
, int rw
,
266 #include "exec/cpu-all.h"
268 static inline void cpu_get_tb_cpu_state(CPULM32State
*env
, target_ulong
*pc
,
269 target_ulong
*cs_base
, uint32_t *flags
)
276 #include "exec/exec-all.h"