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Revert "pc: memhp: force gaps between DIMM's GPA"
[qemu/cris-port.git] / target-arm / helper.c
blob1966f9c04502cf1aae04c2823b343ea5f7720001
1 #include "cpu.h"
2 #include "internals.h"
3 #include "exec/gdbstub.h"
4 #include "exec/helper-proto.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include "exec/cpu_ldst.h"
11 #include "arm_ldst.h"
12 #include <zlib.h> /* For crc32 */
13 #include "exec/semihost.h"
14
15 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
16
17 #ifndef CONFIG_USER_ONLY
18 static bool get_phys_addr(CPUARMState *env, target_ulong address,
19 int access_type, ARMMMUIdx mmu_idx,
20 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
21 target_ulong *page_size, uint32_t *fsr,
22 ARMMMUFaultInfo *fi);
23
24 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
25 int access_type, ARMMMUIdx mmu_idx,
26 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
27 target_ulong *page_size_ptr, uint32_t *fsr,
28 ARMMMUFaultInfo *fi);
29
30 /* Definitions for the PMCCNTR and PMCR registers */
31 #define PMCRD 0x8
32 #define PMCRC 0x4
33 #define PMCRE 0x1
34 #endif
35
36 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
37 {
38 int nregs;
39
40 /* VFP data registers are always little-endian. */
41 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
42 if (reg < nregs) {
43 stfq_le_p(buf, env->vfp.regs[reg]);
44 return 8;
45 }
46 if (arm_feature(env, ARM_FEATURE_NEON)) {
47 /* Aliases for Q regs. */
48 nregs += 16;
49 if (reg < nregs) {
50 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
51 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
52 return 16;
53 }
54 }
55 switch (reg - nregs) {
56 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
57 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
58 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
59 }
60 return 0;
61 }
62
63 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
64 {
65 int nregs;
66
67 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
68 if (reg < nregs) {
69 env->vfp.regs[reg] = ldfq_le_p(buf);
70 return 8;
71 }
72 if (arm_feature(env, ARM_FEATURE_NEON)) {
73 nregs += 16;
74 if (reg < nregs) {
75 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
76 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
77 return 16;
78 }
79 }
80 switch (reg - nregs) {
81 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
82 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
83 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
84 }
85 return 0;
86 }
87
88 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
89 {
90 switch (reg) {
91 case 0 ... 31:
92 /* 128 bit FP register */
93 stfq_le_p(buf, env->vfp.regs[reg * 2]);
94 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
95 return 16;
96 case 32:
97 /* FPSR */
98 stl_p(buf, vfp_get_fpsr(env));
99 return 4;
100 case 33:
101 /* FPCR */
102 stl_p(buf, vfp_get_fpcr(env));
103 return 4;
104 default:
105 return 0;
106 }
107 }
108
109 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
110 {
111 switch (reg) {
112 case 0 ... 31:
113 /* 128 bit FP register */
114 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
115 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
116 return 16;
117 case 32:
118 /* FPSR */
119 vfp_set_fpsr(env, ldl_p(buf));
120 return 4;
121 case 33:
122 /* FPCR */
123 vfp_set_fpcr(env, ldl_p(buf));
124 return 4;
125 default:
126 return 0;
127 }
128 }
129
130 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
131 {
132 assert(ri->fieldoffset);
133 if (cpreg_field_is_64bit(ri)) {
134 return CPREG_FIELD64(env, ri);
135 } else {
136 return CPREG_FIELD32(env, ri);
137 }
138 }
139
140 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
141 uint64_t value)
142 {
143 assert(ri->fieldoffset);
144 if (cpreg_field_is_64bit(ri)) {
145 CPREG_FIELD64(env, ri) = value;
146 } else {
147 CPREG_FIELD32(env, ri) = value;
148 }
149 }
150
151 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
152 {
153 return (char *)env + ri->fieldoffset;
154 }
155
156 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
157 {
158 /* Raw read of a coprocessor register (as needed for migration, etc). */
159 if (ri->type & ARM_CP_CONST) {
160 return ri->resetvalue;
161 } else if (ri->raw_readfn) {
162 return ri->raw_readfn(env, ri);
163 } else if (ri->readfn) {
164 return ri->readfn(env, ri);
165 } else {
166 return raw_read(env, ri);
167 }
168 }
169
170 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
171 uint64_t v)
172 {
173 /* Raw write of a coprocessor register (as needed for migration, etc).
174 * Note that constant registers are treated as write-ignored; the
175 * caller should check for success by whether a readback gives the
176 * value written.
177 */
178 if (ri->type & ARM_CP_CONST) {
179 return;
180 } else if (ri->raw_writefn) {
181 ri->raw_writefn(env, ri, v);
182 } else if (ri->writefn) {
183 ri->writefn(env, ri, v);
184 } else {
185 raw_write(env, ri, v);
186 }
187 }
188
189 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
190 {
191 /* Return true if the regdef would cause an assertion if you called
192 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
193 * program bug for it not to have the NO_RAW flag).
194 * NB that returning false here doesn't necessarily mean that calling
195 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
196 * read/write access functions which are safe for raw use" from "has
197 * read/write access functions which have side effects but has forgotten
198 * to provide raw access functions".
199 * The tests here line up with the conditions in read/write_raw_cp_reg()
200 * and assertions in raw_read()/raw_write().
201 */
202 if ((ri->type & ARM_CP_CONST) ||
203 ri->fieldoffset ||
204 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
205 return false;
206 }
207 return true;
208 }
209
210 bool write_cpustate_to_list(ARMCPU *cpu)
211 {
212 /* Write the coprocessor state from cpu->env to the (index,value) list. */
213 int i;
214 bool ok = true;
215
216 for (i = 0; i < cpu->cpreg_array_len; i++) {
217 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
218 const ARMCPRegInfo *ri;
219
220 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
221 if (!ri) {
222 ok = false;
223 continue;
224 }
225 if (ri->type & ARM_CP_NO_RAW) {
226 continue;
227 }
228 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
229 }
230 return ok;
231 }
232
233 bool write_list_to_cpustate(ARMCPU *cpu)
234 {
235 int i;
236 bool ok = true;
237
238 for (i = 0; i < cpu->cpreg_array_len; i++) {
239 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
240 uint64_t v = cpu->cpreg_values[i];
241 const ARMCPRegInfo *ri;
242
243 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
244 if (!ri) {
245 ok = false;
246 continue;
247 }
248 if (ri->type & ARM_CP_NO_RAW) {
249 continue;
250 }
251 /* Write value and confirm it reads back as written
252 * (to catch read-only registers and partially read-only
253 * registers where the incoming migration value doesn't match)
254 */
255 write_raw_cp_reg(&cpu->env, ri, v);
256 if (read_raw_cp_reg(&cpu->env, ri) != v) {
257 ok = false;
258 }
259 }
260 return ok;
261 }
262
263 static void add_cpreg_to_list(gpointer key, gpointer opaque)
264 {
265 ARMCPU *cpu = opaque;
266 uint64_t regidx;
267 const ARMCPRegInfo *ri;
268
269 regidx = *(uint32_t *)key;
270 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
271
272 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
273 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
274 /* The value array need not be initialized at this point */
275 cpu->cpreg_array_len++;
276 }
277 }
278
279 static void count_cpreg(gpointer key, gpointer opaque)
280 {
281 ARMCPU *cpu = opaque;
282 uint64_t regidx;
283 const ARMCPRegInfo *ri;
284
285 regidx = *(uint32_t *)key;
286 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
287
288 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
289 cpu->cpreg_array_len++;
290 }
291 }
292
293 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
294 {
295 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
296 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
297
298 if (aidx > bidx) {
299 return 1;
300 }
301 if (aidx < bidx) {
302 return -1;
303 }
304 return 0;
305 }
306
307 void init_cpreg_list(ARMCPU *cpu)
308 {
309 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
310 * Note that we require cpreg_tuples[] to be sorted by key ID.
311 */
312 GList *keys;
313 int arraylen;
314
315 keys = g_hash_table_get_keys(cpu->cp_regs);
316 keys = g_list_sort(keys, cpreg_key_compare);
317
318 cpu->cpreg_array_len = 0;
319
320 g_list_foreach(keys, count_cpreg, cpu);
321
322 arraylen = cpu->cpreg_array_len;
323 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
324 cpu->cpreg_values = g_new(uint64_t, arraylen);
325 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
326 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
327 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
328 cpu->cpreg_array_len = 0;
329
330 g_list_foreach(keys, add_cpreg_to_list, cpu);
331
332 assert(cpu->cpreg_array_len == arraylen);
333
334 g_list_free(keys);
335 }
336
337 /*
338 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
339 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
340 *
341 * access_el3_aa32ns: Used to check AArch32 register views.
342 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
343 */
344 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
345 const ARMCPRegInfo *ri)
346 {
347 bool secure = arm_is_secure_below_el3(env);
348
349 assert(!arm_el_is_aa64(env, 3));
350 if (secure) {
351 return CP_ACCESS_TRAP_UNCATEGORIZED;
352 }
353 return CP_ACCESS_OK;
354 }
355
356 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
357 const ARMCPRegInfo *ri)
358 {
359 if (!arm_el_is_aa64(env, 3)) {
360 return access_el3_aa32ns(env, ri);
361 }
362 return CP_ACCESS_OK;
363 }
364
365 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
366 {
367 ARMCPU *cpu = arm_env_get_cpu(env);
368
369 raw_write(env, ri, value);
370 tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
371 }
372
373 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
374 {
375 ARMCPU *cpu = arm_env_get_cpu(env);
376
377 if (raw_read(env, ri) != value) {
378 /* Unlike real hardware the qemu TLB uses virtual addresses,
379 * not modified virtual addresses, so this causes a TLB flush.
380 */
381 tlb_flush(CPU(cpu), 1);
382 raw_write(env, ri, value);
383 }
384 }
385
386 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
387 uint64_t value)
388 {
389 ARMCPU *cpu = arm_env_get_cpu(env);
390
391 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
392 && !extended_addresses_enabled(env)) {
393 /* For VMSA (when not using the LPAE long descriptor page table
394 * format) this register includes the ASID, so do a TLB flush.
395 * For PMSA it is purely a process ID and no action is needed.
396 */
397 tlb_flush(CPU(cpu), 1);
398 }
399 raw_write(env, ri, value);
400 }
401
402 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
403 uint64_t value)
404 {
405 /* Invalidate all (TLBIALL) */
406 ARMCPU *cpu = arm_env_get_cpu(env);
407
408 tlb_flush(CPU(cpu), 1);
409 }
410
411 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
412 uint64_t value)
413 {
414 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
415 ARMCPU *cpu = arm_env_get_cpu(env);
416
417 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
418 }
419
420 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
421 uint64_t value)
422 {
423 /* Invalidate by ASID (TLBIASID) */
424 ARMCPU *cpu = arm_env_get_cpu(env);
425
426 tlb_flush(CPU(cpu), value == 0);
427 }
428
429 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
430 uint64_t value)
431 {
432 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
433 ARMCPU *cpu = arm_env_get_cpu(env);
434
435 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
436 }
437
438 /* IS variants of TLB operations must affect all cores */
439 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
440 uint64_t value)
441 {
442 CPUState *other_cs;
443
444 CPU_FOREACH(other_cs) {
445 tlb_flush(other_cs, 1);
446 }
447 }
448
449 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
450 uint64_t value)
451 {
452 CPUState *other_cs;
453
454 CPU_FOREACH(other_cs) {
455 tlb_flush(other_cs, value == 0);
456 }
457 }
458
459 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
460 uint64_t value)
461 {
462 CPUState *other_cs;
463
464 CPU_FOREACH(other_cs) {
465 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
466 }
467 }
468
469 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
470 uint64_t value)
471 {
472 CPUState *other_cs;
473
474 CPU_FOREACH(other_cs) {
475 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
476 }
477 }
478
479 static const ARMCPRegInfo cp_reginfo[] = {
480 /* Define the secure and non-secure FCSE identifier CP registers
481 * separately because there is no secure bank in V8 (no _EL3). This allows
482 * the secure register to be properly reset and migrated. There is also no
483 * v8 EL1 version of the register so the non-secure instance stands alone.
484 */
485 { .name = "FCSEIDR(NS)",
486 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
487 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
488 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
489 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
490 { .name = "FCSEIDR(S)",
491 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
492 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
493 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
494 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
495 /* Define the secure and non-secure context identifier CP registers
496 * separately because there is no secure bank in V8 (no _EL3). This allows
497 * the secure register to be properly reset and migrated. In the
498 * non-secure case, the 32-bit register will have reset and migration
499 * disabled during registration as it is handled by the 64-bit instance.
500 */
501 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
502 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
503 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
504 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
505 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
506 { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
507 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
508 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
509 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
510 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
511 REGINFO_SENTINEL
512 };
513
514 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
515 /* NB: Some of these registers exist in v8 but with more precise
516 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
517 */
518 /* MMU Domain access control / MPU write buffer control */
519 { .name = "DACR",
520 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
521 .access = PL1_RW, .resetvalue = 0,
522 .writefn = dacr_write, .raw_writefn = raw_write,
523 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
524 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
525 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
526 * For v6 and v5, these mappings are overly broad.
527 */
528 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
529 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
530 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
531 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
532 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
533 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
534 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
535 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
536 /* Cache maintenance ops; some of this space may be overridden later. */
537 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
538 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
539 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
540 REGINFO_SENTINEL
541 };
542
543 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
544 /* Not all pre-v6 cores implemented this WFI, so this is slightly
545 * over-broad.
546 */
547 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
548 .access = PL1_W, .type = ARM_CP_WFI },
549 REGINFO_SENTINEL
550 };
551
552 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
553 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
554 * is UNPREDICTABLE; we choose to NOP as most implementations do).
555 */
556 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
557 .access = PL1_W, .type = ARM_CP_WFI },
558 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
559 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
560 * OMAPCP will override this space.
561 */
562 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
563 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
564 .resetvalue = 0 },
565 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
566 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
567 .resetvalue = 0 },
568 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
569 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
570 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
571 .resetvalue = 0 },
572 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
573 * implementing it as RAZ means the "debug architecture version" bits
574 * will read as a reserved value, which should cause Linux to not try
575 * to use the debug hardware.
576 */
577 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
578 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
579 /* MMU TLB control. Note that the wildcarding means we cover not just
580 * the unified TLB ops but also the dside/iside/inner-shareable variants.
581 */
582 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
583 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
584 .type = ARM_CP_NO_RAW },
585 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
586 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
587 .type = ARM_CP_NO_RAW },
588 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
589 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
590 .type = ARM_CP_NO_RAW },
591 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
592 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
593 .type = ARM_CP_NO_RAW },
594 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
595 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
596 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
597 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
598 REGINFO_SENTINEL
599 };
600
601 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
602 uint64_t value)
603 {
604 uint32_t mask = 0;
605
606 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
607 if (!arm_feature(env, ARM_FEATURE_V8)) {
608 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
609 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
610 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
611 */
612 if (arm_feature(env, ARM_FEATURE_VFP)) {
613 /* VFP coprocessor: cp10 & cp11 [23:20] */
614 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
615
616 if (!arm_feature(env, ARM_FEATURE_NEON)) {
617 /* ASEDIS [31] bit is RAO/WI */
618 value |= (1 << 31);
619 }
620
621 /* VFPv3 and upwards with NEON implement 32 double precision
622 * registers (D0-D31).
623 */
624 if (!arm_feature(env, ARM_FEATURE_NEON) ||
625 !arm_feature(env, ARM_FEATURE_VFP3)) {
626 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
627 value |= (1 << 30);
628 }
629 }
630 value &= mask;
631 }
632 env->cp15.cpacr_el1 = value;
633 }
634
635 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri)
636 {
637 if (arm_feature(env, ARM_FEATURE_V8)) {
638 /* Check if CPACR accesses are to be trapped to EL2 */
639 if (arm_current_el(env) == 1 &&
640 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
641 return CP_ACCESS_TRAP_EL2;
642 /* Check if CPACR accesses are to be trapped to EL3 */
643 } else if (arm_current_el(env) < 3 &&
644 (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
645 return CP_ACCESS_TRAP_EL3;
646 }
647 }
648
649 return CP_ACCESS_OK;
650 }
651
652 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri)
653 {
654 /* Check if CPTR accesses are set to trap to EL3 */
655 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
656 return CP_ACCESS_TRAP_EL3;
657 }
658
659 return CP_ACCESS_OK;
660 }
661
662 static const ARMCPRegInfo v6_cp_reginfo[] = {
663 /* prefetch by MVA in v6, NOP in v7 */
664 { .name = "MVA_prefetch",
665 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
666 .access = PL1_W, .type = ARM_CP_NOP },
667 /* We need to break the TB after ISB to execute self-modifying code
668 * correctly and also to take any pending interrupts immediately.
669 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
670 */
671 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
672 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
673 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
674 .access = PL0_W, .type = ARM_CP_NOP },
675 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
676 .access = PL0_W, .type = ARM_CP_NOP },
677 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
678 .access = PL1_RW,
679 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
680 offsetof(CPUARMState, cp15.ifar_ns) },
681 .resetvalue = 0, },
682 /* Watchpoint Fault Address Register : should actually only be present
683 * for 1136, 1176, 11MPCore.
684 */
685 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
686 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
687 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
688 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
689 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
690 .resetvalue = 0, .writefn = cpacr_write },
691 REGINFO_SENTINEL
692 };
693
694 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
695 {
696 /* Performance monitor registers user accessibility is controlled
697 * by PMUSERENR.
698 */
699 if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
700 return CP_ACCESS_TRAP;
701 }
702 return CP_ACCESS_OK;
703 }
704
705 #ifndef CONFIG_USER_ONLY
706
707 static inline bool arm_ccnt_enabled(CPUARMState *env)
708 {
709 /* This does not support checking PMCCFILTR_EL0 register */
710
711 if (!(env->cp15.c9_pmcr & PMCRE)) {
712 return false;
713 }
714
715 return true;
716 }
717
718 void pmccntr_sync(CPUARMState *env)
719 {
720 uint64_t temp_ticks;
721
722 temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
723 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
724
725 if (env->cp15.c9_pmcr & PMCRD) {
726 /* Increment once every 64 processor clock cycles */
727 temp_ticks /= 64;
728 }
729
730 if (arm_ccnt_enabled(env)) {
731 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
732 }
733 }
734
735 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
736 uint64_t value)
737 {
738 pmccntr_sync(env);
739
740 if (value & PMCRC) {
741 /* The counter has been reset */
742 env->cp15.c15_ccnt = 0;
743 }
744
745 /* only the DP, X, D and E bits are writable */
746 env->cp15.c9_pmcr &= ~0x39;
747 env->cp15.c9_pmcr |= (value & 0x39);
748
749 pmccntr_sync(env);
750 }
751
752 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
753 {
754 uint64_t total_ticks;
755
756 if (!arm_ccnt_enabled(env)) {
757 /* Counter is disabled, do not change value */
758 return env->cp15.c15_ccnt;
759 }
760
761 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
762 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
763
764 if (env->cp15.c9_pmcr & PMCRD) {
765 /* Increment once every 64 processor clock cycles */
766 total_ticks /= 64;
767 }
768 return total_ticks - env->cp15.c15_ccnt;
769 }
770
771 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
772 uint64_t value)
773 {
774 uint64_t total_ticks;
775
776 if (!arm_ccnt_enabled(env)) {
777 /* Counter is disabled, set the absolute value */
778 env->cp15.c15_ccnt = value;
779 return;
780 }
781
782 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
783 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
784
785 if (env->cp15.c9_pmcr & PMCRD) {
786 /* Increment once every 64 processor clock cycles */
787 total_ticks /= 64;
788 }
789 env->cp15.c15_ccnt = total_ticks - value;
790 }
791
792 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
793 uint64_t value)
794 {
795 uint64_t cur_val = pmccntr_read(env, NULL);
796
797 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
798 }
799
800 #else /* CONFIG_USER_ONLY */
801
802 void pmccntr_sync(CPUARMState *env)
803 {
804 }
805
806 #endif
807
808 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
809 uint64_t value)
810 {
811 pmccntr_sync(env);
812 env->cp15.pmccfiltr_el0 = value & 0x7E000000;
813 pmccntr_sync(env);
814 }
815
816 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
817 uint64_t value)
818 {
819 value &= (1 << 31);
820 env->cp15.c9_pmcnten |= value;
821 }
822
823 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
824 uint64_t value)
825 {
826 value &= (1 << 31);
827 env->cp15.c9_pmcnten &= ~value;
828 }
829
830 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
831 uint64_t value)
832 {
833 env->cp15.c9_pmovsr &= ~value;
834 }
835
836 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
837 uint64_t value)
838 {
839 env->cp15.c9_pmxevtyper = value & 0xff;
840 }
841
842 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
843 uint64_t value)
844 {
845 env->cp15.c9_pmuserenr = value & 1;
846 }
847
848 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
849 uint64_t value)
850 {
851 /* We have no event counters so only the C bit can be changed */
852 value &= (1 << 31);
853 env->cp15.c9_pminten |= value;
854 }
855
856 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
857 uint64_t value)
858 {
859 value &= (1 << 31);
860 env->cp15.c9_pminten &= ~value;
861 }
862
863 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
864 uint64_t value)
865 {
866 /* Note that even though the AArch64 view of this register has bits
867 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
868 * architectural requirements for bits which are RES0 only in some
869 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
870 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
871 */
872 raw_write(env, ri, value & ~0x1FULL);
873 }
874
875 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
876 {
877 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
878 * For bits that vary between AArch32/64, code needs to check the
879 * current execution mode before directly using the feature bit.
880 */
881 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
882
883 if (!arm_feature(env, ARM_FEATURE_EL2)) {
884 valid_mask &= ~SCR_HCE;
885
886 /* On ARMv7, SMD (or SCD as it is called in v7) is only
887 * supported if EL2 exists. The bit is UNK/SBZP when
888 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
889 * when EL2 is unavailable.
890 * On ARMv8, this bit is always available.
891 */
892 if (arm_feature(env, ARM_FEATURE_V7) &&
893 !arm_feature(env, ARM_FEATURE_V8)) {
894 valid_mask &= ~SCR_SMD;
895 }
896 }
897
898 /* Clear all-context RES0 bits. */
899 value &= valid_mask;
900 raw_write(env, ri, value);
901 }
902
903 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
904 {
905 ARMCPU *cpu = arm_env_get_cpu(env);
906
907 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
908 * bank
909 */
910 uint32_t index = A32_BANKED_REG_GET(env, csselr,
911 ri->secure & ARM_CP_SECSTATE_S);
912
913 return cpu->ccsidr[index];
914 }
915
916 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
917 uint64_t value)
918 {
919 raw_write(env, ri, value & 0xf);
920 }
921
922 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
923 {
924 CPUState *cs = ENV_GET_CPU(env);
925 uint64_t ret = 0;
926
927 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
928 ret |= CPSR_I;
929 }
930 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
931 ret |= CPSR_F;
932 }
933 /* External aborts are not possible in QEMU so A bit is always clear */
934 return ret;
935 }
936
937 static const ARMCPRegInfo v7_cp_reginfo[] = {
938 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
939 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
940 .access = PL1_W, .type = ARM_CP_NOP },
941 /* Performance monitors are implementation defined in v7,
942 * but with an ARM recommended set of registers, which we
943 * follow (although we don't actually implement any counters)
944 *
945 * Performance registers fall into three categories:
946 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
947 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
948 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
949 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
950 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
951 */
952 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
953 .access = PL0_RW, .type = ARM_CP_ALIAS,
954 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
955 .writefn = pmcntenset_write,
956 .accessfn = pmreg_access,
957 .raw_writefn = raw_write },
958 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
959 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
960 .access = PL0_RW, .accessfn = pmreg_access,
961 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
962 .writefn = pmcntenset_write, .raw_writefn = raw_write },
963 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
964 .access = PL0_RW,
965 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
966 .accessfn = pmreg_access,
967 .writefn = pmcntenclr_write,
968 .type = ARM_CP_ALIAS },
969 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
970 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
971 .access = PL0_RW, .accessfn = pmreg_access,
972 .type = ARM_CP_ALIAS,
973 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
974 .writefn = pmcntenclr_write },
975 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
976 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
977 .accessfn = pmreg_access,
978 .writefn = pmovsr_write,
979 .raw_writefn = raw_write },
980 /* Unimplemented so WI. */
981 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
982 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
983 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
984 * We choose to RAZ/WI.
985 */
986 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
987 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
988 .accessfn = pmreg_access },
989 #ifndef CONFIG_USER_ONLY
990 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
991 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
992 .readfn = pmccntr_read, .writefn = pmccntr_write32,
993 .accessfn = pmreg_access },
994 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
995 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
996 .access = PL0_RW, .accessfn = pmreg_access,
997 .type = ARM_CP_IO,
998 .readfn = pmccntr_read, .writefn = pmccntr_write, },
999 #endif
1000 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1001 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1002 .writefn = pmccfiltr_write,
1003 .access = PL0_RW, .accessfn = pmreg_access,
1004 .type = ARM_CP_IO,
1005 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1006 .resetvalue = 0, },
1007 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1008 .access = PL0_RW,
1009 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
1010 .accessfn = pmreg_access, .writefn = pmxevtyper_write,
1011 .raw_writefn = raw_write },
1012 /* Unimplemented, RAZ/WI. */
1013 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1014 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1015 .accessfn = pmreg_access },
1016 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1017 .access = PL0_R | PL1_RW,
1018 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1019 .resetvalue = 0,
1020 .writefn = pmuserenr_write, .raw_writefn = raw_write },
1021 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1022 .access = PL1_RW,
1023 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1024 .resetvalue = 0,
1025 .writefn = pmintenset_write, .raw_writefn = raw_write },
1026 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1027 .access = PL1_RW, .type = ARM_CP_ALIAS,
1028 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1029 .writefn = pmintenclr_write, },
1030 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
1031 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1032 .access = PL1_RW, .writefn = vbar_write,
1033 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
1034 offsetof(CPUARMState, cp15.vbar_ns) },
1035 .resetvalue = 0 },
1036 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1037 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1038 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1039 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1040 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1041 .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1042 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1043 offsetof(CPUARMState, cp15.csselr_ns) } },
1044 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1045 * just RAZ for all cores:
1046 */
1047 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1048 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1049 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1050 /* Auxiliary fault status registers: these also are IMPDEF, and we
1051 * choose to RAZ/WI for all cores.
1052 */
1053 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1054 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1055 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1056 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1057 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1058 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1059 /* MAIR can just read-as-written because we don't implement caches
1060 * and so don't need to care about memory attributes.
1061 */
1062 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1063 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1064 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1065 .resetvalue = 0 },
1066 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1067 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1068 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1069 .resetvalue = 0 },
1070 /* For non-long-descriptor page tables these are PRRR and NMRR;
1071 * regardless they still act as reads-as-written for QEMU.
1072 */
1073 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1074 * allows them to assign the correct fieldoffset based on the endianness
1075 * handled in the field definitions.
1076 */
1077 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1078 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1079 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1080 offsetof(CPUARMState, cp15.mair0_ns) },
1081 .resetfn = arm_cp_reset_ignore },
1082 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1083 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1084 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1085 offsetof(CPUARMState, cp15.mair1_ns) },
1086 .resetfn = arm_cp_reset_ignore },
1087 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1088 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1089 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1090 /* 32 bit ITLB invalidates */
1091 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1092 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1093 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1094 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1095 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1096 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1097 /* 32 bit DTLB invalidates */
1098 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1099 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1100 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1101 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1102 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1103 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1104 /* 32 bit TLB invalidates */
1105 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1106 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1107 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1108 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1109 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1110 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1111 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1112 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1113 REGINFO_SENTINEL
1114 };
1115
1116 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1117 /* 32 bit TLB invalidates, Inner Shareable */
1118 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1119 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1120 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1121 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1122 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1123 .type = ARM_CP_NO_RAW, .access = PL1_W,
1124 .writefn = tlbiasid_is_write },
1125 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1126 .type = ARM_CP_NO_RAW, .access = PL1_W,
1127 .writefn = tlbimvaa_is_write },
1128 REGINFO_SENTINEL
1129 };
1130
1131 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1132 uint64_t value)
1133 {
1134 value &= 1;
1135 env->teecr = value;
1136 }
1137
1138 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
1139 {
1140 if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1141 return CP_ACCESS_TRAP;
1142 }
1143 return CP_ACCESS_OK;
1144 }
1145
1146 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1147 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1148 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1149 .resetvalue = 0,
1150 .writefn = teecr_write },
1151 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1152 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1153 .accessfn = teehbr_access, .resetvalue = 0 },
1154 REGINFO_SENTINEL
1155 };
1156
1157 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1158 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1159 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1160 .access = PL0_RW,
1161 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1162 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1163 .access = PL0_RW,
1164 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1165 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1166 .resetfn = arm_cp_reset_ignore },
1167 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1168 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1169 .access = PL0_R|PL1_W,
1170 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1171 .resetvalue = 0},
1172 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1173 .access = PL0_R|PL1_W,
1174 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1175 offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1176 .resetfn = arm_cp_reset_ignore },
1177 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1178 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1179 .access = PL1_RW,
1180 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1181 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1182 .access = PL1_RW,
1183 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1184 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1185 .resetvalue = 0 },
1186 REGINFO_SENTINEL
1187 };
1188
1189 #ifndef CONFIG_USER_ONLY
1190
1191 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1192 {
1193 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1194 if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1195 return CP_ACCESS_TRAP;
1196 }
1197 return CP_ACCESS_OK;
1198 }
1199
1200 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1201 {
1202 unsigned int cur_el = arm_current_el(env);
1203 bool secure = arm_is_secure(env);
1204
1205 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1206 if (cur_el == 0 &&
1207 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1208 return CP_ACCESS_TRAP;
1209 }
1210
1211 if (arm_feature(env, ARM_FEATURE_EL2) &&
1212 timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1213 !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1214 return CP_ACCESS_TRAP_EL2;
1215 }
1216 return CP_ACCESS_OK;
1217 }
1218
1219 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1220 {
1221 unsigned int cur_el = arm_current_el(env);
1222 bool secure = arm_is_secure(env);
1223
1224 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1225 * EL0[PV]TEN is zero.
1226 */
1227 if (cur_el == 0 &&
1228 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1229 return CP_ACCESS_TRAP;
1230 }
1231
1232 if (arm_feature(env, ARM_FEATURE_EL2) &&
1233 timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1234 !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1235 return CP_ACCESS_TRAP_EL2;
1236 }
1237 return CP_ACCESS_OK;
1238 }
1239
1240 static CPAccessResult gt_pct_access(CPUARMState *env,
1241 const ARMCPRegInfo *ri)
1242 {
1243 return gt_counter_access(env, GTIMER_PHYS);
1244 }
1245
1246 static CPAccessResult gt_vct_access(CPUARMState *env,
1247 const ARMCPRegInfo *ri)
1248 {
1249 return gt_counter_access(env, GTIMER_VIRT);
1250 }
1251
1252 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1253 {
1254 return gt_timer_access(env, GTIMER_PHYS);
1255 }
1256
1257 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1258 {
1259 return gt_timer_access(env, GTIMER_VIRT);
1260 }
1261
1262 static CPAccessResult gt_stimer_access(CPUARMState *env,
1263 const ARMCPRegInfo *ri)
1264 {
1265 /* The AArch64 register view of the secure physical timer is
1266 * always accessible from EL3, and configurably accessible from
1267 * Secure EL1.
1268 */
1269 switch (arm_current_el(env)) {
1270 case 1:
1271 if (!arm_is_secure(env)) {
1272 return CP_ACCESS_TRAP;
1273 }
1274 if (!(env->cp15.scr_el3 & SCR_ST)) {
1275 return CP_ACCESS_TRAP_EL3;
1276 }
1277 return CP_ACCESS_OK;
1278 case 0:
1279 case 2:
1280 return CP_ACCESS_TRAP;
1281 case 3:
1282 return CP_ACCESS_OK;
1283 default:
1284 g_assert_not_reached();
1285 }
1286 }
1287
1288 static uint64_t gt_get_countervalue(CPUARMState *env)
1289 {
1290 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1291 }
1292
1293 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1294 {
1295 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1296
1297 if (gt->ctl & 1) {
1298 /* Timer enabled: calculate and set current ISTATUS, irq, and
1299 * reset timer to when ISTATUS next has to change
1300 */
1301 uint64_t offset = timeridx == GTIMER_VIRT ?
1302 cpu->env.cp15.cntvoff_el2 : 0;
1303 uint64_t count = gt_get_countervalue(&cpu->env);
1304 /* Note that this must be unsigned 64 bit arithmetic: */
1305 int istatus = count - offset >= gt->cval;
1306 uint64_t nexttick;
1307
1308 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1309 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1310 (istatus && !(gt->ctl & 2)));
1311 if (istatus) {
1312 /* Next transition is when count rolls back over to zero */
1313 nexttick = UINT64_MAX;
1314 } else {
1315 /* Next transition is when we hit cval */
1316 nexttick = gt->cval + offset;
1317 }
1318 /* Note that the desired next expiry time might be beyond the
1319 * signed-64-bit range of a QEMUTimer -- in this case we just
1320 * set the timer for as far in the future as possible. When the
1321 * timer expires we will reset the timer for any remaining period.
1322 */
1323 if (nexttick > INT64_MAX / GTIMER_SCALE) {
1324 nexttick = INT64_MAX / GTIMER_SCALE;
1325 }
1326 timer_mod(cpu->gt_timer[timeridx], nexttick);
1327 } else {
1328 /* Timer disabled: ISTATUS and timer output always clear */
1329 gt->ctl &= ~4;
1330 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1331 timer_del(cpu->gt_timer[timeridx]);
1332 }
1333 }
1334
1335 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1336 int timeridx)
1337 {
1338 ARMCPU *cpu = arm_env_get_cpu(env);
1339
1340 timer_del(cpu->gt_timer[timeridx]);
1341 }
1342
1343 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1344 {
1345 return gt_get_countervalue(env);
1346 }
1347
1348 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1349 {
1350 return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1351 }
1352
1353 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1354 int timeridx,
1355 uint64_t value)
1356 {
1357 env->cp15.c14_timer[timeridx].cval = value;
1358 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1359 }
1360
1361 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1362 int timeridx)
1363 {
1364 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1365
1366 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1367 (gt_get_countervalue(env) - offset));
1368 }
1369
1370 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1371 int timeridx,
1372 uint64_t value)
1373 {
1374 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1375
1376 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1377 sextract64(value, 0, 32);
1378 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1379 }
1380
1381 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1382 int timeridx,
1383 uint64_t value)
1384 {
1385 ARMCPU *cpu = arm_env_get_cpu(env);
1386 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1387
1388 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1389 if ((oldval ^ value) & 1) {
1390 /* Enable toggled */
1391 gt_recalc_timer(cpu, timeridx);
1392 } else if ((oldval ^ value) & 2) {
1393 /* IMASK toggled: don't need to recalculate,
1394 * just set the interrupt line based on ISTATUS
1395 */
1396 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1397 (oldval & 4) && !(value & 2));
1398 }
1399 }
1400
1401 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1402 {
1403 gt_timer_reset(env, ri, GTIMER_PHYS);
1404 }
1405
1406 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1407 uint64_t value)
1408 {
1409 gt_cval_write(env, ri, GTIMER_PHYS, value);
1410 }
1411
1412 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1413 {
1414 return gt_tval_read(env, ri, GTIMER_PHYS);
1415 }
1416
1417 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1418 uint64_t value)
1419 {
1420 gt_tval_write(env, ri, GTIMER_PHYS, value);
1421 }
1422
1423 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1424 uint64_t value)
1425 {
1426 gt_ctl_write(env, ri, GTIMER_PHYS, value);
1427 }
1428
1429 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1430 {
1431 gt_timer_reset(env, ri, GTIMER_VIRT);
1432 }
1433
1434 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1435 uint64_t value)
1436 {
1437 gt_cval_write(env, ri, GTIMER_VIRT, value);
1438 }
1439
1440 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1441 {
1442 return gt_tval_read(env, ri, GTIMER_VIRT);
1443 }
1444
1445 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1446 uint64_t value)
1447 {
1448 gt_tval_write(env, ri, GTIMER_VIRT, value);
1449 }
1450
1451 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1452 uint64_t value)
1453 {
1454 gt_ctl_write(env, ri, GTIMER_VIRT, value);
1455 }
1456
1457 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1458 uint64_t value)
1459 {
1460 ARMCPU *cpu = arm_env_get_cpu(env);
1461
1462 raw_write(env, ri, value);
1463 gt_recalc_timer(cpu, GTIMER_VIRT);
1464 }
1465
1466 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1467 {
1468 gt_timer_reset(env, ri, GTIMER_HYP);
1469 }
1470
1471 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1472 uint64_t value)
1473 {
1474 gt_cval_write(env, ri, GTIMER_HYP, value);
1475 }
1476
1477 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1478 {
1479 return gt_tval_read(env, ri, GTIMER_HYP);
1480 }
1481
1482 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1483 uint64_t value)
1484 {
1485 gt_tval_write(env, ri, GTIMER_HYP, value);
1486 }
1487
1488 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1489 uint64_t value)
1490 {
1491 gt_ctl_write(env, ri, GTIMER_HYP, value);
1492 }
1493
1494 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1495 {
1496 gt_timer_reset(env, ri, GTIMER_SEC);
1497 }
1498
1499 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1500 uint64_t value)
1501 {
1502 gt_cval_write(env, ri, GTIMER_SEC, value);
1503 }
1504
1505 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1506 {
1507 return gt_tval_read(env, ri, GTIMER_SEC);
1508 }
1509
1510 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1511 uint64_t value)
1512 {
1513 gt_tval_write(env, ri, GTIMER_SEC, value);
1514 }
1515
1516 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1517 uint64_t value)
1518 {
1519 gt_ctl_write(env, ri, GTIMER_SEC, value);
1520 }
1521
1522 void arm_gt_ptimer_cb(void *opaque)
1523 {
1524 ARMCPU *cpu = opaque;
1525
1526 gt_recalc_timer(cpu, GTIMER_PHYS);
1527 }
1528
1529 void arm_gt_vtimer_cb(void *opaque)
1530 {
1531 ARMCPU *cpu = opaque;
1532
1533 gt_recalc_timer(cpu, GTIMER_VIRT);
1534 }
1535
1536 void arm_gt_htimer_cb(void *opaque)
1537 {
1538 ARMCPU *cpu = opaque;
1539
1540 gt_recalc_timer(cpu, GTIMER_HYP);
1541 }
1542
1543 void arm_gt_stimer_cb(void *opaque)
1544 {
1545 ARMCPU *cpu = opaque;
1546
1547 gt_recalc_timer(cpu, GTIMER_SEC);
1548 }
1549
1550 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1551 /* Note that CNTFRQ is purely reads-as-written for the benefit
1552 * of software; writing it doesn't actually change the timer frequency.
1553 * Our reset value matches the fixed frequency we implement the timer at.
1554 */
1555 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1556 .type = ARM_CP_ALIAS,
1557 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1558 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1559 },
1560 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1561 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1562 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1563 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1564 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1565 },
1566 /* overall control: mostly access permissions */
1567 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1568 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1569 .access = PL1_RW,
1570 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1571 .resetvalue = 0,
1572 },
1573 /* per-timer control */
1574 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1575 .secure = ARM_CP_SECSTATE_NS,
1576 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1577 .accessfn = gt_ptimer_access,
1578 .fieldoffset = offsetoflow32(CPUARMState,
1579 cp15.c14_timer[GTIMER_PHYS].ctl),
1580 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1581 },
1582 { .name = "CNTP_CTL(S)",
1583 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1584 .secure = ARM_CP_SECSTATE_S,
1585 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1586 .accessfn = gt_ptimer_access,
1587 .fieldoffset = offsetoflow32(CPUARMState,
1588 cp15.c14_timer[GTIMER_SEC].ctl),
1589 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1590 },
1591 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1592 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1593 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1594 .accessfn = gt_ptimer_access,
1595 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1596 .resetvalue = 0,
1597 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1598 },
1599 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1600 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1601 .accessfn = gt_vtimer_access,
1602 .fieldoffset = offsetoflow32(CPUARMState,
1603 cp15.c14_timer[GTIMER_VIRT].ctl),
1604 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1605 },
1606 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1607 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1608 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1609 .accessfn = gt_vtimer_access,
1610 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1611 .resetvalue = 0,
1612 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1613 },
1614 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1615 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1616 .secure = ARM_CP_SECSTATE_NS,
1617 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1618 .accessfn = gt_ptimer_access,
1619 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1620 },
1621 { .name = "CNTP_TVAL(S)",
1622 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1623 .secure = ARM_CP_SECSTATE_S,
1624 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1625 .accessfn = gt_ptimer_access,
1626 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1627 },
1628 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1629 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1630 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1631 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1632 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1633 },
1634 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1635 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1636 .accessfn = gt_vtimer_access,
1637 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1638 },
1639 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1640 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1641 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1642 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1643 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1644 },
1645 /* The counter itself */
1646 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1647 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1648 .accessfn = gt_pct_access,
1649 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1650 },
1651 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1652 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1653 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1654 .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1655 },
1656 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1657 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1658 .accessfn = gt_vct_access,
1659 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1660 },
1661 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1662 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1663 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1664 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1665 },
1666 /* Comparison value, indicating when the timer goes off */
1667 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1668 .secure = ARM_CP_SECSTATE_NS,
1669 .access = PL1_RW | PL0_R,
1670 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1671 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1672 .accessfn = gt_ptimer_access,
1673 .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1674 },
1675 { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1676 .secure = ARM_CP_SECSTATE_S,
1677 .access = PL1_RW | PL0_R,
1678 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1679 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1680 .accessfn = gt_ptimer_access,
1681 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1682 },
1683 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1684 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1685 .access = PL1_RW | PL0_R,
1686 .type = ARM_CP_IO,
1687 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1688 .resetvalue = 0, .accessfn = gt_ptimer_access,
1689 .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1690 },
1691 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1692 .access = PL1_RW | PL0_R,
1693 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1694 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1695 .accessfn = gt_vtimer_access,
1696 .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1697 },
1698 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1699 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1700 .access = PL1_RW | PL0_R,
1701 .type = ARM_CP_IO,
1702 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1703 .resetvalue = 0, .accessfn = gt_vtimer_access,
1704 .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1705 },
1706 /* Secure timer -- this is actually restricted to only EL3
1707 * and configurably Secure-EL1 via the accessfn.
1708 */
1709 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1710 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1711 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1712 .accessfn = gt_stimer_access,
1713 .readfn = gt_sec_tval_read,
1714 .writefn = gt_sec_tval_write,
1715 .resetfn = gt_sec_timer_reset,
1716 },
1717 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1718 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1719 .type = ARM_CP_IO, .access = PL1_RW,
1720 .accessfn = gt_stimer_access,
1721 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1722 .resetvalue = 0,
1723 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1724 },
1725 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1726 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1727 .type = ARM_CP_IO, .access = PL1_RW,
1728 .accessfn = gt_stimer_access,
1729 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1730 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1731 },
1732 REGINFO_SENTINEL
1733 };
1734
1735 #else
1736 /* In user-mode none of the generic timer registers are accessible,
1737 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1738 * so instead just don't register any of them.
1739 */
1740 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1741 REGINFO_SENTINEL
1742 };
1743
1744 #endif
1745
1746 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1747 {
1748 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1749 raw_write(env, ri, value);
1750 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1751 raw_write(env, ri, value & 0xfffff6ff);
1752 } else {
1753 raw_write(env, ri, value & 0xfffff1ff);
1754 }
1755 }
1756
1757 #ifndef CONFIG_USER_ONLY
1758 /* get_phys_addr() isn't present for user-mode-only targets */
1759
1760 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1761 {
1762 if (ri->opc2 & 4) {
1763 /* The ATS12NSO* operations must trap to EL3 if executed in
1764 * Secure EL1 (which can only happen if EL3 is AArch64).
1765 * They are simply UNDEF if executed from NS EL1.
1766 * They function normally from EL2 or EL3.
1767 */
1768 if (arm_current_el(env) == 1) {
1769 if (arm_is_secure_below_el3(env)) {
1770 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1771 }
1772 return CP_ACCESS_TRAP_UNCATEGORIZED;
1773 }
1774 }
1775 return CP_ACCESS_OK;
1776 }
1777
1778 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1779 int access_type, ARMMMUIdx mmu_idx)
1780 {
1781 hwaddr phys_addr;
1782 target_ulong page_size;
1783 int prot;
1784 uint32_t fsr;
1785 bool ret;
1786 uint64_t par64;
1787 MemTxAttrs attrs = {};
1788 ARMMMUFaultInfo fi = {};
1789
1790 ret = get_phys_addr(env, value, access_type, mmu_idx,
1791 &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
1792 if (extended_addresses_enabled(env)) {
1793 /* fsr is a DFSR/IFSR value for the long descriptor
1794 * translation table format, but with WnR always clear.
1795 * Convert it to a 64-bit PAR.
1796 */
1797 par64 = (1 << 11); /* LPAE bit always set */
1798 if (!ret) {
1799 par64 |= phys_addr & ~0xfffULL;
1800 if (!attrs.secure) {
1801 par64 |= (1 << 9); /* NS */
1802 }
1803 /* We don't set the ATTR or SH fields in the PAR. */
1804 } else {
1805 par64 |= 1; /* F */
1806 par64 |= (fsr & 0x3f) << 1; /* FS */
1807 /* Note that S2WLK and FSTAGE are always zero, because we don't
1808 * implement virtualization and therefore there can't be a stage 2
1809 * fault.
1810 */
1811 }
1812 } else {
1813 /* fsr is a DFSR/IFSR value for the short descriptor
1814 * translation table format (with WnR always clear).
1815 * Convert it to a 32-bit PAR.
1816 */
1817 if (!ret) {
1818 /* We do not set any attribute bits in the PAR */
1819 if (page_size == (1 << 24)
1820 && arm_feature(env, ARM_FEATURE_V7)) {
1821 par64 = (phys_addr & 0xff000000) | (1 << 1);
1822 } else {
1823 par64 = phys_addr & 0xfffff000;
1824 }
1825 if (!attrs.secure) {
1826 par64 |= (1 << 9); /* NS */
1827 }
1828 } else {
1829 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1830 ((fsr & 0xf) << 1) | 1;
1831 }
1832 }
1833 return par64;
1834 }
1835
1836 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1837 {
1838 int access_type = ri->opc2 & 1;
1839 uint64_t par64;
1840 ARMMMUIdx mmu_idx;
1841 int el = arm_current_el(env);
1842 bool secure = arm_is_secure_below_el3(env);
1843
1844 switch (ri->opc2 & 6) {
1845 case 0:
1846 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1847 switch (el) {
1848 case 3:
1849 mmu_idx = ARMMMUIdx_S1E3;
1850 break;
1851 case 2:
1852 mmu_idx = ARMMMUIdx_S1NSE1;
1853 break;
1854 case 1:
1855 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1856 break;
1857 default:
1858 g_assert_not_reached();
1859 }
1860 break;
1861 case 2:
1862 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1863 switch (el) {
1864 case 3:
1865 mmu_idx = ARMMMUIdx_S1SE0;
1866 break;
1867 case 2:
1868 mmu_idx = ARMMMUIdx_S1NSE0;
1869 break;
1870 case 1:
1871 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1872 break;
1873 default:
1874 g_assert_not_reached();
1875 }
1876 break;
1877 case 4:
1878 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1879 mmu_idx = ARMMMUIdx_S12NSE1;
1880 break;
1881 case 6:
1882 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1883 mmu_idx = ARMMMUIdx_S12NSE0;
1884 break;
1885 default:
1886 g_assert_not_reached();
1887 }
1888
1889 par64 = do_ats_write(env, value, access_type, mmu_idx);
1890
1891 A32_BANKED_CURRENT_REG_SET(env, par, par64);
1892 }
1893
1894 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
1895 uint64_t value)
1896 {
1897 int access_type = ri->opc2 & 1;
1898 uint64_t par64;
1899
1900 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
1901
1902 A32_BANKED_CURRENT_REG_SET(env, par, par64);
1903 }
1904
1905 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
1906 {
1907 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
1908 return CP_ACCESS_TRAP;
1909 }
1910 return CP_ACCESS_OK;
1911 }
1912
1913 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
1914 uint64_t value)
1915 {
1916 int access_type = ri->opc2 & 1;
1917 ARMMMUIdx mmu_idx;
1918 int secure = arm_is_secure_below_el3(env);
1919
1920 switch (ri->opc2 & 6) {
1921 case 0:
1922 switch (ri->opc1) {
1923 case 0: /* AT S1E1R, AT S1E1W */
1924 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1925 break;
1926 case 4: /* AT S1E2R, AT S1E2W */
1927 mmu_idx = ARMMMUIdx_S1E2;
1928 break;
1929 case 6: /* AT S1E3R, AT S1E3W */
1930 mmu_idx = ARMMMUIdx_S1E3;
1931 break;
1932 default:
1933 g_assert_not_reached();
1934 }
1935 break;
1936 case 2: /* AT S1E0R, AT S1E0W */
1937 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1938 break;
1939 case 4: /* AT S12E1R, AT S12E1W */
1940 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
1941 break;
1942 case 6: /* AT S12E0R, AT S12E0W */
1943 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
1944 break;
1945 default:
1946 g_assert_not_reached();
1947 }
1948
1949 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
1950 }
1951 #endif
1952
1953 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1954 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1955 .access = PL1_RW, .resetvalue = 0,
1956 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1957 offsetoflow32(CPUARMState, cp15.par_ns) },
1958 .writefn = par_write },
1959 #ifndef CONFIG_USER_ONLY
1960 /* This underdecoding is safe because the reginfo is NO_RAW. */
1961 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1962 .access = PL1_W, .accessfn = ats_access,
1963 .writefn = ats_write, .type = ARM_CP_NO_RAW },
1964 #endif
1965 REGINFO_SENTINEL
1966 };
1967
1968 /* Return basic MPU access permission bits. */
1969 static uint32_t simple_mpu_ap_bits(uint32_t val)
1970 {
1971 uint32_t ret;
1972 uint32_t mask;
1973 int i;
1974 ret = 0;
1975 mask = 3;
1976 for (i = 0; i < 16; i += 2) {
1977 ret |= (val >> i) & mask;
1978 mask <<= 2;
1979 }
1980 return ret;
1981 }
1982
1983 /* Pad basic MPU access permission bits to extended format. */
1984 static uint32_t extended_mpu_ap_bits(uint32_t val)
1985 {
1986 uint32_t ret;
1987 uint32_t mask;
1988 int i;
1989 ret = 0;
1990 mask = 3;
1991 for (i = 0; i < 16; i += 2) {
1992 ret |= (val & mask) << i;
1993 mask <<= 2;
1994 }
1995 return ret;
1996 }
1997
1998 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1999 uint64_t value)
2000 {
2001 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2002 }
2003
2004 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2005 {
2006 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2007 }
2008
2009 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2010 uint64_t value)
2011 {
2012 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2013 }
2014
2015 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2016 {
2017 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2018 }
2019
2020 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2021 {
2022 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2023
2024 if (!u32p) {
2025 return 0;
2026 }
2027
2028 u32p += env->cp15.c6_rgnr;
2029 return *u32p;
2030 }
2031
2032 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2033 uint64_t value)
2034 {
2035 ARMCPU *cpu = arm_env_get_cpu(env);
2036 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2037
2038 if (!u32p) {
2039 return;
2040 }
2041
2042 u32p += env->cp15.c6_rgnr;
2043 tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2044 *u32p = value;
2045 }
2046
2047 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2048 {
2049 ARMCPU *cpu = arm_env_get_cpu(env);
2050 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2051
2052 if (!u32p) {
2053 return;
2054 }
2055
2056 memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2057 }
2058
2059 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2060 uint64_t value)
2061 {
2062 ARMCPU *cpu = arm_env_get_cpu(env);
2063 uint32_t nrgs = cpu->pmsav7_dregion;
2064
2065 if (value >= nrgs) {
2066 qemu_log_mask(LOG_GUEST_ERROR,
2067 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2068 " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2069 return;
2070 }
2071
2072 raw_write(env, ri, value);
2073 }
2074
2075 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2076 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2077 .access = PL1_RW, .type = ARM_CP_NO_RAW,
2078 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2079 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2080 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2081 .access = PL1_RW, .type = ARM_CP_NO_RAW,
2082 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2083 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2084 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2085 .access = PL1_RW, .type = ARM_CP_NO_RAW,
2086 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2087 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2088 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2089 .access = PL1_RW,
2090 .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2091 .writefn = pmsav7_rgnr_write },
2092 REGINFO_SENTINEL
2093 };
2094
2095 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2096 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2097 .access = PL1_RW, .type = ARM_CP_ALIAS,
2098 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2099 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2100 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2101 .access = PL1_RW, .type = ARM_CP_ALIAS,
2102 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2103 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2104 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2105 .access = PL1_RW,
2106 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2107 .resetvalue = 0, },
2108 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2109 .access = PL1_RW,
2110 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2111 .resetvalue = 0, },
2112 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2113 .access = PL1_RW,
2114 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2115 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2116 .access = PL1_RW,
2117 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2118 /* Protection region base and size registers */
2119 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2120 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2121 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2122 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2123 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2124 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2125 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2126 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2127 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2128 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2129 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2130 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2131 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2132 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2133 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2134 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2135 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2136 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2137 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2138 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2139 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2140 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2141 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2142 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2143 REGINFO_SENTINEL
2144 };
2145
2146 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2147 uint64_t value)
2148 {
2149 TCR *tcr = raw_ptr(env, ri);
2150 int maskshift = extract32(value, 0, 3);
2151
2152 if (!arm_feature(env, ARM_FEATURE_V8)) {
2153 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2154 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2155 * using Long-desciptor translation table format */
2156 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2157 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2158 /* In an implementation that includes the Security Extensions
2159 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2160 * Short-descriptor translation table format.
2161 */
2162 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2163 } else {
2164 value &= TTBCR_N;
2165 }
2166 }
2167
2168 /* Update the masks corresponding to the TCR bank being written
2169 * Note that we always calculate mask and base_mask, but
2170 * they are only used for short-descriptor tables (ie if EAE is 0);
2171 * for long-descriptor tables the TCR fields are used differently
2172 * and the mask and base_mask values are meaningless.
2173 */
2174 tcr->raw_tcr = value;
2175 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2176 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2177 }
2178
2179 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2180 uint64_t value)
2181 {
2182 ARMCPU *cpu = arm_env_get_cpu(env);
2183
2184 if (arm_feature(env, ARM_FEATURE_LPAE)) {
2185 /* With LPAE the TTBCR could result in a change of ASID
2186 * via the TTBCR.A1 bit, so do a TLB flush.
2187 */
2188 tlb_flush(CPU(cpu), 1);
2189 }
2190 vmsa_ttbcr_raw_write(env, ri, value);
2191 }
2192
2193 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2194 {
2195 TCR *tcr = raw_ptr(env, ri);
2196
2197 /* Reset both the TCR as well as the masks corresponding to the bank of
2198 * the TCR being reset.
2199 */
2200 tcr->raw_tcr = 0;
2201 tcr->mask = 0;
2202 tcr->base_mask = 0xffffc000u;
2203 }
2204
2205 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2206 uint64_t value)
2207 {
2208 ARMCPU *cpu = arm_env_get_cpu(env);
2209 TCR *tcr = raw_ptr(env, ri);
2210
2211 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2212 tlb_flush(CPU(cpu), 1);
2213 tcr->raw_tcr = value;
2214 }
2215
2216 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2217 uint64_t value)
2218 {
2219 /* 64 bit accesses to the TTBRs can change the ASID and so we
2220 * must flush the TLB.
2221 */
2222 if (cpreg_field_is_64bit(ri)) {
2223 ARMCPU *cpu = arm_env_get_cpu(env);
2224
2225 tlb_flush(CPU(cpu), 1);
2226 }
2227 raw_write(env, ri, value);
2228 }
2229
2230 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2231 uint64_t value)
2232 {
2233 ARMCPU *cpu = arm_env_get_cpu(env);
2234 CPUState *cs = CPU(cpu);
2235
2236 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2237 if (raw_read(env, ri) != value) {
2238 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2239 ARMMMUIdx_S2NS, -1);
2240 raw_write(env, ri, value);
2241 }
2242 }
2243
2244 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2245 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2246 .access = PL1_RW, .type = ARM_CP_ALIAS,
2247 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2248 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2249 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2250 .access = PL1_RW, .resetvalue = 0,
2251 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2252 offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2253 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2254 .access = PL1_RW, .resetvalue = 0,
2255 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2256 offsetof(CPUARMState, cp15.dfar_ns) } },
2257 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2258 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2259 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2260 .resetvalue = 0, },
2261 REGINFO_SENTINEL
2262 };
2263
2264 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2265 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2266 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2267 .access = PL1_RW,
2268 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2269 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2270 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2271 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2272 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2273 offsetof(CPUARMState, cp15.ttbr0_ns) } },
2274 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2275 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2276 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2277 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2278 offsetof(CPUARMState, cp15.ttbr1_ns) } },
2279 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2280 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2281 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2282 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2283 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2284 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2285 .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2286 .raw_writefn = vmsa_ttbcr_raw_write,
2287 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2288 offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2289 REGINFO_SENTINEL
2290 };
2291
2292 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2293 uint64_t value)
2294 {
2295 env->cp15.c15_ticonfig = value & 0xe7;
2296 /* The OS_TYPE bit in this register changes the reported CPUID! */
2297 env->cp15.c0_cpuid = (value & (1 << 5)) ?
2298 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2299 }
2300
2301 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2302 uint64_t value)
2303 {
2304 env->cp15.c15_threadid = value & 0xffff;
2305 }
2306
2307 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2308 uint64_t value)
2309 {
2310 /* Wait-for-interrupt (deprecated) */
2311 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2312 }
2313
2314 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2315 uint64_t value)
2316 {
2317 /* On OMAP there are registers indicating the max/min index of dcache lines
2318 * containing a dirty line; cache flush operations have to reset these.
2319 */
2320 env->cp15.c15_i_max = 0x000;
2321 env->cp15.c15_i_min = 0xff0;
2322 }
2323
2324 static const ARMCPRegInfo omap_cp_reginfo[] = {
2325 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2326 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2327 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2328 .resetvalue = 0, },
2329 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2330 .access = PL1_RW, .type = ARM_CP_NOP },
2331 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2332 .access = PL1_RW,
2333 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2334 .writefn = omap_ticonfig_write },
2335 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2336 .access = PL1_RW,
2337 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2338 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2339 .access = PL1_RW, .resetvalue = 0xff0,
2340 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2341 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2342 .access = PL1_RW,
2343 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2344 .writefn = omap_threadid_write },
2345 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2346 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2347 .type = ARM_CP_NO_RAW,
2348 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2349 /* TODO: Peripheral port remap register:
2350 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2351 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2352 * when MMU is off.
2353 */
2354 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2355 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2356 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2357 .writefn = omap_cachemaint_write },
2358 { .name = "C9", .cp = 15, .crn = 9,
2359 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2360 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2361 REGINFO_SENTINEL
2362 };
2363
2364 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2365 uint64_t value)
2366 {
2367 env->cp15.c15_cpar = value & 0x3fff;
2368 }
2369
2370 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2371 { .name = "XSCALE_CPAR",
2372 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2373 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2374 .writefn = xscale_cpar_write, },
2375 { .name = "XSCALE_AUXCR",
2376 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2377 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2378 .resetvalue = 0, },
2379 /* XScale specific cache-lockdown: since we have no cache we NOP these
2380 * and hope the guest does not really rely on cache behaviour.
2381 */
2382 { .name = "XSCALE_LOCK_ICACHE_LINE",
2383 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2384 .access = PL1_W, .type = ARM_CP_NOP },
2385 { .name = "XSCALE_UNLOCK_ICACHE",
2386 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2387 .access = PL1_W, .type = ARM_CP_NOP },
2388 { .name = "XSCALE_DCACHE_LOCK",
2389 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2390 .access = PL1_RW, .type = ARM_CP_NOP },
2391 { .name = "XSCALE_UNLOCK_DCACHE",
2392 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2393 .access = PL1_W, .type = ARM_CP_NOP },
2394 REGINFO_SENTINEL
2395 };
2396
2397 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2398 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2399 * implementation of this implementation-defined space.
2400 * Ideally this should eventually disappear in favour of actually
2401 * implementing the correct behaviour for all cores.
2402 */
2403 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2404 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2405 .access = PL1_RW,
2406 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2407 .resetvalue = 0 },
2408 REGINFO_SENTINEL
2409 };
2410
2411 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2412 /* Cache status: RAZ because we have no cache so it's always clean */
2413 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2414 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2415 .resetvalue = 0 },
2416 REGINFO_SENTINEL
2417 };
2418
2419 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2420 /* We never have a a block transfer operation in progress */
2421 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2422 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2423 .resetvalue = 0 },
2424 /* The cache ops themselves: these all NOP for QEMU */
2425 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2426 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2427 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2428 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2429 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2430 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2431 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2432 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2433 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2434 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2435 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2436 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2437 REGINFO_SENTINEL
2438 };
2439
2440 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2441 /* The cache test-and-clean instructions always return (1 << 30)
2442 * to indicate that there are no dirty cache lines.
2443 */
2444 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2445 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2446 .resetvalue = (1 << 30) },
2447 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2448 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2449 .resetvalue = (1 << 30) },
2450 REGINFO_SENTINEL
2451 };
2452
2453 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2454 /* Ignore ReadBuffer accesses */
2455 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2456 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2457 .access = PL1_RW, .resetvalue = 0,
2458 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2459 REGINFO_SENTINEL
2460 };
2461
2462 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2463 {
2464 ARMCPU *cpu = arm_env_get_cpu(env);
2465 unsigned int cur_el = arm_current_el(env);
2466 bool secure = arm_is_secure(env);
2467
2468 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2469 return env->cp15.vpidr_el2;
2470 }
2471 return raw_read(env, ri);
2472 }
2473
2474 static uint64_t mpidr_read_val(CPUARMState *env)
2475 {
2476 ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2477 uint64_t mpidr = cpu->mp_affinity;
2478
2479 if (arm_feature(env, ARM_FEATURE_V7MP)) {
2480 mpidr |= (1U << 31);
2481 /* Cores which are uniprocessor (non-coherent)
2482 * but still implement the MP extensions set
2483 * bit 30. (For instance, Cortex-R5).
2484 */
2485 if (cpu->mp_is_up) {
2486 mpidr |= (1u << 30);
2487 }
2488 }
2489 return mpidr;
2490 }
2491
2492 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2493 {
2494 unsigned int cur_el = arm_current_el(env);
2495 bool secure = arm_is_secure(env);
2496
2497 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2498 return env->cp15.vmpidr_el2;
2499 }
2500 return mpidr_read_val(env);
2501 }
2502
2503 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2504 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2505 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2506 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2507 REGINFO_SENTINEL
2508 };
2509
2510 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2511 /* NOP AMAIR0/1 */
2512 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2513 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2514 .access = PL1_RW, .type = ARM_CP_CONST,
2515 .resetvalue = 0 },
2516 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2517 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2518 .access = PL1_RW, .type = ARM_CP_CONST,
2519 .resetvalue = 0 },
2520 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2521 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2522 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2523 offsetof(CPUARMState, cp15.par_ns)} },
2524 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2525 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2526 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2527 offsetof(CPUARMState, cp15.ttbr0_ns) },
2528 .writefn = vmsa_ttbr_write, },
2529 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2530 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2531 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2532 offsetof(CPUARMState, cp15.ttbr1_ns) },
2533 .writefn = vmsa_ttbr_write, },
2534 REGINFO_SENTINEL
2535 };
2536
2537 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2538 {
2539 return vfp_get_fpcr(env);
2540 }
2541
2542 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2543 uint64_t value)
2544 {
2545 vfp_set_fpcr(env, value);
2546 }
2547
2548 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2549 {
2550 return vfp_get_fpsr(env);
2551 }
2552
2553 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2554 uint64_t value)
2555 {
2556 vfp_set_fpsr(env, value);
2557 }
2558
2559 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
2560 {
2561 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2562 return CP_ACCESS_TRAP;
2563 }
2564 return CP_ACCESS_OK;
2565 }
2566
2567 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2568 uint64_t value)
2569 {
2570 env->daif = value & PSTATE_DAIF;
2571 }
2572
2573 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2574 const ARMCPRegInfo *ri)
2575 {
2576 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2577 * SCTLR_EL1.UCI is set.
2578 */
2579 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2580 return CP_ACCESS_TRAP;
2581 }
2582 return CP_ACCESS_OK;
2583 }
2584
2585 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2586 * Page D4-1736 (DDI0487A.b)
2587 */
2588
2589 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2590 uint64_t value)
2591 {
2592 ARMCPU *cpu = arm_env_get_cpu(env);
2593 CPUState *cs = CPU(cpu);
2594
2595 if (arm_is_secure_below_el3(env)) {
2596 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2597 } else {
2598 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2599 }
2600 }
2601
2602 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2603 uint64_t value)
2604 {
2605 bool sec = arm_is_secure_below_el3(env);
2606 CPUState *other_cs;
2607
2608 CPU_FOREACH(other_cs) {
2609 if (sec) {
2610 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2611 } else {
2612 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2613 ARMMMUIdx_S12NSE0, -1);
2614 }
2615 }
2616 }
2617
2618 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2619 uint64_t value)
2620 {
2621 /* Note that the 'ALL' scope must invalidate both stage 1 and
2622 * stage 2 translations, whereas most other scopes only invalidate
2623 * stage 1 translations.
2624 */
2625 ARMCPU *cpu = arm_env_get_cpu(env);
2626 CPUState *cs = CPU(cpu);
2627
2628 if (arm_is_secure_below_el3(env)) {
2629 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2630 } else {
2631 if (arm_feature(env, ARM_FEATURE_EL2)) {
2632 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2633 ARMMMUIdx_S2NS, -1);
2634 } else {
2635 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2636 }
2637 }
2638 }
2639
2640 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2641 uint64_t value)
2642 {
2643 ARMCPU *cpu = arm_env_get_cpu(env);
2644 CPUState *cs = CPU(cpu);
2645
2646 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2647 }
2648
2649 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2650 uint64_t value)
2651 {
2652 ARMCPU *cpu = arm_env_get_cpu(env);
2653 CPUState *cs = CPU(cpu);
2654
2655 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2656 }
2657
2658 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2659 uint64_t value)
2660 {
2661 /* Note that the 'ALL' scope must invalidate both stage 1 and
2662 * stage 2 translations, whereas most other scopes only invalidate
2663 * stage 1 translations.
2664 */
2665 bool sec = arm_is_secure_below_el3(env);
2666 bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2667 CPUState *other_cs;
2668
2669 CPU_FOREACH(other_cs) {
2670 if (sec) {
2671 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2672 } else if (has_el2) {
2673 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2674 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2675 } else {
2676 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2677 ARMMMUIdx_S12NSE0, -1);
2678 }
2679 }
2680 }
2681
2682 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2683 uint64_t value)
2684 {
2685 CPUState *other_cs;
2686
2687 CPU_FOREACH(other_cs) {
2688 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2689 }
2690 }
2691
2692 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2693 uint64_t value)
2694 {
2695 CPUState *other_cs;
2696
2697 CPU_FOREACH(other_cs) {
2698 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2699 }
2700 }
2701
2702 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2703 uint64_t value)
2704 {
2705 /* Invalidate by VA, EL1&0 (AArch64 version).
2706 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2707 * since we don't support flush-for-specific-ASID-only or
2708 * flush-last-level-only.
2709 */
2710 ARMCPU *cpu = arm_env_get_cpu(env);
2711 CPUState *cs = CPU(cpu);
2712 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2713
2714 if (arm_is_secure_below_el3(env)) {
2715 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2716 ARMMMUIdx_S1SE0, -1);
2717 } else {
2718 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2719 ARMMMUIdx_S12NSE0, -1);
2720 }
2721 }
2722
2723 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2724 uint64_t value)
2725 {
2726 /* Invalidate by VA, EL2
2727 * Currently handles both VAE2 and VALE2, since we don't support
2728 * flush-last-level-only.
2729 */
2730 ARMCPU *cpu = arm_env_get_cpu(env);
2731 CPUState *cs = CPU(cpu);
2732 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2733
2734 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2735 }
2736
2737 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2738 uint64_t value)
2739 {
2740 /* Invalidate by VA, EL3
2741 * Currently handles both VAE3 and VALE3, since we don't support
2742 * flush-last-level-only.
2743 */
2744 ARMCPU *cpu = arm_env_get_cpu(env);
2745 CPUState *cs = CPU(cpu);
2746 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2747
2748 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2749 }
2750
2751 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2752 uint64_t value)
2753 {
2754 bool sec = arm_is_secure_below_el3(env);
2755 CPUState *other_cs;
2756 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2757
2758 CPU_FOREACH(other_cs) {
2759 if (sec) {
2760 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2761 ARMMMUIdx_S1SE0, -1);
2762 } else {
2763 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2764 ARMMMUIdx_S12NSE0, -1);
2765 }
2766 }
2767 }
2768
2769 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2770 uint64_t value)
2771 {
2772 CPUState *other_cs;
2773 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2774
2775 CPU_FOREACH(other_cs) {
2776 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2777 }
2778 }
2779
2780 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2781 uint64_t value)
2782 {
2783 CPUState *other_cs;
2784 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2785
2786 CPU_FOREACH(other_cs) {
2787 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2788 }
2789 }
2790
2791 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2792 uint64_t value)
2793 {
2794 /* Invalidate by IPA. This has to invalidate any structures that
2795 * contain only stage 2 translation information, but does not need
2796 * to apply to structures that contain combined stage 1 and stage 2
2797 * translation information.
2798 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2799 */
2800 ARMCPU *cpu = arm_env_get_cpu(env);
2801 CPUState *cs = CPU(cpu);
2802 uint64_t pageaddr;
2803
2804 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2805 return;
2806 }
2807
2808 pageaddr = sextract64(value << 12, 0, 48);
2809
2810 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2811 }
2812
2813 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2814 uint64_t value)
2815 {
2816 CPUState *other_cs;
2817 uint64_t pageaddr;
2818
2819 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2820 return;
2821 }
2822
2823 pageaddr = sextract64(value << 12, 0, 48);
2824
2825 CPU_FOREACH(other_cs) {
2826 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2827 }
2828 }
2829
2830 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2831 {
2832 /* We don't implement EL2, so the only control on DC ZVA is the
2833 * bit in the SCTLR which can prohibit access for EL0.
2834 */
2835 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2836 return CP_ACCESS_TRAP;
2837 }
2838 return CP_ACCESS_OK;
2839 }
2840
2841 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2842 {
2843 ARMCPU *cpu = arm_env_get_cpu(env);
2844 int dzp_bit = 1 << 4;
2845
2846 /* DZP indicates whether DC ZVA access is allowed */
2847 if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2848 dzp_bit = 0;
2849 }
2850 return cpu->dcz_blocksize | dzp_bit;
2851 }
2852
2853 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2854 {
2855 if (!(env->pstate & PSTATE_SP)) {
2856 /* Access to SP_EL0 is undefined if it's being used as
2857 * the stack pointer.
2858 */
2859 return CP_ACCESS_TRAP_UNCATEGORIZED;
2860 }
2861 return CP_ACCESS_OK;
2862 }
2863
2864 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2865 {
2866 return env->pstate & PSTATE_SP;
2867 }
2868
2869 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2870 {
2871 update_spsel(env, val);
2872 }
2873
2874 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2875 uint64_t value)
2876 {
2877 ARMCPU *cpu = arm_env_get_cpu(env);
2878
2879 if (raw_read(env, ri) == value) {
2880 /* Skip the TLB flush if nothing actually changed; Linux likes
2881 * to do a lot of pointless SCTLR writes.
2882 */
2883 return;
2884 }
2885
2886 raw_write(env, ri, value);
2887 /* ??? Lots of these bits are not implemented. */
2888 /* This may enable/disable the MMU, so do a TLB flush. */
2889 tlb_flush(CPU(cpu), 1);
2890 }
2891
2892 static const ARMCPRegInfo v8_cp_reginfo[] = {
2893 /* Minimal set of EL0-visible registers. This will need to be expanded
2894 * significantly for system emulation of AArch64 CPUs.
2895 */
2896 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2897 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2898 .access = PL0_RW, .type = ARM_CP_NZCV },
2899 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2900 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2901 .type = ARM_CP_NO_RAW,
2902 .access = PL0_RW, .accessfn = aa64_daif_access,
2903 .fieldoffset = offsetof(CPUARMState, daif),
2904 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2905 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2906 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2907 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2908 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2909 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2910 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2911 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2912 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2913 .access = PL0_R, .type = ARM_CP_NO_RAW,
2914 .readfn = aa64_dczid_read },
2915 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2916 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2917 .access = PL0_W, .type = ARM_CP_DC_ZVA,
2918 #ifndef CONFIG_USER_ONLY
2919 /* Avoid overhead of an access check that always passes in user-mode */
2920 .accessfn = aa64_zva_access,
2921 #endif
2922 },
2923 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2924 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2925 .access = PL1_R, .type = ARM_CP_CURRENTEL },
2926 /* Cache ops: all NOPs since we don't emulate caches */
2927 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2928 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2929 .access = PL1_W, .type = ARM_CP_NOP },
2930 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2931 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2932 .access = PL1_W, .type = ARM_CP_NOP },
2933 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2934 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2935 .access = PL0_W, .type = ARM_CP_NOP,
2936 .accessfn = aa64_cacheop_access },
2937 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2938 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2939 .access = PL1_W, .type = ARM_CP_NOP },
2940 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2941 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2942 .access = PL1_W, .type = ARM_CP_NOP },
2943 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2944 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2945 .access = PL0_W, .type = ARM_CP_NOP,
2946 .accessfn = aa64_cacheop_access },
2947 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2948 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2949 .access = PL1_W, .type = ARM_CP_NOP },
2950 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2951 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2952 .access = PL0_W, .type = ARM_CP_NOP,
2953 .accessfn = aa64_cacheop_access },
2954 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2955 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2956 .access = PL0_W, .type = ARM_CP_NOP,
2957 .accessfn = aa64_cacheop_access },
2958 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2959 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2960 .access = PL1_W, .type = ARM_CP_NOP },
2961 /* TLBI operations */
2962 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2963 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2964 .access = PL1_W, .type = ARM_CP_NO_RAW,
2965 .writefn = tlbi_aa64_vmalle1is_write },
2966 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2967 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2968 .access = PL1_W, .type = ARM_CP_NO_RAW,
2969 .writefn = tlbi_aa64_vae1is_write },
2970 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2971 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2972 .access = PL1_W, .type = ARM_CP_NO_RAW,
2973 .writefn = tlbi_aa64_vmalle1is_write },
2974 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2975 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2976 .access = PL1_W, .type = ARM_CP_NO_RAW,
2977 .writefn = tlbi_aa64_vae1is_write },
2978 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2979 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2980 .access = PL1_W, .type = ARM_CP_NO_RAW,
2981 .writefn = tlbi_aa64_vae1is_write },
2982 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2983 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2984 .access = PL1_W, .type = ARM_CP_NO_RAW,
2985 .writefn = tlbi_aa64_vae1is_write },
2986 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2987 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2988 .access = PL1_W, .type = ARM_CP_NO_RAW,
2989 .writefn = tlbi_aa64_vmalle1_write },
2990 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2991 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2992 .access = PL1_W, .type = ARM_CP_NO_RAW,
2993 .writefn = tlbi_aa64_vae1_write },
2994 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2995 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2996 .access = PL1_W, .type = ARM_CP_NO_RAW,
2997 .writefn = tlbi_aa64_vmalle1_write },
2998 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2999 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3000 .access = PL1_W, .type = ARM_CP_NO_RAW,
3001 .writefn = tlbi_aa64_vae1_write },
3002 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3003 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3004 .access = PL1_W, .type = ARM_CP_NO_RAW,
3005 .writefn = tlbi_aa64_vae1_write },
3006 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3007 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3008 .access = PL1_W, .type = ARM_CP_NO_RAW,
3009 .writefn = tlbi_aa64_vae1_write },
3010 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3011 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3012 .access = PL2_W, .type = ARM_CP_NO_RAW,
3013 .writefn = tlbi_aa64_ipas2e1is_write },
3014 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3015 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3016 .access = PL2_W, .type = ARM_CP_NO_RAW,
3017 .writefn = tlbi_aa64_ipas2e1is_write },
3018 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3019 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3020 .access = PL2_W, .type = ARM_CP_NO_RAW,
3021 .writefn = tlbi_aa64_alle1is_write },
3022 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3023 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3024 .access = PL2_W, .type = ARM_CP_NO_RAW,
3025 .writefn = tlbi_aa64_alle1is_write },
3026 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3027 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3028 .access = PL2_W, .type = ARM_CP_NO_RAW,
3029 .writefn = tlbi_aa64_ipas2e1_write },
3030 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3031 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3032 .access = PL2_W, .type = ARM_CP_NO_RAW,
3033 .writefn = tlbi_aa64_ipas2e1_write },
3034 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3035 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3036 .access = PL2_W, .type = ARM_CP_NO_RAW,
3037 .writefn = tlbi_aa64_alle1_write },
3038 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3039 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3040 .access = PL2_W, .type = ARM_CP_NO_RAW,
3041 .writefn = tlbi_aa64_alle1is_write },
3042 #ifndef CONFIG_USER_ONLY
3043 /* 64 bit address translation operations */
3044 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3045 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3046 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3047 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3048 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3049 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3050 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3051 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3052 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3053 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3054 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3055 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3056 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3057 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3058 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3059 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3060 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3061 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3062 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3063 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3064 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3065 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3066 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3067 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3068 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3069 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3070 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3071 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3072 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3073 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3074 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3075 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3076 .type = ARM_CP_ALIAS,
3077 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3078 .access = PL1_RW, .resetvalue = 0,
3079 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3080 .writefn = par_write },
3081 #endif
3082 /* TLB invalidate last level of translation table walk */
3083 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3084 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3085 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3086 .type = ARM_CP_NO_RAW, .access = PL1_W,
3087 .writefn = tlbimvaa_is_write },
3088 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3089 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3090 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3091 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3092 /* 32 bit cache operations */
3093 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3094 .type = ARM_CP_NOP, .access = PL1_W },
3095 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3096 .type = ARM_CP_NOP, .access = PL1_W },
3097 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3098 .type = ARM_CP_NOP, .access = PL1_W },
3099 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3100 .type = ARM_CP_NOP, .access = PL1_W },
3101 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3102 .type = ARM_CP_NOP, .access = PL1_W },
3103 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3104 .type = ARM_CP_NOP, .access = PL1_W },
3105 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3106 .type = ARM_CP_NOP, .access = PL1_W },
3107 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3108 .type = ARM_CP_NOP, .access = PL1_W },
3109 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3110 .type = ARM_CP_NOP, .access = PL1_W },
3111 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3112 .type = ARM_CP_NOP, .access = PL1_W },
3113 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3114 .type = ARM_CP_NOP, .access = PL1_W },
3115 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3116 .type = ARM_CP_NOP, .access = PL1_W },
3117 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3118 .type = ARM_CP_NOP, .access = PL1_W },
3119 /* MMU Domain access control / MPU write buffer control */
3120 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3121 .access = PL1_RW, .resetvalue = 0,
3122 .writefn = dacr_write, .raw_writefn = raw_write,
3123 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3124 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3125 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3126 .type = ARM_CP_ALIAS,
3127 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3128 .access = PL1_RW,
3129 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3130 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3131 .type = ARM_CP_ALIAS,
3132 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3133 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
3134 /* We rely on the access checks not allowing the guest to write to the
3135 * state field when SPSel indicates that it's being used as the stack
3136 * pointer.
3137 */
3138 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3139 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3140 .access = PL1_RW, .accessfn = sp_el0_access,
3141 .type = ARM_CP_ALIAS,
3142 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3143 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3144 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3145 .access = PL2_RW, .type = ARM_CP_ALIAS,
3146 .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3147 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3148 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3149 .type = ARM_CP_NO_RAW,
3150 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3151 REGINFO_SENTINEL
3152 };
3153
3154 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3155 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3156 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3157 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3158 .access = PL2_RW,
3159 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3160 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3161 .type = ARM_CP_NO_RAW,
3162 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3163 .access = PL2_RW,
3164 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3165 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3166 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3167 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3168 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3169 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3170 .access = PL2_RW, .type = ARM_CP_CONST,
3171 .resetvalue = 0 },
3172 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3173 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3174 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3175 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3176 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3177 .access = PL2_RW, .type = ARM_CP_CONST,
3178 .resetvalue = 0 },
3179 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3180 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3181 .access = PL2_RW, .type = ARM_CP_CONST,
3182 .resetvalue = 0 },
3183 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3184 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3185 .access = PL2_RW, .type = ARM_CP_CONST,
3186 .resetvalue = 0 },
3187 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3188 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3189 .access = PL2_RW, .type = ARM_CP_CONST,
3190 .resetvalue = 0 },
3191 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3192 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3193 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3194 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3195 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3196 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3197 .type = ARM_CP_CONST, .resetvalue = 0 },
3198 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3199 .cp = 15, .opc1 = 6, .crm = 2,
3200 .access = PL2_RW, .accessfn = access_el3_aa32ns,
3201 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3202 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3203 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3204 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3205 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3206 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3207 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3208 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3209 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3210 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3211 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3212 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3213 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3214 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3215 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3216 .resetvalue = 0 },
3217 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3218 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3219 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3220 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3221 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3222 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3223 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3224 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3225 .resetvalue = 0 },
3226 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3227 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3228 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3229 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3230 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3231 .resetvalue = 0 },
3232 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3233 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3234 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3235 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3236 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3237 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3238 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3239 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3240 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3241 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3242 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3243 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3244 .type = ARM_CP_CONST, .resetvalue = 0 },
3245 REGINFO_SENTINEL
3246 };
3247
3248 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3249 {
3250 ARMCPU *cpu = arm_env_get_cpu(env);
3251 uint64_t valid_mask = HCR_MASK;
3252
3253 if (arm_feature(env, ARM_FEATURE_EL3)) {
3254 valid_mask &= ~HCR_HCD;
3255 } else {
3256 valid_mask &= ~HCR_TSC;
3257 }
3258
3259 /* Clear RES0 bits. */
3260 value &= valid_mask;
3261
3262 /* These bits change the MMU setup:
3263 * HCR_VM enables stage 2 translation
3264 * HCR_PTW forbids certain page-table setups
3265 * HCR_DC Disables stage1 and enables stage2 translation
3266 */
3267 if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3268 tlb_flush(CPU(cpu), 1);
3269 }
3270 raw_write(env, ri, value);
3271 }
3272
3273 static const ARMCPRegInfo el2_cp_reginfo[] = {
3274 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3275 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3276 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3277 .writefn = hcr_write },
3278 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3279 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3280 .access = PL2_RW, .resetvalue = 0,
3281 .writefn = dacr_write, .raw_writefn = raw_write,
3282 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3283 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3284 .type = ARM_CP_ALIAS,
3285 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3286 .access = PL2_RW,
3287 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3288 { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3289 .type = ARM_CP_ALIAS,
3290 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3291 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3292 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3293 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3294 .access = PL2_RW, .resetvalue = 0,
3295 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3296 { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3297 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3298 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3299 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3300 .type = ARM_CP_ALIAS,
3301 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3302 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
3303 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3304 .type = ARM_CP_ALIAS,
3305 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3306 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[4]) },
3307 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3308 .type = ARM_CP_ALIAS,
3309 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3310 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[2]) },
3311 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3312 .type = ARM_CP_ALIAS,
3313 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3314 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[3]) },
3315 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3316 .type = ARM_CP_ALIAS,
3317 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3318 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[5]) },
3319 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3320 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3321 .access = PL2_RW, .writefn = vbar_write,
3322 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3323 .resetvalue = 0 },
3324 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3325 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3326 .access = PL3_RW, .type = ARM_CP_ALIAS,
3327 .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3328 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3329 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3330 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3331 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3332 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3333 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3334 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3335 .resetvalue = 0 },
3336 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3337 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3338 .access = PL2_RW, .type = ARM_CP_ALIAS,
3339 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3340 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3341 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3342 .access = PL2_RW, .type = ARM_CP_CONST,
3343 .resetvalue = 0 },
3344 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3345 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3346 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3347 .access = PL2_RW, .type = ARM_CP_CONST,
3348 .resetvalue = 0 },
3349 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3350 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3351 .access = PL2_RW, .type = ARM_CP_CONST,
3352 .resetvalue = 0 },
3353 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3354 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3355 .access = PL2_RW, .type = ARM_CP_CONST,
3356 .resetvalue = 0 },
3357 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3358 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3359 .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
3360 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3361 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3362 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3363 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3364 .access = PL2_RW, .accessfn = access_el3_aa32ns,
3365 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3366 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3367 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3368 .access = PL2_RW, .type = ARM_CP_ALIAS,
3369 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3370 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3371 .cp = 15, .opc1 = 6, .crm = 2,
3372 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3373 .access = PL2_RW, .accessfn = access_el3_aa32ns,
3374 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3375 .writefn = vttbr_write },
3376 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3377 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3378 .access = PL2_RW, .writefn = vttbr_write,
3379 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3380 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3381 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3382 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3383 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3384 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3385 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3386 .access = PL2_RW, .resetvalue = 0,
3387 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3388 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3389 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3390 .access = PL2_RW, .resetvalue = 0,
3391 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3392 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3393 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3394 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3395 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3396 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3397 .type = ARM_CP_NO_RAW, .access = PL2_W,
3398 .writefn = tlbi_aa64_alle2_write },
3399 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3400 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3401 .type = ARM_CP_NO_RAW, .access = PL2_W,
3402 .writefn = tlbi_aa64_vae2_write },
3403 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3404 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3405 .access = PL2_W, .type = ARM_CP_NO_RAW,
3406 .writefn = tlbi_aa64_vae2_write },
3407 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3408 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3409 .access = PL2_W, .type = ARM_CP_NO_RAW,
3410 .writefn = tlbi_aa64_alle2is_write },
3411 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3412 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3413 .type = ARM_CP_NO_RAW, .access = PL2_W,
3414 .writefn = tlbi_aa64_vae2is_write },
3415 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3416 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3417 .access = PL2_W, .type = ARM_CP_NO_RAW,
3418 .writefn = tlbi_aa64_vae2is_write },
3419 #ifndef CONFIG_USER_ONLY
3420 /* Unlike the other EL2-related AT operations, these must
3421 * UNDEF from EL3 if EL2 is not implemented, which is why we
3422 * define them here rather than with the rest of the AT ops.
3423 */
3424 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3425 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3426 .access = PL2_W, .accessfn = at_s1e2_access,
3427 .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3428 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3429 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3430 .access = PL2_W, .accessfn = at_s1e2_access,
3431 .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3432 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3433 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3434 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3435 * to behave as if SCR.NS was 1.
3436 */
3437 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3438 .access = PL2_W,
3439 .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3440 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3441 .access = PL2_W,
3442 .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3443 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3444 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3445 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3446 * reset values as IMPDEF. We choose to reset to 3 to comply with
3447 * both ARMv7 and ARMv8.
3448 */
3449 .access = PL2_RW, .resetvalue = 3,
3450 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3451 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3452 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3453 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3454 .writefn = gt_cntvoff_write,
3455 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3456 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3457 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3458 .writefn = gt_cntvoff_write,
3459 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3460 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3461 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3462 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3463 .type = ARM_CP_IO, .access = PL2_RW,
3464 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3465 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3466 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3467 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3468 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3469 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3470 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3471 .type = ARM_CP_IO, .access = PL2_RW,
3472 .resetfn = gt_hyp_timer_reset,
3473 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3474 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3475 .type = ARM_CP_IO,
3476 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3477 .access = PL2_RW,
3478 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3479 .resetvalue = 0,
3480 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3481 #endif
3482 /* The only field of MDCR_EL2 that has a defined architectural reset value
3483 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3484 * don't impelment any PMU event counters, so using zero as a reset
3485 * value for MDCR_EL2 is okay
3486 */
3487 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3488 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3489 .access = PL2_RW, .resetvalue = 0,
3490 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3491 { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3492 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3493 .access = PL2_RW, .accessfn = access_el3_aa32ns,
3494 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3495 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3496 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3497 .access = PL2_RW,
3498 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3499 REGINFO_SENTINEL
3500 };
3501
3502 static const ARMCPRegInfo el3_cp_reginfo[] = {
3503 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3504 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3505 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3506 .resetvalue = 0, .writefn = scr_write },
3507 { .name = "SCR", .type = ARM_CP_ALIAS,
3508 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3509 .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3510 .writefn = scr_write },
3511 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3512 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3513 .access = PL3_RW, .resetvalue = 0,
3514 .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3515 { .name = "SDER",
3516 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3517 .access = PL3_RW, .resetvalue = 0,
3518 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3519 /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
3520 { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
3521 .access = PL3_W | PL1_R, .resetvalue = 0,
3522 .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
3523 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3524 .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
3525 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3526 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
3527 .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
3528 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
3529 .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3530 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
3531 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3532 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3533 .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3534 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3535 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3536 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3537 .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
3538 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3539 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3540 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3541 .type = ARM_CP_ALIAS,
3542 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3543 .access = PL3_RW,
3544 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3545 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3546 .type = ARM_CP_ALIAS,
3547 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3548 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3549 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3550 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3551 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3552 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3553 .type = ARM_CP_ALIAS,
3554 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3555 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
3556 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3557 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3558 .access = PL3_RW, .writefn = vbar_write,
3559 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3560 .resetvalue = 0 },
3561 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3562 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3563 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3564 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3565 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3566 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3567 .access = PL3_RW, .resetvalue = 0,
3568 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3569 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3570 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3571 .access = PL3_RW, .type = ARM_CP_CONST,
3572 .resetvalue = 0 },
3573 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3574 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3575 .access = PL3_RW, .type = ARM_CP_CONST,
3576 .resetvalue = 0 },
3577 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3578 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3579 .access = PL3_RW, .type = ARM_CP_CONST,
3580 .resetvalue = 0 },
3581 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3582 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3583 .access = PL3_W, .type = ARM_CP_NO_RAW,
3584 .writefn = tlbi_aa64_alle3is_write },
3585 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3586 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3587 .access = PL3_W, .type = ARM_CP_NO_RAW,
3588 .writefn = tlbi_aa64_vae3is_write },
3589 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3590 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3591 .access = PL3_W, .type = ARM_CP_NO_RAW,
3592 .writefn = tlbi_aa64_vae3is_write },
3593 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3594 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3595 .access = PL3_W, .type = ARM_CP_NO_RAW,
3596 .writefn = tlbi_aa64_alle3_write },
3597 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3598 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3599 .access = PL3_W, .type = ARM_CP_NO_RAW,
3600 .writefn = tlbi_aa64_vae3_write },
3601 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3602 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3603 .access = PL3_W, .type = ARM_CP_NO_RAW,
3604 .writefn = tlbi_aa64_vae3_write },
3605 REGINFO_SENTINEL
3606 };
3607
3608 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
3609 {
3610 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3611 * but the AArch32 CTR has its own reginfo struct)
3612 */
3613 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3614 return CP_ACCESS_TRAP;
3615 }
3616 return CP_ACCESS_OK;
3617 }
3618
3619 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3620 uint64_t value)
3621 {
3622 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3623 * read via a bit in OSLSR_EL1.
3624 */
3625 int oslock;
3626
3627 if (ri->state == ARM_CP_STATE_AA32) {
3628 oslock = (value == 0xC5ACCE55);
3629 } else {
3630 oslock = value & 1;
3631 }
3632
3633 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
3634 }
3635
3636 static const ARMCPRegInfo debug_cp_reginfo[] = {
3637 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3638 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3639 * unlike DBGDRAR it is never accessible from EL0.
3640 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3641 * accessor.
3642 */
3643 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3644 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3645 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3646 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3647 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3648 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3649 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3650 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3651 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3652 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3653 .access = PL1_RW,
3654 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3655 .resetvalue = 0 },
3656 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3657 * We don't implement the configurable EL0 access.
3658 */
3659 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3660 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3661 .type = ARM_CP_ALIAS,
3662 .access = PL1_R,
3663 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3664 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3665 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3666 .access = PL1_W, .type = ARM_CP_NO_RAW,
3667 .writefn = oslar_write },
3668 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
3669 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
3670 .access = PL1_R, .resetvalue = 10,
3671 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
3672 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3673 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3674 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3675 .access = PL1_RW, .type = ARM_CP_NOP },
3676 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3677 * implement vector catch debug events yet.
3678 */
3679 { .name = "DBGVCR",
3680 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3681 .access = PL1_RW, .type = ARM_CP_NOP },
3682 REGINFO_SENTINEL
3683 };
3684
3685 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3686 /* 64 bit access versions of the (dummy) debug registers */
3687 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3688 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3689 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3690 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3691 REGINFO_SENTINEL
3692 };
3693
3694 void hw_watchpoint_update(ARMCPU *cpu, int n)
3695 {
3696 CPUARMState *env = &cpu->env;
3697 vaddr len = 0;
3698 vaddr wvr = env->cp15.dbgwvr[n];
3699 uint64_t wcr = env->cp15.dbgwcr[n];
3700 int mask;
3701 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3702
3703 if (env->cpu_watchpoint[n]) {
3704 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3705 env->cpu_watchpoint[n] = NULL;
3706 }
3707
3708 if (!extract64(wcr, 0, 1)) {
3709 /* E bit clear : watchpoint disabled */
3710 return;
3711 }
3712
3713 switch (extract64(wcr, 3, 2)) {
3714 case 0:
3715 /* LSC 00 is reserved and must behave as if the wp is disabled */
3716 return;
3717 case 1:
3718 flags |= BP_MEM_READ;
3719 break;
3720 case 2:
3721 flags |= BP_MEM_WRITE;
3722 break;
3723 case 3:
3724 flags |= BP_MEM_ACCESS;
3725 break;
3726 }
3727
3728 /* Attempts to use both MASK and BAS fields simultaneously are
3729 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3730 * thus generating a watchpoint for every byte in the masked region.
3731 */
3732 mask = extract64(wcr, 24, 4);
3733 if (mask == 1 || mask == 2) {
3734 /* Reserved values of MASK; we must act as if the mask value was
3735 * some non-reserved value, or as if the watchpoint were disabled.
3736 * We choose the latter.
3737 */
3738 return;
3739 } else if (mask) {
3740 /* Watchpoint covers an aligned area up to 2GB in size */
3741 len = 1ULL << mask;
3742 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3743 * whether the watchpoint fires when the unmasked bits match; we opt
3744 * to generate the exceptions.
3745 */
3746 wvr &= ~(len - 1);
3747 } else {
3748 /* Watchpoint covers bytes defined by the byte address select bits */
3749 int bas = extract64(wcr, 5, 8);
3750 int basstart;
3751
3752 if (bas == 0) {
3753 /* This must act as if the watchpoint is disabled */
3754 return;
3755 }
3756
3757 if (extract64(wvr, 2, 1)) {
3758 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3759 * ignored, and BAS[3:0] define which bytes to watch.
3760 */
3761 bas &= 0xf;
3762 }
3763 /* The BAS bits are supposed to be programmed to indicate a contiguous
3764 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3765 * we fire for each byte in the word/doubleword addressed by the WVR.
3766 * We choose to ignore any non-zero bits after the first range of 1s.
3767 */
3768 basstart = ctz32(bas);
3769 len = cto32(bas >> basstart);
3770 wvr += basstart;
3771 }
3772
3773 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
3774 &env->cpu_watchpoint[n]);
3775 }
3776
3777 void hw_watchpoint_update_all(ARMCPU *cpu)
3778 {
3779 int i;
3780 CPUARMState *env = &cpu->env;
3781
3782 /* Completely clear out existing QEMU watchpoints and our array, to
3783 * avoid possible stale entries following migration load.
3784 */
3785 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
3786 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
3787
3788 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
3789 hw_watchpoint_update(cpu, i);
3790 }
3791 }
3792
3793 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3794 uint64_t value)
3795 {
3796 ARMCPU *cpu = arm_env_get_cpu(env);
3797 int i = ri->crm;
3798
3799 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
3800 * register reads and behaves as if values written are sign extended.
3801 * Bits [1:0] are RES0.
3802 */
3803 value = sextract64(value, 0, 49) & ~3ULL;
3804
3805 raw_write(env, ri, value);
3806 hw_watchpoint_update(cpu, i);
3807 }
3808
3809 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3810 uint64_t value)
3811 {
3812 ARMCPU *cpu = arm_env_get_cpu(env);
3813 int i = ri->crm;
3814
3815 raw_write(env, ri, value);
3816 hw_watchpoint_update(cpu, i);
3817 }
3818
3819 void hw_breakpoint_update(ARMCPU *cpu, int n)
3820 {
3821 CPUARMState *env = &cpu->env;
3822 uint64_t bvr = env->cp15.dbgbvr[n];
3823 uint64_t bcr = env->cp15.dbgbcr[n];
3824 vaddr addr;
3825 int bt;
3826 int flags = BP_CPU;
3827
3828 if (env->cpu_breakpoint[n]) {
3829 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
3830 env->cpu_breakpoint[n] = NULL;
3831 }
3832
3833 if (!extract64(bcr, 0, 1)) {
3834 /* E bit clear : watchpoint disabled */
3835 return;
3836 }
3837
3838 bt = extract64(bcr, 20, 4);
3839
3840 switch (bt) {
3841 case 4: /* unlinked address mismatch (reserved if AArch64) */
3842 case 5: /* linked address mismatch (reserved if AArch64) */
3843 qemu_log_mask(LOG_UNIMP,
3844 "arm: address mismatch breakpoint types not implemented");
3845 return;
3846 case 0: /* unlinked address match */
3847 case 1: /* linked address match */
3848 {
3849 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
3850 * we behave as if the register was sign extended. Bits [1:0] are
3851 * RES0. The BAS field is used to allow setting breakpoints on 16
3852 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
3853 * a bp will fire if the addresses covered by the bp and the addresses
3854 * covered by the insn overlap but the insn doesn't start at the
3855 * start of the bp address range. We choose to require the insn and
3856 * the bp to have the same address. The constraints on writing to
3857 * BAS enforced in dbgbcr_write mean we have only four cases:
3858 * 0b0000 => no breakpoint
3859 * 0b0011 => breakpoint on addr
3860 * 0b1100 => breakpoint on addr + 2
3861 * 0b1111 => breakpoint on addr
3862 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
3863 */
3864 int bas = extract64(bcr, 5, 4);
3865 addr = sextract64(bvr, 0, 49) & ~3ULL;
3866 if (bas == 0) {
3867 return;
3868 }
3869 if (bas == 0xc) {
3870 addr += 2;
3871 }
3872 break;
3873 }
3874 case 2: /* unlinked context ID match */
3875 case 8: /* unlinked VMID match (reserved if no EL2) */
3876 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
3877 qemu_log_mask(LOG_UNIMP,
3878 "arm: unlinked context breakpoint types not implemented");
3879 return;
3880 case 9: /* linked VMID match (reserved if no EL2) */
3881 case 11: /* linked context ID and VMID match (reserved if no EL2) */
3882 case 3: /* linked context ID match */
3883 default:
3884 /* We must generate no events for Linked context matches (unless
3885 * they are linked to by some other bp/wp, which is handled in
3886 * updates for the linking bp/wp). We choose to also generate no events
3887 * for reserved values.
3888 */
3889 return;
3890 }
3891
3892 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
3893 }
3894
3895 void hw_breakpoint_update_all(ARMCPU *cpu)
3896 {
3897 int i;
3898 CPUARMState *env = &cpu->env;
3899
3900 /* Completely clear out existing QEMU breakpoints and our array, to
3901 * avoid possible stale entries following migration load.
3902 */
3903 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
3904 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
3905
3906 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
3907 hw_breakpoint_update(cpu, i);
3908 }
3909 }
3910
3911 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3912 uint64_t value)
3913 {
3914 ARMCPU *cpu = arm_env_get_cpu(env);
3915 int i = ri->crm;
3916
3917 raw_write(env, ri, value);
3918 hw_breakpoint_update(cpu, i);
3919 }
3920
3921 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3922 uint64_t value)
3923 {
3924 ARMCPU *cpu = arm_env_get_cpu(env);
3925 int i = ri->crm;
3926
3927 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3928 * copy of BAS[0].
3929 */
3930 value = deposit64(value, 6, 1, extract64(value, 5, 1));
3931 value = deposit64(value, 8, 1, extract64(value, 7, 1));
3932
3933 raw_write(env, ri, value);
3934 hw_breakpoint_update(cpu, i);
3935 }
3936
3937 static void define_debug_regs(ARMCPU *cpu)
3938 {
3939 /* Define v7 and v8 architectural debug registers.
3940 * These are just dummy implementations for now.
3941 */
3942 int i;
3943 int wrps, brps, ctx_cmps;
3944 ARMCPRegInfo dbgdidr = {
3945 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
3946 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
3947 };
3948
3949 /* Note that all these register fields hold "number of Xs minus 1". */
3950 brps = extract32(cpu->dbgdidr, 24, 4);
3951 wrps = extract32(cpu->dbgdidr, 28, 4);
3952 ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
3953
3954 assert(ctx_cmps <= brps);
3955
3956 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3957 * of the debug registers such as number of breakpoints;
3958 * check that if they both exist then they agree.
3959 */
3960 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
3961 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
3962 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
3963 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
3964 }
3965
3966 define_one_arm_cp_reg(cpu, &dbgdidr);
3967 define_arm_cp_regs(cpu, debug_cp_reginfo);
3968
3969 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
3970 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
3971 }
3972
3973 for (i = 0; i < brps + 1; i++) {
3974 ARMCPRegInfo dbgregs[] = {
3975 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
3976 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
3977 .access = PL1_RW,
3978 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
3979 .writefn = dbgbvr_write, .raw_writefn = raw_write
3980 },
3981 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
3982 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
3983 .access = PL1_RW,
3984 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
3985 .writefn = dbgbcr_write, .raw_writefn = raw_write
3986 },
3987 REGINFO_SENTINEL
3988 };
3989 define_arm_cp_regs(cpu, dbgregs);
3990 }
3991
3992 for (i = 0; i < wrps + 1; i++) {
3993 ARMCPRegInfo dbgregs[] = {
3994 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
3995 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
3996 .access = PL1_RW,
3997 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
3998 .writefn = dbgwvr_write, .raw_writefn = raw_write
3999 },
4000 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4001 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4002 .access = PL1_RW,
4003 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4004 .writefn = dbgwcr_write, .raw_writefn = raw_write
4005 },
4006 REGINFO_SENTINEL
4007 };
4008 define_arm_cp_regs(cpu, dbgregs);
4009 }
4010 }
4011
4012 void register_cp_regs_for_features(ARMCPU *cpu)
4013 {
4014 /* Register all the coprocessor registers based on feature bits */
4015 CPUARMState *env = &cpu->env;
4016 if (arm_feature(env, ARM_FEATURE_M)) {
4017 /* M profile has no coprocessor registers */
4018 return;
4019 }
4020
4021 define_arm_cp_regs(cpu, cp_reginfo);
4022 if (!arm_feature(env, ARM_FEATURE_V8)) {
4023 /* Must go early as it is full of wildcards that may be
4024 * overridden by later definitions.
4025 */
4026 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4027 }
4028
4029 if (arm_feature(env, ARM_FEATURE_V6)) {
4030 /* The ID registers all have impdef reset values */
4031 ARMCPRegInfo v6_idregs[] = {
4032 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4033 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4034 .access = PL1_R, .type = ARM_CP_CONST,
4035 .resetvalue = cpu->id_pfr0 },
4036 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4037 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4038 .access = PL1_R, .type = ARM_CP_CONST,
4039 .resetvalue = cpu->id_pfr1 },
4040 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4041 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4042 .access = PL1_R, .type = ARM_CP_CONST,
4043 .resetvalue = cpu->id_dfr0 },
4044 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4045 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4046 .access = PL1_R, .type = ARM_CP_CONST,
4047 .resetvalue = cpu->id_afr0 },
4048 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4049 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4050 .access = PL1_R, .type = ARM_CP_CONST,
4051 .resetvalue = cpu->id_mmfr0 },
4052 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4053 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4054 .access = PL1_R, .type = ARM_CP_CONST,
4055 .resetvalue = cpu->id_mmfr1 },
4056 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4057 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4058 .access = PL1_R, .type = ARM_CP_CONST,
4059 .resetvalue = cpu->id_mmfr2 },
4060 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4061 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4062 .access = PL1_R, .type = ARM_CP_CONST,
4063 .resetvalue = cpu->id_mmfr3 },
4064 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4065 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4066 .access = PL1_R, .type = ARM_CP_CONST,
4067 .resetvalue = cpu->id_isar0 },
4068 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4069 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4070 .access = PL1_R, .type = ARM_CP_CONST,
4071 .resetvalue = cpu->id_isar1 },
4072 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4073 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4074 .access = PL1_R, .type = ARM_CP_CONST,
4075 .resetvalue = cpu->id_isar2 },
4076 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4077 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4078 .access = PL1_R, .type = ARM_CP_CONST,
4079 .resetvalue = cpu->id_isar3 },
4080 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4081 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4082 .access = PL1_R, .type = ARM_CP_CONST,
4083 .resetvalue = cpu->id_isar4 },
4084 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4085 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4086 .access = PL1_R, .type = ARM_CP_CONST,
4087 .resetvalue = cpu->id_isar5 },
4088 /* 6..7 are as yet unallocated and must RAZ */
4089 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
4090 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
4091 .resetvalue = 0 },
4092 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
4093 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
4094 .resetvalue = 0 },
4095 REGINFO_SENTINEL
4096 };
4097 define_arm_cp_regs(cpu, v6_idregs);
4098 define_arm_cp_regs(cpu, v6_cp_reginfo);
4099 } else {
4100 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4101 }
4102 if (arm_feature(env, ARM_FEATURE_V6K)) {
4103 define_arm_cp_regs(cpu, v6k_cp_reginfo);
4104 }
4105 if (arm_feature(env, ARM_FEATURE_V7MP) &&
4106 !arm_feature(env, ARM_FEATURE_MPU)) {
4107 define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4108 }
4109 if (arm_feature(env, ARM_FEATURE_V7)) {
4110 /* v7 performance monitor control register: same implementor
4111 * field as main ID register, and we implement only the cycle
4112 * count register.
4113 */
4114 #ifndef CONFIG_USER_ONLY
4115 ARMCPRegInfo pmcr = {
4116 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4117 .access = PL0_RW,
4118 .type = ARM_CP_IO | ARM_CP_ALIAS,
4119 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4120 .accessfn = pmreg_access, .writefn = pmcr_write,
4121 .raw_writefn = raw_write,
4122 };
4123 ARMCPRegInfo pmcr64 = {
4124 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4125 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4126 .access = PL0_RW, .accessfn = pmreg_access,
4127 .type = ARM_CP_IO,
4128 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4129 .resetvalue = cpu->midr & 0xff000000,
4130 .writefn = pmcr_write, .raw_writefn = raw_write,
4131 };
4132 define_one_arm_cp_reg(cpu, &pmcr);
4133 define_one_arm_cp_reg(cpu, &pmcr64);
4134 #endif
4135 ARMCPRegInfo clidr = {
4136 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4137 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4138 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4139 };
4140 define_one_arm_cp_reg(cpu, &clidr);
4141 define_arm_cp_regs(cpu, v7_cp_reginfo);
4142 define_debug_regs(cpu);
4143 } else {
4144 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4145 }
4146 if (arm_feature(env, ARM_FEATURE_V8)) {
4147 /* AArch64 ID registers, which all have impdef reset values */
4148 ARMCPRegInfo v8_idregs[] = {
4149 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4150 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4151 .access = PL1_R, .type = ARM_CP_CONST,
4152 .resetvalue = cpu->id_aa64pfr0 },
4153 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4154 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4155 .access = PL1_R, .type = ARM_CP_CONST,
4156 .resetvalue = cpu->id_aa64pfr1},
4157 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4158 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4159 .access = PL1_R, .type = ARM_CP_CONST,
4160 /* We mask out the PMUVer field, because we don't currently
4161 * implement the PMU. Not advertising it prevents the guest
4162 * from trying to use it and getting UNDEFs on registers we
4163 * don't implement.
4164 */
4165 .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
4166 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4167 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4168 .access = PL1_R, .type = ARM_CP_CONST,
4169 .resetvalue = cpu->id_aa64dfr1 },
4170 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4171 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4172 .access = PL1_R, .type = ARM_CP_CONST,
4173 .resetvalue = cpu->id_aa64afr0 },
4174 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4175 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4176 .access = PL1_R, .type = ARM_CP_CONST,
4177 .resetvalue = cpu->id_aa64afr1 },
4178 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4179 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4180 .access = PL1_R, .type = ARM_CP_CONST,
4181 .resetvalue = cpu->id_aa64isar0 },
4182 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4183 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4184 .access = PL1_R, .type = ARM_CP_CONST,
4185 .resetvalue = cpu->id_aa64isar1 },
4186 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4187 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4188 .access = PL1_R, .type = ARM_CP_CONST,
4189 .resetvalue = cpu->id_aa64mmfr0 },
4190 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4191 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4192 .access = PL1_R, .type = ARM_CP_CONST,
4193 .resetvalue = cpu->id_aa64mmfr1 },
4194 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4195 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4196 .access = PL1_R, .type = ARM_CP_CONST,
4197 .resetvalue = cpu->mvfr0 },
4198 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4199 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4200 .access = PL1_R, .type = ARM_CP_CONST,
4201 .resetvalue = cpu->mvfr1 },
4202 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4203 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4204 .access = PL1_R, .type = ARM_CP_CONST,
4205 .resetvalue = cpu->mvfr2 },
4206 REGINFO_SENTINEL
4207 };
4208 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4209 if (!arm_feature(env, ARM_FEATURE_EL3) &&
4210 !arm_feature(env, ARM_FEATURE_EL2)) {
4211 ARMCPRegInfo rvbar = {
4212 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4213 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4214 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4215 };
4216 define_one_arm_cp_reg(cpu, &rvbar);
4217 }
4218 define_arm_cp_regs(cpu, v8_idregs);
4219 define_arm_cp_regs(cpu, v8_cp_reginfo);
4220 }
4221 if (arm_feature(env, ARM_FEATURE_EL2)) {
4222 uint64_t vmpidr_def = mpidr_read_val(env);
4223 ARMCPRegInfo vpidr_regs[] = {
4224 { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4225 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4226 .access = PL2_RW, .accessfn = access_el3_aa32ns,
4227 .resetvalue = cpu->midr,
4228 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4229 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4230 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4231 .access = PL2_RW, .resetvalue = cpu->midr,
4232 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4233 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4234 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4235 .access = PL2_RW, .accessfn = access_el3_aa32ns,
4236 .resetvalue = vmpidr_def,
4237 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4238 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4239 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4240 .access = PL2_RW,
4241 .resetvalue = vmpidr_def,
4242 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4243 REGINFO_SENTINEL
4244 };
4245 define_arm_cp_regs(cpu, vpidr_regs);
4246 define_arm_cp_regs(cpu, el2_cp_reginfo);
4247 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4248 if (!arm_feature(env, ARM_FEATURE_EL3)) {
4249 ARMCPRegInfo rvbar = {
4250 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4251 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4252 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4253 };
4254 define_one_arm_cp_reg(cpu, &rvbar);
4255 }
4256 } else {
4257 /* If EL2 is missing but higher ELs are enabled, we need to
4258 * register the no_el2 reginfos.
4259 */
4260 if (arm_feature(env, ARM_FEATURE_EL3)) {
4261 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4262 * of MIDR_EL1 and MPIDR_EL1.
4263 */
4264 ARMCPRegInfo vpidr_regs[] = {
4265 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4266 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4267 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4268 .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4269 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4270 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4271 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4272 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4273 .type = ARM_CP_NO_RAW,
4274 .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4275 REGINFO_SENTINEL
4276 };
4277 define_arm_cp_regs(cpu, vpidr_regs);
4278 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4279 }
4280 }
4281 if (arm_feature(env, ARM_FEATURE_EL3)) {
4282 define_arm_cp_regs(cpu, el3_cp_reginfo);
4283 ARMCPRegInfo rvbar = {
4284 .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4285 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4286 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
4287 };
4288 define_one_arm_cp_reg(cpu, &rvbar);
4289 }
4290 if (arm_feature(env, ARM_FEATURE_MPU)) {
4291 if (arm_feature(env, ARM_FEATURE_V6)) {
4292 /* PMSAv6 not implemented */
4293 assert(arm_feature(env, ARM_FEATURE_V7));
4294 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4295 define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4296 } else {
4297 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4298 }
4299 } else {
4300 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4301 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4302 }
4303 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4304 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4305 }
4306 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4307 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4308 }
4309 if (arm_feature(env, ARM_FEATURE_VAPA)) {
4310 define_arm_cp_regs(cpu, vapa_cp_reginfo);
4311 }
4312 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4313 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4314 }
4315 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4316 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4317 }
4318 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4319 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4320 }
4321 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4322 define_arm_cp_regs(cpu, omap_cp_reginfo);
4323 }
4324 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4325 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4326 }
4327 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4328 define_arm_cp_regs(cpu, xscale_cp_reginfo);
4329 }
4330 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4331 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4332 }
4333 if (arm_feature(env, ARM_FEATURE_LPAE)) {
4334 define_arm_cp_regs(cpu, lpae_cp_reginfo);
4335 }
4336 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4337 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4338 * be read-only (ie write causes UNDEF exception).
4339 */
4340 {
4341 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4342 /* Pre-v8 MIDR space.
4343 * Note that the MIDR isn't a simple constant register because
4344 * of the TI925 behaviour where writes to another register can
4345 * cause the MIDR value to change.
4346 *
4347 * Unimplemented registers in the c15 0 0 0 space default to
4348 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4349 * and friends override accordingly.
4350 */
4351 { .name = "MIDR",
4352 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4353 .access = PL1_R, .resetvalue = cpu->midr,
4354 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4355 .readfn = midr_read,
4356 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4357 .type = ARM_CP_OVERRIDE },
4358 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4359 { .name = "DUMMY",
4360 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4361 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4362 { .name = "DUMMY",
4363 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4364 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4365 { .name = "DUMMY",
4366 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4367 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4368 { .name = "DUMMY",
4369 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4370 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4371 { .name = "DUMMY",
4372 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4373 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4374 REGINFO_SENTINEL
4375 };
4376 ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4377 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4378 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4379 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
4380 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4381 .readfn = midr_read },
4382 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4383 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4384 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4385 .access = PL1_R, .resetvalue = cpu->midr },
4386 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4387 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4388 .access = PL1_R, .resetvalue = cpu->midr },
4389 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4390 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4391 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4392 REGINFO_SENTINEL
4393 };
4394 ARMCPRegInfo id_cp_reginfo[] = {
4395 /* These are common to v8 and pre-v8 */
4396 { .name = "CTR",
4397 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4398 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4399 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4400 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4401 .access = PL0_R, .accessfn = ctr_el0_access,
4402 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4403 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4404 { .name = "TCMTR",
4405 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4406 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4407 REGINFO_SENTINEL
4408 };
4409 /* TLBTR is specific to VMSA */
4410 ARMCPRegInfo id_tlbtr_reginfo = {
4411 .name = "TLBTR",
4412 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4413 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4414 };
4415 /* MPUIR is specific to PMSA V6+ */
4416 ARMCPRegInfo id_mpuir_reginfo = {
4417 .name = "MPUIR",
4418 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4419 .access = PL1_R, .type = ARM_CP_CONST,
4420 .resetvalue = cpu->pmsav7_dregion << 8
4421 };
4422 ARMCPRegInfo crn0_wi_reginfo = {
4423 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4424 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4425 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4426 };
4427 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4428 arm_feature(env, ARM_FEATURE_STRONGARM)) {
4429 ARMCPRegInfo *r;
4430 /* Register the blanket "writes ignored" value first to cover the
4431 * whole space. Then update the specific ID registers to allow write
4432 * access, so that they ignore writes rather than causing them to
4433 * UNDEF.
4434 */
4435 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4436 for (r = id_pre_v8_midr_cp_reginfo;
4437 r->type != ARM_CP_SENTINEL; r++) {
4438 r->access = PL1_RW;
4439 }
4440 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4441 r->access = PL1_RW;
4442 }
4443 id_tlbtr_reginfo.access = PL1_RW;
4444 id_tlbtr_reginfo.access = PL1_RW;
4445 }
4446 if (arm_feature(env, ARM_FEATURE_V8)) {
4447 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4448 } else {
4449 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4450 }
4451 define_arm_cp_regs(cpu, id_cp_reginfo);
4452 if (!arm_feature(env, ARM_FEATURE_MPU)) {
4453 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4454 } else if (arm_feature(env, ARM_FEATURE_V7)) {
4455 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4456 }
4457 }
4458
4459 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4460 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4461 }
4462
4463 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4464 ARMCPRegInfo auxcr_reginfo[] = {
4465 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4466 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4467 .access = PL1_RW, .type = ARM_CP_CONST,
4468 .resetvalue = cpu->reset_auxcr },
4469 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4470 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4471 .access = PL2_RW, .type = ARM_CP_CONST,
4472 .resetvalue = 0 },
4473 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4474 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4475 .access = PL3_RW, .type = ARM_CP_CONST,
4476 .resetvalue = 0 },
4477 REGINFO_SENTINEL
4478 };
4479 define_arm_cp_regs(cpu, auxcr_reginfo);
4480 }
4481
4482 if (arm_feature(env, ARM_FEATURE_CBAR)) {
4483 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4484 /* 32 bit view is [31:18] 0...0 [43:32]. */
4485 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4486 | extract64(cpu->reset_cbar, 32, 12);
4487 ARMCPRegInfo cbar_reginfo[] = {
4488 { .name = "CBAR",
4489 .type = ARM_CP_CONST,
4490 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4491 .access = PL1_R, .resetvalue = cpu->reset_cbar },
4492 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4493 .type = ARM_CP_CONST,
4494 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4495 .access = PL1_R, .resetvalue = cbar32 },
4496 REGINFO_SENTINEL
4497 };
4498 /* We don't implement a r/w 64 bit CBAR currently */
4499 assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4500 define_arm_cp_regs(cpu, cbar_reginfo);
4501 } else {
4502 ARMCPRegInfo cbar = {
4503 .name = "CBAR",
4504 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4505 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4506 .fieldoffset = offsetof(CPUARMState,
4507 cp15.c15_config_base_address)
4508 };
4509 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4510 cbar.access = PL1_R;
4511 cbar.fieldoffset = 0;
4512 cbar.type = ARM_CP_CONST;
4513 }
4514 define_one_arm_cp_reg(cpu, &cbar);
4515 }
4516 }
4517
4518 /* Generic registers whose values depend on the implementation */
4519 {
4520 ARMCPRegInfo sctlr = {
4521 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4522 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4523 .access = PL1_RW,
4524 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4525 offsetof(CPUARMState, cp15.sctlr_ns) },
4526 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4527 .raw_writefn = raw_write,
4528 };
4529 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4530 /* Normally we would always end the TB on an SCTLR write, but Linux
4531 * arch/arm/mach-pxa/sleep.S expects two instructions following
4532 * an MMU enable to execute from cache. Imitate this behaviour.
4533 */
4534 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4535 }
4536 define_one_arm_cp_reg(cpu, &sctlr);
4537 }
4538 }
4539
4540 ARMCPU *cpu_arm_init(const char *cpu_model)
4541 {
4542 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4543 }
4544
4545 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4546 {
4547 CPUState *cs = CPU(cpu);
4548 CPUARMState *env = &cpu->env;
4549
4550 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4551 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4552 aarch64_fpu_gdb_set_reg,
4553 34, "aarch64-fpu.xml", 0);
4554 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4555 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4556 51, "arm-neon.xml", 0);
4557 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4558 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4559 35, "arm-vfp3.xml", 0);
4560 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4561 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4562 19, "arm-vfp.xml", 0);
4563 }
4564 }
4565
4566 /* Sort alphabetically by type name, except for "any". */
4567 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4568 {
4569 ObjectClass *class_a = (ObjectClass *)a;
4570 ObjectClass *class_b = (ObjectClass *)b;
4571 const char *name_a, *name_b;
4572
4573 name_a = object_class_get_name(class_a);
4574 name_b = object_class_get_name(class_b);
4575 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4576 return 1;
4577 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4578 return -1;
4579 } else {
4580 return strcmp(name_a, name_b);
4581 }
4582 }
4583
4584 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4585 {
4586 ObjectClass *oc = data;
4587 CPUListState *s = user_data;
4588 const char *typename;
4589 char *name;
4590
4591 typename = object_class_get_name(oc);
4592 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
4593 (*s->cpu_fprintf)(s->file, " %s\n",
4594 name);
4595 g_free(name);
4596 }
4597
4598 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
4599 {
4600 CPUListState s = {
4601 .file = f,
4602 .cpu_fprintf = cpu_fprintf,
4603 };
4604 GSList *list;
4605
4606 list = object_class_get_list(TYPE_ARM_CPU, false);
4607 list = g_slist_sort(list, arm_cpu_list_compare);
4608 (*cpu_fprintf)(f, "Available CPUs:\n");
4609 g_slist_foreach(list, arm_cpu_list_entry, &s);
4610 g_slist_free(list);
4611 #ifdef CONFIG_KVM
4612 /* The 'host' CPU type is dynamically registered only if KVM is
4613 * enabled, so we have to special-case it here:
4614 */
4615 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
4616 #endif
4617 }
4618
4619 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
4620 {
4621 ObjectClass *oc = data;
4622 CpuDefinitionInfoList **cpu_list = user_data;
4623 CpuDefinitionInfoList *entry;
4624 CpuDefinitionInfo *info;
4625 const char *typename;
4626
4627 typename = object_class_get_name(oc);
4628 info = g_malloc0(sizeof(*info));
4629 info->name = g_strndup(typename,
4630 strlen(typename) - strlen("-" TYPE_ARM_CPU));
4631
4632 entry = g_malloc0(sizeof(*entry));
4633 entry->value = info;
4634 entry->next = *cpu_list;
4635 *cpu_list = entry;
4636 }
4637
4638 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
4639 {
4640 CpuDefinitionInfoList *cpu_list = NULL;
4641 GSList *list;
4642
4643 list = object_class_get_list(TYPE_ARM_CPU, false);
4644 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
4645 g_slist_free(list);
4646
4647 return cpu_list;
4648 }
4649
4650 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
4651 void *opaque, int state, int secstate,
4652 int crm, int opc1, int opc2)
4653 {
4654 /* Private utility function for define_one_arm_cp_reg_with_opaque():
4655 * add a single reginfo struct to the hash table.
4656 */
4657 uint32_t *key = g_new(uint32_t, 1);
4658 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
4659 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
4660 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
4661
4662 /* Reset the secure state to the specific incoming state. This is
4663 * necessary as the register may have been defined with both states.
4664 */
4665 r2->secure = secstate;
4666
4667 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4668 /* Register is banked (using both entries in array).
4669 * Overwriting fieldoffset as the array is only used to define
4670 * banked registers but later only fieldoffset is used.
4671 */
4672 r2->fieldoffset = r->bank_fieldoffsets[ns];
4673 }
4674
4675 if (state == ARM_CP_STATE_AA32) {
4676 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4677 /* If the register is banked then we don't need to migrate or
4678 * reset the 32-bit instance in certain cases:
4679 *
4680 * 1) If the register has both 32-bit and 64-bit instances then we
4681 * can count on the 64-bit instance taking care of the
4682 * non-secure bank.
4683 * 2) If ARMv8 is enabled then we can count on a 64-bit version
4684 * taking care of the secure bank. This requires that separate
4685 * 32 and 64-bit definitions are provided.
4686 */
4687 if ((r->state == ARM_CP_STATE_BOTH && ns) ||
4688 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
4689 r2->type |= ARM_CP_ALIAS;
4690 }
4691 } else if ((secstate != r->secure) && !ns) {
4692 /* The register is not banked so we only want to allow migration of
4693 * the non-secure instance.
4694 */
4695 r2->type |= ARM_CP_ALIAS;
4696 }
4697
4698 if (r->state == ARM_CP_STATE_BOTH) {
4699 /* We assume it is a cp15 register if the .cp field is left unset.
4700 */
4701 if (r2->cp == 0) {
4702 r2->cp = 15;
4703 }
4704
4705 #ifdef HOST_WORDS_BIGENDIAN
4706 if (r2->fieldoffset) {
4707 r2->fieldoffset += sizeof(uint32_t);
4708 }
4709 #endif
4710 }
4711 }
4712 if (state == ARM_CP_STATE_AA64) {
4713 /* To allow abbreviation of ARMCPRegInfo
4714 * definitions, we treat cp == 0 as equivalent to
4715 * the value for "standard guest-visible sysreg".
4716 * STATE_BOTH definitions are also always "standard
4717 * sysreg" in their AArch64 view (the .cp value may
4718 * be non-zero for the benefit of the AArch32 view).
4719 */
4720 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
4721 r2->cp = CP_REG_ARM64_SYSREG_CP;
4722 }
4723 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
4724 r2->opc0, opc1, opc2);
4725 } else {
4726 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
4727 }
4728 if (opaque) {
4729 r2->opaque = opaque;
4730 }
4731 /* reginfo passed to helpers is correct for the actual access,
4732 * and is never ARM_CP_STATE_BOTH:
4733 */
4734 r2->state = state;
4735 /* Make sure reginfo passed to helpers for wildcarded regs
4736 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
4737 */
4738 r2->crm = crm;
4739 r2->opc1 = opc1;
4740 r2->opc2 = opc2;
4741 /* By convention, for wildcarded registers only the first
4742 * entry is used for migration; the others are marked as
4743 * ALIAS so we don't try to transfer the register
4744 * multiple times. Special registers (ie NOP/WFI) are
4745 * never migratable and not even raw-accessible.
4746 */
4747 if ((r->type & ARM_CP_SPECIAL)) {
4748 r2->type |= ARM_CP_NO_RAW;
4749 }
4750 if (((r->crm == CP_ANY) && crm != 0) ||
4751 ((r->opc1 == CP_ANY) && opc1 != 0) ||
4752 ((r->opc2 == CP_ANY) && opc2 != 0)) {
4753 r2->type |= ARM_CP_ALIAS;
4754 }
4755
4756 /* Check that raw accesses are either forbidden or handled. Note that
4757 * we can't assert this earlier because the setup of fieldoffset for
4758 * banked registers has to be done first.
4759 */
4760 if (!(r2->type & ARM_CP_NO_RAW)) {
4761 assert(!raw_accessors_invalid(r2));
4762 }
4763
4764 /* Overriding of an existing definition must be explicitly
4765 * requested.
4766 */
4767 if (!(r->type & ARM_CP_OVERRIDE)) {
4768 ARMCPRegInfo *oldreg;
4769 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
4770 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
4771 fprintf(stderr, "Register redefined: cp=%d %d bit "
4772 "crn=%d crm=%d opc1=%d opc2=%d, "
4773 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
4774 r2->crn, r2->crm, r2->opc1, r2->opc2,
4775 oldreg->name, r2->name);
4776 g_assert_not_reached();
4777 }
4778 }
4779 g_hash_table_insert(cpu->cp_regs, key, r2);
4780 }
4781
4782
4783 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
4784 const ARMCPRegInfo *r, void *opaque)
4785 {
4786 /* Define implementations of coprocessor registers.
4787 * We store these in a hashtable because typically
4788 * there are less than 150 registers in a space which
4789 * is 16*16*16*8*8 = 262144 in size.
4790 * Wildcarding is supported for the crm, opc1 and opc2 fields.
4791 * If a register is defined twice then the second definition is
4792 * used, so this can be used to define some generic registers and
4793 * then override them with implementation specific variations.
4794 * At least one of the original and the second definition should
4795 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
4796 * against accidental use.
4797 *
4798 * The state field defines whether the register is to be
4799 * visible in the AArch32 or AArch64 execution state. If the
4800 * state is set to ARM_CP_STATE_BOTH then we synthesise a
4801 * reginfo structure for the AArch32 view, which sees the lower
4802 * 32 bits of the 64 bit register.
4803 *
4804 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
4805 * be wildcarded. AArch64 registers are always considered to be 64
4806 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
4807 * the register, if any.
4808 */
4809 int crm, opc1, opc2, state;
4810 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
4811 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
4812 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
4813 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
4814 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
4815 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
4816 /* 64 bit registers have only CRm and Opc1 fields */
4817 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
4818 /* op0 only exists in the AArch64 encodings */
4819 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
4820 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
4821 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
4822 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
4823 * encodes a minimum access level for the register. We roll this
4824 * runtime check into our general permission check code, so check
4825 * here that the reginfo's specified permissions are strict enough
4826 * to encompass the generic architectural permission check.
4827 */
4828 if (r->state != ARM_CP_STATE_AA32) {
4829 int mask = 0;
4830 switch (r->opc1) {
4831 case 0: case 1: case 2:
4832 /* min_EL EL1 */
4833 mask = PL1_RW;
4834 break;
4835 case 3:
4836 /* min_EL EL0 */
4837 mask = PL0_RW;
4838 break;
4839 case 4:
4840 /* min_EL EL2 */
4841 mask = PL2_RW;
4842 break;
4843 case 5:
4844 /* unallocated encoding, so not possible */
4845 assert(false);
4846 break;
4847 case 6:
4848 /* min_EL EL3 */
4849 mask = PL3_RW;
4850 break;
4851 case 7:
4852 /* min_EL EL1, secure mode only (we don't check the latter) */
4853 mask = PL1_RW;
4854 break;
4855 default:
4856 /* broken reginfo with out-of-range opc1 */
4857 assert(false);
4858 break;
4859 }
4860 /* assert our permissions are not too lax (stricter is fine) */
4861 assert((r->access & ~mask) == 0);
4862 }
4863
4864 /* Check that the register definition has enough info to handle
4865 * reads and writes if they are permitted.
4866 */
4867 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
4868 if (r->access & PL3_R) {
4869 assert((r->fieldoffset ||
4870 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4871 r->readfn);
4872 }
4873 if (r->access & PL3_W) {
4874 assert((r->fieldoffset ||
4875 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4876 r->writefn);
4877 }
4878 }
4879 /* Bad type field probably means missing sentinel at end of reg list */
4880 assert(cptype_valid(r->type));
4881 for (crm = crmmin; crm <= crmmax; crm++) {
4882 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
4883 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
4884 for (state = ARM_CP_STATE_AA32;
4885 state <= ARM_CP_STATE_AA64; state++) {
4886 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
4887 continue;
4888 }
4889 if (state == ARM_CP_STATE_AA32) {
4890 /* Under AArch32 CP registers can be common
4891 * (same for secure and non-secure world) or banked.
4892 */
4893 switch (r->secure) {
4894 case ARM_CP_SECSTATE_S:
4895 case ARM_CP_SECSTATE_NS:
4896 add_cpreg_to_hashtable(cpu, r, opaque, state,
4897 r->secure, crm, opc1, opc2);
4898 break;
4899 default:
4900 add_cpreg_to_hashtable(cpu, r, opaque, state,
4901 ARM_CP_SECSTATE_S,
4902 crm, opc1, opc2);
4903 add_cpreg_to_hashtable(cpu, r, opaque, state,
4904 ARM_CP_SECSTATE_NS,
4905 crm, opc1, opc2);
4906 break;
4907 }
4908 } else {
4909 /* AArch64 registers get mapped to non-secure instance
4910 * of AArch32 */
4911 add_cpreg_to_hashtable(cpu, r, opaque, state,
4912 ARM_CP_SECSTATE_NS,
4913 crm, opc1, opc2);
4914 }
4915 }
4916 }
4917 }
4918 }
4919 }
4920
4921 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
4922 const ARMCPRegInfo *regs, void *opaque)
4923 {
4924 /* Define a whole list of registers */
4925 const ARMCPRegInfo *r;
4926 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
4927 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
4928 }
4929 }
4930
4931 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
4932 {
4933 return g_hash_table_lookup(cpregs, &encoded_cp);
4934 }
4935
4936 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
4937 uint64_t value)
4938 {
4939 /* Helper coprocessor write function for write-ignore registers */
4940 }
4941
4942 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
4943 {
4944 /* Helper coprocessor write function for read-as-zero registers */
4945 return 0;
4946 }
4947
4948 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
4949 {
4950 /* Helper coprocessor reset function for do-nothing-on-reset registers */
4951 }
4952
4953 static int bad_mode_switch(CPUARMState *env, int mode)
4954 {
4955 /* Return true if it is not valid for us to switch to
4956 * this CPU mode (ie all the UNPREDICTABLE cases in
4957 * the ARM ARM CPSRWriteByInstr pseudocode).
4958 */
4959 switch (mode) {
4960 case ARM_CPU_MODE_USR:
4961 case ARM_CPU_MODE_SYS:
4962 case ARM_CPU_MODE_SVC:
4963 case ARM_CPU_MODE_ABT:
4964 case ARM_CPU_MODE_UND:
4965 case ARM_CPU_MODE_IRQ:
4966 case ARM_CPU_MODE_FIQ:
4967 return 0;
4968 case ARM_CPU_MODE_MON:
4969 return !arm_is_secure(env);
4970 default:
4971 return 1;
4972 }
4973 }
4974
4975 uint32_t cpsr_read(CPUARMState *env)
4976 {
4977 int ZF;
4978 ZF = (env->ZF == 0);
4979 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
4980 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
4981 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
4982 | ((env->condexec_bits & 0xfc) << 8)
4983 | (env->GE << 16) | (env->daif & CPSR_AIF);
4984 }
4985
4986 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
4987 {
4988 uint32_t changed_daif;
4989
4990 if (mask & CPSR_NZCV) {
4991 env->ZF = (~val) & CPSR_Z;
4992 env->NF = val;
4993 env->CF = (val >> 29) & 1;
4994 env->VF = (val << 3) & 0x80000000;
4995 }
4996 if (mask & CPSR_Q)
4997 env->QF = ((val & CPSR_Q) != 0);
4998 if (mask & CPSR_T)
4999 env->thumb = ((val & CPSR_T) != 0);
5000 if (mask & CPSR_IT_0_1) {
5001 env->condexec_bits &= ~3;
5002 env->condexec_bits |= (val >> 25) & 3;
5003 }
5004 if (mask & CPSR_IT_2_7) {
5005 env->condexec_bits &= 3;
5006 env->condexec_bits |= (val >> 8) & 0xfc;
5007 }
5008 if (mask & CPSR_GE) {
5009 env->GE = (val >> 16) & 0xf;
5010 }
5011
5012 /* In a V7 implementation that includes the security extensions but does
5013 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5014 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5015 * bits respectively.
5016 *
5017 * In a V8 implementation, it is permitted for privileged software to
5018 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5019 */
5020 if (!arm_feature(env, ARM_FEATURE_V8) &&
5021 arm_feature(env, ARM_FEATURE_EL3) &&
5022 !arm_feature(env, ARM_FEATURE_EL2) &&
5023 !arm_is_secure(env)) {
5024
5025 changed_daif = (env->daif ^ val) & mask;
5026
5027 if (changed_daif & CPSR_A) {
5028 /* Check to see if we are allowed to change the masking of async
5029 * abort exceptions from a non-secure state.
5030 */
5031 if (!(env->cp15.scr_el3 & SCR_AW)) {
5032 qemu_log_mask(LOG_GUEST_ERROR,
5033 "Ignoring attempt to switch CPSR_A flag from "
5034 "non-secure world with SCR.AW bit clear\n");
5035 mask &= ~CPSR_A;
5036 }
5037 }
5038
5039 if (changed_daif & CPSR_F) {
5040 /* Check to see if we are allowed to change the masking of FIQ
5041 * exceptions from a non-secure state.
5042 */
5043 if (!(env->cp15.scr_el3 & SCR_FW)) {
5044 qemu_log_mask(LOG_GUEST_ERROR,
5045 "Ignoring attempt to switch CPSR_F flag from "
5046 "non-secure world with SCR.FW bit clear\n");
5047 mask &= ~CPSR_F;
5048 }
5049
5050 /* Check whether non-maskable FIQ (NMFI) support is enabled.
5051 * If this bit is set software is not allowed to mask
5052 * FIQs, but is allowed to set CPSR_F to 0.
5053 */
5054 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5055 (val & CPSR_F)) {
5056 qemu_log_mask(LOG_GUEST_ERROR,
5057 "Ignoring attempt to enable CPSR_F flag "
5058 "(non-maskable FIQ [NMFI] support enabled)\n");
5059 mask &= ~CPSR_F;
5060 }
5061 }
5062 }
5063
5064 env->daif &= ~(CPSR_AIF & mask);
5065 env->daif |= val & CPSR_AIF & mask;
5066
5067 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
5068 if (bad_mode_switch(env, val & CPSR_M)) {
5069 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
5070 * We choose to ignore the attempt and leave the CPSR M field
5071 * untouched.
5072 */
5073 mask &= ~CPSR_M;
5074 } else {
5075 switch_mode(env, val & CPSR_M);
5076 }
5077 }
5078 mask &= ~CACHED_CPSR_BITS;
5079 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5080 }
5081
5082 /* Sign/zero extend */
5083 uint32_t HELPER(sxtb16)(uint32_t x)
5084 {
5085 uint32_t res;
5086 res = (uint16_t)(int8_t)x;
5087 res |= (uint32_t)(int8_t)(x >> 16) << 16;
5088 return res;
5089 }
5090
5091 uint32_t HELPER(uxtb16)(uint32_t x)
5092 {
5093 uint32_t res;
5094 res = (uint16_t)(uint8_t)x;
5095 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5096 return res;
5097 }
5098
5099 uint32_t HELPER(clz)(uint32_t x)
5100 {
5101 return clz32(x);
5102 }
5103
5104 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5105 {
5106 if (den == 0)
5107 return 0;
5108 if (num == INT_MIN && den == -1)
5109 return INT_MIN;
5110 return num / den;
5111 }
5112
5113 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5114 {
5115 if (den == 0)
5116 return 0;
5117 return num / den;
5118 }
5119
5120 uint32_t HELPER(rbit)(uint32_t x)
5121 {
5122 return revbit32(x);
5123 }
5124
5125 #if defined(CONFIG_USER_ONLY)
5126
5127 /* These should probably raise undefined insn exceptions. */
5128 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5129 {
5130 ARMCPU *cpu = arm_env_get_cpu(env);
5131
5132 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5133 }
5134
5135 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5136 {
5137 ARMCPU *cpu = arm_env_get_cpu(env);
5138
5139 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5140 return 0;
5141 }
5142
5143 void switch_mode(CPUARMState *env, int mode)
5144 {
5145 ARMCPU *cpu = arm_env_get_cpu(env);
5146
5147 if (mode != ARM_CPU_MODE_USR) {
5148 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5149 }
5150 }
5151
5152 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
5153 {
5154 ARMCPU *cpu = arm_env_get_cpu(env);
5155
5156 cpu_abort(CPU(cpu), "banked r13 write\n");
5157 }
5158
5159 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
5160 {
5161 ARMCPU *cpu = arm_env_get_cpu(env);
5162
5163 cpu_abort(CPU(cpu), "banked r13 read\n");
5164 return 0;
5165 }
5166
5167 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5168 uint32_t cur_el, bool secure)
5169 {
5170 return 1;
5171 }
5172
5173 void aarch64_sync_64_to_32(CPUARMState *env)
5174 {
5175 g_assert_not_reached();
5176 }
5177
5178 #else
5179
5180 /* Map CPU modes onto saved register banks. */
5181 int bank_number(int mode)
5182 {
5183 switch (mode) {
5184 case ARM_CPU_MODE_USR:
5185 case ARM_CPU_MODE_SYS:
5186 return 0;
5187 case ARM_CPU_MODE_SVC:
5188 return 1;
5189 case ARM_CPU_MODE_ABT:
5190 return 2;
5191 case ARM_CPU_MODE_UND:
5192 return 3;
5193 case ARM_CPU_MODE_IRQ:
5194 return 4;
5195 case ARM_CPU_MODE_FIQ:
5196 return 5;
5197 case ARM_CPU_MODE_HYP:
5198 return 6;
5199 case ARM_CPU_MODE_MON:
5200 return 7;
5201 }
5202 g_assert_not_reached();
5203 }
5204
5205 void switch_mode(CPUARMState *env, int mode)
5206 {
5207 int old_mode;
5208 int i;
5209
5210 old_mode = env->uncached_cpsr & CPSR_M;
5211 if (mode == old_mode)
5212 return;
5213
5214 if (old_mode == ARM_CPU_MODE_FIQ) {
5215 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5216 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5217 } else if (mode == ARM_CPU_MODE_FIQ) {
5218 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5219 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5220 }
5221
5222 i = bank_number(old_mode);
5223 env->banked_r13[i] = env->regs[13];
5224 env->banked_r14[i] = env->regs[14];
5225 env->banked_spsr[i] = env->spsr;
5226
5227 i = bank_number(mode);
5228 env->regs[13] = env->banked_r13[i];
5229 env->regs[14] = env->banked_r14[i];
5230 env->spsr = env->banked_spsr[i];
5231 }
5232
5233 /* Physical Interrupt Target EL Lookup Table
5234 *
5235 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5236 *
5237 * The below multi-dimensional table is used for looking up the target
5238 * exception level given numerous condition criteria. Specifically, the
5239 * target EL is based on SCR and HCR routing controls as well as the
5240 * currently executing EL and secure state.
5241 *
5242 * Dimensions:
5243 * target_el_table[2][2][2][2][2][4]
5244 * | | | | | +--- Current EL
5245 * | | | | +------ Non-secure(0)/Secure(1)
5246 * | | | +--------- HCR mask override
5247 * | | +------------ SCR exec state control
5248 * | +--------------- SCR mask override
5249 * +------------------ 32-bit(0)/64-bit(1) EL3
5250 *
5251 * The table values are as such:
5252 * 0-3 = EL0-EL3
5253 * -1 = Cannot occur
5254 *
5255 * The ARM ARM target EL table includes entries indicating that an "exception
5256 * is not taken". The two cases where this is applicable are:
5257 * 1) An exception is taken from EL3 but the SCR does not have the exception
5258 * routed to EL3.
5259 * 2) An exception is taken from EL2 but the HCR does not have the exception
5260 * routed to EL2.
5261 * In these two cases, the below table contain a target of EL1. This value is
5262 * returned as it is expected that the consumer of the table data will check
5263 * for "target EL >= current EL" to ensure the exception is not taken.
5264 *
5265 * SCR HCR
5266 * 64 EA AMO From
5267 * BIT IRQ IMO Non-secure Secure
5268 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
5269 */
5270 static const int8_t target_el_table[2][2][2][2][2][4] = {
5271 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5272 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
5273 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5274 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
5275 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5276 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
5277 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5278 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
5279 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
5280 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
5281 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
5282 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
5283 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5284 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
5285 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5286 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
5287 };
5288
5289 /*
5290 * Determine the target EL for physical exceptions
5291 */
5292 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5293 uint32_t cur_el, bool secure)
5294 {
5295 CPUARMState *env = cs->env_ptr;
5296 int rw;
5297 int scr;
5298 int hcr;
5299 int target_el;
5300 /* Is the highest EL AArch64? */
5301 int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
5302
5303 if (arm_feature(env, ARM_FEATURE_EL3)) {
5304 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5305 } else {
5306 /* Either EL2 is the highest EL (and so the EL2 register width
5307 * is given by is64); or there is no EL2 or EL3, in which case
5308 * the value of 'rw' does not affect the table lookup anyway.
5309 */
5310 rw = is64;
5311 }
5312
5313 switch (excp_idx) {
5314 case EXCP_IRQ:
5315 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5316 hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5317 break;
5318 case EXCP_FIQ:
5319 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5320 hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5321 break;
5322 default:
5323 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5324 hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5325 break;
5326 };
5327
5328 /* If HCR.TGE is set then HCR is treated as being 1 */
5329 hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5330
5331 /* Perform a table-lookup for the target EL given the current state */
5332 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5333
5334 assert(target_el > 0);
5335
5336 return target_el;
5337 }
5338
5339 static void v7m_push(CPUARMState *env, uint32_t val)
5340 {
5341 CPUState *cs = CPU(arm_env_get_cpu(env));
5342
5343 env->regs[13] -= 4;
5344 stl_phys(cs->as, env->regs[13], val);
5345 }
5346
5347 static uint32_t v7m_pop(CPUARMState *env)
5348 {
5349 CPUState *cs = CPU(arm_env_get_cpu(env));
5350 uint32_t val;
5351
5352 val = ldl_phys(cs->as, env->regs[13]);
5353 env->regs[13] += 4;
5354 return val;
5355 }
5356
5357 /* Switch to V7M main or process stack pointer. */
5358 static void switch_v7m_sp(CPUARMState *env, int process)
5359 {
5360 uint32_t tmp;
5361 if (env->v7m.current_sp != process) {
5362 tmp = env->v7m.other_sp;
5363 env->v7m.other_sp = env->regs[13];
5364 env->regs[13] = tmp;
5365 env->v7m.current_sp = process;
5366 }
5367 }
5368
5369 static void do_v7m_exception_exit(CPUARMState *env)
5370 {
5371 uint32_t type;
5372 uint32_t xpsr;
5373
5374 type = env->regs[15];
5375 if (env->v7m.exception != 0)
5376 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5377
5378 /* Switch to the target stack. */
5379 switch_v7m_sp(env, (type & 4) != 0);
5380 /* Pop registers. */
5381 env->regs[0] = v7m_pop(env);
5382 env->regs[1] = v7m_pop(env);
5383 env->regs[2] = v7m_pop(env);
5384 env->regs[3] = v7m_pop(env);
5385 env->regs[12] = v7m_pop(env);
5386 env->regs[14] = v7m_pop(env);
5387 env->regs[15] = v7m_pop(env);
5388 if (env->regs[15] & 1) {
5389 qemu_log_mask(LOG_GUEST_ERROR,
5390 "M profile return from interrupt with misaligned "
5391 "PC is UNPREDICTABLE\n");
5392 /* Actual hardware seems to ignore the lsbit, and there are several
5393 * RTOSes out there which incorrectly assume the r15 in the stack
5394 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5395 */
5396 env->regs[15] &= ~1U;
5397 }
5398 xpsr = v7m_pop(env);
5399 xpsr_write(env, xpsr, 0xfffffdff);
5400 /* Undo stack alignment. */
5401 if (xpsr & 0x200)
5402 env->regs[13] |= 4;
5403 /* ??? The exception return type specifies Thread/Handler mode. However
5404 this is also implied by the xPSR value. Not sure what to do
5405 if there is a mismatch. */
5406 /* ??? Likewise for mismatches between the CONTROL register and the stack
5407 pointer. */
5408 }
5409
5410 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5411 {
5412 ARMCPU *cpu = ARM_CPU(cs);
5413 CPUARMState *env = &cpu->env;
5414 uint32_t xpsr = xpsr_read(env);
5415 uint32_t lr;
5416 uint32_t addr;
5417
5418 arm_log_exception(cs->exception_index);
5419
5420 lr = 0xfffffff1;
5421 if (env->v7m.current_sp)
5422 lr |= 4;
5423 if (env->v7m.exception == 0)
5424 lr |= 8;
5425
5426 /* For exceptions we just mark as pending on the NVIC, and let that
5427 handle it. */
5428 /* TODO: Need to escalate if the current priority is higher than the
5429 one we're raising. */
5430 switch (cs->exception_index) {
5431 case EXCP_UDEF:
5432 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5433 return;
5434 case EXCP_SWI:
5435 /* The PC already points to the next instruction. */
5436 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5437 return;
5438 case EXCP_PREFETCH_ABORT:
5439 case EXCP_DATA_ABORT:
5440 /* TODO: if we implemented the MPU registers, this is where we
5441 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5442 */
5443 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5444 return;
5445 case EXCP_BKPT:
5446 if (semihosting_enabled()) {
5447 int nr;
5448 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5449 if (nr == 0xab) {
5450 env->regs[15] += 2;
5451 qemu_log_mask(CPU_LOG_INT,
5452 "...handling as semihosting call 0x%x\n",
5453 env->regs[0]);
5454 env->regs[0] = do_arm_semihosting(env);
5455 return;
5456 }
5457 }
5458 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5459 return;
5460 case EXCP_IRQ:
5461 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5462 break;
5463 case EXCP_EXCEPTION_EXIT:
5464 do_v7m_exception_exit(env);
5465 return;
5466 default:
5467 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5468 return; /* Never happens. Keep compiler happy. */
5469 }
5470
5471 /* Align stack pointer. */
5472 /* ??? Should only do this if Configuration Control Register
5473 STACKALIGN bit is set. */
5474 if (env->regs[13] & 4) {
5475 env->regs[13] -= 4;
5476 xpsr |= 0x200;
5477 }
5478 /* Switch to the handler mode. */
5479 v7m_push(env, xpsr);
5480 v7m_push(env, env->regs[15]);
5481 v7m_push(env, env->regs[14]);
5482 v7m_push(env, env->regs[12]);
5483 v7m_push(env, env->regs[3]);
5484 v7m_push(env, env->regs[2]);
5485 v7m_push(env, env->regs[1]);
5486 v7m_push(env, env->regs[0]);
5487 switch_v7m_sp(env, 0);
5488 /* Clear IT bits */
5489 env->condexec_bits = 0;
5490 env->regs[14] = lr;
5491 addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5492 env->regs[15] = addr & 0xfffffffe;
5493 env->thumb = addr & 1;
5494 }
5495
5496 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5497 * register set. This is necessary when switching between AArch32 and AArch64
5498 * execution state.
5499 */
5500 void aarch64_sync_32_to_64(CPUARMState *env)
5501 {
5502 int i;
5503 uint32_t mode = env->uncached_cpsr & CPSR_M;
5504
5505 /* We can blanket copy R[0:7] to X[0:7] */
5506 for (i = 0; i < 8; i++) {
5507 env->xregs[i] = env->regs[i];
5508 }
5509
5510 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5511 * Otherwise, they come from the banked user regs.
5512 */
5513 if (mode == ARM_CPU_MODE_FIQ) {
5514 for (i = 8; i < 13; i++) {
5515 env->xregs[i] = env->usr_regs[i - 8];
5516 }
5517 } else {
5518 for (i = 8; i < 13; i++) {
5519 env->xregs[i] = env->regs[i];
5520 }
5521 }
5522
5523 /* Registers x13-x23 are the various mode SP and FP registers. Registers
5524 * r13 and r14 are only copied if we are in that mode, otherwise we copy
5525 * from the mode banked register.
5526 */
5527 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5528 env->xregs[13] = env->regs[13];
5529 env->xregs[14] = env->regs[14];
5530 } else {
5531 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5532 /* HYP is an exception in that it is copied from r14 */
5533 if (mode == ARM_CPU_MODE_HYP) {
5534 env->xregs[14] = env->regs[14];
5535 } else {
5536 env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5537 }
5538 }
5539
5540 if (mode == ARM_CPU_MODE_HYP) {
5541 env->xregs[15] = env->regs[13];
5542 } else {
5543 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5544 }
5545
5546 if (mode == ARM_CPU_MODE_IRQ) {
5547 env->xregs[16] = env->regs[14];
5548 env->xregs[17] = env->regs[13];
5549 } else {
5550 env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5551 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5552 }
5553
5554 if (mode == ARM_CPU_MODE_SVC) {
5555 env->xregs[18] = env->regs[14];
5556 env->xregs[19] = env->regs[13];
5557 } else {
5558 env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5559 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5560 }
5561
5562 if (mode == ARM_CPU_MODE_ABT) {
5563 env->xregs[20] = env->regs[14];
5564 env->xregs[21] = env->regs[13];
5565 } else {
5566 env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5567 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5568 }
5569
5570 if (mode == ARM_CPU_MODE_UND) {
5571 env->xregs[22] = env->regs[14];
5572 env->xregs[23] = env->regs[13];
5573 } else {
5574 env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5575 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5576 }
5577
5578 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
5579 * mode, then we can copy from r8-r14. Otherwise, we copy from the
5580 * FIQ bank for r8-r14.
5581 */
5582 if (mode == ARM_CPU_MODE_FIQ) {
5583 for (i = 24; i < 31; i++) {
5584 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
5585 }
5586 } else {
5587 for (i = 24; i < 29; i++) {
5588 env->xregs[i] = env->fiq_regs[i - 24];
5589 }
5590 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
5591 env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
5592 }
5593
5594 env->pc = env->regs[15];
5595 }
5596
5597 /* Function used to synchronize QEMU's AArch32 register set with AArch64
5598 * register set. This is necessary when switching between AArch32 and AArch64
5599 * execution state.
5600 */
5601 void aarch64_sync_64_to_32(CPUARMState *env)
5602 {
5603 int i;
5604 uint32_t mode = env->uncached_cpsr & CPSR_M;
5605
5606 /* We can blanket copy X[0:7] to R[0:7] */
5607 for (i = 0; i < 8; i++) {
5608 env->regs[i] = env->xregs[i];
5609 }
5610
5611 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
5612 * Otherwise, we copy x8-x12 into the banked user regs.
5613 */
5614 if (mode == ARM_CPU_MODE_FIQ) {
5615 for (i = 8; i < 13; i++) {
5616 env->usr_regs[i - 8] = env->xregs[i];
5617 }
5618 } else {
5619 for (i = 8; i < 13; i++) {
5620 env->regs[i] = env->xregs[i];
5621 }
5622 }
5623
5624 /* Registers r13 & r14 depend on the current mode.
5625 * If we are in a given mode, we copy the corresponding x registers to r13
5626 * and r14. Otherwise, we copy the x register to the banked r13 and r14
5627 * for the mode.
5628 */
5629 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5630 env->regs[13] = env->xregs[13];
5631 env->regs[14] = env->xregs[14];
5632 } else {
5633 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
5634
5635 /* HYP is an exception in that it does not have its own banked r14 but
5636 * shares the USR r14
5637 */
5638 if (mode == ARM_CPU_MODE_HYP) {
5639 env->regs[14] = env->xregs[14];
5640 } else {
5641 env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
5642 }
5643 }
5644
5645 if (mode == ARM_CPU_MODE_HYP) {
5646 env->regs[13] = env->xregs[15];
5647 } else {
5648 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
5649 }
5650
5651 if (mode == ARM_CPU_MODE_IRQ) {
5652 env->regs[14] = env->xregs[16];
5653 env->regs[13] = env->xregs[17];
5654 } else {
5655 env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
5656 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
5657 }
5658
5659 if (mode == ARM_CPU_MODE_SVC) {
5660 env->regs[14] = env->xregs[18];
5661 env->regs[13] = env->xregs[19];
5662 } else {
5663 env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
5664 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
5665 }
5666
5667 if (mode == ARM_CPU_MODE_ABT) {
5668 env->regs[14] = env->xregs[20];
5669 env->regs[13] = env->xregs[21];
5670 } else {
5671 env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
5672 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
5673 }
5674
5675 if (mode == ARM_CPU_MODE_UND) {
5676 env->regs[14] = env->xregs[22];
5677 env->regs[13] = env->xregs[23];
5678 } else {
5679 env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
5680 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
5681 }
5682
5683 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
5684 * mode, then we can copy to r8-r14. Otherwise, we copy to the
5685 * FIQ bank for r8-r14.
5686 */
5687 if (mode == ARM_CPU_MODE_FIQ) {
5688 for (i = 24; i < 31; i++) {
5689 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
5690 }
5691 } else {
5692 for (i = 24; i < 29; i++) {
5693 env->fiq_regs[i - 24] = env->xregs[i];
5694 }
5695 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
5696 env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
5697 }
5698
5699 env->regs[15] = env->pc;
5700 }
5701
5702 /* Handle a CPU exception. */
5703 void arm_cpu_do_interrupt(CPUState *cs)
5704 {
5705 ARMCPU *cpu = ARM_CPU(cs);
5706 CPUARMState *env = &cpu->env;
5707 uint32_t addr;
5708 uint32_t mask;
5709 int new_mode;
5710 uint32_t offset;
5711 uint32_t moe;
5712
5713 assert(!IS_M(env));
5714
5715 arm_log_exception(cs->exception_index);
5716
5717 if (arm_is_psci_call(cpu, cs->exception_index)) {
5718 arm_handle_psci_call(cpu);
5719 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
5720 return;
5721 }
5722
5723 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
5724 switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
5725 case EC_BREAKPOINT:
5726 case EC_BREAKPOINT_SAME_EL:
5727 moe = 1;
5728 break;
5729 case EC_WATCHPOINT:
5730 case EC_WATCHPOINT_SAME_EL:
5731 moe = 10;
5732 break;
5733 case EC_AA32_BKPT:
5734 moe = 3;
5735 break;
5736 case EC_VECTORCATCH:
5737 moe = 5;
5738 break;
5739 default:
5740 moe = 0;
5741 break;
5742 }
5743
5744 if (moe) {
5745 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
5746 }
5747
5748 /* TODO: Vectored interrupt controller. */
5749 switch (cs->exception_index) {
5750 case EXCP_UDEF:
5751 new_mode = ARM_CPU_MODE_UND;
5752 addr = 0x04;
5753 mask = CPSR_I;
5754 if (env->thumb)
5755 offset = 2;
5756 else
5757 offset = 4;
5758 break;
5759 case EXCP_SWI:
5760 if (semihosting_enabled()) {
5761 /* Check for semihosting interrupt. */
5762 if (env->thumb) {
5763 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
5764 & 0xff;
5765 } else {
5766 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
5767 & 0xffffff;
5768 }
5769 /* Only intercept calls from privileged modes, to provide some
5770 semblance of security. */
5771 if (((mask == 0x123456 && !env->thumb)
5772 || (mask == 0xab && env->thumb))
5773 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
5774 qemu_log_mask(CPU_LOG_INT,
5775 "...handling as semihosting call 0x%x\n",
5776 env->regs[0]);
5777 env->regs[0] = do_arm_semihosting(env);
5778 return;
5779 }
5780 }
5781 new_mode = ARM_CPU_MODE_SVC;
5782 addr = 0x08;
5783 mask = CPSR_I;
5784 /* The PC already points to the next instruction. */
5785 offset = 0;
5786 break;
5787 case EXCP_BKPT:
5788 /* See if this is a semihosting syscall. */
5789 if (env->thumb && semihosting_enabled()) {
5790 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5791 if (mask == 0xab
5792 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
5793 env->regs[15] += 2;
5794 qemu_log_mask(CPU_LOG_INT,
5795 "...handling as semihosting call 0x%x\n",
5796 env->regs[0]);
5797 env->regs[0] = do_arm_semihosting(env);
5798 return;
5799 }
5800 }
5801 env->exception.fsr = 2;
5802 /* Fall through to prefetch abort. */
5803 case EXCP_PREFETCH_ABORT:
5804 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
5805 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
5806 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
5807 env->exception.fsr, (uint32_t)env->exception.vaddress);
5808 new_mode = ARM_CPU_MODE_ABT;
5809 addr = 0x0c;
5810 mask = CPSR_A | CPSR_I;
5811 offset = 4;
5812 break;
5813 case EXCP_DATA_ABORT:
5814 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
5815 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
5816 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
5817 env->exception.fsr,
5818 (uint32_t)env->exception.vaddress);
5819 new_mode = ARM_CPU_MODE_ABT;
5820 addr = 0x10;
5821 mask = CPSR_A | CPSR_I;
5822 offset = 8;
5823 break;
5824 case EXCP_IRQ:
5825 new_mode = ARM_CPU_MODE_IRQ;
5826 addr = 0x18;
5827 /* Disable IRQ and imprecise data aborts. */
5828 mask = CPSR_A | CPSR_I;
5829 offset = 4;
5830 if (env->cp15.scr_el3 & SCR_IRQ) {
5831 /* IRQ routed to monitor mode */
5832 new_mode = ARM_CPU_MODE_MON;
5833 mask |= CPSR_F;
5834 }
5835 break;
5836 case EXCP_FIQ:
5837 new_mode = ARM_CPU_MODE_FIQ;
5838 addr = 0x1c;
5839 /* Disable FIQ, IRQ and imprecise data aborts. */
5840 mask = CPSR_A | CPSR_I | CPSR_F;
5841 if (env->cp15.scr_el3 & SCR_FIQ) {
5842 /* FIQ routed to monitor mode */
5843 new_mode = ARM_CPU_MODE_MON;
5844 }
5845 offset = 4;
5846 break;
5847 case EXCP_SMC:
5848 new_mode = ARM_CPU_MODE_MON;
5849 addr = 0x08;
5850 mask = CPSR_A | CPSR_I | CPSR_F;
5851 offset = 0;
5852 break;
5853 default:
5854 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5855 return; /* Never happens. Keep compiler happy. */
5856 }
5857
5858 if (new_mode == ARM_CPU_MODE_MON) {
5859 addr += env->cp15.mvbar;
5860 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
5861 /* High vectors. When enabled, base address cannot be remapped. */
5862 addr += 0xffff0000;
5863 } else {
5864 /* ARM v7 architectures provide a vector base address register to remap
5865 * the interrupt vector table.
5866 * This register is only followed in non-monitor mode, and is banked.
5867 * Note: only bits 31:5 are valid.
5868 */
5869 addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
5870 }
5871
5872 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
5873 env->cp15.scr_el3 &= ~SCR_NS;
5874 }
5875
5876 switch_mode (env, new_mode);
5877 /* For exceptions taken to AArch32 we must clear the SS bit in both
5878 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
5879 */
5880 env->uncached_cpsr &= ~PSTATE_SS;
5881 env->spsr = cpsr_read(env);
5882 /* Clear IT bits. */
5883 env->condexec_bits = 0;
5884 /* Switch to the new mode, and to the correct instruction set. */
5885 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
5886 env->daif |= mask;
5887 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
5888 * and we should just guard the thumb mode on V4 */
5889 if (arm_feature(env, ARM_FEATURE_V4T)) {
5890 env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
5891 }
5892 env->regs[14] = env->regs[15] + offset;
5893 env->regs[15] = addr;
5894 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
5895 }
5896
5897
5898 /* Return the exception level which controls this address translation regime */
5899 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
5900 {
5901 switch (mmu_idx) {
5902 case ARMMMUIdx_S2NS:
5903 case ARMMMUIdx_S1E2:
5904 return 2;
5905 case ARMMMUIdx_S1E3:
5906 return 3;
5907 case ARMMMUIdx_S1SE0:
5908 return arm_el_is_aa64(env, 3) ? 1 : 3;
5909 case ARMMMUIdx_S1SE1:
5910 case ARMMMUIdx_S1NSE0:
5911 case ARMMMUIdx_S1NSE1:
5912 return 1;
5913 default:
5914 g_assert_not_reached();
5915 }
5916 }
5917
5918 /* Return true if this address translation regime is secure */
5919 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
5920 {
5921 switch (mmu_idx) {
5922 case ARMMMUIdx_S12NSE0:
5923 case ARMMMUIdx_S12NSE1:
5924 case ARMMMUIdx_S1NSE0:
5925 case ARMMMUIdx_S1NSE1:
5926 case ARMMMUIdx_S1E2:
5927 case ARMMMUIdx_S2NS:
5928 return false;
5929 case ARMMMUIdx_S1E3:
5930 case ARMMMUIdx_S1SE0:
5931 case ARMMMUIdx_S1SE1:
5932 return true;
5933 default:
5934 g_assert_not_reached();
5935 }
5936 }
5937
5938 /* Return the SCTLR value which controls this address translation regime */
5939 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
5940 {
5941 return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
5942 }
5943
5944 /* Return true if the specified stage of address translation is disabled */
5945 static inline bool regime_translation_disabled(CPUARMState *env,
5946 ARMMMUIdx mmu_idx)
5947 {
5948 if (mmu_idx == ARMMMUIdx_S2NS) {
5949 return (env->cp15.hcr_el2 & HCR_VM) == 0;
5950 }
5951 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
5952 }
5953
5954 /* Return the TCR controlling this translation regime */
5955 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
5956 {
5957 if (mmu_idx == ARMMMUIdx_S2NS) {
5958 return &env->cp15.vtcr_el2;
5959 }
5960 return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
5961 }
5962
5963 /* Return the TTBR associated with this translation regime */
5964 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
5965 int ttbrn)
5966 {
5967 if (mmu_idx == ARMMMUIdx_S2NS) {
5968 return env->cp15.vttbr_el2;
5969 }
5970 if (ttbrn == 0) {
5971 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
5972 } else {
5973 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
5974 }
5975 }
5976
5977 /* Return true if the translation regime is using LPAE format page tables */
5978 static inline bool regime_using_lpae_format(CPUARMState *env,
5979 ARMMMUIdx mmu_idx)
5980 {
5981 int el = regime_el(env, mmu_idx);
5982 if (el == 2 || arm_el_is_aa64(env, el)) {
5983 return true;
5984 }
5985 if (arm_feature(env, ARM_FEATURE_LPAE)
5986 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
5987 return true;
5988 }
5989 return false;
5990 }
5991
5992 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
5993 {
5994 switch (mmu_idx) {
5995 case ARMMMUIdx_S1SE0:
5996 case ARMMMUIdx_S1NSE0:
5997 return true;
5998 default:
5999 return false;
6000 case ARMMMUIdx_S12NSE0:
6001 case ARMMMUIdx_S12NSE1:
6002 g_assert_not_reached();
6003 }
6004 }
6005
6006 /* Translate section/page access permissions to page
6007 * R/W protection flags
6008 *
6009 * @env: CPUARMState
6010 * @mmu_idx: MMU index indicating required translation regime
6011 * @ap: The 3-bit access permissions (AP[2:0])
6012 * @domain_prot: The 2-bit domain access permissions
6013 */
6014 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
6015 int ap, int domain_prot)
6016 {
6017 bool is_user = regime_is_user(env, mmu_idx);
6018
6019 if (domain_prot == 3) {
6020 return PAGE_READ | PAGE_WRITE;
6021 }
6022
6023 switch (ap) {
6024 case 0:
6025 if (arm_feature(env, ARM_FEATURE_V7)) {
6026 return 0;
6027 }
6028 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
6029 case SCTLR_S:
6030 return is_user ? 0 : PAGE_READ;
6031 case SCTLR_R:
6032 return PAGE_READ;
6033 default:
6034 return 0;
6035 }
6036 case 1:
6037 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6038 case 2:
6039 if (is_user) {
6040 return PAGE_READ;
6041 } else {
6042 return PAGE_READ | PAGE_WRITE;
6043 }
6044 case 3:
6045 return PAGE_READ | PAGE_WRITE;
6046 case 4: /* Reserved. */
6047 return 0;
6048 case 5:
6049 return is_user ? 0 : PAGE_READ;
6050 case 6:
6051 return PAGE_READ;
6052 case 7:
6053 if (!arm_feature(env, ARM_FEATURE_V6K)) {
6054 return 0;
6055 }
6056 return PAGE_READ;
6057 default:
6058 g_assert_not_reached();
6059 }
6060 }
6061
6062 /* Translate section/page access permissions to page
6063 * R/W protection flags.
6064 *
6065 * @ap: The 2-bit simple AP (AP[2:1])
6066 * @is_user: TRUE if accessing from PL0
6067 */
6068 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
6069 {
6070 switch (ap) {
6071 case 0:
6072 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6073 case 1:
6074 return PAGE_READ | PAGE_WRITE;
6075 case 2:
6076 return is_user ? 0 : PAGE_READ;
6077 case 3:
6078 return PAGE_READ;
6079 default:
6080 g_assert_not_reached();
6081 }
6082 }
6083
6084 static inline int
6085 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
6086 {
6087 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
6088 }
6089
6090 /* Translate S2 section/page access permissions to protection flags
6091 *
6092 * @env: CPUARMState
6093 * @s2ap: The 2-bit stage2 access permissions (S2AP)
6094 * @xn: XN (execute-never) bit
6095 */
6096 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
6097 {
6098 int prot = 0;
6099
6100 if (s2ap & 1) {
6101 prot |= PAGE_READ;
6102 }
6103 if (s2ap & 2) {
6104 prot |= PAGE_WRITE;
6105 }
6106 if (!xn) {
6107 prot |= PAGE_EXEC;
6108 }
6109 return prot;
6110 }
6111
6112 /* Translate section/page access permissions to protection flags
6113 *
6114 * @env: CPUARMState
6115 * @mmu_idx: MMU index indicating required translation regime
6116 * @is_aa64: TRUE if AArch64
6117 * @ap: The 2-bit simple AP (AP[2:1])
6118 * @ns: NS (non-secure) bit
6119 * @xn: XN (execute-never) bit
6120 * @pxn: PXN (privileged execute-never) bit
6121 */
6122 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
6123 int ap, int ns, int xn, int pxn)
6124 {
6125 bool is_user = regime_is_user(env, mmu_idx);
6126 int prot_rw, user_rw;
6127 bool have_wxn;
6128 int wxn = 0;
6129
6130 assert(mmu_idx != ARMMMUIdx_S2NS);
6131
6132 user_rw = simple_ap_to_rw_prot_is_user(ap, true);
6133 if (is_user) {
6134 prot_rw = user_rw;
6135 } else {
6136 prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
6137 }
6138
6139 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
6140 return prot_rw;
6141 }
6142
6143 /* TODO have_wxn should be replaced with
6144 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6145 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6146 * compatible processors have EL2, which is required for [U]WXN.
6147 */
6148 have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
6149
6150 if (have_wxn) {
6151 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
6152 }
6153
6154 if (is_aa64) {
6155 switch (regime_el(env, mmu_idx)) {
6156 case 1:
6157 if (!is_user) {
6158 xn = pxn || (user_rw & PAGE_WRITE);
6159 }
6160 break;
6161 case 2:
6162 case 3:
6163 break;
6164 }
6165 } else if (arm_feature(env, ARM_FEATURE_V7)) {
6166 switch (regime_el(env, mmu_idx)) {
6167 case 1:
6168 case 3:
6169 if (is_user) {
6170 xn = xn || !(user_rw & PAGE_READ);
6171 } else {
6172 int uwxn = 0;
6173 if (have_wxn) {
6174 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
6175 }
6176 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
6177 (uwxn && (user_rw & PAGE_WRITE));
6178 }
6179 break;
6180 case 2:
6181 break;
6182 }
6183 } else {
6184 xn = wxn = 0;
6185 }
6186
6187 if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
6188 return prot_rw;
6189 }
6190 return prot_rw | PAGE_EXEC;
6191 }
6192
6193 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
6194 uint32_t *table, uint32_t address)
6195 {
6196 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6197 TCR *tcr = regime_tcr(env, mmu_idx);
6198
6199 if (address & tcr->mask) {
6200 if (tcr->raw_tcr & TTBCR_PD1) {
6201 /* Translation table walk disabled for TTBR1 */
6202 return false;
6203 }
6204 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
6205 } else {
6206 if (tcr->raw_tcr & TTBCR_PD0) {
6207 /* Translation table walk disabled for TTBR0 */
6208 return false;
6209 }
6210 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
6211 }
6212 *table |= (address >> 18) & 0x3ffc;
6213 return true;
6214 }
6215
6216 /* Translate a S1 pagetable walk through S2 if needed. */
6217 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
6218 hwaddr addr, MemTxAttrs txattrs,
6219 uint32_t *fsr,
6220 ARMMMUFaultInfo *fi)
6221 {
6222 if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
6223 !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
6224 target_ulong s2size;
6225 hwaddr s2pa;
6226 int s2prot;
6227 int ret;
6228
6229 ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
6230 &txattrs, &s2prot, &s2size, fsr, fi);
6231 if (ret) {
6232 fi->s2addr = addr;
6233 fi->stage2 = true;
6234 fi->s1ptw = true;
6235 return ~0;
6236 }
6237 addr = s2pa;
6238 }
6239 return addr;
6240 }
6241
6242 /* All loads done in the course of a page table walk go through here.
6243 * TODO: rather than ignoring errors from physical memory reads (which
6244 * are external aborts in ARM terminology) we should propagate this
6245 * error out so that we can turn it into a Data Abort if this walk
6246 * was being done for a CPU load/store or an address translation instruction
6247 * (but not if it was for a debug access).
6248 */
6249 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6250 ARMMMUIdx mmu_idx, uint32_t *fsr,
6251 ARMMMUFaultInfo *fi)
6252 {
6253 ARMCPU *cpu = ARM_CPU(cs);
6254 CPUARMState *env = &cpu->env;
6255 MemTxAttrs attrs = {};
6256
6257 attrs.secure = is_secure;
6258 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6259 if (fi->s1ptw) {
6260 return 0;
6261 }
6262 return address_space_ldl(cs->as, addr, attrs, NULL);
6263 }
6264
6265 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6266 ARMMMUIdx mmu_idx, uint32_t *fsr,
6267 ARMMMUFaultInfo *fi)
6268 {
6269 ARMCPU *cpu = ARM_CPU(cs);
6270 CPUARMState *env = &cpu->env;
6271 MemTxAttrs attrs = {};
6272
6273 attrs.secure = is_secure;
6274 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6275 if (fi->s1ptw) {
6276 return 0;
6277 }
6278 return address_space_ldq(cs->as, addr, attrs, NULL);
6279 }
6280
6281 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6282 int access_type, ARMMMUIdx mmu_idx,
6283 hwaddr *phys_ptr, int *prot,
6284 target_ulong *page_size, uint32_t *fsr,
6285 ARMMMUFaultInfo *fi)
6286 {
6287 CPUState *cs = CPU(arm_env_get_cpu(env));
6288 int code;
6289 uint32_t table;
6290 uint32_t desc;
6291 int type;
6292 int ap;
6293 int domain = 0;
6294 int domain_prot;
6295 hwaddr phys_addr;
6296 uint32_t dacr;
6297
6298 /* Pagetable walk. */
6299 /* Lookup l1 descriptor. */
6300 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6301 /* Section translation fault if page walk is disabled by PD0 or PD1 */
6302 code = 5;
6303 goto do_fault;
6304 }
6305 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6306 mmu_idx, fsr, fi);
6307 type = (desc & 3);
6308 domain = (desc >> 5) & 0x0f;
6309 if (regime_el(env, mmu_idx) == 1) {
6310 dacr = env->cp15.dacr_ns;
6311 } else {
6312 dacr = env->cp15.dacr_s;
6313 }
6314 domain_prot = (dacr >> (domain * 2)) & 3;
6315 if (type == 0) {
6316 /* Section translation fault. */
6317 code = 5;
6318 goto do_fault;
6319 }
6320 if (domain_prot == 0 || domain_prot == 2) {
6321 if (type == 2)
6322 code = 9; /* Section domain fault. */
6323 else
6324 code = 11; /* Page domain fault. */
6325 goto do_fault;
6326 }
6327 if (type == 2) {
6328 /* 1Mb section. */
6329 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6330 ap = (desc >> 10) & 3;
6331 code = 13;
6332 *page_size = 1024 * 1024;
6333 } else {
6334 /* Lookup l2 entry. */
6335 if (type == 1) {
6336 /* Coarse pagetable. */
6337 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6338 } else {
6339 /* Fine pagetable. */
6340 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6341 }
6342 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6343 mmu_idx, fsr, fi);
6344 switch (desc & 3) {
6345 case 0: /* Page translation fault. */
6346 code = 7;
6347 goto do_fault;
6348 case 1: /* 64k page. */
6349 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6350 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6351 *page_size = 0x10000;
6352 break;
6353 case 2: /* 4k page. */
6354 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6355 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6356 *page_size = 0x1000;
6357 break;
6358 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6359 if (type == 1) {
6360 /* ARMv6/XScale extended small page format */
6361 if (arm_feature(env, ARM_FEATURE_XSCALE)
6362 || arm_feature(env, ARM_FEATURE_V6)) {
6363 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6364 *page_size = 0x1000;
6365 } else {
6366 /* UNPREDICTABLE in ARMv5; we choose to take a
6367 * page translation fault.
6368 */
6369 code = 7;
6370 goto do_fault;
6371 }
6372 } else {
6373 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6374 *page_size = 0x400;
6375 }
6376 ap = (desc >> 4) & 3;
6377 break;
6378 default:
6379 /* Never happens, but compiler isn't smart enough to tell. */
6380 abort();
6381 }
6382 code = 15;
6383 }
6384 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6385 *prot |= *prot ? PAGE_EXEC : 0;
6386 if (!(*prot & (1 << access_type))) {
6387 /* Access permission fault. */
6388 goto do_fault;
6389 }
6390 *phys_ptr = phys_addr;
6391 return false;
6392 do_fault:
6393 *fsr = code | (domain << 4);
6394 return true;
6395 }
6396
6397 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
6398 int access_type, ARMMMUIdx mmu_idx,
6399 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
6400 target_ulong *page_size, uint32_t *fsr,
6401 ARMMMUFaultInfo *fi)
6402 {
6403 CPUState *cs = CPU(arm_env_get_cpu(env));
6404 int code;
6405 uint32_t table;
6406 uint32_t desc;
6407 uint32_t xn;
6408 uint32_t pxn = 0;
6409 int type;
6410 int ap;
6411 int domain = 0;
6412 int domain_prot;
6413 hwaddr phys_addr;
6414 uint32_t dacr;
6415 bool ns;
6416
6417 /* Pagetable walk. */
6418 /* Lookup l1 descriptor. */
6419 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6420 /* Section translation fault if page walk is disabled by PD0 or PD1 */
6421 code = 5;
6422 goto do_fault;
6423 }
6424 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6425 mmu_idx, fsr, fi);
6426 type = (desc & 3);
6427 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
6428 /* Section translation fault, or attempt to use the encoding
6429 * which is Reserved on implementations without PXN.
6430 */
6431 code = 5;
6432 goto do_fault;
6433 }
6434 if ((type == 1) || !(desc & (1 << 18))) {
6435 /* Page or Section. */
6436 domain = (desc >> 5) & 0x0f;
6437 }
6438 if (regime_el(env, mmu_idx) == 1) {
6439 dacr = env->cp15.dacr_ns;
6440 } else {
6441 dacr = env->cp15.dacr_s;
6442 }
6443 domain_prot = (dacr >> (domain * 2)) & 3;
6444 if (domain_prot == 0 || domain_prot == 2) {
6445 if (type != 1) {
6446 code = 9; /* Section domain fault. */
6447 } else {
6448 code = 11; /* Page domain fault. */
6449 }
6450 goto do_fault;
6451 }
6452 if (type != 1) {
6453 if (desc & (1 << 18)) {
6454 /* Supersection. */
6455 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
6456 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
6457 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
6458 *page_size = 0x1000000;
6459 } else {
6460 /* Section. */
6461 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6462 *page_size = 0x100000;
6463 }
6464 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
6465 xn = desc & (1 << 4);
6466 pxn = desc & 1;
6467 code = 13;
6468 ns = extract32(desc, 19, 1);
6469 } else {
6470 if (arm_feature(env, ARM_FEATURE_PXN)) {
6471 pxn = (desc >> 2) & 1;
6472 }
6473 ns = extract32(desc, 3, 1);
6474 /* Lookup l2 entry. */
6475 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6476 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6477 mmu_idx, fsr, fi);
6478 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
6479 switch (desc & 3) {
6480 case 0: /* Page translation fault. */
6481 code = 7;
6482 goto do_fault;
6483 case 1: /* 64k page. */
6484 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6485 xn = desc & (1 << 15);
6486 *page_size = 0x10000;
6487 break;
6488 case 2: case 3: /* 4k page. */
6489 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6490 xn = desc & 1;
6491 *page_size = 0x1000;
6492 break;
6493 default:
6494 /* Never happens, but compiler isn't smart enough to tell. */
6495 abort();
6496 }
6497 code = 15;
6498 }
6499 if (domain_prot == 3) {
6500 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
6501 } else {
6502 if (pxn && !regime_is_user(env, mmu_idx)) {
6503 xn = 1;
6504 }
6505 if (xn && access_type == 2)
6506 goto do_fault;
6507
6508 if (arm_feature(env, ARM_FEATURE_V6K) &&
6509 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
6510 /* The simplified model uses AP[0] as an access control bit. */
6511 if ((ap & 1) == 0) {
6512 /* Access flag fault. */
6513 code = (code == 15) ? 6 : 3;
6514 goto do_fault;
6515 }
6516 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
6517 } else {
6518 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6519 }
6520 if (*prot && !xn) {
6521 *prot |= PAGE_EXEC;
6522 }
6523 if (!(*prot & (1 << access_type))) {
6524 /* Access permission fault. */
6525 goto do_fault;
6526 }
6527 }
6528 if (ns) {
6529 /* The NS bit will (as required by the architecture) have no effect if
6530 * the CPU doesn't support TZ or this is a non-secure translation
6531 * regime, because the attribute will already be non-secure.
6532 */
6533 attrs->secure = false;
6534 }
6535 *phys_ptr = phys_addr;
6536 return false;
6537 do_fault:
6538 *fsr = code | (domain << 4);
6539 return true;
6540 }
6541
6542 /* Fault type for long-descriptor MMU fault reporting; this corresponds
6543 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
6544 */
6545 typedef enum {
6546 translation_fault = 1,
6547 access_fault = 2,
6548 permission_fault = 3,
6549 } MMUFaultType;
6550
6551 /*
6552 * check_s2_startlevel
6553 * @cpu: ARMCPU
6554 * @is_aa64: True if the translation regime is in AArch64 state
6555 * @startlevel: Suggested starting level
6556 * @inputsize: Bitsize of IPAs
6557 * @stride: Page-table stride (See the ARM ARM)
6558 *
6559 * Returns true if the suggested starting level is OK and false otherwise.
6560 */
6561 static bool check_s2_startlevel(ARMCPU *cpu, bool is_aa64, int level,
6562 int inputsize, int stride)
6563 {
6564 /* Negative levels are never allowed. */
6565 if (level < 0) {
6566 return false;
6567 }
6568
6569 if (is_aa64) {
6570 unsigned int pamax = arm_pamax(cpu);
6571
6572 switch (stride) {
6573 case 13: /* 64KB Pages. */
6574 if (level == 0 || (level == 1 && pamax <= 42)) {
6575 return false;
6576 }
6577 break;
6578 case 11: /* 16KB Pages. */
6579 if (level == 0 || (level == 1 && pamax <= 40)) {
6580 return false;
6581 }
6582 break;
6583 case 9: /* 4KB Pages. */
6584 if (level == 0 && pamax <= 42) {
6585 return false;
6586 }
6587 break;
6588 default:
6589 g_assert_not_reached();
6590 }
6591 } else {
6592 const int grainsize = stride + 3;
6593 int startsizecheck;
6594
6595 /* AArch32 only supports 4KB pages. Assert on that. */
6596 assert(stride == 9);
6597
6598 if (level == 0) {
6599 return false;
6600 }
6601
6602 startsizecheck = inputsize - ((3 - level) * stride + grainsize);
6603 if (startsizecheck < 1 || startsizecheck > stride + 4) {
6604 return false;
6605 }
6606 }
6607 return true;
6608 }
6609
6610 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
6611 int access_type, ARMMMUIdx mmu_idx,
6612 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
6613 target_ulong *page_size_ptr, uint32_t *fsr,
6614 ARMMMUFaultInfo *fi)
6615 {
6616 ARMCPU *cpu = arm_env_get_cpu(env);
6617 CPUState *cs = CPU(cpu);
6618 /* Read an LPAE long-descriptor translation table. */
6619 MMUFaultType fault_type = translation_fault;
6620 uint32_t level = 1;
6621 uint32_t epd = 0;
6622 int32_t t0sz, t1sz;
6623 uint32_t tg;
6624 uint64_t ttbr;
6625 int ttbr_select;
6626 hwaddr descaddr, descmask;
6627 uint32_t tableattrs;
6628 target_ulong page_size;
6629 uint32_t attrs;
6630 int32_t stride = 9;
6631 int32_t va_size = 32;
6632 int inputsize;
6633 int32_t tbi = 0;
6634 TCR *tcr = regime_tcr(env, mmu_idx);
6635 int ap, ns, xn, pxn;
6636 uint32_t el = regime_el(env, mmu_idx);
6637 bool ttbr1_valid = true;
6638
6639 /* TODO:
6640 * This code does not handle the different format TCR for VTCR_EL2.
6641 * This code also does not support shareability levels.
6642 * Attribute and permission bit handling should also be checked when adding
6643 * support for those page table walks.
6644 */
6645 if (arm_el_is_aa64(env, el)) {
6646 va_size = 64;
6647 if (el > 1) {
6648 if (mmu_idx != ARMMMUIdx_S2NS) {
6649 tbi = extract64(tcr->raw_tcr, 20, 1);
6650 }
6651 } else {
6652 if (extract64(address, 55, 1)) {
6653 tbi = extract64(tcr->raw_tcr, 38, 1);
6654 } else {
6655 tbi = extract64(tcr->raw_tcr, 37, 1);
6656 }
6657 }
6658 tbi *= 8;
6659
6660 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
6661 * invalid.
6662 */
6663 if (el > 1) {
6664 ttbr1_valid = false;
6665 }
6666 } else {
6667 /* There is no TTBR1 for EL2 */
6668 if (el == 2) {
6669 ttbr1_valid = false;
6670 }
6671 }
6672
6673 /* Determine whether this address is in the region controlled by
6674 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
6675 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
6676 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
6677 */
6678 if (va_size == 64) {
6679 /* AArch64 translation. */
6680 t0sz = extract32(tcr->raw_tcr, 0, 6);
6681 t0sz = MIN(t0sz, 39);
6682 t0sz = MAX(t0sz, 16);
6683 } else if (mmu_idx != ARMMMUIdx_S2NS) {
6684 /* AArch32 stage 1 translation. */
6685 t0sz = extract32(tcr->raw_tcr, 0, 3);
6686 } else {
6687 /* AArch32 stage 2 translation. */
6688 bool sext = extract32(tcr->raw_tcr, 4, 1);
6689 bool sign = extract32(tcr->raw_tcr, 3, 1);
6690 t0sz = sextract32(tcr->raw_tcr, 0, 4);
6691
6692 /* If the sign-extend bit is not the same as t0sz[3], the result
6693 * is unpredictable. Flag this as a guest error. */
6694 if (sign != sext) {
6695 qemu_log_mask(LOG_GUEST_ERROR,
6696 "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
6697 }
6698 }
6699 t1sz = extract32(tcr->raw_tcr, 16, 6);
6700 if (va_size == 64) {
6701 t1sz = MIN(t1sz, 39);
6702 t1sz = MAX(t1sz, 16);
6703 }
6704 if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
6705 /* there is a ttbr0 region and we are in it (high bits all zero) */
6706 ttbr_select = 0;
6707 } else if (ttbr1_valid && t1sz &&
6708 !extract64(~address, va_size - t1sz, t1sz - tbi)) {
6709 /* there is a ttbr1 region and we are in it (high bits all one) */
6710 ttbr_select = 1;
6711 } else if (!t0sz) {
6712 /* ttbr0 region is "everything not in the ttbr1 region" */
6713 ttbr_select = 0;
6714 } else if (!t1sz && ttbr1_valid) {
6715 /* ttbr1 region is "everything not in the ttbr0 region" */
6716 ttbr_select = 1;
6717 } else {
6718 /* in the gap between the two regions, this is a Translation fault */
6719 fault_type = translation_fault;
6720 goto do_fault;
6721 }
6722
6723 /* Note that QEMU ignores shareability and cacheability attributes,
6724 * so we don't need to do anything with the SH, ORGN, IRGN fields
6725 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
6726 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
6727 * implement any ASID-like capability so we can ignore it (instead
6728 * we will always flush the TLB any time the ASID is changed).
6729 */
6730 if (ttbr_select == 0) {
6731 ttbr = regime_ttbr(env, mmu_idx, 0);
6732 if (el < 2) {
6733 epd = extract32(tcr->raw_tcr, 7, 1);
6734 }
6735 inputsize = va_size - t0sz;
6736
6737 tg = extract32(tcr->raw_tcr, 14, 2);
6738 if (tg == 1) { /* 64KB pages */
6739 stride = 13;
6740 }
6741 if (tg == 2) { /* 16KB pages */
6742 stride = 11;
6743 }
6744 } else {
6745 /* We should only be here if TTBR1 is valid */
6746 assert(ttbr1_valid);
6747
6748 ttbr = regime_ttbr(env, mmu_idx, 1);
6749 epd = extract32(tcr->raw_tcr, 23, 1);
6750 inputsize = va_size - t1sz;
6751
6752 tg = extract32(tcr->raw_tcr, 30, 2);
6753 if (tg == 3) { /* 64KB pages */
6754 stride = 13;
6755 }
6756 if (tg == 1) { /* 16KB pages */
6757 stride = 11;
6758 }
6759 }
6760
6761 /* Here we should have set up all the parameters for the translation:
6762 * va_size, inputsize, ttbr, epd, stride, tbi
6763 */
6764
6765 if (epd) {
6766 /* Translation table walk disabled => Translation fault on TLB miss
6767 * Note: This is always 0 on 64-bit EL2 and EL3.
6768 */
6769 goto do_fault;
6770 }
6771
6772 if (mmu_idx != ARMMMUIdx_S2NS) {
6773 /* The starting level depends on the virtual address size (which can
6774 * be up to 48 bits) and the translation granule size. It indicates
6775 * the number of strides (stride bits at a time) needed to
6776 * consume the bits of the input address. In the pseudocode this is:
6777 * level = 4 - RoundUp((inputsize - grainsize) / stride)
6778 * where their 'inputsize' is our 'inputsize', 'grainsize' is
6779 * our 'stride + 3' and 'stride' is our 'stride'.
6780 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
6781 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
6782 * = 4 - (inputsize - 4) / stride;
6783 */
6784 level = 4 - (inputsize - 4) / stride;
6785 } else {
6786 /* For stage 2 translations the starting level is specified by the
6787 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
6788 */
6789 int startlevel = extract32(tcr->raw_tcr, 6, 2);
6790 bool ok;
6791
6792 if (va_size == 32 || stride == 9) {
6793 /* AArch32 or 4KB pages */
6794 level = 2 - startlevel;
6795 } else {
6796 /* 16KB or 64KB pages */
6797 level = 3 - startlevel;
6798 }
6799
6800 /* Check that the starting level is valid. */
6801 ok = check_s2_startlevel(cpu, va_size == 64, level,
6802 inputsize, stride);
6803 if (!ok) {
6804 /* AArch64 reports these as level 0 faults.
6805 * AArch32 reports these as level 1 faults.
6806 */
6807 level = va_size == 64 ? 0 : 1;
6808 fault_type = translation_fault;
6809 goto do_fault;
6810 }
6811 }
6812
6813 /* Clear the vaddr bits which aren't part of the within-region address,
6814 * so that we don't have to special case things when calculating the
6815 * first descriptor address.
6816 */
6817 if (va_size != inputsize) {
6818 address &= (1ULL << inputsize) - 1;
6819 }
6820
6821 descmask = (1ULL << (stride + 3)) - 1;
6822
6823 /* Now we can extract the actual base address from the TTBR */
6824 descaddr = extract64(ttbr, 0, 48);
6825 descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
6826
6827 /* Secure accesses start with the page table in secure memory and
6828 * can be downgraded to non-secure at any step. Non-secure accesses
6829 * remain non-secure. We implement this by just ORing in the NSTable/NS
6830 * bits at each step.
6831 */
6832 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
6833 for (;;) {
6834 uint64_t descriptor;
6835 bool nstable;
6836
6837 descaddr |= (address >> (stride * (4 - level))) & descmask;
6838 descaddr &= ~7ULL;
6839 nstable = extract32(tableattrs, 4, 1);
6840 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
6841 if (fi->s1ptw) {
6842 goto do_fault;
6843 }
6844
6845 if (!(descriptor & 1) ||
6846 (!(descriptor & 2) && (level == 3))) {
6847 /* Invalid, or the Reserved level 3 encoding */
6848 goto do_fault;
6849 }
6850 descaddr = descriptor & 0xfffffff000ULL;
6851
6852 if ((descriptor & 2) && (level < 3)) {
6853 /* Table entry. The top five bits are attributes which may
6854 * propagate down through lower levels of the table (and
6855 * which are all arranged so that 0 means "no effect", so
6856 * we can gather them up by ORing in the bits at each level).
6857 */
6858 tableattrs |= extract64(descriptor, 59, 5);
6859 level++;
6860 continue;
6861 }
6862 /* Block entry at level 1 or 2, or page entry at level 3.
6863 * These are basically the same thing, although the number
6864 * of bits we pull in from the vaddr varies.
6865 */
6866 page_size = (1ULL << ((stride * (4 - level)) + 3));
6867 descaddr |= (address & (page_size - 1));
6868 /* Extract attributes from the descriptor */
6869 attrs = extract64(descriptor, 2, 10)
6870 | (extract64(descriptor, 52, 12) << 10);
6871
6872 if (mmu_idx == ARMMMUIdx_S2NS) {
6873 /* Stage 2 table descriptors do not include any attribute fields */
6874 break;
6875 }
6876 /* Merge in attributes from table descriptors */
6877 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
6878 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
6879 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
6880 * means "force PL1 access only", which means forcing AP[1] to 0.
6881 */
6882 if (extract32(tableattrs, 2, 1)) {
6883 attrs &= ~(1 << 4);
6884 }
6885 attrs |= nstable << 3; /* NS */
6886 break;
6887 }
6888 /* Here descaddr is the final physical address, and attributes
6889 * are all in attrs.
6890 */
6891 fault_type = access_fault;
6892 if ((attrs & (1 << 8)) == 0) {
6893 /* Access flag */
6894 goto do_fault;
6895 }
6896
6897 ap = extract32(attrs, 4, 2);
6898 xn = extract32(attrs, 12, 1);
6899
6900 if (mmu_idx == ARMMMUIdx_S2NS) {
6901 ns = true;
6902 *prot = get_S2prot(env, ap, xn);
6903 } else {
6904 ns = extract32(attrs, 3, 1);
6905 pxn = extract32(attrs, 11, 1);
6906 *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
6907 }
6908
6909 fault_type = permission_fault;
6910 if (!(*prot & (1 << access_type))) {
6911 goto do_fault;
6912 }
6913
6914 if (ns) {
6915 /* The NS bit will (as required by the architecture) have no effect if
6916 * the CPU doesn't support TZ or this is a non-secure translation
6917 * regime, because the attribute will already be non-secure.
6918 */
6919 txattrs->secure = false;
6920 }
6921 *phys_ptr = descaddr;
6922 *page_size_ptr = page_size;
6923 return false;
6924
6925 do_fault:
6926 /* Long-descriptor format IFSR/DFSR value */
6927 *fsr = (1 << 9) | (fault_type << 2) | level;
6928 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
6929 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
6930 return true;
6931 }
6932
6933 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
6934 ARMMMUIdx mmu_idx,
6935 int32_t address, int *prot)
6936 {
6937 *prot = PAGE_READ | PAGE_WRITE;
6938 switch (address) {
6939 case 0xF0000000 ... 0xFFFFFFFF:
6940 if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
6941 *prot |= PAGE_EXEC;
6942 }
6943 break;
6944 case 0x00000000 ... 0x7FFFFFFF:
6945 *prot |= PAGE_EXEC;
6946 break;
6947 }
6948
6949 }
6950
6951 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
6952 int access_type, ARMMMUIdx mmu_idx,
6953 hwaddr *phys_ptr, int *prot, uint32_t *fsr)
6954 {
6955 ARMCPU *cpu = arm_env_get_cpu(env);
6956 int n;
6957 bool is_user = regime_is_user(env, mmu_idx);
6958
6959 *phys_ptr = address;
6960 *prot = 0;
6961
6962 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
6963 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
6964 } else { /* MPU enabled */
6965 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
6966 /* region search */
6967 uint32_t base = env->pmsav7.drbar[n];
6968 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
6969 uint32_t rmask;
6970 bool srdis = false;
6971
6972 if (!(env->pmsav7.drsr[n] & 0x1)) {
6973 continue;
6974 }
6975
6976 if (!rsize) {
6977 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
6978 continue;
6979 }
6980 rsize++;
6981 rmask = (1ull << rsize) - 1;
6982
6983 if (base & rmask) {
6984 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
6985 "to DRSR region size, mask = %" PRIx32,
6986 base, rmask);
6987 continue;
6988 }
6989
6990 if (address < base || address > base + rmask) {
6991 continue;
6992 }
6993
6994 /* Region matched */
6995
6996 if (rsize >= 8) { /* no subregions for regions < 256 bytes */
6997 int i, snd;
6998 uint32_t srdis_mask;
6999
7000 rsize -= 3; /* sub region size (power of 2) */
7001 snd = ((address - base) >> rsize) & 0x7;
7002 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
7003
7004 srdis_mask = srdis ? 0x3 : 0x0;
7005 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
7006 /* This will check in groups of 2, 4 and then 8, whether
7007 * the subregion bits are consistent. rsize is incremented
7008 * back up to give the region size, considering consistent
7009 * adjacent subregions as one region. Stop testing if rsize
7010 * is already big enough for an entire QEMU page.
7011 */
7012 int snd_rounded = snd & ~(i - 1);
7013 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
7014 snd_rounded + 8, i);
7015 if (srdis_mask ^ srdis_multi) {
7016 break;
7017 }
7018 srdis_mask = (srdis_mask << i) | srdis_mask;
7019 rsize++;
7020 }
7021 }
7022 if (rsize < TARGET_PAGE_BITS) {
7023 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
7024 "alignment of %" PRIu32 " bits. Minimum is %d\n",
7025 rsize, TARGET_PAGE_BITS);
7026 continue;
7027 }
7028 if (srdis) {
7029 continue;
7030 }
7031 break;
7032 }
7033
7034 if (n == -1) { /* no hits */
7035 if (cpu->pmsav7_dregion &&
7036 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
7037 /* background fault */
7038 *fsr = 0;
7039 return true;
7040 }
7041 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7042 } else { /* a MPU hit! */
7043 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
7044
7045 if (is_user) { /* User mode AP bit decoding */
7046 switch (ap) {
7047 case 0:
7048 case 1:
7049 case 5:
7050 break; /* no access */
7051 case 3:
7052 *prot |= PAGE_WRITE;
7053 /* fall through */
7054 case 2:
7055 case 6:
7056 *prot |= PAGE_READ | PAGE_EXEC;
7057 break;
7058 default:
7059 qemu_log_mask(LOG_GUEST_ERROR,
7060 "Bad value for AP bits in DRACR %"
7061 PRIx32 "\n", ap);
7062 }
7063 } else { /* Priv. mode AP bits decoding */
7064 switch (ap) {
7065 case 0:
7066 break; /* no access */
7067 case 1:
7068 case 2:
7069 case 3:
7070 *prot |= PAGE_WRITE;
7071 /* fall through */
7072 case 5:
7073 case 6:
7074 *prot |= PAGE_READ | PAGE_EXEC;
7075 break;
7076 default:
7077 qemu_log_mask(LOG_GUEST_ERROR,
7078 "Bad value for AP bits in DRACR %"
7079 PRIx32 "\n", ap);
7080 }
7081 }
7082
7083 /* execute never */
7084 if (env->pmsav7.dracr[n] & (1 << 12)) {
7085 *prot &= ~PAGE_EXEC;
7086 }
7087 }
7088 }
7089
7090 *fsr = 0x00d; /* Permission fault */
7091 return !(*prot & (1 << access_type));
7092 }
7093
7094 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
7095 int access_type, ARMMMUIdx mmu_idx,
7096 hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7097 {
7098 int n;
7099 uint32_t mask;
7100 uint32_t base;
7101 bool is_user = regime_is_user(env, mmu_idx);
7102
7103 *phys_ptr = address;
7104 for (n = 7; n >= 0; n--) {
7105 base = env->cp15.c6_region[n];
7106 if ((base & 1) == 0) {
7107 continue;
7108 }
7109 mask = 1 << ((base >> 1) & 0x1f);
7110 /* Keep this shift separate from the above to avoid an
7111 (undefined) << 32. */
7112 mask = (mask << 1) - 1;
7113 if (((base ^ address) & ~mask) == 0) {
7114 break;
7115 }
7116 }
7117 if (n < 0) {
7118 *fsr = 2;
7119 return true;
7120 }
7121
7122 if (access_type == 2) {
7123 mask = env->cp15.pmsav5_insn_ap;
7124 } else {
7125 mask = env->cp15.pmsav5_data_ap;
7126 }
7127 mask = (mask >> (n * 4)) & 0xf;
7128 switch (mask) {
7129 case 0:
7130 *fsr = 1;
7131 return true;
7132 case 1:
7133 if (is_user) {
7134 *fsr = 1;
7135 return true;
7136 }
7137 *prot = PAGE_READ | PAGE_WRITE;
7138 break;
7139 case 2:
7140 *prot = PAGE_READ;
7141 if (!is_user) {
7142 *prot |= PAGE_WRITE;
7143 }
7144 break;
7145 case 3:
7146 *prot = PAGE_READ | PAGE_WRITE;
7147 break;
7148 case 5:
7149 if (is_user) {
7150 *fsr = 1;
7151 return true;
7152 }
7153 *prot = PAGE_READ;
7154 break;
7155 case 6:
7156 *prot = PAGE_READ;
7157 break;
7158 default:
7159 /* Bad permission. */
7160 *fsr = 1;
7161 return true;
7162 }
7163 *prot |= PAGE_EXEC;
7164 return false;
7165 }
7166
7167 /* get_phys_addr - get the physical address for this virtual address
7168 *
7169 * Find the physical address corresponding to the given virtual address,
7170 * by doing a translation table walk on MMU based systems or using the
7171 * MPU state on MPU based systems.
7172 *
7173 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7174 * prot and page_size may not be filled in, and the populated fsr value provides
7175 * information on why the translation aborted, in the format of a
7176 * DFSR/IFSR fault register, with the following caveats:
7177 * * we honour the short vs long DFSR format differences.
7178 * * the WnR bit is never set (the caller must do this).
7179 * * for PSMAv5 based systems we don't bother to return a full FSR format
7180 * value.
7181 *
7182 * @env: CPUARMState
7183 * @address: virtual address to get physical address for
7184 * @access_type: 0 for read, 1 for write, 2 for execute
7185 * @mmu_idx: MMU index indicating required translation regime
7186 * @phys_ptr: set to the physical address corresponding to the virtual address
7187 * @attrs: set to the memory transaction attributes to use
7188 * @prot: set to the permissions for the page containing phys_ptr
7189 * @page_size: set to the size of the page containing phys_ptr
7190 * @fsr: set to the DFSR/IFSR value on failure
7191 */
7192 static bool get_phys_addr(CPUARMState *env, target_ulong address,
7193 int access_type, ARMMMUIdx mmu_idx,
7194 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7195 target_ulong *page_size, uint32_t *fsr,
7196 ARMMMUFaultInfo *fi)
7197 {
7198 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7199 /* Call ourselves recursively to do the stage 1 and then stage 2
7200 * translations.
7201 */
7202 if (arm_feature(env, ARM_FEATURE_EL2)) {
7203 hwaddr ipa;
7204 int s2_prot;
7205 int ret;
7206
7207 ret = get_phys_addr(env, address, access_type,
7208 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
7209 prot, page_size, fsr, fi);
7210
7211 /* If S1 fails or S2 is disabled, return early. */
7212 if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7213 *phys_ptr = ipa;
7214 return ret;
7215 }
7216
7217 /* S1 is done. Now do S2 translation. */
7218 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
7219 phys_ptr, attrs, &s2_prot,
7220 page_size, fsr, fi);
7221 fi->s2addr = ipa;
7222 /* Combine the S1 and S2 perms. */
7223 *prot &= s2_prot;
7224 return ret;
7225 } else {
7226 /*
7227 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7228 */
7229 mmu_idx += ARMMMUIdx_S1NSE0;
7230 }
7231 }
7232
7233 /* The page table entries may downgrade secure to non-secure, but
7234 * cannot upgrade an non-secure translation regime's attributes
7235 * to secure.
7236 */
7237 attrs->secure = regime_is_secure(env, mmu_idx);
7238 attrs->user = regime_is_user(env, mmu_idx);
7239
7240 /* Fast Context Switch Extension. This doesn't exist at all in v8.
7241 * In v7 and earlier it affects all stage 1 translations.
7242 */
7243 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
7244 && !arm_feature(env, ARM_FEATURE_V8)) {
7245 if (regime_el(env, mmu_idx) == 3) {
7246 address += env->cp15.fcseidr_s;
7247 } else {
7248 address += env->cp15.fcseidr_ns;
7249 }
7250 }
7251
7252 /* pmsav7 has special handling for when MPU is disabled so call it before
7253 * the common MMU/MPU disabled check below.
7254 */
7255 if (arm_feature(env, ARM_FEATURE_MPU) &&
7256 arm_feature(env, ARM_FEATURE_V7)) {
7257 *page_size = TARGET_PAGE_SIZE;
7258 return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
7259 phys_ptr, prot, fsr);
7260 }
7261
7262 if (regime_translation_disabled(env, mmu_idx)) {
7263 /* MMU/MPU disabled. */
7264 *phys_ptr = address;
7265 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7266 *page_size = TARGET_PAGE_SIZE;
7267 return 0;
7268 }
7269
7270 if (arm_feature(env, ARM_FEATURE_MPU)) {
7271 /* Pre-v7 MPU */
7272 *page_size = TARGET_PAGE_SIZE;
7273 return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
7274 phys_ptr, prot, fsr);
7275 }
7276
7277 if (regime_using_lpae_format(env, mmu_idx)) {
7278 return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
7279 attrs, prot, page_size, fsr, fi);
7280 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
7281 return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
7282 attrs, prot, page_size, fsr, fi);
7283 } else {
7284 return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
7285 prot, page_size, fsr, fi);
7286 }
7287 }
7288
7289 /* Walk the page table and (if the mapping exists) add the page
7290 * to the TLB. Return false on success, or true on failure. Populate
7291 * fsr with ARM DFSR/IFSR fault register format value on failure.
7292 */
7293 bool arm_tlb_fill(CPUState *cs, vaddr address,
7294 int access_type, int mmu_idx, uint32_t *fsr,
7295 ARMMMUFaultInfo *fi)
7296 {
7297 ARMCPU *cpu = ARM_CPU(cs);
7298 CPUARMState *env = &cpu->env;
7299 hwaddr phys_addr;
7300 target_ulong page_size;
7301 int prot;
7302 int ret;
7303 MemTxAttrs attrs = {};
7304
7305 ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
7306 &attrs, &prot, &page_size, fsr, fi);
7307 if (!ret) {
7308 /* Map a single [sub]page. */
7309 phys_addr &= TARGET_PAGE_MASK;
7310 address &= TARGET_PAGE_MASK;
7311 tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
7312 prot, mmu_idx, page_size);
7313 return 0;
7314 }
7315
7316 return ret;
7317 }
7318
7319 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
7320 {
7321 ARMCPU *cpu = ARM_CPU(cs);
7322 CPUARMState *env = &cpu->env;
7323 hwaddr phys_addr;
7324 target_ulong page_size;
7325 int prot;
7326 bool ret;
7327 uint32_t fsr;
7328 MemTxAttrs attrs = {};
7329 ARMMMUFaultInfo fi = {};
7330
7331 ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
7332 &attrs, &prot, &page_size, &fsr, &fi);
7333
7334 if (ret) {
7335 return -1;
7336 }
7337
7338 return phys_addr;
7339 }
7340
7341 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
7342 {
7343 if ((env->uncached_cpsr & CPSR_M) == mode) {
7344 env->regs[13] = val;
7345 } else {
7346 env->banked_r13[bank_number(mode)] = val;
7347 }
7348 }
7349
7350 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
7351 {
7352 if ((env->uncached_cpsr & CPSR_M) == mode) {
7353 return env->regs[13];
7354 } else {
7355 return env->banked_r13[bank_number(mode)];
7356 }
7357 }
7358
7359 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
7360 {
7361 ARMCPU *cpu = arm_env_get_cpu(env);
7362
7363 switch (reg) {
7364 case 0: /* APSR */
7365 return xpsr_read(env) & 0xf8000000;
7366 case 1: /* IAPSR */
7367 return xpsr_read(env) & 0xf80001ff;
7368 case 2: /* EAPSR */
7369 return xpsr_read(env) & 0xff00fc00;
7370 case 3: /* xPSR */
7371 return xpsr_read(env) & 0xff00fdff;
7372 case 5: /* IPSR */
7373 return xpsr_read(env) & 0x000001ff;
7374 case 6: /* EPSR */
7375 return xpsr_read(env) & 0x0700fc00;
7376 case 7: /* IEPSR */
7377 return xpsr_read(env) & 0x0700edff;
7378 case 8: /* MSP */
7379 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
7380 case 9: /* PSP */
7381 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
7382 case 16: /* PRIMASK */
7383 return (env->daif & PSTATE_I) != 0;
7384 case 17: /* BASEPRI */
7385 case 18: /* BASEPRI_MAX */
7386 return env->v7m.basepri;
7387 case 19: /* FAULTMASK */
7388 return (env->daif & PSTATE_F) != 0;
7389 case 20: /* CONTROL */
7390 return env->v7m.control;
7391 default:
7392 /* ??? For debugging only. */
7393 cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
7394 return 0;
7395 }
7396 }
7397
7398 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
7399 {
7400 ARMCPU *cpu = arm_env_get_cpu(env);
7401
7402 switch (reg) {
7403 case 0: /* APSR */
7404 xpsr_write(env, val, 0xf8000000);
7405 break;
7406 case 1: /* IAPSR */
7407 xpsr_write(env, val, 0xf8000000);
7408 break;
7409 case 2: /* EAPSR */
7410 xpsr_write(env, val, 0xfe00fc00);
7411 break;
7412 case 3: /* xPSR */
7413 xpsr_write(env, val, 0xfe00fc00);
7414 break;
7415 case 5: /* IPSR */
7416 /* IPSR bits are readonly. */
7417 break;
7418 case 6: /* EPSR */
7419 xpsr_write(env, val, 0x0600fc00);
7420 break;
7421 case 7: /* IEPSR */
7422 xpsr_write(env, val, 0x0600fc00);
7423 break;
7424 case 8: /* MSP */
7425 if (env->v7m.current_sp)
7426 env->v7m.other_sp = val;
7427 else
7428 env->regs[13] = val;
7429 break;
7430 case 9: /* PSP */
7431 if (env->v7m.current_sp)
7432 env->regs[13] = val;
7433 else
7434 env->v7m.other_sp = val;
7435 break;
7436 case 16: /* PRIMASK */
7437 if (val & 1) {
7438 env->daif |= PSTATE_I;
7439 } else {
7440 env->daif &= ~PSTATE_I;
7441 }
7442 break;
7443 case 17: /* BASEPRI */
7444 env->v7m.basepri = val & 0xff;
7445 break;
7446 case 18: /* BASEPRI_MAX */
7447 val &= 0xff;
7448 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
7449 env->v7m.basepri = val;
7450 break;
7451 case 19: /* FAULTMASK */
7452 if (val & 1) {
7453 env->daif |= PSTATE_F;
7454 } else {
7455 env->daif &= ~PSTATE_F;
7456 }
7457 break;
7458 case 20: /* CONTROL */
7459 env->v7m.control = val & 3;
7460 switch_v7m_sp(env, (val & 2) != 0);
7461 break;
7462 default:
7463 /* ??? For debugging only. */
7464 cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
7465 return;
7466 }
7467 }
7468
7469 #endif
7470
7471 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
7472 {
7473 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
7474 * Note that we do not implement the (architecturally mandated)
7475 * alignment fault for attempts to use this on Device memory
7476 * (which matches the usual QEMU behaviour of not implementing either
7477 * alignment faults or any memory attribute handling).
7478 */
7479
7480 ARMCPU *cpu = arm_env_get_cpu(env);
7481 uint64_t blocklen = 4 << cpu->dcz_blocksize;
7482 uint64_t vaddr = vaddr_in & ~(blocklen - 1);
7483
7484 #ifndef CONFIG_USER_ONLY
7485 {
7486 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
7487 * the block size so we might have to do more than one TLB lookup.
7488 * We know that in fact for any v8 CPU the page size is at least 4K
7489 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
7490 * 1K as an artefact of legacy v5 subpage support being present in the
7491 * same QEMU executable.
7492 */
7493 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
7494 void *hostaddr[maxidx];
7495 int try, i;
7496 unsigned mmu_idx = cpu_mmu_index(env, false);
7497 TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
7498
7499 for (try = 0; try < 2; try++) {
7500
7501 for (i = 0; i < maxidx; i++) {
7502 hostaddr[i] = tlb_vaddr_to_host(env,
7503 vaddr + TARGET_PAGE_SIZE * i,
7504 1, mmu_idx);
7505 if (!hostaddr[i]) {
7506 break;
7507 }
7508 }
7509 if (i == maxidx) {
7510 /* If it's all in the TLB it's fair game for just writing to;
7511 * we know we don't need to update dirty status, etc.
7512 */
7513 for (i = 0; i < maxidx - 1; i++) {
7514 memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
7515 }
7516 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
7517 return;
7518 }
7519 /* OK, try a store and see if we can populate the tlb. This
7520 * might cause an exception if the memory isn't writable,
7521 * in which case we will longjmp out of here. We must for
7522 * this purpose use the actual register value passed to us
7523 * so that we get the fault address right.
7524 */
7525 helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
7526 /* Now we can populate the other TLB entries, if any */
7527 for (i = 0; i < maxidx; i++) {
7528 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
7529 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
7530 helper_ret_stb_mmu(env, va, 0, oi, GETRA());
7531 }
7532 }
7533 }
7534
7535 /* Slow path (probably attempt to do this to an I/O device or
7536 * similar, or clearing of a block of code we have translations
7537 * cached for). Just do a series of byte writes as the architecture
7538 * demands. It's not worth trying to use a cpu_physical_memory_map(),
7539 * memset(), unmap() sequence here because:
7540 * + we'd need to account for the blocksize being larger than a page
7541 * + the direct-RAM access case is almost always going to be dealt
7542 * with in the fastpath code above, so there's no speed benefit
7543 * + we would have to deal with the map returning NULL because the
7544 * bounce buffer was in use
7545 */
7546 for (i = 0; i < blocklen; i++) {
7547 helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
7548 }
7549 }
7550 #else
7551 memset(g2h(vaddr), 0, blocklen);
7552 #endif
7553 }
7554
7555 /* Note that signed overflow is undefined in C. The following routines are
7556 careful to use unsigned types where modulo arithmetic is required.
7557 Failure to do so _will_ break on newer gcc. */
7558
7559 /* Signed saturating arithmetic. */
7560
7561 /* Perform 16-bit signed saturating addition. */
7562 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
7563 {
7564 uint16_t res;
7565
7566 res = a + b;
7567 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
7568 if (a & 0x8000)
7569 res = 0x8000;
7570 else
7571 res = 0x7fff;
7572 }
7573 return res;
7574 }
7575
7576 /* Perform 8-bit signed saturating addition. */
7577 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
7578 {
7579 uint8_t res;
7580
7581 res = a + b;
7582 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
7583 if (a & 0x80)
7584 res = 0x80;
7585 else
7586 res = 0x7f;
7587 }
7588 return res;
7589 }
7590
7591 /* Perform 16-bit signed saturating subtraction. */
7592 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
7593 {
7594 uint16_t res;
7595
7596 res = a - b;
7597 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
7598 if (a & 0x8000)
7599 res = 0x8000;
7600 else
7601 res = 0x7fff;
7602 }
7603 return res;
7604 }
7605
7606 /* Perform 8-bit signed saturating subtraction. */
7607 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
7608 {
7609 uint8_t res;
7610
7611 res = a - b;
7612 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
7613 if (a & 0x80)
7614 res = 0x80;
7615 else
7616 res = 0x7f;
7617 }
7618 return res;
7619 }
7620
7621 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
7622 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
7623 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
7624 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
7625 #define PFX q
7626
7627 #include "op_addsub.h"
7628
7629 /* Unsigned saturating arithmetic. */
7630 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
7631 {
7632 uint16_t res;
7633 res = a + b;
7634 if (res < a)
7635 res = 0xffff;
7636 return res;
7637 }
7638
7639 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
7640 {
7641 if (a > b)
7642 return a - b;
7643 else
7644 return 0;
7645 }
7646
7647 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
7648 {
7649 uint8_t res;
7650 res = a + b;
7651 if (res < a)
7652 res = 0xff;
7653 return res;
7654 }
7655
7656 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
7657 {
7658 if (a > b)
7659 return a - b;
7660 else
7661 return 0;
7662 }
7663
7664 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
7665 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
7666 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
7667 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
7668 #define PFX uq
7669
7670 #include "op_addsub.h"
7671
7672 /* Signed modulo arithmetic. */
7673 #define SARITH16(a, b, n, op) do { \
7674 int32_t sum; \
7675 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
7676 RESULT(sum, n, 16); \
7677 if (sum >= 0) \
7678 ge |= 3 << (n * 2); \
7679 } while(0)
7680
7681 #define SARITH8(a, b, n, op) do { \
7682 int32_t sum; \
7683 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
7684 RESULT(sum, n, 8); \
7685 if (sum >= 0) \
7686 ge |= 1 << n; \
7687 } while(0)
7688
7689
7690 #define ADD16(a, b, n) SARITH16(a, b, n, +)
7691 #define SUB16(a, b, n) SARITH16(a, b, n, -)
7692 #define ADD8(a, b, n) SARITH8(a, b, n, +)
7693 #define SUB8(a, b, n) SARITH8(a, b, n, -)
7694 #define PFX s
7695 #define ARITH_GE
7696
7697 #include "op_addsub.h"
7698
7699 /* Unsigned modulo arithmetic. */
7700 #define ADD16(a, b, n) do { \
7701 uint32_t sum; \
7702 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
7703 RESULT(sum, n, 16); \
7704 if ((sum >> 16) == 1) \
7705 ge |= 3 << (n * 2); \
7706 } while(0)
7707
7708 #define ADD8(a, b, n) do { \
7709 uint32_t sum; \
7710 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
7711 RESULT(sum, n, 8); \
7712 if ((sum >> 8) == 1) \
7713 ge |= 1 << n; \
7714 } while(0)
7715
7716 #define SUB16(a, b, n) do { \
7717 uint32_t sum; \
7718 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
7719 RESULT(sum, n, 16); \
7720 if ((sum >> 16) == 0) \
7721 ge |= 3 << (n * 2); \
7722 } while(0)
7723
7724 #define SUB8(a, b, n) do { \
7725 uint32_t sum; \
7726 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
7727 RESULT(sum, n, 8); \
7728 if ((sum >> 8) == 0) \
7729 ge |= 1 << n; \
7730 } while(0)
7731
7732 #define PFX u
7733 #define ARITH_GE
7734
7735 #include "op_addsub.h"
7736
7737 /* Halved signed arithmetic. */
7738 #define ADD16(a, b, n) \
7739 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
7740 #define SUB16(a, b, n) \
7741 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
7742 #define ADD8(a, b, n) \
7743 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
7744 #define SUB8(a, b, n) \
7745 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
7746 #define PFX sh
7747
7748 #include "op_addsub.h"
7749
7750 /* Halved unsigned arithmetic. */
7751 #define ADD16(a, b, n) \
7752 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7753 #define SUB16(a, b, n) \
7754 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7755 #define ADD8(a, b, n) \
7756 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7757 #define SUB8(a, b, n) \
7758 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7759 #define PFX uh
7760
7761 #include "op_addsub.h"
7762
7763 static inline uint8_t do_usad(uint8_t a, uint8_t b)
7764 {
7765 if (a > b)
7766 return a - b;
7767 else
7768 return b - a;
7769 }
7770
7771 /* Unsigned sum of absolute byte differences. */
7772 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
7773 {
7774 uint32_t sum;
7775 sum = do_usad(a, b);
7776 sum += do_usad(a >> 8, b >> 8);
7777 sum += do_usad(a >> 16, b >>16);
7778 sum += do_usad(a >> 24, b >> 24);
7779 return sum;
7780 }
7781
7782 /* For ARMv6 SEL instruction. */
7783 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
7784 {
7785 uint32_t mask;
7786
7787 mask = 0;
7788 if (flags & 1)
7789 mask |= 0xff;
7790 if (flags & 2)
7791 mask |= 0xff00;
7792 if (flags & 4)
7793 mask |= 0xff0000;
7794 if (flags & 8)
7795 mask |= 0xff000000;
7796 return (a & mask) | (b & ~mask);
7797 }
7798
7799 /* VFP support. We follow the convention used for VFP instructions:
7800 Single precision routines have a "s" suffix, double precision a
7801 "d" suffix. */
7802
7803 /* Convert host exception flags to vfp form. */
7804 static inline int vfp_exceptbits_from_host(int host_bits)
7805 {
7806 int target_bits = 0;
7807
7808 if (host_bits & float_flag_invalid)
7809 target_bits |= 1;
7810 if (host_bits & float_flag_divbyzero)
7811 target_bits |= 2;
7812 if (host_bits & float_flag_overflow)
7813 target_bits |= 4;
7814 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
7815 target_bits |= 8;
7816 if (host_bits & float_flag_inexact)
7817 target_bits |= 0x10;
7818 if (host_bits & float_flag_input_denormal)
7819 target_bits |= 0x80;
7820 return target_bits;
7821 }
7822
7823 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
7824 {
7825 int i;
7826 uint32_t fpscr;
7827
7828 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
7829 | (env->vfp.vec_len << 16)
7830 | (env->vfp.vec_stride << 20);
7831 i = get_float_exception_flags(&env->vfp.fp_status);
7832 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
7833 fpscr |= vfp_exceptbits_from_host(i);
7834 return fpscr;
7835 }
7836
7837 uint32_t vfp_get_fpscr(CPUARMState *env)
7838 {
7839 return HELPER(vfp_get_fpscr)(env);
7840 }
7841
7842 /* Convert vfp exception flags to target form. */
7843 static inline int vfp_exceptbits_to_host(int target_bits)
7844 {
7845 int host_bits = 0;
7846
7847 if (target_bits & 1)
7848 host_bits |= float_flag_invalid;
7849 if (target_bits & 2)
7850 host_bits |= float_flag_divbyzero;
7851 if (target_bits & 4)
7852 host_bits |= float_flag_overflow;
7853 if (target_bits & 8)
7854 host_bits |= float_flag_underflow;
7855 if (target_bits & 0x10)
7856 host_bits |= float_flag_inexact;
7857 if (target_bits & 0x80)
7858 host_bits |= float_flag_input_denormal;
7859 return host_bits;
7860 }
7861
7862 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
7863 {
7864 int i;
7865 uint32_t changed;
7866
7867 changed = env->vfp.xregs[ARM_VFP_FPSCR];
7868 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
7869 env->vfp.vec_len = (val >> 16) & 7;
7870 env->vfp.vec_stride = (val >> 20) & 3;
7871
7872 changed ^= val;
7873 if (changed & (3 << 22)) {
7874 i = (val >> 22) & 3;
7875 switch (i) {
7876 case FPROUNDING_TIEEVEN:
7877 i = float_round_nearest_even;
7878 break;
7879 case FPROUNDING_POSINF:
7880 i = float_round_up;
7881 break;
7882 case FPROUNDING_NEGINF:
7883 i = float_round_down;
7884 break;
7885 case FPROUNDING_ZERO:
7886 i = float_round_to_zero;
7887 break;
7888 }
7889 set_float_rounding_mode(i, &env->vfp.fp_status);
7890 }
7891 if (changed & (1 << 24)) {
7892 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
7893 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
7894 }
7895 if (changed & (1 << 25))
7896 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
7897
7898 i = vfp_exceptbits_to_host(val);
7899 set_float_exception_flags(i, &env->vfp.fp_status);
7900 set_float_exception_flags(0, &env->vfp.standard_fp_status);
7901 }
7902
7903 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
7904 {
7905 HELPER(vfp_set_fpscr)(env, val);
7906 }
7907
7908 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
7909
7910 #define VFP_BINOP(name) \
7911 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
7912 { \
7913 float_status *fpst = fpstp; \
7914 return float32_ ## name(a, b, fpst); \
7915 } \
7916 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
7917 { \
7918 float_status *fpst = fpstp; \
7919 return float64_ ## name(a, b, fpst); \
7920 }
7921 VFP_BINOP(add)
7922 VFP_BINOP(sub)
7923 VFP_BINOP(mul)
7924 VFP_BINOP(div)
7925 VFP_BINOP(min)
7926 VFP_BINOP(max)
7927 VFP_BINOP(minnum)
7928 VFP_BINOP(maxnum)
7929 #undef VFP_BINOP
7930
7931 float32 VFP_HELPER(neg, s)(float32 a)
7932 {
7933 return float32_chs(a);
7934 }
7935
7936 float64 VFP_HELPER(neg, d)(float64 a)
7937 {
7938 return float64_chs(a);
7939 }
7940
7941 float32 VFP_HELPER(abs, s)(float32 a)
7942 {
7943 return float32_abs(a);
7944 }
7945
7946 float64 VFP_HELPER(abs, d)(float64 a)
7947 {
7948 return float64_abs(a);
7949 }
7950
7951 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
7952 {
7953 return float32_sqrt(a, &env->vfp.fp_status);
7954 }
7955
7956 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
7957 {
7958 return float64_sqrt(a, &env->vfp.fp_status);
7959 }
7960
7961 /* XXX: check quiet/signaling case */
7962 #define DO_VFP_cmp(p, type) \
7963 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
7964 { \
7965 uint32_t flags; \
7966 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
7967 case 0: flags = 0x6; break; \
7968 case -1: flags = 0x8; break; \
7969 case 1: flags = 0x2; break; \
7970 default: case 2: flags = 0x3; break; \
7971 } \
7972 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
7973 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
7974 } \
7975 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
7976 { \
7977 uint32_t flags; \
7978 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
7979 case 0: flags = 0x6; break; \
7980 case -1: flags = 0x8; break; \
7981 case 1: flags = 0x2; break; \
7982 default: case 2: flags = 0x3; break; \
7983 } \
7984 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
7985 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
7986 }
7987 DO_VFP_cmp(s, float32)
7988 DO_VFP_cmp(d, float64)
7989 #undef DO_VFP_cmp
7990
7991 /* Integer to float and float to integer conversions */
7992
7993 #define CONV_ITOF(name, fsz, sign) \
7994 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
7995 { \
7996 float_status *fpst = fpstp; \
7997 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
7998 }
7999
8000 #define CONV_FTOI(name, fsz, sign, round) \
8001 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8002 { \
8003 float_status *fpst = fpstp; \
8004 if (float##fsz##_is_any_nan(x)) { \
8005 float_raise(float_flag_invalid, fpst); \
8006 return 0; \
8007 } \
8008 return float##fsz##_to_##sign##int32##round(x, fpst); \
8009 }
8010
8011 #define FLOAT_CONVS(name, p, fsz, sign) \
8012 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8013 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8014 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8015
8016 FLOAT_CONVS(si, s, 32, )
8017 FLOAT_CONVS(si, d, 64, )
8018 FLOAT_CONVS(ui, s, 32, u)
8019 FLOAT_CONVS(ui, d, 64, u)
8020
8021 #undef CONV_ITOF
8022 #undef CONV_FTOI
8023 #undef FLOAT_CONVS
8024
8025 /* floating point conversion */
8026 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
8027 {
8028 float64 r = float32_to_float64(x, &env->vfp.fp_status);
8029 /* ARM requires that S<->D conversion of any kind of NaN generates
8030 * a quiet NaN by forcing the most significant frac bit to 1.
8031 */
8032 return float64_maybe_silence_nan(r);
8033 }
8034
8035 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
8036 {
8037 float32 r = float64_to_float32(x, &env->vfp.fp_status);
8038 /* ARM requires that S<->D conversion of any kind of NaN generates
8039 * a quiet NaN by forcing the most significant frac bit to 1.
8040 */
8041 return float32_maybe_silence_nan(r);
8042 }
8043
8044 /* VFP3 fixed point conversion. */
8045 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8046 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
8047 void *fpstp) \
8048 { \
8049 float_status *fpst = fpstp; \
8050 float##fsz tmp; \
8051 tmp = itype##_to_##float##fsz(x, fpst); \
8052 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8053 }
8054
8055 /* Notice that we want only input-denormal exception flags from the
8056 * scalbn operation: the other possible flags (overflow+inexact if
8057 * we overflow to infinity, output-denormal) aren't correct for the
8058 * complete scale-and-convert operation.
8059 */
8060 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8061 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8062 uint32_t shift, \
8063 void *fpstp) \
8064 { \
8065 float_status *fpst = fpstp; \
8066 int old_exc_flags = get_float_exception_flags(fpst); \
8067 float##fsz tmp; \
8068 if (float##fsz##_is_any_nan(x)) { \
8069 float_raise(float_flag_invalid, fpst); \
8070 return 0; \
8071 } \
8072 tmp = float##fsz##_scalbn(x, shift, fpst); \
8073 old_exc_flags |= get_float_exception_flags(fpst) \
8074 & float_flag_input_denormal; \
8075 set_float_exception_flags(old_exc_flags, fpst); \
8076 return float##fsz##_to_##itype##round(tmp, fpst); \
8077 }
8078
8079 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
8080 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8081 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8082 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8083
8084 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
8085 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8086 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8087
8088 VFP_CONV_FIX(sh, d, 64, 64, int16)
8089 VFP_CONV_FIX(sl, d, 64, 64, int32)
8090 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8091 VFP_CONV_FIX(uh, d, 64, 64, uint16)
8092 VFP_CONV_FIX(ul, d, 64, 64, uint32)
8093 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8094 VFP_CONV_FIX(sh, s, 32, 32, int16)
8095 VFP_CONV_FIX(sl, s, 32, 32, int32)
8096 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8097 VFP_CONV_FIX(uh, s, 32, 32, uint16)
8098 VFP_CONV_FIX(ul, s, 32, 32, uint32)
8099 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
8100 #undef VFP_CONV_FIX
8101 #undef VFP_CONV_FIX_FLOAT
8102 #undef VFP_CONV_FLOAT_FIX_ROUND
8103
8104 /* Set the current fp rounding mode and return the old one.
8105 * The argument is a softfloat float_round_ value.
8106 */
8107 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
8108 {
8109 float_status *fp_status = &env->vfp.fp_status;
8110
8111 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8112 set_float_rounding_mode(rmode, fp_status);
8113
8114 return prev_rmode;
8115 }
8116
8117 /* Set the current fp rounding mode in the standard fp status and return
8118 * the old one. This is for NEON instructions that need to change the
8119 * rounding mode but wish to use the standard FPSCR values for everything
8120 * else. Always set the rounding mode back to the correct value after
8121 * modifying it.
8122 * The argument is a softfloat float_round_ value.
8123 */
8124 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
8125 {
8126 float_status *fp_status = &env->vfp.standard_fp_status;
8127
8128 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8129 set_float_rounding_mode(rmode, fp_status);
8130
8131 return prev_rmode;
8132 }
8133
8134 /* Half precision conversions. */
8135 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
8136 {
8137 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8138 float32 r = float16_to_float32(make_float16(a), ieee, s);
8139 if (ieee) {
8140 return float32_maybe_silence_nan(r);
8141 }
8142 return r;
8143 }
8144
8145 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
8146 {
8147 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8148 float16 r = float32_to_float16(a, ieee, s);
8149 if (ieee) {
8150 r = float16_maybe_silence_nan(r);
8151 }
8152 return float16_val(r);
8153 }
8154
8155 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8156 {
8157 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
8158 }
8159
8160 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8161 {
8162 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
8163 }
8164
8165 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8166 {
8167 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
8168 }
8169
8170 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8171 {
8172 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
8173 }
8174
8175 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
8176 {
8177 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8178 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
8179 if (ieee) {
8180 return float64_maybe_silence_nan(r);
8181 }
8182 return r;
8183 }
8184
8185 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
8186 {
8187 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8188 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
8189 if (ieee) {
8190 r = float16_maybe_silence_nan(r);
8191 }
8192 return float16_val(r);
8193 }
8194
8195 #define float32_two make_float32(0x40000000)
8196 #define float32_three make_float32(0x40400000)
8197 #define float32_one_point_five make_float32(0x3fc00000)
8198
8199 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
8200 {
8201 float_status *s = &env->vfp.standard_fp_status;
8202 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8203 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8204 if (!(float32_is_zero(a) || float32_is_zero(b))) {
8205 float_raise(float_flag_input_denormal, s);
8206 }
8207 return float32_two;
8208 }
8209 return float32_sub(float32_two, float32_mul(a, b, s), s);
8210 }
8211
8212 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
8213 {
8214 float_status *s = &env->vfp.standard_fp_status;
8215 float32 product;
8216 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8217 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8218 if (!(float32_is_zero(a) || float32_is_zero(b))) {
8219 float_raise(float_flag_input_denormal, s);
8220 }
8221 return float32_one_point_five;
8222 }
8223 product = float32_mul(a, b, s);
8224 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
8225 }
8226
8227 /* NEON helpers. */
8228
8229 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8230 * int->float conversions at run-time. */
8231 #define float64_256 make_float64(0x4070000000000000LL)
8232 #define float64_512 make_float64(0x4080000000000000LL)
8233 #define float32_maxnorm make_float32(0x7f7fffff)
8234 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8235
8236 /* Reciprocal functions
8237 *
8238 * The algorithm that must be used to calculate the estimate
8239 * is specified by the ARM ARM, see FPRecipEstimate()
8240 */
8241
8242 static float64 recip_estimate(float64 a, float_status *real_fp_status)
8243 {
8244 /* These calculations mustn't set any fp exception flags,
8245 * so we use a local copy of the fp_status.
8246 */
8247 float_status dummy_status = *real_fp_status;
8248 float_status *s = &dummy_status;
8249 /* q = (int)(a * 512.0) */
8250 float64 q = float64_mul(float64_512, a, s);
8251 int64_t q_int = float64_to_int64_round_to_zero(q, s);
8252
8253 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8254 q = int64_to_float64(q_int, s);
8255 q = float64_add(q, float64_half, s);
8256 q = float64_div(q, float64_512, s);
8257 q = float64_div(float64_one, q, s);
8258
8259 /* s = (int)(256.0 * r + 0.5) */
8260 q = float64_mul(q, float64_256, s);
8261 q = float64_add(q, float64_half, s);
8262 q_int = float64_to_int64_round_to_zero(q, s);
8263
8264 /* return (double)s / 256.0 */
8265 return float64_div(int64_to_float64(q_int, s), float64_256, s);
8266 }
8267
8268 /* Common wrapper to call recip_estimate */
8269 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
8270 {
8271 uint64_t val64 = float64_val(num);
8272 uint64_t frac = extract64(val64, 0, 52);
8273 int64_t exp = extract64(val64, 52, 11);
8274 uint64_t sbit;
8275 float64 scaled, estimate;
8276
8277 /* Generate the scaled number for the estimate function */
8278 if (exp == 0) {
8279 if (extract64(frac, 51, 1) == 0) {
8280 exp = -1;
8281 frac = extract64(frac, 0, 50) << 2;
8282 } else {
8283 frac = extract64(frac, 0, 51) << 1;
8284 }
8285 }
8286
8287 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8288 scaled = make_float64((0x3feULL << 52)
8289 | extract64(frac, 44, 8) << 44);
8290
8291 estimate = recip_estimate(scaled, fpst);
8292
8293 /* Build new result */
8294 val64 = float64_val(estimate);
8295 sbit = 0x8000000000000000ULL & val64;
8296 exp = off - exp;
8297 frac = extract64(val64, 0, 52);
8298
8299 if (exp == 0) {
8300 frac = 1ULL << 51 | extract64(frac, 1, 51);
8301 } else if (exp == -1) {
8302 frac = 1ULL << 50 | extract64(frac, 2, 50);
8303 exp = 0;
8304 }
8305
8306 return make_float64(sbit | (exp << 52) | frac);
8307 }
8308
8309 static bool round_to_inf(float_status *fpst, bool sign_bit)
8310 {
8311 switch (fpst->float_rounding_mode) {
8312 case float_round_nearest_even: /* Round to Nearest */
8313 return true;
8314 case float_round_up: /* Round to +Inf */
8315 return !sign_bit;
8316 case float_round_down: /* Round to -Inf */
8317 return sign_bit;
8318 case float_round_to_zero: /* Round to Zero */
8319 return false;
8320 }
8321
8322 g_assert_not_reached();
8323 }
8324
8325 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
8326 {
8327 float_status *fpst = fpstp;
8328 float32 f32 = float32_squash_input_denormal(input, fpst);
8329 uint32_t f32_val = float32_val(f32);
8330 uint32_t f32_sbit = 0x80000000ULL & f32_val;
8331 int32_t f32_exp = extract32(f32_val, 23, 8);
8332 uint32_t f32_frac = extract32(f32_val, 0, 23);
8333 float64 f64, r64;
8334 uint64_t r64_val;
8335 int64_t r64_exp;
8336 uint64_t r64_frac;
8337
8338 if (float32_is_any_nan(f32)) {
8339 float32 nan = f32;
8340 if (float32_is_signaling_nan(f32)) {
8341 float_raise(float_flag_invalid, fpst);
8342 nan = float32_maybe_silence_nan(f32);
8343 }
8344 if (fpst->default_nan_mode) {
8345 nan = float32_default_nan;
8346 }
8347 return nan;
8348 } else if (float32_is_infinity(f32)) {
8349 return float32_set_sign(float32_zero, float32_is_neg(f32));
8350 } else if (float32_is_zero(f32)) {
8351 float_raise(float_flag_divbyzero, fpst);
8352 return float32_set_sign(float32_infinity, float32_is_neg(f32));
8353 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
8354 /* Abs(value) < 2.0^-128 */
8355 float_raise(float_flag_overflow | float_flag_inexact, fpst);
8356 if (round_to_inf(fpst, f32_sbit)) {
8357 return float32_set_sign(float32_infinity, float32_is_neg(f32));
8358 } else {
8359 return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
8360 }
8361 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
8362 float_raise(float_flag_underflow, fpst);
8363 return float32_set_sign(float32_zero, float32_is_neg(f32));
8364 }
8365
8366
8367 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
8368 r64 = call_recip_estimate(f64, 253, fpst);
8369 r64_val = float64_val(r64);
8370 r64_exp = extract64(r64_val, 52, 11);
8371 r64_frac = extract64(r64_val, 0, 52);
8372
8373 /* result = sign : result_exp<7:0> : fraction<51:29>; */
8374 return make_float32(f32_sbit |
8375 (r64_exp & 0xff) << 23 |
8376 extract64(r64_frac, 29, 24));
8377 }
8378
8379 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
8380 {
8381 float_status *fpst = fpstp;
8382 float64 f64 = float64_squash_input_denormal(input, fpst);
8383 uint64_t f64_val = float64_val(f64);
8384 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
8385 int64_t f64_exp = extract64(f64_val, 52, 11);
8386 float64 r64;
8387 uint64_t r64_val;
8388 int64_t r64_exp;
8389 uint64_t r64_frac;
8390
8391 /* Deal with any special cases */
8392 if (float64_is_any_nan(f64)) {
8393 float64 nan = f64;
8394 if (float64_is_signaling_nan(f64)) {
8395 float_raise(float_flag_invalid, fpst);
8396 nan = float64_maybe_silence_nan(f64);
8397 }
8398 if (fpst->default_nan_mode) {
8399 nan = float64_default_nan;
8400 }
8401 return nan;
8402 } else if (float64_is_infinity(f64)) {
8403 return float64_set_sign(float64_zero, float64_is_neg(f64));
8404 } else if (float64_is_zero(f64)) {
8405 float_raise(float_flag_divbyzero, fpst);
8406 return float64_set_sign(float64_infinity, float64_is_neg(f64));
8407 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
8408 /* Abs(value) < 2.0^-1024 */
8409 float_raise(float_flag_overflow | float_flag_inexact, fpst);
8410 if (round_to_inf(fpst, f64_sbit)) {
8411 return float64_set_sign(float64_infinity, float64_is_neg(f64));
8412 } else {
8413 return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
8414 }
8415 } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
8416 float_raise(float_flag_underflow, fpst);
8417 return float64_set_sign(float64_zero, float64_is_neg(f64));
8418 }
8419
8420 r64 = call_recip_estimate(f64, 2045, fpst);
8421 r64_val = float64_val(r64);
8422 r64_exp = extract64(r64_val, 52, 11);
8423 r64_frac = extract64(r64_val, 0, 52);
8424
8425 /* result = sign : result_exp<10:0> : fraction<51:0> */
8426 return make_float64(f64_sbit |
8427 ((r64_exp & 0x7ff) << 52) |
8428 r64_frac);
8429 }
8430
8431 /* The algorithm that must be used to calculate the estimate
8432 * is specified by the ARM ARM.
8433 */
8434 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
8435 {
8436 /* These calculations mustn't set any fp exception flags,
8437 * so we use a local copy of the fp_status.
8438 */
8439 float_status dummy_status = *real_fp_status;
8440 float_status *s = &dummy_status;
8441 float64 q;
8442 int64_t q_int;
8443
8444 if (float64_lt(a, float64_half, s)) {
8445 /* range 0.25 <= a < 0.5 */
8446
8447 /* a in units of 1/512 rounded down */
8448 /* q0 = (int)(a * 512.0); */
8449 q = float64_mul(float64_512, a, s);
8450 q_int = float64_to_int64_round_to_zero(q, s);
8451
8452 /* reciprocal root r */
8453 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
8454 q = int64_to_float64(q_int, s);
8455 q = float64_add(q, float64_half, s);
8456 q = float64_div(q, float64_512, s);
8457 q = float64_sqrt(q, s);
8458 q = float64_div(float64_one, q, s);
8459 } else {
8460 /* range 0.5 <= a < 1.0 */
8461
8462 /* a in units of 1/256 rounded down */
8463 /* q1 = (int)(a * 256.0); */
8464 q = float64_mul(float64_256, a, s);
8465 int64_t q_int = float64_to_int64_round_to_zero(q, s);
8466
8467 /* reciprocal root r */
8468 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
8469 q = int64_to_float64(q_int, s);
8470 q = float64_add(q, float64_half, s);
8471 q = float64_div(q, float64_256, s);
8472 q = float64_sqrt(q, s);
8473 q = float64_div(float64_one, q, s);
8474 }
8475 /* r in units of 1/256 rounded to nearest */
8476 /* s = (int)(256.0 * r + 0.5); */
8477
8478 q = float64_mul(q, float64_256,s );
8479 q = float64_add(q, float64_half, s);
8480 q_int = float64_to_int64_round_to_zero(q, s);
8481
8482 /* return (double)s / 256.0;*/
8483 return float64_div(int64_to_float64(q_int, s), float64_256, s);
8484 }
8485
8486 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
8487 {
8488 float_status *s = fpstp;
8489 float32 f32 = float32_squash_input_denormal(input, s);
8490 uint32_t val = float32_val(f32);
8491 uint32_t f32_sbit = 0x80000000 & val;
8492 int32_t f32_exp = extract32(val, 23, 8);
8493 uint32_t f32_frac = extract32(val, 0, 23);
8494 uint64_t f64_frac;
8495 uint64_t val64;
8496 int result_exp;
8497 float64 f64;
8498
8499 if (float32_is_any_nan(f32)) {
8500 float32 nan = f32;
8501 if (float32_is_signaling_nan(f32)) {
8502 float_raise(float_flag_invalid, s);
8503 nan = float32_maybe_silence_nan(f32);
8504 }
8505 if (s->default_nan_mode) {
8506 nan = float32_default_nan;
8507 }
8508 return nan;
8509 } else if (float32_is_zero(f32)) {
8510 float_raise(float_flag_divbyzero, s);
8511 return float32_set_sign(float32_infinity, float32_is_neg(f32));
8512 } else if (float32_is_neg(f32)) {
8513 float_raise(float_flag_invalid, s);
8514 return float32_default_nan;
8515 } else if (float32_is_infinity(f32)) {
8516 return float32_zero;
8517 }
8518
8519 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8520 * preserving the parity of the exponent. */
8521
8522 f64_frac = ((uint64_t) f32_frac) << 29;
8523 if (f32_exp == 0) {
8524 while (extract64(f64_frac, 51, 1) == 0) {
8525 f64_frac = f64_frac << 1;
8526 f32_exp = f32_exp-1;
8527 }
8528 f64_frac = extract64(f64_frac, 0, 51) << 1;
8529 }
8530
8531 if (extract64(f32_exp, 0, 1) == 0) {
8532 f64 = make_float64(((uint64_t) f32_sbit) << 32
8533 | (0x3feULL << 52)
8534 | f64_frac);
8535 } else {
8536 f64 = make_float64(((uint64_t) f32_sbit) << 32
8537 | (0x3fdULL << 52)
8538 | f64_frac);
8539 }
8540
8541 result_exp = (380 - f32_exp) / 2;
8542
8543 f64 = recip_sqrt_estimate(f64, s);
8544
8545 val64 = float64_val(f64);
8546
8547 val = ((result_exp & 0xff) << 23)
8548 | ((val64 >> 29) & 0x7fffff);
8549 return make_float32(val);
8550 }
8551
8552 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
8553 {
8554 float_status *s = fpstp;
8555 float64 f64 = float64_squash_input_denormal(input, s);
8556 uint64_t val = float64_val(f64);
8557 uint64_t f64_sbit = 0x8000000000000000ULL & val;
8558 int64_t f64_exp = extract64(val, 52, 11);
8559 uint64_t f64_frac = extract64(val, 0, 52);
8560 int64_t result_exp;
8561 uint64_t result_frac;
8562
8563 if (float64_is_any_nan(f64)) {
8564 float64 nan = f64;
8565 if (float64_is_signaling_nan(f64)) {
8566 float_raise(float_flag_invalid, s);
8567 nan = float64_maybe_silence_nan(f64);
8568 }
8569 if (s->default_nan_mode) {
8570 nan = float64_default_nan;
8571 }
8572 return nan;
8573 } else if (float64_is_zero(f64)) {
8574 float_raise(float_flag_divbyzero, s);
8575 return float64_set_sign(float64_infinity, float64_is_neg(f64));
8576 } else if (float64_is_neg(f64)) {
8577 float_raise(float_flag_invalid, s);
8578 return float64_default_nan;
8579 } else if (float64_is_infinity(f64)) {
8580 return float64_zero;
8581 }
8582
8583 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8584 * preserving the parity of the exponent. */
8585
8586 if (f64_exp == 0) {
8587 while (extract64(f64_frac, 51, 1) == 0) {
8588 f64_frac = f64_frac << 1;
8589 f64_exp = f64_exp - 1;
8590 }
8591 f64_frac = extract64(f64_frac, 0, 51) << 1;
8592 }
8593
8594 if (extract64(f64_exp, 0, 1) == 0) {
8595 f64 = make_float64(f64_sbit
8596 | (0x3feULL << 52)
8597 | f64_frac);
8598 } else {
8599 f64 = make_float64(f64_sbit
8600 | (0x3fdULL << 52)
8601 | f64_frac);
8602 }
8603
8604 result_exp = (3068 - f64_exp) / 2;
8605
8606 f64 = recip_sqrt_estimate(f64, s);
8607
8608 result_frac = extract64(float64_val(f64), 0, 52);
8609
8610 return make_float64(f64_sbit |
8611 ((result_exp & 0x7ff) << 52) |
8612 result_frac);
8613 }
8614
8615 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
8616 {
8617 float_status *s = fpstp;
8618 float64 f64;
8619
8620 if ((a & 0x80000000) == 0) {
8621 return 0xffffffff;
8622 }
8623
8624 f64 = make_float64((0x3feULL << 52)
8625 | ((int64_t)(a & 0x7fffffff) << 21));
8626
8627 f64 = recip_estimate(f64, s);
8628
8629 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8630 }
8631
8632 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
8633 {
8634 float_status *fpst = fpstp;
8635 float64 f64;
8636
8637 if ((a & 0xc0000000) == 0) {
8638 return 0xffffffff;
8639 }
8640
8641 if (a & 0x80000000) {
8642 f64 = make_float64((0x3feULL << 52)
8643 | ((uint64_t)(a & 0x7fffffff) << 21));
8644 } else { /* bits 31-30 == '01' */
8645 f64 = make_float64((0x3fdULL << 52)
8646 | ((uint64_t)(a & 0x3fffffff) << 22));
8647 }
8648
8649 f64 = recip_sqrt_estimate(f64, fpst);
8650
8651 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8652 }
8653
8654 /* VFPv4 fused multiply-accumulate */
8655 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
8656 {
8657 float_status *fpst = fpstp;
8658 return float32_muladd(a, b, c, 0, fpst);
8659 }
8660
8661 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
8662 {
8663 float_status *fpst = fpstp;
8664 return float64_muladd(a, b, c, 0, fpst);
8665 }
8666
8667 /* ARMv8 round to integral */
8668 float32 HELPER(rints_exact)(float32 x, void *fp_status)
8669 {
8670 return float32_round_to_int(x, fp_status);
8671 }
8672
8673 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
8674 {
8675 return float64_round_to_int(x, fp_status);
8676 }
8677
8678 float32 HELPER(rints)(float32 x, void *fp_status)
8679 {
8680 int old_flags = get_float_exception_flags(fp_status), new_flags;
8681 float32 ret;
8682
8683 ret = float32_round_to_int(x, fp_status);
8684
8685 /* Suppress any inexact exceptions the conversion produced */
8686 if (!(old_flags & float_flag_inexact)) {
8687 new_flags = get_float_exception_flags(fp_status);
8688 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8689 }
8690
8691 return ret;
8692 }
8693
8694 float64 HELPER(rintd)(float64 x, void *fp_status)
8695 {
8696 int old_flags = get_float_exception_flags(fp_status), new_flags;
8697 float64 ret;
8698
8699 ret = float64_round_to_int(x, fp_status);
8700
8701 new_flags = get_float_exception_flags(fp_status);
8702
8703 /* Suppress any inexact exceptions the conversion produced */
8704 if (!(old_flags & float_flag_inexact)) {
8705 new_flags = get_float_exception_flags(fp_status);
8706 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8707 }
8708
8709 return ret;
8710 }
8711
8712 /* Convert ARM rounding mode to softfloat */
8713 int arm_rmode_to_sf(int rmode)
8714 {
8715 switch (rmode) {
8716 case FPROUNDING_TIEAWAY:
8717 rmode = float_round_ties_away;
8718 break;
8719 case FPROUNDING_ODD:
8720 /* FIXME: add support for TIEAWAY and ODD */
8721 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
8722 rmode);
8723 case FPROUNDING_TIEEVEN:
8724 default:
8725 rmode = float_round_nearest_even;
8726 break;
8727 case FPROUNDING_POSINF:
8728 rmode = float_round_up;
8729 break;
8730 case FPROUNDING_NEGINF:
8731 rmode = float_round_down;
8732 break;
8733 case FPROUNDING_ZERO:
8734 rmode = float_round_to_zero;
8735 break;
8736 }
8737 return rmode;
8738 }
8739
8740 /* CRC helpers.
8741 * The upper bytes of val (above the number specified by 'bytes') must have
8742 * been zeroed out by the caller.
8743 */
8744 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
8745 {
8746 uint8_t buf[4];
8747
8748 stl_le_p(buf, val);
8749
8750 /* zlib crc32 converts the accumulator and output to one's complement. */
8751 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
8752 }
8753
8754 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
8755 {
8756 uint8_t buf[4];
8757
8758 stl_le_p(buf, val);
8759
8760 /* Linux crc32c converts the output to one's complement. */
8761 return crc32c(acc, buf, bytes) ^ 0xffffffff;
8762 }
CRIS target port of Qemu